Added test for PWM peripheral.
diff --git a/verilog/dv/peripheralsPWM/Makefile b/verilog/dv/peripheralsPWM/Makefile new file mode 100644 index 0000000..3fd0b56 --- /dev/null +++ b/verilog/dv/peripheralsPWM/Makefile
@@ -0,0 +1,32 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + + + +PWDD := $(shell pwd) +BLOCKS := $(shell basename $(PWDD)) + +# ---- Include Partitioned Makefiles ---- + +CONFIG = caravel_user_project + + +include $(MCW_ROOT)/verilog/dv/make/env.makefile +include $(MCW_ROOT)/verilog/dv/make/var.makefile +include $(MCW_ROOT)/verilog/dv/make/cpu.makefile +include $(MCW_ROOT)/verilog/dv/make/sim.makefile + +
diff --git a/verilog/dv/peripheralsPWM/peripheralsPWM.c b/verilog/dv/peripheralsPWM/peripheralsPWM.c new file mode 100644 index 0000000..49dc4fc --- /dev/null +++ b/verilog/dv/peripheralsPWM/peripheralsPWM.c
@@ -0,0 +1,261 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +// This include is relative to $CARAVEL_PATH (see Makefile) +#include <defs.h> +#include <stub.c> + +/* + IO Test: + - Configures MPRJ lower 8-IO pins as outputs + - Observes counter value through the MPRJ lower 8 IO pins (in the testbench) +*/ + +#define GPIO0_OE_WRITE_ADDR ((uint32_t*)0x33031000) +#define GPIO0_OE_SET_ADDR ((uint32_t*)0x33031004) +#define GPIO0_OE_CLEAR_ADDR ((uint32_t*)0x33031008) +#define GPIO0_OE_TOGGLE_ADDR ((uint32_t*)0x3303100C) +#define GPIO0_OUTPUT_WRITE_ADDR ((uint32_t*)0x33031010) +#define GPIO0_OUTPUT_SET_ADDR ((uint32_t*)0x33031014) +#define GPIO0_OUTPUT_CLEAR_ADDR ((uint32_t*)0x33031018) +#define GPIO0_OUTPUT_TOGGLE_ADDR ((uint32_t*)0x3303101C) +#define GPIO0_INPUT_ADDR ((uint32_t*)0x33031020) +#define GPIO1_OE_WRITE_ADDR ((uint32_t*)0x33032000) +#define GPIO1_OE_SET_ADDR ((uint32_t*)0x33032004) +#define GPIO1_OE_CLEAR_ADDR ((uint32_t*)0x33032008) +#define GPIO1_OE_TOGGLE_ADDR ((uint32_t*)0x3303200C) +#define GPIO1_OUTPUT_WRITE_ADDR ((uint32_t*)0x33032010) +#define GPIO1_OUTPUT_SET_ADDR ((uint32_t*)0x33032014) +#define GPIO1_OUTPUT_CLEAR_ADDR ((uint32_t*)0x33032018) +#define GPIO1_OUTPUT_TOGGLE_ADDR ((uint32_t*)0x3303201C) +#define GPIO1_INPUT_ADDR ((uint32_t*)0x33032020) + +#define PWM0_CONFIGURATION_REGISTER ((uint32_t*)0x33021000) +#define PWM0_COUNTER_TOP_VALUE ((uint32_t*)0x33021004) +#define PWM0_COUNTER_VALUE ((uint32_t*)0x33021008) +#define PWM0_OUTPUT0_COMPARE ((uint32_t*)0x33021010) +#define PWM0_OUTPUT1_COMPARE ((uint32_t*)0x33021014) +#define PWM0_OUTPUT2_COMPARE ((uint32_t*)0x33021018) +#define PWM0_OUTPUT3_COMPARE ((uint32_t*)0x3302101C) +#define PWM1_CONFIGURATION_REGISTER ((uint32_t*)0x33022000) +#define PWM1_COUNTER_TOP_VALUE ((uint32_t*)0x33022004) +#define PWM1_COUNTER_VALUE ((uint32_t*)0x33022008) +#define PWM1_OUTPUT0_COMPARE ((uint32_t*)0x33022010) +#define PWM1_OUTPUT1_COMPARE ((uint32_t*)0x33022014) +#define PWM1_OUTPUT2_COMPARE ((uint32_t*)0x33022018) +#define PWM1_OUTPUT3_COMPARE ((uint32_t*)0x3302201C) +#define PWM2_CONFIGURATION_REGISTER ((uint32_t*)0x33023000) +#define PWM2_COUNTER_TOP_VALUE ((uint32_t*)0x33023004) +#define PWM2_COUNTER_VALUE ((uint32_t*)0x33023008) +#define PWM2_OUTPUT0_COMPARE ((uint32_t*)0x33023010) +#define PWM2_OUTPUT1_COMPARE ((uint32_t*)0x33023015) +#define PWM2_OUTPUT2_COMPARE ((uint32_t*)0x33023018) +#define PWM2_OUTPUT3_COMPARE ((uint32_t*)0x3302301C) +#define PWM3_CONFIGURATION_REGISTER ((uint32_t*)0x33024000) +#define PWM3_COUNTER_TOP_VALUE ((uint32_t*)0x33024004) +#define PWM3_COUNTER_VALUE ((uint32_t*)0x33024008) +#define PWM3_OUTPUT0_COMPARE ((uint32_t*)0x33024010) +#define PWM3_OUTPUT1_COMPARE ((uint32_t*)0x33024014) +#define PWM3_OUTPUT2_COMPARE ((uint32_t*)0x33024018) +#define PWM3_OUTPUT3_COMPARE ((uint32_t*)0x3302401C) + +#define MPRJ_WB_ADDRESS (*(volatile uint32_t*)0x30000000) +#define MPRJ_WB_DATA_LOCATION 0x30008000 + +void wbWrite (uint32_t* location, uint32_t value) +{ + // Write the address + uint32_t locationData = (uint32_t)location; + MPRJ_WB_ADDRESS = locationData & 0xFFFF8000; + + // Write the data + uint32_t writeAddress = (locationData & 0x00007FFF) | MPRJ_WB_DATA_LOCATION; + *((volatile uint32_t*)writeAddress) = value; +} + +uint32_t wbRead (uint32_t* location) +{ + // Write the address + uint32_t locationData = (uint32_t)location; + MPRJ_WB_ADDRESS = locationData & 0xFFFF8000; + + // Write the data + uint32_t writeAddress = (locationData & 0x00007FFF) | MPRJ_WB_DATA_LOCATION; + return *((volatile uint32_t*)writeAddress); +} + +void nextTest (bool testPassing) +{ + if (testPassing) + { + wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x03000); + } + else + { + wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x01000); + wbWrite (GPIO0_OUTPUT_SET_ADDR, 0x02000); + } + + wbWrite (GPIO0_OUTPUT_CLEAR_ADDR, 0x02000); +} + +uint32_t tryGetPWMState (uint32_t* address, uint32_t valueMask, uint32_t state, uint32_t maxTries) +{ + uint32_t tries = maxTries; + while (tries > 0 && (wbRead (address) & valueMask) != state) tries--; + return tries; +} + +void main () +{ + /* + IO Control Registers + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | + + Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | + + + Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | + + */ + + /* Set up the housekeeping SPI to be connected internally so */ + /* that external pin changes don't affect it. */ + + // Connect the housekeeping SPI to the SPI master + // so that the CSB line is not left floating. This allows + // all of the GPIO pins to be used for user functions. + + // https://github.com/efabless/caravel/blob/main/docs/other/gpio.txt + + // Enable the wishbone bus + reg_wb_enable = 1; + + // Enable GPIO + reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT; + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1) {} + + // Setup test output + bool testPass = true; + wbWrite (GPIO0_OUTPUT_WRITE_ADDR, 0x01000); + wbWrite (GPIO0_OE_WRITE_ADDR, ~0x03000); + + // Check device 0 config + uint32_t device0Config = (0b11001100 << 6) | (0x1 << 5) | 0x03; + wbWrite (PWM0_CONFIGURATION_REGISTER, device0Config); + if (wbRead (PWM0_CONFIGURATION_REGISTER) != device0Config) testPass = false; + nextTest (testPass); + + // Check device 0 counter top value + uint32_t device0TopValue = 0x1388 - 1; + wbWrite (PWM0_COUNTER_TOP_VALUE, device0TopValue); + if (wbRead (PWM0_COUNTER_TOP_VALUE) != device0TopValue) testPass = false; + nextTest (testPass); + + // Check device 1 config + uint32_t device1Config = (0b00010001 << 6) | (0x1 << 5) | 0x02; + wbWrite (PWM1_CONFIGURATION_REGISTER, device1Config); + if (wbRead (PWM1_CONFIGURATION_REGISTER) != device1Config) testPass = false; + nextTest (testPass); + + // Check device 1 counter top value + uint32_t device1TopValue = 0x2710 - 1; + wbWrite (PWM1_COUNTER_TOP_VALUE, device1TopValue); + if (wbRead (PWM1_COUNTER_TOP_VALUE) != device1TopValue) testPass = false; + nextTest (testPass); + + // Check device 0 ouput value 2 compare value + uint32_t device0Output2Compare = 0x09C4 - 1; // 2500 -> 0.5ms off 0.5ms on + wbWrite (PWM0_OUTPUT2_COMPARE, device0Output2Compare); + if (wbRead (PWM0_OUTPUT2_COMPARE) != device0Output2Compare) testPass = false; + nextTest (testPass); + + // Check device 0 ouput value 3 compare value + uint32_t device0Output3Compare = 0x0DAC - 1; // 4500 -> 0.7ms off 0.3ms on + wbWrite (PWM0_OUTPUT3_COMPARE, device0Output3Compare); + if (wbRead (PWM0_OUTPUT3_COMPARE) != device0Output3Compare) testPass = false; + nextTest (testPass); + + // Check device 1 ouput value 0 compare value + uint32_t device1Output0Compare = 0x07D0 - 1; // 2000 -> 0.2ms off 0.8ms on + wbWrite (PWM1_OUTPUT0_COMPARE, device1Output0Compare); + if (wbRead (PWM1_OUTPUT0_COMPARE) != device1Output0Compare) testPass = false; + nextTest (testPass); + + // Check device 0 counter changes + uint32_t counterValue = wbRead (PWM0_COUNTER_VALUE) & 0xFFFF; + // Check twice to make absolutely sure that it wasn't just an unlucky coincidence that they where the same + if ((wbRead (PWM0_COUNTER_VALUE) & 0xFFFF) == counterValue && (wbRead (PWM0_COUNTER_VALUE) & 0xFFFF) == counterValue) testPass = false; + nextTest (testPass); + + // Check internal value goes high + uint32_t tries = tryGetPWMState (PWM0_COUNTER_VALUE, 0x40000, 0x40000, 20); + if (tries == 0) testPass = false; + nextTest (testPass); + + // Check internal value goes low + tries = tryGetPWMState (PWM0_COUNTER_VALUE, 0x40000, 0x00000, 20); + if (tries == 0) testPass = false; + nextTest (testPass); + + //----------------Device 0 ouput value 2----------------// + tries = tryGetPWMState (PWM0_COUNTER_VALUE, 0x40000, 0x00000, 20); + if (tries == 0) testPass = false; + + tries = tryGetPWMState (PWM0_COUNTER_VALUE, 0x40000, 0x40000, 20); + if (tries == 0) testPass = false; + + tries = tryGetPWMState (PWM0_COUNTER_VALUE, 0x40000, 0x00000, 20); + if (tries == 0) testPass = false; + nextTest (testPass); + + //----------------Device 0 ouput value 3----------------// + tries = tryGetPWMState (PWM0_COUNTER_VALUE, 0x80000, 0x00000, 20); + if (tries == 0) testPass = false; + + tries = tryGetPWMState (PWM0_COUNTER_VALUE, 0x80000, 0x80000, 20); + if (tries == 0) testPass = false; + + tries = tryGetPWMState (PWM0_COUNTER_VALUE, 0x80000, 0x00000, 20); + if (tries == 0) testPass = false; + nextTest (testPass); + + //----------------Device 1 ouput value 0----------------// + tries = tryGetPWMState (PWM1_COUNTER_VALUE, 0x10000, 0x00000, 20); + if (tries == 0) testPass = false; + + tries = tryGetPWMState (PWM1_COUNTER_VALUE, 0x10000, 0x10000, 20); + if (tries == 0) testPass = false; + + tries = tryGetPWMState (PWM1_COUNTER_VALUE, 0x10000, 0x00000, 20); + if (tries == 0) testPass = false; + + // Finish test + nextTest (testPass); +}
diff --git a/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v b/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v new file mode 100644 index 0000000..6c06022 --- /dev/null +++ b/verilog/dv/peripheralsPWM/peripheralsPWM_tb.v
@@ -0,0 +1,282 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none + +`timescale 1 ns / 1 ps + +module peripheralsPWM_tb; + reg clock; + reg RSTB; + reg CSB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + + wire[2:0] pwmOutputs = {mprj_io[16], mprj_io[15], mprj_io[14]}; + wire succesOutput = mprj_io[12]; + wire nextTestOutput = mprj_io[13]; + reg timingValid = 1'b1; + + pullup(mprj_io[3]); + assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + always #12.5 clock <= (clock === 1'b0); + + // Need to add pulls (can be up or down) to all unsed io so that input data is known + assign mprj_io[2:0] = 3'b0; + assign mprj_io[11:4] = 8'b0; + assign mprj_io[37:14] = 24'b0; + + initial begin + clock = 0; + timingValid = 1'b1; + end + + realtime timerStart; + realtime timerLength; + + initial begin + $dumpfile("peripheralsPWM.vcd"); + +`ifdef SIM + $dumpvars(0, peripheralsPWM_tb); +`else + $dumpvars(1, peripheralsPWM_tb); + $dumpvars(2, peripheralsPWM_tb.uut.mprj); +`endif + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (750) begin + repeat (1000) @(posedge clock); + //$display("+1000 cycles"); + end + $display("%c[1;35m",27); + `ifdef GL + $display ("Monitor: Timeout, Peripherals PWM Test (GL) Failed"); + `else + $display ("Monitor: Timeout, Peripherals PWM Test (RTL) Failed"); + `endif + $display("%c[0m",27); + $finish; + end + + initial begin + + // Check device 0 config + @(posedge nextTestOutput); + + // Check device 0 counter top value + @(posedge nextTestOutput); + + // Check device 1 config + @(posedge nextTestOutput); + + // Check device 1 counter top value + @(posedge nextTestOutput); + + // Check device 0 ouput value 2 compare value + @(posedge nextTestOutput); + + // Check device 0 ouput value 3 compare value + @(posedge nextTestOutput); + + // Check device 1 ouput value 0 compare value + @(posedge nextTestOutput); + + // Check device 0 counter changes + @(posedge nextTestOutput); + + // Check internal value goes high + @(posedge nextTestOutput); + + // Check internal value goes low + @(posedge nextTestOutput); + + //----------------Device 0 ouput value 2----------------// + // Has 0.2us resolution + // Wait for start of device 0 ouput value 0 signal + @(negedge pwmOutputs[0]); + timerStart = $realtime; + + // Measure device 0 ouput value 2 low time + @(posedge pwmOutputs[0]); + timerLength = $realtime - timerStart; + $display("Device 0 Output 2 Low Time: ", timerLength); + if (timerLength < 499800000 || timerLength > 500200000) timingValid = 1'b0; + + // Measure device 0 ouput value 2 period + @(negedge pwmOutputs[0]); + timerLength = $realtime - timerStart; + $display("Device 0 Output 2 Period: ", timerLength); + if (timerLength < 999800000 || timerLength > 1000200000) timingValid = 1'b0; + @(posedge nextTestOutput); + + //----------------Device 0 ouput value 3----------------// + // Has 0.2us resolution + // Wait for start of device 0 ouput value 1 signal + @(negedge pwmOutputs[1]); + timerStart = $realtime; + + // Measure device 0 ouput value 3 low time + @(posedge pwmOutputs[1]); + timerLength = $realtime - timerStart; + $display("Device 0 Output 3 Low Time: ", timerLength); + if (timerLength < 699800000 || timerLength > 700200000) timingValid = 1'b0; + + // Measure device 0 ouput value 3 period + @(negedge pwmOutputs[1]); + timerLength = $realtime - timerStart; + $display("Device 0 Output 3 Period: ", timerLength); + if (timerLength < 999800000 || timerLength > 1000200000) timingValid = 1'b0; + @(posedge nextTestOutput); + + //----------------Device 1 ouput value 0----------------// + // Has 0.1us resolution + // Wait for start of device 1 ouput value 0 signal + @(negedge pwmOutputs[2]); + timerStart = $realtime; + + // Measure device 1 ouput value 0 low time + @(posedge pwmOutputs[2]); + timerLength = $realtime - timerStart; + $display("Device 1 Output 0 Low Time: ", timerLength); + if (timerLength < 799900000 || timerLength > 800100000) timingValid = 1'b0; + + // Measure device 1 ouput value 0 period + @(negedge pwmOutputs[2]); + timerLength = $realtime - timerStart; + $display("Device 1 Output 0 Period: ", timerLength); + if (timerLength < 999900000 || timerLength > 1000100000) timingValid = 1'b0; + + // Wait for management core to output the final output test result + @(posedge nextTestOutput); + + if (!timingValid) begin + $display("%c[1;31m",27); + `ifdef GL + $display ("Monitor: Peripherals PWM Timing (GL) Failed"); + `else + $display ("Monitor: Peripherals PWM Timing (RTL) Failed"); + `endif + $display("%c[0m",27); + end else if (succesOutput) begin + $display("%c[1;92m",27); + `ifdef GL + $display("Monitor: Peripherals PWM Test (GL) Passed"); + `else + $display("Monitor: Peripherals PWM Test (RTL) Passed"); + `endif + $display("%c[0m",27); + end else begin + $display("%c[1;31m",27); + `ifdef GL + $display ("Monitor: Peripherals PWM Test (GL) Failed"); + `else + $display ("Monitor: Peripherals PWM Test (RTL) Failed"); + `endif + $display("%c[0m",27); + end + $finish; + end + + initial begin + RSTB <= 1'b0; + CSB <= 1'b1; // Force CSB high + #2000; + RSTB <= 1'b1; // Release reset + #300000; + CSB = 1'b0; // CSB can be released + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #100; + power1 <= 1'b1; + #100; + power2 <= 1'b1; + #100; + power3 <= 1'b1; + #100; + power4 <= 1'b1; + end + + always @(succesOutput, nextTestOutput) begin + #1 $display("Success:0b%b Next test:0b%b", succesOutput, nextTestOutput); + end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD3V3; + wire VDD1V8; + wire VSS; + + assign VDD3V3 = power1; + assign VDD1V8 = power2; + assign VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vddio_2 (VDD3V3), + .vssio (VSS), + .vssio_2 (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (VDD3V3), + .vdda1_2 (VDD3V3), + .vdda2 (VDD3V3), + .vssa1 (VSS), + .vssa1_2 (VSS), + .vssa2 (VSS), + .vccd1 (VDD1V8), + .vccd2 (VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("peripheralsPWM.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + +endmodule +`default_nettype wire