Files converted to single precision
diff --git a/verilog/dv/FPU_Single/FPU_Single_tb.v b/verilog/dv/FPU_Single/FPU_Single_tb.v
index f2bfa86..486d350 100644
--- a/verilog/dv/FPU_Single/FPU_Single_tb.v
+++ b/verilog/dv/FPU_Single/FPU_Single_tb.v
@@ -63,7 +63,7 @@
initial begin
wait(mprj_ready == 1'b1)
// Observe Output pins [23:8] for Fmove
- /*
+
wait(mprj_io_0 == 16'h4000);
wait(mprj_io_0 == 16'h4020);
wait(mprj_io_0 == 16'h4060);
@@ -72,7 +72,7 @@
wait(mprj_io_0 == 16'h40d0);
wait(mprj_io_0 == 16'hC158);
wait(mprj_io_0 == 16'hC178);
- */
+
// Observe Output pins [23:8] for Fsign and I2F
/*wait(mprj_io_0 == 16'h449A);
wait(mprj_io_0 == 16'h3042);
diff --git a/verilog/rtl/FPU/Execution.v b/verilog/rtl/FPU/Execution.v
index 25c7e48..104b133 100644
--- a/verilog/rtl/FPU/Execution.v
+++ b/verilog/rtl/FPU/Execution.v
@@ -1,14 +1,14 @@
module Execution(clk,rst_l,RS1_d,RS2_d,result,Flag_ADDI,Flag_LI,Activation_Signal,Flag_Reset,fpu_active,illegal_config,valid_execution,fs1_data,fs2_data,fs3_data,sfpu_op,fpu_pre,fpu_rounding,float_control,fpu_result_1,S_flag,dec_i0_rs1_en_d,dec_i0_rs2_en_d,IV_exception,fpu_complete,fpu_sel,fpu_result_rd_w,fpu_complete_rd);
input clk,rst_l,Flag_ADDI,Flag_LI,Flag_Reset,fpu_active,illegal_config,valid_execution,dec_i0_rs1_en_d,dec_i0_rs2_en_d;
input [31:0]RS1_d,RS2_d;
- input [15:0]fs1_data,fs2_data,fs3_data;
+ input [31:0]fs1_data,fs2_data,fs3_data;
input [23:0]sfpu_op;
input [2:0]fpu_pre,fpu_rounding;
input [3:0]float_control;
input [2:0]fpu_sel;
output reg[31:0]result;
output reg Activation_Signal;
- output [15:0]fpu_result_1;
+ output [31:0]fpu_result_1;
output [4:0]S_flag;
output IV_exception;
output fpu_complete;
diff --git a/verilog/rtl/FPU/FPU_FSM_Control_Decode.v b/verilog/rtl/FPU/FPU_FSM_Control_Decode.v
index 8bd5804..9534432 100644
--- a/verilog/rtl/FPU/FPU_FSM_Control_Decode.v
+++ b/verilog/rtl/FPU/FPU_FSM_Control_Decode.v
@@ -6,10 +6,8 @@
output reg[31:0]PC;
output [31:0]Instruction_out;
- //wire [23:0]Uncontrolled_Opcode;
reg [1:0]State;
wire [1:0]Next_State;
- wire [4:0]Input_Opcode;
wire Exception;
/*
@@ -38,37 +36,7 @@
sfpu[22] = unsign
sfpu[23] = sign
*/
- /*
- assign Input_Opcode = Instruction[4:0];
-
- assign Output_1_Hot_Encoded_Opcode[0] = ~Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & ~Input_Opcode[1] & ~Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[1] = ~Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & ~Input_Opcode[1] & Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[2] = ~Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & Input_Opcode[1] & ~Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[3] = ~Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & Input_Opcode[1] & Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[4] = ~Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & ~Input_Opcode[1] & ~Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[5] = ~Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & ~Input_Opcode[1] & Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[6] = ~Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & Input_Opcode[1] & ~Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[7] = ~Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & Input_Opcode[1] & Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[8] = ~Input_Opcode[4] & Input_Opcode[3] & ~Input_Opcode[2] & ~Input_Opcode[1] & ~Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[9] = ~Input_Opcode[4] & Input_Opcode[3] & ~Input_Opcode[2] & ~Input_Opcode[1] & Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[10] = ~Input_Opcode[4] & Input_Opcode[3] & ~Input_Opcode[2] & Input_Opcode[1] & ~Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[11] = ~Input_Opcode[4] & Input_Opcode[3] & ~Input_Opcode[2] & Input_Opcode[1] & Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[12] = ~Input_Opcode[4] & Input_Opcode[3] & Input_Opcode[2] & ~Input_Opcode[1] & ~Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[13] = ~Input_Opcode[4] & Input_Opcode[3] & Input_Opcode[2] & ~Input_Opcode[1] & Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[14] = ~Input_Opcode[4] & Input_Opcode[3] & Input_Opcode[2] & Input_Opcode[1] & ~Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[15] = ~Input_Opcode[4] & Input_Opcode[3] & Input_Opcode[2] & Input_Opcode[1] & Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[16] = Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & ~Input_Opcode[1] & ~Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[17] = Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & ~Input_Opcode[1] & Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[18] = Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & Input_Opcode[1] & ~Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[19] = Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & Input_Opcode[1] & Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[20] = Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & ~Input_Opcode[1] & ~Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[21] = Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & ~Input_Opcode[1] & Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[22] = Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & Input_Opcode[1] & ~Input_Opcode[0];
- assign Output_1_Hot_Encoded_Opcode[23] = Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & Input_Opcode[1] & Input_Opcode[0];
-
- //assign Single_Cycle = (Output_1_Hot_Encoded_Opcode[0] | Output_1_Hot_Encoded_Opcode[1] | Output_1_Hot_Encoded_Opcode[2] | Output_1_Hot_Encoded_Opcode[5] | Output_1_Hot_Encoded_Opcode[6] | Output_1_Hot_Encoded_Opcode[7] | Output_1_Hot_Encoded_Opcode[8] | Output_1_Hot_Encoded_Opcode[9] | Output_1_Hot_Encoded_Opcode[10] | Output_1_Hot_Encoded_Opcode[11] | Output_1_Hot_Encoded_Opcode[14] | Output_1_Hot_Encoded_Opcode[15] | Output_1_Hot_Encoded_Opcode[18] | Output_1_Hot_Encoded_Opcode[19] | Output_1_Hot_Encoded_Opcode[20] | Output_1_Hot_Encoded_Opcode[21] | Output_1_Hot_Encoded_Opcode[22] | Output_1_Hot_Encoded_Opcode[23]);
- assign Multi_Cycle = (Output_1_Hot_Encoded_Opcode[3] | Output_1_Hot_Encoded_Opcode[4] | Output_1_Hot_Encoded_Opcode[12] | Output_1_Hot_Encoded_Opcode[13] | Output_1_Hot_Encoded_Opcode[16] | Output_1_Hot_Encoded_Opcode[17]);
- */
+
//assign Multi_Cycle = 1'b0;
assign Memory_Activation = (((~Next_State[1]) & (Next_State[0])) & (Active_Process));
assign Next_State[0] = (((~State[0]) & (State[1] | Active_Process)) | ((State[1] & State[0]) & ((~Activation_Signal) | (Activation_Signal & (~Multi_Cycle)))));
diff --git a/verilog/rtl/FPU/FPU_FSM_TOP.v b/verilog/rtl/FPU/FPU_FSM_TOP.v
index 0e28e4f..0fc1ac3 100644
--- a/verilog/rtl/FPU/FPU_FSM_TOP.v
+++ b/verilog/rtl/FPU/FPU_FSM_TOP.v
@@ -49,7 +49,7 @@
`include "LZD_comb.v"
*/
-module FPU_FSM_TOP(vccd1,vssd1,r_Rx_Serial,clk,rst_l,FPU_hp_result);
+module FPU_FSM_TOP(vccd1,vssd1,r_Rx_Serial,clk,rst_l,FPU_sp_result);
`ifdef USE_POWER_PINS
inout vccd1; // User area 1 1.8V supply
@@ -62,7 +62,7 @@
// FPU FSM
input clk,rst_l;
- output [15:0] FPU_hp_result;
+ output [31:0] FPU_sp_result;
// FPU FSM
wire o_Rx_DV;
@@ -88,11 +88,11 @@
wire [3:0]float_control;
wire valid_execution;
wire illegal_config;
- wire [15:0] fs1_data,fs2_data,fs3_data;
+ wire [31:0] fs1_data,fs2_data,fs3_data;
wire [2:0] fpu_pre,fpu_rounding;
wire [23:0] sfpu_op;
wire fpu_active,fpu_complete,fpu_complete_rd;
- wire [15:0]fpu_result_1;
+ wire [31:0]fpu_result_1;
wire dec_i0_rs1_en_d,dec_i0_rs2_en_d;
wire [4:0]S_flag;
wire IV_exception;
@@ -101,7 +101,7 @@
- assign FPU_hp_result = (rst_l == 1'b0) ? 16'h0000 : (fpu_complete_rd & Active_Process) ? fpu_result_rd_w[15:0] : (fpu_complete & ~fpu_complete_rd & Active_Process) ? fpu_result_1 : 16'h0000;
+ assign FPU_sp_result = (rst_l == 1'b0) ? 32'h00000000 : (fpu_complete_rd & Active_Process) ? fpu_result_rd_w[31:0] : (fpu_complete & ~fpu_complete_rd & Active_Process) ? fpu_result_1 : 32'h00000000;
FPU_FSM FSM(
.clk(clk),
diff --git a/verilog/rtl/FPU/FPU_Top_Single_Cycle.v b/verilog/rtl/FPU/FPU_Top_Single_Cycle.v
index 79cf168..8a4a61b 100644
--- a/verilog/rtl/FPU/FPU_Top_Single_Cycle.v
+++ b/verilog/rtl/FPU/FPU_Top_Single_Cycle.v
@@ -15,11 +15,11 @@
module FPU_Top (Operand_A,Operand_B,Operand_C, clk,rst_l, frm, sfpu_op,vfpu_op,fpu_sel,FPU_resultant, S_Flags, Exception_flag, interupt_Pin,FPU_Result_rd,Operand_Int);
-parameter std= 15;
-parameter man = 9;
-parameter exp = 4;
-parameter Bias = 15 /*8'b01111111*/;
-parameter lzd = 3;
+parameter std= 31;
+parameter man = 22;
+parameter exp = 7;
+parameter Bias = 127 /*8'b01111111*/;
+parameter lzd = 4;
//inputs
diff --git a/verilog/rtl/FPU/FPU_decode.v b/verilog/rtl/FPU/FPU_decode.v
index ca3d2f5..b340c96 100644
--- a/verilog/rtl/FPU/FPU_decode.v
+++ b/verilog/rtl/FPU/FPU_decode.v
@@ -1,11 +1,11 @@
-module FPU_decode #(parameter FPLEN = 16)
+module FPU_decode #(parameter FPLEN = 32)
(
input clk,
input rst_l,
input [31:0] instr,
input fpu_active,
input fpu_complete,
- input [FPLEN-1:0]fpu_result_1,
+ input [FPLEN-1:0] fpu_result_1,
output [2:0] scalar_control,
output [4:0] rs1_address,
output [4:0] rs2_address,
@@ -76,13 +76,13 @@
assign illegal_instr = (rst_l == 1'b0) ? 1'b0 : ((fpu_active) & (control_signals[51] == 1'b0) & (~control_signals_r[51])) ? 1'b1 : 1'b0;
- // For half precision
- assign valid_execution = (rst_l == 1'b0) ? 1'b0 : (illegal_instr) ? 1'b0 : (fpu_active & control_signals[92] & control_signals_r[92] & ~control_signals[91] & ~control_signals_r[91]) ? 1'b0 : (fpu_active & (control_signals[91] | control_signals_r[91])) ? 1'b1 : 1'b0;
+ // For Single precision
+ assign valid_execution = (rst_l == 1'b0) ? 1'b0 : (illegal_instr) ? 1'b0 : (fpu_active & control_signals[92] & control_signals_r[92] & ~control_signals[89] & ~control_signals_r[89]) ? 1'b0 : (fpu_active & (control_signals[89] | control_signals_r[89])) ? 1'b1 : 1'b0;
assign scalar_control = (rst_l == 1'b0) ? 3'b00 : control_signals[2:0]; // Contain the active signals for rs1, rs2, rd
- // for half precision
- assign illegal_config = (rst_l == 1'b0) ? 1'b0 : (fpu_active & (control_signals[89] | control_signals[90])) ? 1'b1 : 1'b0;
+ // for Single precision
+ assign illegal_config = (rst_l == 1'b0) ? 1'b0 : (fpu_active & (control_signals[91] | control_signals[90])) ? 1'b1 : 1'b0;
// Scalar Register address
assign rs1_address = (rst_l == 1'b0) ? 5'h00 : (valid_execution | control_signals[10]) ? instr[19:15] : 5'h00;
diff --git a/verilog/rtl/FPU/FPU_exu.v b/verilog/rtl/FPU/FPU_exu.v
index eaa4786..460216a 100644
--- a/verilog/rtl/FPU/FPU_exu.v
+++ b/verilog/rtl/FPU/FPU_exu.v
@@ -1,4 +1,4 @@
-module FPU_exu #(parameter FPLEN = 16) (
+module FPU_exu #(parameter FPLEN = 32) (
input clk,
input rst_l,
input scan_mode,
@@ -32,7 +32,6 @@
wire [FPLEN-1:0] fs3_d;
//wire [FPLEN-1:0] fpu_result_exu;
wire [FPLEN-1:0] fpu_result_top;
-wire [FPLEN-1:0] fpu_result_rx;
wire [4:0] fpu_flags;
wire [31:0]FPU_Result_rd,Operand_Int;
@@ -75,12 +74,12 @@
end
// FPU operands
- assign fs1_d[15:0] = (rst_l == 1'b0) ? {FPLEN{1'b0}} : (({FPLEN{valid_execution & dec_i0_rs1_en_d & ~float_control[0]}} & gpr_i0_rs1_d[31:0] ) |
+ assign fs1_d[31:0] = (rst_l == 1'b0) ? {FPLEN{1'b0}} : (({FPLEN{valid_execution & dec_i0_rs1_en_d & ~float_control[0]}} & gpr_i0_rs1_d[31:0] ) |
({FPLEN{valid_execution & ~dec_i0_rs1_en_d & float_control[0] }} & fs1_data ));
assign Operand_Int = (rst_l == 1'b0) ? 32'h00000000 : (({32{valid_execution & dec_i0_rs1_en_d & ~float_control[0]}} & gpr_i0_rs1_d[31:0] )) ;
- assign fs2_d[15:0] = (rst_l == 1'b0) ? {FPLEN{1'b0}} : (({FPLEN{valid_execution & float_control[1] }} & fs2_data ));
+ assign fs2_d[31:0] = (rst_l == 1'b0) ? {FPLEN{1'b0}} : (({FPLEN{valid_execution & float_control[1] }} & fs2_data ));
- assign fs3_d[15:0] = (rst_l == 1'b0) ? {FPLEN{1'b0}} : (({FPLEN{valid_execution & float_control[2] }} & fs3_data ));
+ assign fs3_d[31:0] = (rst_l == 1'b0) ? {FPLEN{1'b0}} : (({FPLEN{valid_execution & float_control[2] }} & fs3_data ));
// FPU Top Module
diff --git a/verilog/rtl/FPU/FPU_fpr_ctl.v b/verilog/rtl/FPU/FPU_fpr_ctl.v
index fd0ea3f..1a2f7ac 100644
--- a/verilog/rtl/FPU/FPU_fpr_ctl.v
+++ b/verilog/rtl/FPU/FPU_fpr_ctl.v
@@ -15,7 +15,7 @@
module FPU_fpr_ctl
#(
- parameter FPLEN = 16
+ parameter FPLEN = 32
) (
input rden0,
@@ -51,7 +51,7 @@
genvar j;
generate
for (j=0; j<32; j=j+1)
- rvdffe #(16) fprff (.*, .en(fpr_wr_en[j]), .din(fpr_in[j][FPLEN-1:0]), .dout(fpr_out[j][FPLEN-1:0]));
+ rvdffe #(32) fprff (.*, .en(fpr_wr_en[j]), .din(fpr_in[j][FPLEN-1:0]), .dout(fpr_out[j][FPLEN-1:0]));
endgenerate
diff --git a/verilog/rtl/FPU/Main_Decode.v b/verilog/rtl/FPU/Main_Decode.v
index 99956ec..3521178 100644
--- a/verilog/rtl/FPU/Main_Decode.v
+++ b/verilog/rtl/FPU/Main_Decode.v
@@ -4,10 +4,10 @@
input clk,rst_l,Activation_Signal,fpu_active,fpu_complete,fpu_complete_rd;
input [4:0]S_flag;
input [31:0]Instruction,result,fpu_result_rd_w;
- input [15:0]fpu_result_1;
+ input [31:0]fpu_result_1;
output Flag_ADDI,Flag_LI,Flag_Reset,Flag_CSR,CSR_Write,valid_execution,illegal_config,halt_req,dec_i0_rs1_en_d,dec_i0_rs2_en_d;
output [31:0]RS1_d,RS2_d;
- output [15:0]fs1_data,fs2_data,fs3_data;
+ output [31:0]fs1_data,fs2_data,fs3_data;
output reg Flag_CSR_r;
output [23:0]sfpu_op;
output [2:0]fpu_pre,fpu_rounding,fpu_sel;
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index ad7cc28..73a8fc0 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -71,7 +71,7 @@
wire clk;
wire rst;
wire rx_i;
- wire [15:0] FPU_hp_result;
+ wire [31:0] FPU_sp_result;
wire [`MPRJ_IO_PADS-1:0] io_in;
wire [`MPRJ_IO_PADS-1:0] io_out;
@@ -79,9 +79,11 @@
// IO for input mode set 1 and for output mode set 0
+ assign io_oeb[4] = 1'b0;
assign io_oeb[5] = 1'b1;
- assign io_oeb[23:8] = 16'h0000;
- assign io_out[23:8] = FPU_hp_result;
+ assign io_oeb[36:6] = 31'h00000000;
+ assign io_out[4] = FPU_sp_result[31];
+ assign io_out[36:6] = FPU_sp_result[30:0];
// Uart Pin
assign rx_i = (~la_oenb[1]) ? la_data_in[1] : io_in[5];
@@ -89,10 +91,10 @@
// IRQ
assign irq = 3'b000; // Unused
- // Ouptut at LA bits [31:16]
- assign la_data_out[15:0] = 16'h0000;
- assign la_data_out[31:16] = (&la_oenb[31:16]) ? FPU_hp_result : 16'h0000;
- assign la_data_out[127:32] = {(127-BITS){1'b0}};
+ // Ouptut at LA bits [63:32]
+ assign la_data_out[31:0] = 32'h00000000;
+ assign la_data_out[63:32] = (&la_oenb[63:32]) ? FPU_sp_result : 32'h00000000;
+ assign la_data_out[127:64] = {(127-64){1'b0}};
// Assuming LA probes [65:64] are for controlling the count clk & reset
assign clk = (~la_oenb[64]) ? la_data_in[64] : wb_clk_i;
@@ -100,7 +102,7 @@
// Initiation of TOP Module
- FPU_FSM_TOP FPU_Half_Precision_Top (
+ FPU_FSM_TOP FPU_Single_Precision_Top (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // User area 1 1.8V supply
.vssd1(vssd1), // User area 1 digital ground
@@ -108,7 +110,7 @@
.clk(clk),
.rst_l(rst),
.r_Rx_Serial(rx_i),
- .FPU_hp_result(FPU_hp_result)
+ .FPU_sp_result(FPU_sp_result)
);
endmodule
