Define added
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v index 73a8fc0..8442ee0 100644 --- a/verilog/rtl/user_proj_example.v +++ b/verilog/rtl/user_proj_example.v
@@ -35,6 +35,8 @@ *------------------------------------------------------------- */ +`define MPRJ_IO_PADS 38 + module user_proj_example #( parameter BITS = 32 )(