commit 8b76b134b6fa602f2c93a707b68b8d013d1a843d
author hamzashabbir517 <shabbirhamza517@gmail.com> Sat May 21 12:22:15 2022 +0500
committer hamzashabbir517 <shabbirhamza517@gmail.com> Sat May 21 12:22:15 2022 +0500
tree 9006d96e8796bdcbb2feb32790b1ce5db8a3c4a2
parent cc84a9905fea1ee3eebf291033be5e8493fad17f

Define added

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 73a8fc0..8442ee0 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -35,6 +35,8 @@
  *-------------------------------------------------------------
  */
 
+`define MPRJ_IO_PADS 38
+
 module user_proj_example #(
     parameter BITS = 32
 )(