commit 4ff58d7cae6b867902785304e96170e84627a3db
author hamzashabbir517 <shabbirhamza517@gmail.com> Fri May 27 13:34:23 2022 +0500
committer hamzashabbir517 <shabbirhamza517@gmail.com> Fri May 27 13:34:23 2022 +0500
tree ca3e2df88510eec8b8aa0a2162da79feafed95b9
parent 54b3587f0c4406e97d8fa53e6635a43a900acc2f

Mismatch solved

verilog/rtl/FPU/beh_lib.v

diff --git a/verilog/rtl/FPU/beh_lib.v b/verilog/rtl/FPU/beh_lib.v
index 67b166f..082550d 100644
--- a/verilog/rtl/FPU/beh_lib.v
+++ b/verilog/rtl/FPU/beh_lib.v
@@ -18,7 +18,7 @@
 		end
 		else always @(posedge clk or negedge rst_l)
 			if (rst_l == 0)
-				dout[WIDTH - 1:0] <= {{WIDTH{0}};
+				dout[WIDTH - 1:0] <= {WIDTH{1'b0}};
 			else
 				dout[WIDTH - 1:0] <= din[WIDTH - 1:0];
 	endgenerate