Files Update
diff --git a/verilog/rtl/FPU/FMADD_Add_Post_Normalization.v b/verilog/rtl/FPU/FMADD_Add_Post_Normalization.v index e83f122..5d78cd6 100644 --- a/verilog/rtl/FPU/FMADD_Add_Post_Normalization.v +++ b/verilog/rtl/FPU/FMADD_Add_Post_Normalization.v
@@ -7,6 +7,7 @@ parameter std = 31; parameter man = 22; parameter exp = 7; +parameter lzd = 4; //declaration of putptu ports input [man+man+3:0] Post_Normalization_input_Mantissa; @@ -22,7 +23,7 @@ wire [exp:0] Post_Normaliaation_Bit_Shamt_interim; wire [exp:0] Post_Normaliaation_Bit_Shamt_1; wire [23:0] Post_Normaliaation_Bit_input_LZD; -wire [4:0] Post_Normaliaation_Bit_output_LZD; +wire [lzd:0] Post_Normaliaation_Bit_output_LZD; wire Post_Normaliaation_Bit_exp_LZD_Comp; wire [exp:0] Post_Normaliaation_Bit_Shift_Amount; wire [man+man+3:0] Post_Normalization_Shifter_Output_Sub,Post_Normalization_Shifter_Output_add,Post_Normalization_Shifter_input_add; @@ -33,18 +34,19 @@ //instantition of LZD - FMADD_PN_LZD m2 ( + FMADD_PN_LZD Lzd_PN_AD ( .FMADD_PN_LZD_input_man_48 ( Post_Normaliaation_Bit_input_LZD ), .FMADD_PN_LZD_output_pos ( Post_Normaliaation_Bit_output_LZD) ) ; - + defparam Lzd_PN_AD.man = man; + defparam Lzd_PN_AD.lzd = lzd; //main functionality //subtraction lane assign Post_Normaliaation_Bit_Shamt_interim = Post_Normalization_input_exponent - 1'b1; assign Post_Normaliaation_Bit_Shamt_1 = (Post_Normalization_input_Eff_sub) ? Post_Normaliaation_Bit_Shamt_interim : 8'h00; -assign Post_Normaliaation_Bit_input_LZD = (Post_Normalization_input_Eff_sub) ? Post_Normalization_input_Mantissa[man+man+3:man+2] : {(man+2){1'b0}}; +assign Post_Normaliaation_Bit_input_LZD = (Post_Normalization_input_Eff_sub) ? { { 24-(man+2){1'b0} },Post_Normalization_input_Mantissa[man+man+3:man+2]} : {man+2{1'b0}}; assign Post_Normaliaation_Bit_exp_LZD_Comp = Post_Normalization_input_exponent > Post_Normaliaation_Bit_output_LZD; assign Post_Normaliaation_Bit_Shift_Amount = (Post_Normaliaation_Bit_exp_LZD_Comp) ? { {exp-4 {1'b0}},Post_Normaliaation_Bit_output_LZD} : Post_Normaliaation_Bit_Shamt_1 ; assign Post_Normalization_Shifter_Output_Sub = Post_Normalization_input_Mantissa << Post_Normaliaation_Bit_Shift_Amount; @@ -53,7 +55,7 @@ //additio lanse assign Post_Normaliaation_EFF_add_interim_Exponent = {1'b0,Post_Normalization_input_exponent} + Post_Normalization_input_Carry ; -assign Post_Normalization_Shifter_input_add = (Post_Normalization_input_Eff_add) ? Post_Normalization_input_Mantissa : {(man+man+4){1'b0}}; +assign Post_Normalization_Shifter_input_add = (Post_Normalization_input_Eff_add) ? Post_Normalization_input_Mantissa : 48'h000000000000; assign Post_Normalization_Shifter_Output_add = (Post_Normalization_input_Carry) ? { Post_Normalization_input_Carry,Post_Normalization_Shifter_input_add[man+man+3:1] } : Post_Normalization_Shifter_input_add[man+man+3:0] ; //Output Selestion and Round bits extarcion
diff --git a/verilog/rtl/FPU/FMADD_Exponent_Matching.v b/verilog/rtl/FPU/FMADD_Exponent_Matching.v index bc8c78c..57fe640 100644 --- a/verilog/rtl/FPU/FMADD_Exponent_Matching.v +++ b/verilog/rtl/FPU/FMADD_Exponent_Matching.v
@@ -1,6 +1,6 @@ //module is responsible for matching the exponents for addition -module FMADD_Exponent_Matching (Exponent_Matching_input_Sign_A,Exponent_Matching_input_Sign_B,Exponent_Matching_input_Exp_A,Exponent_Matching_input_Exp_B,Exponent_Matching_input_Mantissa_A,Exponent_Matching_input_Mantissa_B,Exponent_Matching_input_opcode,Exponent_Matching_output_Mantissa_A,Exponent_Matching_output_Mantissa_B,Exponent_Matching_output_Exp,Exponent_Matching_output_Guard,Exponent_Matching_output_Round,Exponent_Matching_output_Sticky,Exponent_Matching_output_Sign,Exponent_Matching_output_Eff_Sub,Exponent_Matching_output_Eff_add); +module FMADD_Exponent_Matching (Exponent_Matching_input_Sign_A,Exponent_Matching_input_Sign_B,Exponent_Matching_input_Exp_A,Exponent_Matching_input_Exp_B,Exponent_Matching_input_Mantissa_A,Exponent_Matching_input_Mantissa_B,Exponent_Matching_input_opcode,Exponent_Matching_output_Mantissa_A,Exponent_Matching_output_Mantissa_B,Exponent_Matching_output_Exp,Exponent_Matching_output_Guard,Exponent_Matching_output_Round,Exponent_Matching_output_Sticky,Exponent_Matching_output_Sign,Exponent_Matching_output_Eff_Sub,Exponent_Matching_output_Eff_add,Exponent_Matching_output_Exp_Diff_Check); //defination of prameters parameter std =31; @@ -17,11 +17,10 @@ input [1:0] Exponent_Matching_input_opcode; //declaration of putptu ports -output Exponent_Matching_output_Sign; +output Exponent_Matching_output_Sign , Exponent_Matching_output_Exp_Diff_Check; output [man+man+3:0] Exponent_Matching_output_Mantissa_A,Exponent_Matching_output_Mantissa_B; output [exp:0] Exponent_Matching_output_Exp; output Exponent_Matching_output_Guard,Exponent_Matching_output_Round,Exponent_Matching_output_Sticky,Exponent_Matching_output_Eff_Sub,Exponent_Matching_output_Eff_add; - //main funtionality //declaration for wires @@ -65,10 +64,14 @@ //decision of xponent assign Exponent_Matching_output_Exp = Exponent_Matching_Exp_Sub_input_1; +//Decision for the exponent difference on the basis of which this is t be decided that either 1 or 0 will be added in the compliment_B and recompliment of the final answer (Please refer to the documentation fo detailed analyssis) +assign Exponent_Matching_output_Exp_Diff_Check = Exponent_Matching_Shif_Amount >= 8'b00110000 ; + + //decision fo rrounding bits assign Exponent_Matching_output_Guard = Exponent_Matching_Shifter_output[man+man+3] ; assign Exponent_Matching_output_Round = Exponent_Matching_Shifter_output[man+man+2] ; -assign Exponent_Matching_output_Sticky = (Exponent_Matching_Shif_Amount >= 96) ? 1'b1: (|Exponent_Matching_Shifter_output [man+man+1:0]) ; +assign Exponent_Matching_output_Sticky = ( &(~Exponent_Matching_Shifter_output) ) ? 1'b1: (|Exponent_Matching_Shifter_output [man+man+1:0]) ; endmodule \ No newline at end of file
diff --git a/verilog/rtl/FPU/FMADD_LZD_L4.v b/verilog/rtl/FPU/FMADD_LZD_L4.v index 816bd8e..a0815fa 100644 --- a/verilog/rtl/FPU/FMADD_LZD_L4.v +++ b/verilog/rtl/FPU/FMADD_LZD_L4.v
@@ -25,7 +25,6 @@ L4_wire_output_val & L4_wire_output_pos[1], L4_wire_output_val & L4_wire_output_pos[0]}; -//5'b1100 == 2;s compliment of 8, 8 is subtracted from the final result since the LZD is of 32 bit and actual data is of 24 bit. -assign L4_output_pos = L4_wire_output_pos_32 + 5'b11000; +assign L4_output_pos = L4_wire_output_pos_32 ; -endmodule +endmodule \ No newline at end of file
diff --git a/verilog/rtl/FPU/FMADD_LZD_main.v b/verilog/rtl/FPU/FMADD_LZD_main.v index 8a52ce0..1b22a0c 100644 --- a/verilog/rtl/FPU/FMADD_LZD_main.v +++ b/verilog/rtl/FPU/FMADD_LZD_main.v
@@ -6,12 +6,15 @@ module FMADD_PN_LZD (FMADD_PN_LZD_input_man_48, FMADD_PN_LZD_output_pos); - -parameter layer = 1; +parameter lzd = 4; +parameter man = 22; input [23 : 0]FMADD_PN_LZD_input_man_48; -output [4: 0]FMADD_PN_LZD_output_pos; +output [lzd : 0]FMADD_PN_LZD_output_pos; + +wire [4 : 0]FMADD_PN_LZD_output_pos_interim_1; +wire [5 : 0]FMADD_PN_LZD_output_pos_interim_2; wire [23 : 0] LZD_wire_output_L0; wire [17 : 0] LZD_wire_output_L1; @@ -31,6 +34,14 @@ FMADD_LZD_layer_3 L3 (.L3_input_pos_val(LZD_wire_output_L2), .L3_output_pos_val(LZD_wire_output_L3)); //Layer 4 -FMADD_LZD_layer_4 L4 (.L4_input_pos_val(LZD_wire_output_L3), .L4_output_pos(FMADD_PN_LZD_output_pos)); +FMADD_LZD_layer_4 L4 (.L4_input_pos_val(LZD_wire_output_L3), .L4_output_pos(FMADD_PN_LZD_output_pos_interim_1)); -endmodule +assign FMADD_PN_LZD_output_pos_interim_2 = +(man == 22) ? (({1'b0,FMADD_PN_LZD_output_pos_interim_1}) + 6'b011000) : //-8 for SP +(man == 9 ) ? (({1'b0,FMADD_PN_LZD_output_pos_interim_1}) + 6'b101011) : //-21 for IEEE16 + (({1'b0,FMADD_PN_LZD_output_pos_interim_1}) + 6'b101000) ; //-24 for Bf16 + + +assign FMADD_PN_LZD_output_pos = FMADD_PN_LZD_output_pos_interim_2[lzd : 0]; + +endmodule \ No newline at end of file
diff --git a/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v b/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v index 781d5c2..e79a7ba 100644 --- a/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v +++ b/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v
@@ -54,11 +54,12 @@ `include "FMADD_add_rounding_Block.v" */ + module FPU_FMADD_SUBB_Top (FMADD_SUBB_input_IEEE_A, FMADD_SUBB_input_IEEE_B, FMADD_SUBB_input_IEEE_C, FMADD_SUBB_input_opcode,rst_l,FMADD_SUBB_input_Frm,FMADD_SUBB_output_IEEE_FMADD, FMADD_SUBB_output_S_Flags_FMADD, FMADD_SUBB_output_IEEE_FMUL, FMADD_SUBB_output_S_Flags_FMUL ); parameter std =31; parameter man =22; -parameter exp = 7; +parameter exp =7; parameter bias = 127; parameter lzd = 4; @@ -172,20 +173,33 @@ //instantiation of LZD module wire [23:0] input_LZD; -wire [lzd : 0] output_interim_LZD, output_interim_1_LZD; +//wire [4:0] output_LZD; +wire [lzd : 0] output_LZD; -assign input_LZD = (output_interim_A_sub_norm) ? output_interim_M_G_A[man+1:0] : output_interim_M_G_B[man+1:0] ; + +wire [23 : 0] input_interim_A_LZD, input_interim_B_LZD ; + +assign input_interim_A_LZD = +(man == 22) ? (output_interim_M_G_A[man+1:0]) : //-8 for SP +(man == 9 ) ? ({ ({(24-(man+2)){1'b0}}) ,(output_interim_M_G_A[man+1:0])}) : //-21 for IEEE16, concatinate 24-(man+2) zero to make the mantissa size == 24 + ({ ({(24-(man+2)){1'b0}}) ,(output_interim_M_G_A[man+1:0])}) ; //-24 for Bf16, concatinate 24-(man+2) zero to make the mantissa size == 24 +assign input_interim_B_LZD = +(man == 22) ? (output_interim_M_G_B[man+1:0]) : //-8 for SP +(man == 9 ) ? ({ ({(24-(man+2)){1'b0}}) ,(output_interim_M_G_B[man+1:0])}) : //-21 for IEEE16, concatinate 24-(man+2) zero to make the mantissa size == 24 + ({ ({(24-(man+2)){1'b0}}) ,(output_interim_M_G_B[man+1:0])}) ; //-24 for Bf16, concatinate 24-(man+2) zero to make the mantissa size == 24 + +assign input_LZD = (output_interim_A_sub_norm) ? input_interim_A_LZD : input_interim_B_LZD ; + + +//assign input_LZD = (output_interim_A_sub_norm) ? output_interim_M_G_A[man+1:0] : output_interim_M_G_B[man+1:0] ; FMADD_PN_LZD Leading_Zero_detection ( .FMADD_PN_LZD_input_man_48(input_LZD), - .FMADD_PN_LZD_output_pos(output_interim_LZD) -); - -//5'b1100 == 2;s compliment of 8, 8 is subtracted from the final result since the LZD is of 32 bit and actual data is of 24 bit. -//assign to_add_in_lzd_mul = (output_interim_LZD + 5'b11000); -assign output_interim_1_LZD = output_interim_LZD ; - + .FMADD_PN_LZD_output_pos(output_LZD) + ); +defparam Leading_Zero_detection.man = man; +defparam Leading_Zero_detection.lzd = lzd; //post normalaization Module wire [1+exp+2*(man+2):0] output_interim_post_normalization_IEEE; @@ -195,7 +209,7 @@ . FMADD_PN_MUL_input_sign (output_interim_exponent_addition_sign), . FMADD_PN_MUL_input_multiplied_man (output_interim_mantissa_multiplication), . FMADD_PN_MUL_input_exp_DB (output_interim_exponent_addition), - . FMADD_PN_MUL_input_lzd (output_interim_1_LZD), + . FMADD_PN_MUL_input_lzd (output_LZD), . FMADD_PN_MUL_input_A_sub (output_interim_A_sub_norm), . FMADD_PN_MUL_input_B_sub (output_interim_B_sub_norm), . FMADD_PN_MUL_input_A_pos (output_interim_A_pos_exp), @@ -251,7 +265,7 @@ wire output_interim_Exponent_Mathcing_Guard; wire output_interim_Exponent_Mathcing_Round; wire output_interim_Exponent_Mathcing_Sticky; - +wire output_interim_Exponent_Mathcing_Exp_Diff_Check; FMADD_Exponent_Matching Exponent_Matching ( @@ -270,7 +284,8 @@ .Exponent_Matching_output_Round( output_interim_Exponent_Mathcing_Round), .Exponent_Matching_output_Sticky( output_interim_Exponent_Mathcing_Sticky), .Exponent_Matching_output_Eff_Sub( output_interim_Exponent_Mathcing_Eff_sub), - .Exponent_Matching_output_Eff_add( output_interim_Exponent_Mathcing_Eff_add) + .Exponent_Matching_output_Eff_add( output_interim_Exponent_Mathcing_Eff_add), + .Exponent_Matching_output_Exp_Diff_Check (output_interim_Exponent_Mathcing_Exp_Diff_Check) ); defparam Exponent_Matching.std = std; defparam Exponent_Matching.exp = exp; @@ -285,7 +300,8 @@ .Mantissa_Addition_input_Mantissa_B( output_interim_Exponent_Mathcing_Mantissa_B), .Mantissa_Addition_input_Eff_Sub( output_interim_Exponent_Mathcing_Eff_sub), .Mantissa_Addition_output_Mantissa(output_interim_Mantissa_Addition_Mantissa ), - .Mantissa_Addition_output_Carry(output_interim_Mantissa_Addition_Carry) + .Mantissa_Addition_output_Carry(output_interim_Mantissa_Addition_Carry), + .Mantissa_Addition_input_Exp_Diff_Check (output_interim_Exponent_Mathcing_Exp_Diff_Check) ); defparam Mantissa_Addition.std = std; defparam Mantissa_Addition.exp = exp;
diff --git a/verilog/rtl/FPU/FMADD_mantissa_addition.v b/verilog/rtl/FPU/FMADD_mantissa_addition.v index 6df4a66..d50180d 100644 --- a/verilog/rtl/FPU/FMADD_mantissa_addition.v +++ b/verilog/rtl/FPU/FMADD_mantissa_addition.v
@@ -1,7 +1,7 @@ //mantissa addition module -module FMADD_Mantissa_Addition( Mantissa_Addition_input_Mantissa_A,Mantissa_Addition_input_Mantissa_B,Mantissa_Addition_input_Eff_Sub,Mantissa_Addition_output_Mantissa, Mantissa_Addition_output_Carry ); +module FMADD_Mantissa_Addition( Mantissa_Addition_input_Mantissa_A,Mantissa_Addition_input_Mantissa_B,Mantissa_Addition_input_Eff_Sub,Mantissa_Addition_output_Mantissa, Mantissa_Addition_output_Carry,Mantissa_Addition_input_Exp_Diff_Check ); //declaration of paramters parameter std =31; @@ -11,6 +11,7 @@ //declaration of input ports input [man+man+3:0] Mantissa_Addition_input_Mantissa_A,Mantissa_Addition_input_Mantissa_B; input Mantissa_Addition_input_Eff_Sub; +input Mantissa_Addition_input_Exp_Diff_Check; /* opcode[0]= fadd; @@ -21,19 +22,19 @@ wire [man+man+3:0] interim_mantissa_B,interim_mantissa_B_adder; wire Mantissa_Addition_interim_Carry; wire [man+man+3:0] Mantissa_Addition_Compliment_B; -wire Mantissa_Addition_interim_Compliment_Carry; + //declartion of output piorts output Mantissa_Addition_output_Carry; output [man+man+3:0] Mantissa_Addition_output_Mantissa; //Main functionality -assign {Mantissa_Addition_interim_Compliment_Carry,Mantissa_Addition_Compliment_B} = ( {1'b0,(~(Mantissa_Addition_input_Mantissa_B))} + 1'b1); +assign Mantissa_Addition_Compliment_B = ( (~(Mantissa_Addition_input_Mantissa_B)) + (~Mantissa_Addition_input_Exp_Diff_Check) ); assign interim_mantissa_B = (Mantissa_Addition_input_Eff_Sub) ? Mantissa_Addition_Compliment_B : Mantissa_Addition_input_Mantissa_B ; assign {Mantissa_Addition_interim_Carry,interim_mantissa_B_adder} = {1'b0, interim_mantissa_B} + {1'b0,Mantissa_Addition_input_Mantissa_A}; -assign Mantissa_Addition_output_Mantissa = ( (~Mantissa_Addition_interim_Carry) & Mantissa_Addition_input_Eff_Sub & (~Mantissa_Addition_interim_Compliment_Carry) ) ? ( ~(interim_mantissa_B_adder) + 1'b1 ) : interim_mantissa_B_adder; +assign Mantissa_Addition_output_Mantissa = ( (~Mantissa_Addition_interim_Carry) & Mantissa_Addition_input_Eff_Sub ) ? ( ~(interim_mantissa_B_adder) + (~Mantissa_Addition_input_Exp_Diff_Check) ) : interim_mantissa_B_adder; assign Mantissa_Addition_output_Carry = Mantissa_Addition_interim_Carry;
diff --git a/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v b/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v index 812bf9c..cc5705b 100644 --- a/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v +++ b/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v
@@ -13,7 +13,7 @@ output [std : 0] FMADD_ROUND_MUL_output_no; output [2 : 0]FMADD_ROUND_MUL_output_S_Flags; -assign FMADD_ROUND_MUL_output_S_Flags = {FMADD_ROUND_MUL_output_overflow,FMADD_ROUND_MUL_output_underflow,FMADD_ROUND_MUL_output_inexact}; + wire FMADD_ROUND_MUL_output_inexact, FMADD_ROUND_MUL_output_underflow, FMADD_ROUND_MUL_output_overflow; @@ -25,6 +25,8 @@ wire [exp : 0] FMADD_ROUND_MUL_wire_rounded_exp; wire [man : 0] FMADD_ROUND_MUL_wire_final_man; +assign FMADD_ROUND_MUL_output_S_Flags = {FMADD_ROUND_MUL_output_overflow,FMADD_ROUND_MUL_output_underflow,FMADD_ROUND_MUL_output_inexact}; + assign FMADD_ROUND_MUL_wire_guard = FMADD_ROUND_MUL_input_no[man+1]; assign FMADD_ROUND_MUL_wire_round = FMADD_ROUND_MUL_input_no[man]; assign FMADD_ROUND_MUL_wire_sticky = |FMADD_ROUND_MUL_input_no[man-1 : 0]; @@ -53,4 +55,4 @@ assign FMADD_ROUND_MUL_output_no = {FMADD_ROUND_MUL_input_no[man+man+exp+5], (FMADD_ROUND_MUL_wire_rounded_exp), FMADD_ROUND_MUL_wire_rounded_man[man:0]}; -endmodule \ No newline at end of file +endmodule