| /root/floating_point_unit_bfloat16/Makefile |
| /root/floating_point_unit_bfloat16/docs/Makefile |
| /root/floating_point_unit_bfloat16/docs/environment.yml |
| /root/floating_point_unit_bfloat16/docs/source/conf.py |
| /root/floating_point_unit_bfloat16/docs/source/index.rst |
| /root/floating_point_unit_bfloat16/docs/source/quickstart.rst |
| /root/floating_point_unit_bfloat16/openlane/user_proj_example/config.json |
| /root/floating_point_unit_bfloat16/openlane/user_proj_example/config.tcl |
| /root/floating_point_unit_bfloat16/openlane/user_project_wrapper/config.json |
| /root/floating_point_unit_bfloat16/openlane/user_project_wrapper/config.tcl |
| /root/floating_point_unit_bfloat16/verilog/dv/Makefile |
| /root/floating_point_unit_bfloat16/verilog/dv/FPU_Bfloat/FPU_Bfloat.c |
| /root/floating_point_unit_bfloat16/verilog/dv/FPU_Bfloat/FPU_Bfloat_tb.v |
| /root/floating_point_unit_bfloat16/verilog/dv/FPU_Bfloat/Makefile |
| /root/floating_point_unit_bfloat16/verilog/dv/FPU_Bfloat/tb_prog.v |
| /root/floating_point_unit_bfloat16/verilog/dv/io_ports/Makefile |
| /root/floating_point_unit_bfloat16/verilog/dv/io_ports/io_ports.c |
| /root/floating_point_unit_bfloat16/verilog/dv/io_ports/io_ports_tb.v |
| /root/floating_point_unit_bfloat16/verilog/dv/la_test1/Makefile |
| /root/floating_point_unit_bfloat16/verilog/dv/la_test1/la_test1.c |
| /root/floating_point_unit_bfloat16/verilog/dv/la_test1/la_test1_tb.v |
| /root/floating_point_unit_bfloat16/verilog/dv/la_test2/Makefile |
| /root/floating_point_unit_bfloat16/verilog/dv/la_test2/la_test2.c |
| /root/floating_point_unit_bfloat16/verilog/dv/la_test2/la_test2_tb.v |
| /root/floating_point_unit_bfloat16/verilog/dv/mprj_stimulus/Makefile |
| /root/floating_point_unit_bfloat16/verilog/dv/mprj_stimulus/mprj_stimulus.c |
| /root/floating_point_unit_bfloat16/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v |
| /root/floating_point_unit_bfloat16/verilog/dv/wb_port/Makefile |
| /root/floating_point_unit_bfloat16/verilog/dv/wb_port/wb_port.c |
| /root/floating_point_unit_bfloat16/verilog/dv/wb_port/wb_port_tb.v |
| /root/floating_point_unit_bfloat16/verilog/includes/includes.gl+sdf.caravel_user_project |
| /root/floating_point_unit_bfloat16/verilog/includes/includes.gl.caravel_user_project |
| /root/floating_point_unit_bfloat16/verilog/includes/includes.rtl.caravel_user_project |
| /root/floating_point_unit_bfloat16/verilog/rtl/uprj_netlists.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/user_proj_example.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/user_project_wrapper.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/Dec_gpr_ctl.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/Execution.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FMADD_Add_Post_Normalization.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FMADD_Exponent_Matching.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FMADD_LZD_L0.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FMADD_LZD_L1.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FMADD_LZD_L2.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FMADD_LZD_L3.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FMADD_LZD_L4.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FMADD_LZD_main.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FMADD_exponent_addition.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FMADD_extender.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FMADD_mantissa_addition.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FMADD_mantissa_generator.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FMADD_mantissa_multiplication.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FMADD_rounding_block_Addition.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FPU_CSR.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FPU_F2I.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FPU_FSM_Control_Decode.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FPU_FSM_TOP.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FPU_Fclass.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FPU_Input_Validation.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FPU_Top_Single_Cycle.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FPU_comparison.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FPU_dec_ctl.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FPU_decode.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FPU_exu.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FPU_fpr_ctl.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FPU_move.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/FPU_sign_injection.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/I2F_main.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/LZD_comb.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/LZD_layer0.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/LZD_layer1.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/LZD_layer2.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/LZD_layer3.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/LZD_layer4.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/LZD_main.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/LZD_mux.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/Main_Decode.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/Sky130_SRAM_1kbyte_Memory.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/beh_lib.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/iccm_controller.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/inst_checker.v |
| /root/floating_point_unit_bfloat16/verilog/rtl/FPU/uart_rx_prog.v |