Updated the user_proj_example
diff --git a/verilog/dv/FPU_Half/FPU_Half.c b/verilog/dv/FPU_Half/FPU_Half.c
index 5e5befc..7a575db 100644
--- a/verilog/dv/FPU_Half/FPU_Half.c
+++ b/verilog/dv/FPU_Half/FPU_Half.c
@@ -65,7 +65,7 @@
// Configure LA probes as inputs to the cpu put zero
// Configure LA probes as outputs from the cpu put one
-
+ reg_la0_oenb = reg_la0_iena = 0x00000000; // configuring as output
reg_la2_oenb = reg_la2_iena = 0x00000002; // 65 bit as input to user proj and output from cpu for reset
reg_la2_data = 0x00000000; // reset
reg_la2_data = 0x00000002;
diff --git a/verilog/dv/FPU_Half/FPU_Half_tb.v b/verilog/dv/FPU_Half/FPU_Half_tb.v
index c8b94f8..6dd3d8b 100644
--- a/verilog/dv/FPU_Half/FPU_Half_tb.v
+++ b/verilog/dv/FPU_Half/FPU_Half_tb.v
@@ -15,7 +15,7 @@
`default_nettype wire
-`timescale 1 ns / 1 ps
+//`timescale 1 ns / 1 ps
//`include "uprj_netlists.v"
//`include "caravel_netlists.v"
@@ -63,17 +63,19 @@
initial begin
wait(mprj_ready == 1'b1)
// Observe Output pins [23:8] for multliplication_table
- wait(mprj_io_0 == 16'd5);
- wait(mprj_io_0 == 16'd10);
- wait(mprj_io_0 == 16'd15);
- wait(mprj_io_0 == 16'd20);
- wait(mprj_io_0 == 16'd25);
- wait(mprj_io_0 == 16'd30);
+ wait(mprj_io_0 == 16'h4000);
+ wait(mprj_io_0 == 16'h4020);
+ wait(mprj_io_0 == 16'h4060);
+ wait(mprj_io_0 == 16'h4090);
+ wait(mprj_io_0 == 16'h40b0);
+ wait(mprj_io_0 == 16'h40d0);
+ wait(mprj_io_0 == 16'hC158);
+ wait(mprj_io_0 == 16'hC178);
- $display("MPRJ-IO state = %d", mprj_io[23:8]);
+ $display("MPRJ-IO state = %h", mprj_io[23:8]);
`ifdef GL
- $display("Monitor: Test 1 Mega-Project IO (GL) Passed");
+ $display("Monitor: Test 1 Mega-Project IO (GL) Passed");
`else
$display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
`endif
@@ -105,9 +107,9 @@
power4 <= 1'b1;
end
- //always @(mprj_io) begin
- // #1 $display("MPRJ-IO state = %d, at time = %0t ", mprj_io[23:8], $time);
- //end
+ always @(mprj_io_0) begin
+ #1 $display("MPRJ-IO state = %h, at time = %0t ", mprj_io[23:8], $time);
+ end
wire flash_csb;
wire flash_clk;
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 9224a38..ad7cc28 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -89,13 +89,16 @@
// IRQ
assign irq = 3'b000; // Unused
- // LA
- assign la_data_out = {{127{1'b0}}};
+ // Ouptut at LA bits [31:16]
+ assign la_data_out[15:0] = 16'h0000;
+ assign la_data_out[31:16] = (&la_oenb[31:16]) ? FPU_hp_result : 16'h0000;
+ assign la_data_out[127:32] = {(127-BITS){1'b0}};
// Assuming LA probes [65:64] are for controlling the count clk & reset
assign clk = (~la_oenb[64]) ? la_data_in[64] : wb_clk_i;
assign rst = (~la_oenb[65]) ? la_data_in[65] : ~wb_rst_i;
+
// Initiation of TOP Module
FPU_FSM_TOP FPU_Half_Precision_Top (
`ifdef USE_POWER_PINS
