Finals Files
diff --git a/verilog/rtl/FPU/FMADD_Add_Post_Normalization.v b/verilog/rtl/FPU/FMADD_Add_Post_Normalization.v
index 9b83be6..ad35cd7 100644
--- a/verilog/rtl/FPU/FMADD_Add_Post_Normalization.v
+++ b/verilog/rtl/FPU/FMADD_Add_Post_Normalization.v
@@ -56,7 +56,7 @@
//additio lanse
assign Post_Normaliaation_EFF_add_interim_Exponent = Post_Normalization_input_exponent + Post_Normalization_input_Carry ;
-assign Post_Normalization_Shifter_input_add = (Post_Normalization_input_Eff_add) ? Post_Normalization_input_Mantissa : 48'h000000000000;
+assign Post_Normalization_Shifter_input_add = (Post_Normalization_input_Eff_add) ? Post_Normalization_input_Mantissa : {(man+man+4){1'b0}};
assign Post_Normalization_Shifter_Output_add = (Post_Normalization_input_Carry) ? { Post_Normalization_input_Carry,Post_Normalization_Shifter_input_add[man+man+3:1] } : Post_Normalization_Shifter_input_add[man+man+3:0] ;
//Output Selestion and Round bits extarcion
@@ -66,7 +66,7 @@
assign Post_Normalization_output_Round = Post_Normalization_Mantissa_interim_48[man] ;
assign Post_Normalization_output_Guard = Post_Normalization_Mantissa_interim_48[man+1];
assign Post_Normalization_output_Sticky = ( (|Post_Normalization_Mantissa_interim_48[man-1:0]) | Post_Normalization_input_Guard | Post_Normalization_input_Round | Post_Normalization_input_Sticky);
-assign Post_Normalization_output_exponent = (Post_Normalization_input_Eff_sub) ? {1'b0,Post_Normaliaation_EFF_Sub_interim_Exponent} : Post_Normaliaation_EFF_add_interim_Exponent;
+assign Post_Normalization_output_exponent = (Post_Normalization_input_Eff_sub) ? Post_Normaliaation_EFF_Sub_interim_Exponent : Post_Normaliaation_EFF_add_interim_Exponent;
endmodule
diff --git a/verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v b/verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v
index cc7e802..c2398ab 100644
--- a/verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v
+++ b/verilog/rtl/FPU/FMADD_Mul_Post_Normalization.v
@@ -104,9 +104,9 @@
assign FMADD_PN_LZD_wire_direction_shifts = (FMADD_PN_MUL_wire_op_5 & PM_MUL_wire_sub_or_norm_op5) | FMADD_PN_MUL_wire_op_4 | (FMADD_PN_MUL_input_A_sub & FMADD_PN_MUL_input_B_sub);
//DTRS = Data To Right Shift
-assign FMADD_PN_MUL_wire_DTRS = FMADD_PN_LZD_wire_direction_shifts ? FMADD_PN_MUL_input_multiplied_man : 48'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 ;
+assign FMADD_PN_MUL_wire_DTRS = FMADD_PN_LZD_wire_direction_shifts ? FMADD_PN_MUL_input_multiplied_man : {(man+man+4){1'b0}} ;
//DTLS = Data To Left Shift
-assign FMADD_PN_MUL_wire_DTLS = FMADD_PN_LZD_wire_direction_shifts ? 48'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000 : FMADD_PN_MUL_input_multiplied_man ;
+assign FMADD_PN_MUL_wire_DTLS = FMADD_PN_LZD_wire_direction_shifts ? {(man+man+4){1'b0}} : FMADD_PN_MUL_input_multiplied_man ;
//RS == Right Shifted
assign FMADD_PN_MUL_wire_RS_data = ({1'b0, FMADD_PN_MUL_wire_DTRS}) >> FMADD_PN_MUL_wire_shifts_final;
@@ -150,4 +150,4 @@
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v b/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v
index 8e9a69f..6a89bee 100644
--- a/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v
+++ b/verilog/rtl/FPU/FMADD_Top_Single_Cycle.v
@@ -222,8 +222,8 @@
wire [2+exp+2*(man+2):0] output_interim_post_normalization_IEEE;
//inputs to the FMADD LANE
-assign input_interim_ADD_LANE_A = ( |(FMADD_SUBB_input_opcode[1:0] ) ) ? output_interim_Extender_A : (| FMADD_SUBB_input_opcode[6:3]) ? output_interim_post_normalization_IEEE : 57'h000000000000000 ;
-assign input_interim_ADD_LANE_B = (|(FMADD_SUBB_input_opcode[1:0] ) ) ? output_interim_Extender_B : (| FMADD_SUBB_input_opcode[6:3]) ? output_interim_Extender_B : 57'h000000000000000;
+assign input_interim_ADD_LANE_A = (rst_l) ? (( |(FMADD_SUBB_input_opcode[1:0] ) ) ? output_interim_Extender_A : (| FMADD_SUBB_input_opcode[6:3]) ? output_interim_post_normalization_IEEE : {3+exp+2*(man+2){1'b0}} ) : {3+exp+2*(man+2){1'b0}} ;
+assign input_interim_ADD_LANE_B = (rst_l) ? ((|(FMADD_SUBB_input_opcode[1:0] ) ) ? output_interim_Extender_B : (| FMADD_SUBB_input_opcode[6:3]) ? output_interim_Extender_B : {3+exp+2*(man+2){1'b0}} ) : {3+exp+2*(man+2){1'b0}};
//exponent_Matching
wire output_interim_Exponent_Mathcing_Sign;
@@ -306,6 +306,7 @@
defparam Post_Normalization_Add.std = std;
defparam Post_Normalization_Add.exp = exp;
defparam Post_Normalization_Add.man = man;
+defparam Post_Normalization_Add.lzd = lzd;
//Rounding Mode Module
wire [exp:0] output_interim_Rounding_Block_Exp;
diff --git a/verilog/rtl/FPU/FMADD_exponent_addition.v b/verilog/rtl/FPU/FMADD_exponent_addition.v
index 4990447..1e64dcd 100644
--- a/verilog/rtl/FPU/FMADD_exponent_addition.v
+++ b/verilog/rtl/FPU/FMADD_exponent_addition.v
@@ -16,7 +16,7 @@
wire [exp+1:0] Exponent_addition_wire_exp;
//functionality
-assign Exponent_addition_wire_exp = (Exponent_addition_input_Activation_Signal) ? (Exponent_addition_input_A[exp:0] + Exponent_addition_input_B[exp:0]): 9'b000000000;
+assign Exponent_addition_wire_exp = (Exponent_addition_input_Activation_Signal) ? (Exponent_addition_input_A[exp:0] + Exponent_addition_input_B[exp:0]): {(exp+2){1'b0}};
assign output_underflow_check = Exponent_addition_wire_exp < 103;
assign Exponent_addition_output_exp = Exponent_addition_wire_exp;
assign Exponent_addition_output_sign = (Exponent_addition_input_Activation_Signal) ? (Exponent_addition_input_A [exp+1] ^ Exponent_addition_input_B[exp+1]) : 1'b0;
diff --git a/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v b/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v
index e330e87..400fc07 100644
--- a/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v
+++ b/verilog/rtl/FPU/FMADD_rounding_block_Multiplication.v
@@ -52,8 +52,6 @@
assign FMADD_ROUND_MUL_wire_rounded_exp = ((!FMADD_ROUND_MUL_input_no[man+man+3]) & (FMADD_ROUND_MUL_wire_rounded_man[man+1])) ?
FMADD_ROUND_MUL_input_no[man+man+exp+4 : man+man+4] + 1'b1 : FMADD_ROUND_MUL_input_no[man+man+exp+4 : man+man+4];
-wire [56:0] check;
-assign check = ({ FMADD_ROUND_MUL_input_no[man+man+exp+6], ({{exp{1'b1}}, 1'b0}), ({man+man+4{1'b1}}) });
diff --git a/verilog/rtl/FPU/FPU_F2I.v b/verilog/rtl/FPU/FPU_F2I.v
index e698e05..7fa0943 100644
--- a/verilog/rtl/FPU/FPU_F2I.v
+++ b/verilog/rtl/FPU/FPU_F2I.v
@@ -50,7 +50,7 @@
wire FLOAT_TO_INT_wire_hidden_bit_decision;
//Setting the input to zero if rst_l or opcode_FI is low
-assign FLOAT_TO_INT_input_wire_float = (FLOAT_TO_INT_input_opcode_FI && rst_l) ? FLOAT_TO_INT_input_float : {32{1'b0}};
+assign FLOAT_TO_INT_input_wire_float = (FLOAT_TO_INT_input_opcode_FI && rst_l) ? FLOAT_TO_INT_input_float : {(std+1){1'b0}};
//Mapping the data to 64bit precision std
assign FLOAT_TO_INT_wire_float_mapped = {FLOAT_TO_INT_input_wire_float[std], (FLOAT_TO_INT_input_wire_float[std-1 : man+1] - bias[exp : 0] + 11'b011_1111_1111), ( {FLOAT_TO_INT_input_wire_float[man:0], {(51-man){1'b0}}} ) };
diff --git a/verilog/rtl/FPU/FPU_Input_Validation.v b/verilog/rtl/FPU/FPU_Input_Validation.v
index 08a577e..dced614 100644
--- a/verilog/rtl/FPU/FPU_Input_Validation.v
+++ b/verilog/rtl/FPU/FPU_Input_Validation.v
@@ -461,7 +461,7 @@
assign INPUT_VALIDATION_Output_Flag_DZ = (rst_l) ? INPUT_VALIDATION_Bit_positive_infinity_Caught_Fdiv : 1'b0;
// Mux for sleection of coresponding exceptional output and FLags (P.S: Refer to coments against each bolen check)
-assign INPUT_VALIDATION_Output_temp_storage = (rst_l) ? (INPUT_VALIDATION_Bit_SNAN_Caught ? 32'h7fa00000 : INPUT_VALIDATION_Bit_No_Comp_A_Caught ? INPUT_VALIDATION_input_ieee_A : INPUT_VALIDATION_Bit_Positive_No_Comp_A_Caught ? {1'b0,INPUT_VALIDATION_input_ieee_A[std-1:0]} : INPUT_VALIDATION_Bit_Negative_No_Comp_A_Caught ? {1'b1,INPUT_VALIDATION_input_ieee_A[std-1:0]} : INPUT_VALIDATION_Bit_No_Comp_B_Caught ? INPUT_VALIDATION_input_ieee_B: INPUT_VALIDATION_Bit_Positive_No_Comp_B_Caught ? {1'b0,INPUT_VALIDATION_input_ieee_B[std-1:0]} : INPUT_VALIDATION_Bit_Negative_No_Comp_B_Caught ? {1'b1,INPUT_VALIDATION_input_ieee_B[std-1:0]}: INPUT_VALIDATION_Bit_No_Comp_C_Caught ? INPUT_VALIDATION_input_ieee_C : INPUT_VALIDATION_Bit_Positive_No_Comp_C_Caught ? {1'b0,INPUT_VALIDATION_input_ieee_C[std-1:0]} : INPUT_VALIDATION_Bit_Negative_No_Comp_C_Caught ? {1'b1,INPUT_VALIDATION_input_ieee_C[std-1:0]} : INPUT_VALIDATION_Bit_negative_infinity_Caught ? 32'hff800000 : INPUT_VALIDATION_Bit_Positive_infinity_Caught ? 32'h7f800000 : INPUT_VALIDATION_Bit_positive_zero_Caught ? 32'h00000000 : INPUT_VALIDATION_Bit_negative_zero_Caught ? 32'h80000000 : INPUT_VALIDATION_Bit_Positive_One_Caught ? 32'h3f800000 : INPUT_VALIDATION_Bit_Negative_One_Caught ? 32'hbf800000 : 32'h00000000) : 32'h00000000 ;
+ assign INPUT_VALIDATION_Output_temp_storage = (rst_l) ? (INPUT_VALIDATION_Bit_SNAN_Caught ? { 1'b0, {(exp+1){1'b1}}, {1'b0,1'b1,{(man-1){1'b0}} } } : INPUT_VALIDATION_Bit_No_Comp_A_Caught ? INPUT_VALIDATION_input_ieee_A : INPUT_VALIDATION_Bit_Positive_No_Comp_A_Caught ? {1'b0,INPUT_VALIDATION_input_ieee_A[std-1:0]} : INPUT_VALIDATION_Bit_Negative_No_Comp_A_Caught ? {1'b1,INPUT_VALIDATION_input_ieee_A[std-1:0]} : INPUT_VALIDATION_Bit_No_Comp_B_Caught ? INPUT_VALIDATION_input_ieee_B: INPUT_VALIDATION_Bit_Positive_No_Comp_B_Caught ? {1'b0,INPUT_VALIDATION_input_ieee_B[std-1:0]} : INPUT_VALIDATION_Bit_Negative_No_Comp_B_Caught ? {1'b1,INPUT_VALIDATION_input_ieee_B[std-1:0]}: INPUT_VALIDATION_Bit_No_Comp_C_Caught ? INPUT_VALIDATION_input_ieee_C : INPUT_VALIDATION_Bit_Positive_No_Comp_C_Caught ? {1'b0,INPUT_VALIDATION_input_ieee_C[std-1:0]} : INPUT_VALIDATION_Bit_Negative_No_Comp_C_Caught ? {1'b1,INPUT_VALIDATION_input_ieee_C[std-1:0]} : INPUT_VALIDATION_Bit_negative_infinity_Caught ? { 1'b1, {(exp+1){1'b1}} , {(man+1){1'b0}} } : INPUT_VALIDATION_Bit_Positive_infinity_Caught ? { 1'b0, {(exp+1){1'b1}} , {(man+1){1'b0}} } : INPUT_VALIDATION_Bit_positive_zero_Caught ? {(std+1){1'b0}} : INPUT_VALIDATION_Bit_negative_zero_Caught ? { 1'b1,{(std){1'b0}} } : INPUT_VALIDATION_Bit_Positive_One_Caught ? { 1'b0, {1'b0 , { (exp){1'b1} } } , {(man+1){1'b0}} } : INPUT_VALIDATION_Bit_Negative_One_Caught ? { 1'b1, {1'b0 , { (exp){1'b1} } }, {man+1{1'b0}} } : {(std+1){1'b0}} ) : {(std+1){1'b0}} ;
//interupt pin assignment, this will be High if at least one input is either SNAN or QNAN
assign interupt_Pin = (rst_l) ? INPUT_VALIDATION_Bit_SNAN_Caught : 1'b0 ;
diff --git a/verilog/rtl/FPU/FPU_Top_Single_Cycle.v b/verilog/rtl/FPU/FPU_Top_Single_Cycle.v
index 17379a5..445eeef 100644
--- a/verilog/rtl/FPU/FPU_Top_Single_Cycle.v
+++ b/verilog/rtl/FPU/FPU_Top_Single_Cycle.v
@@ -75,7 +75,7 @@
end
end
//assigment of interim register on outptu ports
-assign FPU_resultant = (rst_l) ? FPU_resultant_reg:32'h00000000;
+ assign FPU_resultant = (rst_l) ? FPU_resultant_reg:{std+1{1'b0}};
assign S_Flags = (rst_l) ? S_Flags_reg:5'b00000 ;
assign FPU_Result_rd = (rst_l) ? FPU_Result_rd_reg : 32'h00000000;
@@ -285,14 +285,14 @@
if (~rst_l)
begin
- FPU_resultant_reg <= 32'h00000000;
+ FPU_resultant_reg <= {(std+1){1'b0}};
FPU_Result_rd_reg <= 32'h00000000;
S_Flags_reg <= 5'b00000;
end
else if (Exception_flag_interim)
begin
FPU_resultant_reg <= output_interim_input_validation_temp_storage;
- FPU_Result_rd_reg <= output_interim_input_validation_temp_storage;
+ FPU_Result_rd_reg <= (std==15) ? {16'h0000,output_interim_input_validation_temp_storage[15:0]} : output_interim_input_validation_temp_storage;
S_Flags_reg <= { output_interim_input_validation_invalid_flag , output_interim_input_validation_Divide_By_Zero , 3'b000 } ;
end
@@ -337,14 +337,14 @@
else if (sfpu_op[14] | vfpu_op[18]) //output selection logic for Float to int instruction FCVT.W.S
begin
- FPU_resultant_reg <= 32'h00000000;
+ FPU_resultant_reg <= {(std+1){1'b0}};
FPU_Result_rd_reg <= output_interim_FLOAT_to_Int;
S_Flags_reg <= {output_interim_Invalid_Flag_Float_To_Int,3'b000,output_interim_Inexact_Flag_Float_To_Int};
end
else if (sfpu_op[9] | sfpu_op[10] | sfpu_op[11] | (|vfpu_op[10:5])) //output selection for comparision instructions
begin
- FPU_resultant_reg <= 32'h00000000;
+ FPU_resultant_reg <= {(std+1){1'b0}};
FPU_Result_rd_reg <= output_interim_Comparison;
S_Flags_reg <= 5'b00000;
end
@@ -358,13 +358,13 @@
else if (sfpu_op[21] | vfpu_op[25]) //output slection for Fclass instructions
begin
- FPU_resultant_reg <= 32'h00000000;
+ FPU_resultant_reg <= {(std+1){1'b0}};
FPU_Result_rd_reg <= output_interim_Fclass;
S_Flags_reg <= 5'b00000;
end
else
begin
- FPU_resultant_reg <= 32'h00000000;
+ FPU_resultant_reg <= {(std+1){1'b0}};
FPU_Result_rd_reg <= 32'h00000000;
S_Flags_reg <= 5'b00000;
end
diff --git a/verilog/rtl/FPU/FPU_exu.v b/verilog/rtl/FPU/FPU_exu.v
index 479cfdf..e84c91c 100644
--- a/verilog/rtl/FPU/FPU_exu.v
+++ b/verilog/rtl/FPU/FPU_exu.v
@@ -80,8 +80,8 @@
end
// FPU operands
- assign fs1_d[15:0] = (rst_l == 1'b0) ? {FPLEN{1'b0}} : (({FPLEN{valid_execution & dec_i0_rs1_en_d & ~float_control[0]}} & gpr_i0_rs1_d[31:0] ) |
- ({FPLEN{valid_execution & ~dec_i0_rs1_en_d & float_control[0] }} & fs1_data ));
+ assign fs1_d[15:0] = (rst_l == 1'b0) ? {FPLEN{1'b0}} : (({FPLEN{valid_execution & dec_i0_rs1_en_d & (~float_control[0])}} & gpr_i0_rs1_d[FPLEN-1:0]) |
+ ({FPLEN{valid_execution & ~dec_i0_rs1_en_d & float_control[0] }} & fs1_data ));
assign Operand_Int = (rst_l == 1'b0) ? 32'h00000000 : (({32{valid_execution & dec_i0_rs1_en_d & ~float_control[0]}} & gpr_i0_rs1_d[31:0] )) ;
assign fs2_d[15:0] = (rst_l == 1'b0) ? {FPLEN{1'b0}} : (({FPLEN{valid_execution & float_control[1] }} & fs2_data ));
diff --git a/verilog/rtl/FPU/FPU_move.v b/verilog/rtl/FPU/FPU_move.v
index 59320b6..51c3d77 100644
--- a/verilog/rtl/FPU/FPU_move.v
+++ b/verilog/rtl/FPU/FPU_move.v
@@ -11,6 +11,6 @@
wire [Std : 0] Move_Output_IEEE; // Define reg becuase it is Output of IEEE754 32 Move Instruction
// New logic will be
- assign Move_Output_IEEE = (rst_l == 1'b0) ? 32'h00000000 : (opcode[0] == 1'b1) ? Move_Input_IEEE : (opcode[1] == 1'b1) ? Move_Input_IEEE : 32'h00000000;
+ assign Move_Output_IEEE = (rst_l == 1'b0) ? { (Std+1){1'b0} } : (opcode[0] == 1'b1) ? Move_Input_IEEE : (opcode[1] == 1'b1) ? Move_Input_IEEE : { (Std+1){1'b0} } ;
endmodule
diff --git a/verilog/rtl/FPU/FPU_sign_injection.v b/verilog/rtl/FPU/FPU_sign_injection.v
index 8110b58..9120f1c 100644
--- a/verilog/rtl/FPU/FPU_sign_injection.v
+++ b/verilog/rtl/FPU/FPU_sign_injection.v
@@ -19,8 +19,8 @@
// New logic
assign Sign_A = (rst_l == 1'b0) ? 1'b0 : IEEE_A[Std];
assign Sign_B = (rst_l == 1'b0) ? 1'b0 : IEEE_B[Std];
- assign Exp_A = (rst_l == 1'b0) ? 8'h00 : IEEE_A[Std - 1 : Std - Exp - 1];
- assign Mantissa_A = (rst_l == 1'b0) ? 23'h0 : IEEE_A[Man : 0];
- assign IEEE_out = (rst_l == 1'b0) ? 32'h0 : (op[0]) ? {Sign_B,Exp_A,Mantissa_A} : (op[1]) ? {~Sign_B,Exp_A,Mantissa_A} : (op[2]) ? {(Sign_A ^ Sign_B),Exp_A,Mantissa_A} : 32'h0;
+ assign Exp_A = (rst_l == 1'b0) ? {(Exp+1){1'b0}} : IEEE_A[Std - 1 : Std - Exp - 1];
+ assign Mantissa_A = (rst_l == 1'b0) ? {(Man+1){1'b0}} : IEEE_A[Man : 0];
+ assign IEEE_out = (rst_l == 1'b0) ? {(Std+1){1'b0}} : (op[0]) ? {Sign_B,Exp_A,Mantissa_A} : (op[1]) ? {~Sign_B,Exp_A,Mantissa_A} : (op[2]) ? {(Sign_A ^ Sign_B),Exp_A,Mantissa_A} : {(Std+1){1'b0}};
endmodule
