commit c6795f34f9e3fd9940d51d409365a9646995fc49
author hamzashabbir517 <shabbirhamza517@gmail.com> Mon May 30 10:23:25 2022 +0500
committer hamzashabbir517 <shabbirhamza517@gmail.com> Mon May 30 10:23:25 2022 +0500
tree ba0008cb3de58d95387275f9396205a239681b98
parent f7bc070147a1bd18c9984a2ad32176ec8358dbe2

Testbench

verilog/dv/FPU_Half/FPU_Half_tb.v

diff --git a/verilog/dv/FPU_Half/FPU_Half_tb.v b/verilog/dv/FPU_Half/FPU_Half_tb.v
index 5de42be..b3479ef 100644
--- a/verilog/dv/FPU_Half/FPU_Half_tb.v
+++ b/verilog/dv/FPU_Half/FPU_Half_tb.v
@@ -175,14 +175,6 @@
             */
             // Observe Output pins [23:8] for FNMADD/FNMSUB
             
-            wait(mprj_io_0 == 16'hE0B9);
-            wait(mprj_io_0 == 16'hA252);
-            wait(mprj_io_0 == 16'hE7F5);
-            wait(mprj_io_0 == 16'hF8D8);
-            wait(mprj_io_0 == 16'hFC00);
-            wait(mprj_io_0 == 16'hDD7E);
-            wait(mprj_io_0 == 16'hE3DC);
-            wait(mprj_io_0 == 16'hBD78);
             wait(mprj_io_0 == 16'hE0CB);
             wait(mprj_io_0 == 16'hB475);
             wait(mprj_io_0 == 16'hE805);
@@ -191,6 +183,14 @@
             wait(mprj_io_0 == 16'h5c34);
             wait(mprj_io_0 == 16'hd698);
             wait(mprj_io_0 == 16'h3d78);
+            wait(mprj_io_0 == 16'hE0B9);
+            wait(mprj_io_0 == 16'hA252);
+            wait(mprj_io_0 == 16'hE7F5);
+            wait(mprj_io_0 == 16'hF8D8);
+            wait(mprj_io_0 == 16'hFC00);
+            wait(mprj_io_0 == 16'hDD7E);
+            wait(mprj_io_0 == 16'hE3DC);
+            wait(mprj_io_0 == 16'hBD78);
             
             $display("MPRJ-IO state = %h", mprj_io[23:8]);