Mismatch solved

diff --git a/verilog/rtl/FPU/beh_lib.v b/verilog/rtl/FPU/beh_lib.v
index 67b166f..082550d 100644
--- a/verilog/rtl/FPU/beh_lib.v
+++ b/verilog/rtl/FPU/beh_lib.v

@@ -18,7 +18,7 @@
 		end
 		else always @(posedge clk or negedge rst_l)
 			if (rst_l == 0)
-				dout[WIDTH - 1:0] <= {{WIDTH{0}};
+				dout[WIDTH - 1:0] <= {WIDTH{1'b0}};
 			else
 				dout[WIDTH - 1:0] <= din[WIDTH - 1:0];
 	endgenerate