commit 4f3386858ce1b9712d2dc3508a6967dff6a7ec5a
author hamzashabbir517 <shabbirhamza517@gmail.com> Fri May 27 13:33:44 2022 +0500
committer hamzashabbir517 <shabbirhamza517@gmail.com> Fri May 27 13:33:44 2022 +0500
tree 9a0954845b54229b5fa501335feff35f93a3f4e6
parent 97d3e820891ca22de73d6ba17c55c38eca4c3f5a

Mismatch solved

verilog/rtl/FPU/beh_lib.v

diff --git a/verilog/rtl/FPU/beh_lib.v b/verilog/rtl/FPU/beh_lib.v
index 67b166f..082550d 100644
--- a/verilog/rtl/FPU/beh_lib.v
+++ b/verilog/rtl/FPU/beh_lib.v
@@ -18,7 +18,7 @@
 		end
 		else always @(posedge clk or negedge rst_l)
 			if (rst_l == 0)
-				dout[WIDTH - 1:0] <= {{WIDTH{0}};
+				dout[WIDTH - 1:0] <= {WIDTH{1'b0}};
 			else
 				dout[WIDTH - 1:0] <= din[WIDTH - 1:0];
 	endgenerate