Testbench Updated
diff --git a/verilog/dv/FPU_Half/FPU_Half.c b/verilog/dv/FPU_Half/FPU_Half.c
index 42cd35c..5e5befc 100644
--- a/verilog/dv/FPU_Half/FPU_Half.c
+++ b/verilog/dv/FPU_Half/FPU_Half.c
@@ -69,7 +69,7 @@
reg_la2_oenb = reg_la2_iena = 0x00000002; // 65 bit as input to user proj and output from cpu for reset
reg_la2_data = 0x00000000; // reset
reg_la2_data = 0x00000002;
- reg_la2_oenb = reg_la2_iena = 0x00000003; // 64 anf 65 bit as input to user proj and output from cpu
+ reg_la2_oenb = reg_la2_iena = 0x00000000; // 64 anf 65 bit as input to user proj and output from cpu
//reg_la1_oenb = reg_la1_iena = 0x00000000;
//reg_la1_data = 0x00000015C; // Clk_per_bit
diff --git a/verilog/dv/FPU_Half/FPU_Half_tb.v b/verilog/dv/FPU_Half/FPU_Half_tb.v
index 09e34d2..c8b94f8 100644
--- a/verilog/dv/FPU_Half/FPU_Half_tb.v
+++ b/verilog/dv/FPU_Half/FPU_Half_tb.v
@@ -62,26 +62,6 @@
initial begin
wait(mprj_ready == 1'b1)
- // Observe Output pins [35:8] for factorial
- /*wait(mprj_io_0 == 28'h0000001);
- wait(mprj_io_0 == 28'h0000002);
- wait(mprj_io_0 == 28'h0000006);
- wait(mprj_io_0 == 28'h0000018);
- wait(mprj_io_0 == 28'h0000078);
- wait(mprj_io_0 == 28'h00002D0);
- wait(mprj_io_0 == 28'h00013B0);
- wait(mprj_io_0 == 28'h0009D80);
- wait(mprj_io_0 == 28'h0058980);
- wait(mprj_io_0 == 28'h0375F00);
- */
- // Observe Output pins [35:8] for prime_num
- /*wait(mprj_io_0 == 28'd1);
- wait(mprj_io_0 == 28'd3);
- wait(mprj_io_0 == 28'd5);
- wait(mprj_io_0 == 28'd7);
- wait(mprj_io_0 == 28'd11);
- wait(mprj_io_0 == 28'd13);
- */
// Observe Output pins [23:8] for multliplication_table
wait(mprj_io_0 == 16'd5);
wait(mprj_io_0 == 16'd10);
@@ -89,42 +69,7 @@
wait(mprj_io_0 == 16'd20);
wait(mprj_io_0 == 16'd25);
wait(mprj_io_0 == 16'd30);
-
- // Observe Output pins [35:8] for mean & Determinant
- // wait(mprj_io_0 == 28'd5);
-
- // Observe Output pins [35:8] for power
- //wait(mprj_io_0 == 28'd64);
-
- // Observe Output pins [35:8] for flip number
- //wait(mprj_io_0 == 28'd4889874);
-
- // Observe Output pins [35:8] for Queue
- //wait(mprj_io_0 == 28'd5);
- //wait(mprj_io_0 == 28'd6);
- //wait(mprj_io_0 == 28'd7);
-
- // Observe Output pins [35:8] for perfect square
- //wait(mprj_io_0 == 28'd5);
-
- // Observe Output pins [35:8] for counter / ascending / reverse
- /*wait(mprj_io_0 == 28'd0);
- wait(mprj_io_0 == 28'd1);
- wait(mprj_io_0 == 28'd2);
- wait(mprj_io_0 == 28'd3);
- wait(mprj_io_0 == 28'd4);
- wait(mprj_io_0 == 28'd5);
- wait(mprj_io_0 == 28'd6);
- wait(mprj_io_0 == 28'd7);
- wait(mprj_io_0 == 28'd8);
- wait(mprj_io_0 == 28'd9);
- wait(mprj_io_0 == 28'd10);
- wait(mprj_io_0 == 28'd11);
- */
- //wait(mprj_io_0 == 28'd3);
- //wait(mprj_io_0 == 28'd2);
- //wait(mprj_io_0 == 28'd1);
- //wait(mprj_io_0 == 28'd0);
+
$display("MPRJ-IO state = %d", mprj_io[23:8]);
`ifdef GL
@@ -160,9 +105,9 @@
power4 <= 1'b1;
end
- always @(mprj_io) begin
- #1 $display("MPRJ-IO state = %d, at time = %0t ", mprj_io[23:8], $time);
- end
+ //always @(mprj_io) begin
+ // #1 $display("MPRJ-IO state = %d, at time = %0t ", mprj_io[23:8], $time);
+ //end
wire flash_csb;
wire flash_clk;
diff --git a/verilog/rtl/FPU/FPU_FSM_TOP.v b/verilog/rtl/FPU/FPU_FSM_TOP.v
index 1e01b07..0e28e4f 100644
--- a/verilog/rtl/FPU/FPU_FSM_TOP.v
+++ b/verilog/rtl/FPU/FPU_FSM_TOP.v
@@ -101,7 +101,7 @@
- assign FPU_hp_result = (rst_l == 1'b0) ? 16'h0000 : (fpu_result_rd_w & Active_Process) ? fpu_complete_rd[15:0] : (fpu_complete & ~fpu_result_rd_w & Active_Process) ? fpu_result_1 : 16'h0000;
+ assign FPU_hp_result = (rst_l == 1'b0) ? 16'h0000 : (fpu_complete_rd & Active_Process) ? fpu_result_rd_w[15:0] : (fpu_complete & ~fpu_complete_rd & Active_Process) ? fpu_result_1 : 16'h0000;
FPU_FSM FSM(
.clk(clk),
