commit 1dbaa35fe50c25dbe46f350043dca57384482682
author hamzashabbir517 <shabbirhamza517@gmail.com> Sat May 28 20:37:38 2022 +0500
committer hamzashabbir517 <shabbirhamza517@gmail.com> Sat May 28 20:37:38 2022 +0500
tree d9e31ad39af69ea4fccdb6f48b9753a2060721f7
parent 4f3386858ce1b9712d2dc3508a6967dff6a7ec5a

Update

verilog/rtl/FPU/FPU_FSM_TOP.v

diff --git a/verilog/rtl/FPU/FPU_FSM_TOP.v b/verilog/rtl/FPU/FPU_FSM_TOP.v
index 8095aac..e381fda 100644
--- a/verilog/rtl/FPU/FPU_FSM_TOP.v
+++ b/verilog/rtl/FPU/FPU_FSM_TOP.v
@@ -101,8 +101,6 @@
     wire[2:0]fpu_sel;
     wire [31:0]fpu_result_rd_w;
 
-
-
     assign FPU_hp_result = (rst_l == 1'b0) ? 16'h0000 : (fpu_complete_rd & Active_Process) ? fpu_result_rd_w[15:0] : (fpu_complete & ~fpu_complete_rd & Active_Process) ? fpu_result_1 : 16'h0000;
     
     FPU_FSM FSM(