| /root/mixed_signal_circuits_mpw6/Makefile |
| /root/mixed_signal_circuits_mpw6/docs/Makefile |
| /root/mixed_signal_circuits_mpw6/docs/environment.yml |
| /root/mixed_signal_circuits_mpw6/docs/source/conf.py |
| /root/mixed_signal_circuits_mpw6/docs/source/index.rst |
| /root/mixed_signal_circuits_mpw6/netgen/run_lvs_por.sh |
| /root/mixed_signal_circuits_mpw6/netgen/run_lvs_wrapper_verilog.sh |
| /root/mixed_signal_circuits_mpw6/netgen/run_lvs_wrapper_xschem.sh |
| /root/mixed_signal_circuits_mpw6/verilog/dv/Makefile |
| /root/mixed_signal_circuits_mpw6/verilog/dv/mprj_por/Makefile |
| /root/mixed_signal_circuits_mpw6/verilog/dv/mprj_por/mprj_por.c |
| /root/mixed_signal_circuits_mpw6/verilog/dv/mprj_por/mprj_por_tb.v |
| /root/mixed_signal_circuits_mpw6/verilog/rtl/example_por.v |
| /root/mixed_signal_circuits_mpw6/verilog/rtl/uprj_analog_netlists.v |
| /root/mixed_signal_circuits_mpw6/verilog/rtl/user_analog_proj_example.v |
| /root/mixed_signal_circuits_mpw6/verilog/rtl/user_analog_project_wrapper.v |
| /root/mixed_signal_circuits_mpw6/xschem/.spiceinit |
| /root/mixed_signal_circuits_mpw6/xschem/1T1R_2x2.sch |
| /root/mixed_signal_circuits_mpw6/xschem/1T1R_2x2.sym |
| /root/mixed_signal_circuits_mpw6/xschem/C4.sch |
| /root/mixed_signal_circuits_mpw6/xschem/C4.sym |
| /root/mixed_signal_circuits_mpw6/xschem/FG_pfet.sch |
| /root/mixed_signal_circuits_mpw6/xschem/FG_pfet.sym |
| /root/mixed_signal_circuits_mpw6/xschem/amux.sch |
| /root/mixed_signal_circuits_mpw6/xschem/amux.sym |
| /root/mixed_signal_circuits_mpw6/xschem/analog_wrapper_tb.sch |
| /root/mixed_signal_circuits_mpw6/xschem/example_por.sch |
| /root/mixed_signal_circuits_mpw6/xschem/example_por.sym |
| /root/mixed_signal_circuits_mpw6/xschem/example_por_tb.sch |
| /root/mixed_signal_circuits_mpw6/xschem/example_por_tb.spice.orig |
| /root/mixed_signal_circuits_mpw6/xschem/hv_tgate.sch |
| /root/mixed_signal_circuits_mpw6/xschem/hv_tgate.sym |
| /root/mixed_signal_circuits_mpw6/xschem/reram.sym |
| /root/mixed_signal_circuits_mpw6/xschem/sky130_fd_pr_reram__reram_cell.va |
| /root/mixed_signal_circuits_mpw6/xschem/sky130_sc_ams__comparator_1.sch |
| /root/mixed_signal_circuits_mpw6/xschem/sky130_sc_ams__comparator_1.sym |
| /root/mixed_signal_circuits_mpw6/xschem/sky130_sc_ams__ota_1.sch |
| /root/mixed_signal_circuits_mpw6/xschem/sky130_sc_ams__ota_1.sym |
| /root/mixed_signal_circuits_mpw6/xschem/test.data |
| /root/mixed_signal_circuits_mpw6/xschem/user_analog_project_wrapper-example.sch |
| /root/mixed_signal_circuits_mpw6/xschem/user_analog_project_wrapper.sch |
| /root/mixed_signal_circuits_mpw6/xschem/user_analog_project_wrapper.sym |
| /root/mixed_signal_circuits_mpw6/xschem/xschemrc |
| /root/mixed_signal_circuits_mpw6/xschem/sky130/nfet_01v8.sym |
| /root/mixed_signal_circuits_mpw6/xschem/sky130/nfet_03v3_nvt.sym |
| /root/mixed_signal_circuits_mpw6/xschem/sky130/pfet_01v8.sym |
| /root/mixed_signal_circuits_mpw6/xschem/sky130_fd_pr/cap_mim_m3_1.sch |
| /root/mixed_signal_circuits_mpw6/xschem/sky130_fd_pr/cap_mim_m3_1.sym |
| /root/mixed_signal_circuits_mpw6/xschem/sky130_fd_pr/nfet_01v8.sym |
| /root/mixed_signal_circuits_mpw6/xschem/sky130_fd_pr/nfet_g5v0d10v5.sym |
| /root/mixed_signal_circuits_mpw6/xschem/sky130_fd_pr/pfet_01v8.sym |
| /root/mixed_signal_circuits_mpw6/xschem/sky130_fd_pr/pfet_g5v0d10v5.sym |
| /root/mixed_signal_circuits_mpw6/xschem/sky130_fd_pr/res_xhigh_po.sym |
| /root/mixed_signal_circuits_mpw6/xschem/sky130_tests/top.sch |
