adding missing cap layout
1 file changed
tree: 4ebccff00916212923f2ea0b7798f6192aeb36f7
  1. .github/
  2. docs/
  3. gds/
  4. mag/
  5. netgen/
  6. openlane/
  7. verilog/
  8. xschem/
  9. .gitignore
  10. LICENSE
  11. Makefile
  12. README.md
README.md

Caravel Analog User

License CI Caravan Build


The focus of this tape-out is integrating analog synapses. Specifically, we are integrating ReRAM based synapse and FG-based synapse. ReRAM based array is a 1T-1R strucuture with the goal of increasing the size of the array. FG synapses is built using the high voltage transistors present on the SKY130 process.