|author||Tim Edwards <firstname.lastname@example.org>||Sat Dec 18 10:44:16 2021 -0500|
|committer||Tim Edwards <email@example.com>||Sat Dec 18 10:44:16 2021 -0500|
Updated the layout to properly use the metal resistors in front of pins that are connected to the same net. Updated the GDS with this change, and also to properly generate hierarchical layers, which apparently had not been done previously. Verilog and schematic have not yet been updated with the metal resistor change, and so will fail LVS until they are.
|:exclamation: Important Note|
|:warning:||Use this sample project for analog user projects.|
Refer to README for this sample project documentation.