commit	ea5ff7d937a3422c805b506215ae5242935638b2	[log] [tgz]
author	Tim Edwards <tim@opencircuitdesign.com>	Sat Dec 18 10:44:16 2021 -0500
committer	Tim Edwards <tim@opencircuitdesign.com>	Sat Dec 18 10:44:16 2021 -0500
tree	76d81ffcbd54654fb9857c795d14849d62e8d675
parent	4afe80a9c6351d7ac4dd01538be61801a0e14d26 [diff]

Updated the layout to properly use the metal resistors in front of
pins that are connected to the same net.  Updated the GDS with this
change, and also to properly generate hierarchical layers, which
apparently had not been done previously.  Verilog and schematic
have not yet been updated with the metal resistor change, and so
will fail LVS until they are.

gds/user_analog_project_wrapper.gds[diff]
mag/user_analog_proj_example.mag[diff]
mag/user_analog_project_wrapper.mag[diff]

3 files changed

tree: 76d81ffcbd54654fb9857c795d14849d62e8d675

.github/
docs/
gds/
mag/
netgen/
openlane/
verilog/
xschem/
caravel
.gitignore
LICENSE
Makefile
README.md

README.md

Caravel Analog User

:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:	Use this sample project for analog user projects.

Refer to README for this sample project documentation.