tree 76d81ffcbd54654fb9857c795d14849d62e8d675
parent 4afe80a9c6351d7ac4dd01538be61801a0e14d26
author Tim Edwards <tim@opencircuitdesign.com> 1639842256 -0500
committer Tim Edwards <tim@opencircuitdesign.com> 1639842256 -0500

Updated the layout to properly use the metal resistors in front of
pins that are connected to the same net.  Updated the GDS with this
change, and also to properly generate hierarchical layers, which
apparently had not been done previously.  Verilog and schematic
have not yet been updated with the metal resistor change, and so
will fail LVS until they are.