removing extra c4 structure
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
index dfc63c4..31f79f8 100644
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag
@@ -1,7 +1,7 @@
magic
tech sky130B
magscale 1 2
-timestamp 1654013377
+timestamp 1654184506
<< metal1 >>
rect 561180 686400 561428 686442
rect 561180 686254 561216 686400
@@ -1072,12 +1072,8 @@
timestamp 1654006311
transform 1 0 52313 0 1 660624
box -2563 -40 1390 600
-use c4_1 c4_1_0
-timestamp 1654006311
-transform 1 0 372 0 1 32
-box -372 -32 306 458
use c4_1 c4_1_1
-timestamp 1654006311
+timestamp 1654184506
transform 1 0 256206 0 1 656412
box -372 -32 306 458
<< labels >>
diff --git a/xschem/user_analog_project_wrapper.spice b/xschem/user_analog_project_wrapper.spice
index 6d7ac52..f9a3c6c 100644
--- a/xschem/user_analog_project_wrapper.spice
+++ b/xschem/user_analog_project_wrapper.spice
@@ -1,5 +1,5 @@
** sch_path:
-*+ /home/charana/IC/design/mixed-signal-re-ram-mpw-6/xschem/user_analog_project_wrapper.sch
+*+ /home/charana/IC/design/mixed-signal-re-ram-mpw-6_1/xschem/user_analog_project_wrapper.sch
**.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2 wb_clk_i
*+ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
@@ -67,8 +67,8 @@
**.ends
* expanding symbol: 1T1R_2x2.sym # of pins=7
-** sym_path: /home/charana/IC/design/mixed-signal-re-ram-mpw-6/xschem/1T1R_2x2.sym
-** sch_path: /home/charana/IC/design/mixed-signal-re-ram-mpw-6/xschem/1T1R_2x2.sch
+** sym_path: /home/charana/IC/design/mixed-signal-re-ram-mpw-6_1/xschem/1T1R_2x2.sym
+** sch_path: /home/charana/IC/design/mixed-signal-re-ram-mpw-6_1/xschem/1T1R_2x2.sch
.subckt 1T1R_2x2 wl1 wl2 sl2 bl1 bl2 sl1 VSS
*.iopin sl2
*.iopin sl1
@@ -102,8 +102,8 @@
* expanding symbol: FG_pfet.sym # of pins=4
-** sym_path: /home/charana/IC/design/mixed-signal-re-ram-mpw-6/xschem/FG_pfet.sym
-** sch_path: /home/charana/IC/design/mixed-signal-re-ram-mpw-6/xschem/FG_pfet.sch
+** sym_path: /home/charana/IC/design/mixed-signal-re-ram-mpw-6_1/xschem/FG_pfet.sym
+** sch_path: /home/charana/IC/design/mixed-signal-re-ram-mpw-6_1/xschem/FG_pfet.sch
.subckt FG_pfet vtun vin vsource vd
*.iopin vtun
*.iopin vin
@@ -122,8 +122,8 @@
* expanding symbol: C4.sym # of pins=6
-** sym_path: /home/charana/IC/design/mixed-signal-re-ram-mpw-6/xschem/C4.sym
-** sch_path: /home/charana/IC/design/mixed-signal-re-ram-mpw-6/xschem/C4.sch
+** sym_path: /home/charana/IC/design/mixed-signal-re-ram-mpw-6_1/xschem/C4.sym
+** sch_path: /home/charana/IC/design/mixed-signal-re-ram-mpw-6_1/xschem/C4.sch
.subckt C4 vth vdda vtl vin vout vss
*.ipin vth
*.ipin vtl
