blob: 33b6f37b846b92a3dc3d63b0222f3f6b6e0521f4 [file] [log] [blame]
Kesami Hagiwara9628e162022-05-27 16:17:09 +09001+define+PRINTF_COND=1
2+define+RANDOMIZE_MEM_INIT
3+define+RANDOMIZE_REG_INIT
4+define+RANDOMIZE_DELAY=1
5+define+UART_HIGH_SPEED
6+define+WAVEFORM
7
Marwan Abbas0f930452022-02-22 09:18:53 -08008# Caravel user project includes
9-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
Marwan Abbas0f930452022-02-22 09:18:53 -080010
Kesami Hagiwara9628e162022-05-27 16:17:09 +090011+incdir+$(USER_PROJECT_VERILOG)/rtl/marmot
12-v $(USER_PROJECT_VERILOG)/rtl/marmot/AsyncResetReg.v
13-v $(USER_PROJECT_VERILOG)/rtl/marmot/BootROM.v
14-v $(USER_PROJECT_VERILOG)/rtl/marmot/Marmot_sram_control.v
15-v $(USER_PROJECT_VERILOG)/rtl/marmot/Marmot.v
16-v $(USER_PROJECT_VERILOG)/rtl/marmot/plusarg_reader.v
17-v $(USER_PROJECT_VERILOG)/rtl/marmot/shc.marmotcaravel.MarmotCaravelConfig.no_sram.v
18-v $(USER_PROJECT_VERILOG)/rtl/marmot/SRLatch.v
19
20-v $(USER_PROJECT_VERILOG)/lib/sky130_sram_1kbyte_1rw1r_32x256_8.v
21#-v $(USER_PROJECT_VERILOG)/lib/sky130_sram_2kbyte_1rw1r_32x512_8.v
22
23// SPI Flash model
24+define+SPEEDSIM
25-v $(USER_PROJECT_VERILOG)/dv/vip/MX25U3235F.v
26
27// SPI RAM model (protected, Questa is needed)
28//-v $(USER_PROJECT_VERILOG)/dv/vip/APM_APS6404L-3SQN_SQPI_PSRAM_model_v2.9_encrypt.vp_modelsim
29
30// UART model
31+incdir+$(USER_PROJECT_VERILOG)/dv/vip/uart
32-v $(USER_PROJECT_VERILOG)/dv/vip/uart/uart_tb.v
33