| ////////////////////////////////////////////////////////////////////////////// |
| // SPDX-FileCopyrightText: 2021 , Dinesh Annayya |
| // |
| // Licensed under the Apache License, Version 2.0 (the "License"); |
| // you may not use this file except in compliance with the License. |
| // You may obtain a copy of the License at |
| // |
| // http://www.apache.org/licenses/LICENSE-2.0 |
| // |
| // Unless required by applicable law or agreed to in writing, software |
| // distributed under the License is distributed on an "AS IS" BASIS, |
| // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| // See the License for the specific language governing permissions and |
| // limitations under the License. |
| // SPDX-License-Identifier: Apache-2.0 |
| // SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> |
| // SPDX-FileContributor: Modified by SH CONSULTING K.K. |
| // |
| ////////////////////////////////////////////////////////////////////// |
| //// //// |
| //// clock skew adjust //// |
| //// //// |
| //// Description //// |
| //// This block is useful for global clock skew adjustment //// |
| //// logic implementation: //// |
| //// clk_out = (sel=0) ? clk_in : //// |
| //// (sel=1) ? clk_d1 : //// |
| //// (sel=2) ? clk_d2 : //// |
| //// ..... //// |
| //// (sel=31)? clk_d31 :clk_in //// |
| //// //// |
| //// Note: each d* indicate clk buf delay //// |
| //// //// |
| //// //// |
| //// To Do: //// |
| //// nothing //// |
| //// //// |
| //// Author(s): //// |
| //// - Dinesh Annayya, dinesha@opencores.org //// |
| //// - SH CONSULTING K.K. //// |
| //// //// |
| //// Revision : //// |
| //// 0.0 - 29th Feb 2021, Dinesh A //// |
| //// Initial version //// |
| //// 0.1 - 29th May 2022, SH CONSULTING K.K. //// |
| //// Extend to 31 stages //// |
| //// //// |
| //// //// |
| ////////////////////////////////////////////////////////////////////// |
| //// //// |
| //// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
| //// //// |
| //// This source file may be used and distributed without //// |
| //// restriction provided that this copyright statement is not //// |
| //// removed from the file and that any derivative work contains //// |
| //// the original copyright notice and the associated disclaimer. //// |
| //// //// |
| //// This source file is free software; you can redistribute it //// |
| //// and/or modify it under the terms of the GNU Lesser General //// |
| //// Public License as published by the Free Software Foundation; //// |
| //// either version 2.1 of the License, or (at your option) any //// |
| //// later version. //// |
| //// //// |
| //// This source is distributed in the hope that it will be //// |
| //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
| //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
| //// PURPOSE. See the GNU Lesser General Public License for more //// |
| //// details. //// |
| //// //// |
| //// You should have received a copy of the GNU Lesser General //// |
| //// Public License along with this source; if not, download it //// |
| //// from http://www.opencores.org/lgpl.shtml //// |
| //// //// |
| ////////////////////////////////////////////////////////////////////// |
| |
| module clk_skew_adjust( |
| `ifdef USE_POWER_PINS |
| vccd1,// User area 1 1.8V supply |
| vssd1,// User area 1 digital ground |
| `endif |
| clk_in, sel, clk_out); |
| |
| |
| `ifdef USE_POWER_PINS |
| input vccd1;// User area 1 1.8V supply |
| input vssd1;// User area 1 digital ground |
| `endif |
| input clk_in; |
| output clk_out; |
| input [4:0] sel; |
| |
| wire clk_d1; |
| wire clk_d2; |
| wire clk_d3; |
| wire clk_d4; |
| wire clk_d5; |
| wire clk_d6; |
| wire clk_d7; |
| wire clk_d8; |
| wire clk_d9; |
| wire clk_d10; |
| wire clk_d11; |
| wire clk_d12; |
| wire clk_d13; |
| wire clk_d14; |
| wire clk_d15; |
| wire clk_d16; |
| wire clk_d17; |
| wire clk_d18; |
| wire clk_d19; |
| wire clk_d20; |
| wire clk_d21; |
| wire clk_d22; |
| wire clk_d23; |
| wire clk_d24; |
| wire clk_d25; |
| wire clk_d26; |
| wire clk_d27; |
| wire clk_d28; |
| wire clk_d29; |
| wire clk_d30; |
| wire clk_d31; |
| |
| wire d00; |
| wire d01; |
| wire d02; |
| wire d03; |
| wire d04; |
| wire d05; |
| wire d06; |
| wire d07; |
| wire d08; |
| wire d09; |
| wire d0a; |
| wire d0b; |
| wire d0c; |
| wire d0d; |
| wire d0e; |
| wire d0f; |
| wire d10; |
| wire d11; |
| wire d12; |
| wire d13; |
| wire d14; |
| wire d15; |
| wire d16; |
| wire d17; |
| wire d20; |
| wire d21; |
| wire d22; |
| wire d23; |
| wire d30; |
| wire d31; |
| wire d40; |
| |
| ctech_delay_clkbuf clkbuf_1 (.A(clk_in), .X(clk_d1)); |
| ctech_delay_clkbuf clkbuf_2 (.A(clk_d1), .X(clk_d2)); |
| ctech_delay_clkbuf clkbuf_3 (.A(clk_d2), .X(clk_d3)); |
| ctech_delay_clkbuf clkbuf_4 (.A(clk_d3), .X(clk_d4)); |
| ctech_delay_clkbuf clkbuf_5 (.A(clk_d4), .X(clk_d5)); |
| ctech_delay_clkbuf clkbuf_6 (.A(clk_d5), .X(clk_d6)); |
| ctech_delay_clkbuf clkbuf_7 (.A(clk_d6), .X(clk_d7)); |
| ctech_delay_clkbuf clkbuf_8 (.A(clk_d7), .X(clk_d8)); |
| ctech_delay_clkbuf clkbuf_9 (.A(clk_d8), .X(clk_d9)); |
| ctech_delay_clkbuf clkbuf_10 (.A(clk_d9), .X(clk_d10)); |
| ctech_delay_clkbuf clkbuf_11 (.A(clk_d10), .X(clk_d11)); |
| ctech_delay_clkbuf clkbuf_12 (.A(clk_d11), .X(clk_d12)); |
| ctech_delay_clkbuf clkbuf_13 (.A(clk_d12), .X(clk_d13)); |
| ctech_delay_clkbuf clkbuf_14 (.A(clk_d13), .X(clk_d14)); |
| ctech_delay_clkbuf clkbuf_15 (.A(clk_d14), .X(clk_d15)); |
| ctech_delay_clkbuf clkbuf_16 (.A(clk_d15), .X(clk_d16)); |
| ctech_delay_clkbuf clkbuf_17 (.A(clk_d16), .X(clk_d17)); |
| ctech_delay_clkbuf clkbuf_18 (.A(clk_d17), .X(clk_d18)); |
| ctech_delay_clkbuf clkbuf_19 (.A(clk_d18), .X(clk_d19)); |
| ctech_delay_clkbuf clkbuf_20 (.A(clk_d19), .X(clk_d20)); |
| ctech_delay_clkbuf clkbuf_21 (.A(clk_d20), .X(clk_d21)); |
| ctech_delay_clkbuf clkbuf_22 (.A(clk_d21), .X(clk_d22)); |
| ctech_delay_clkbuf clkbuf_23 (.A(clk_d22), .X(clk_d23)); |
| ctech_delay_clkbuf clkbuf_24 (.A(clk_d23), .X(clk_d24)); |
| ctech_delay_clkbuf clkbuf_25 (.A(clk_d24), .X(clk_d25)); |
| ctech_delay_clkbuf clkbuf_26 (.A(clk_d25), .X(clk_d26)); |
| ctech_delay_clkbuf clkbuf_27 (.A(clk_d26), .X(clk_d27)); |
| ctech_delay_clkbuf clkbuf_28 (.A(clk_d27), .X(clk_d28)); |
| ctech_delay_clkbuf clkbuf_29 (.A(clk_d28), .X(clk_d29)); |
| ctech_delay_clkbuf clkbuf_30 (.A(clk_d29), .X(clk_d30)); |
| ctech_delay_clkbuf clkbuf_31 (.A(clk_d30), .X(clk_d31)); |
| |
| // first level mux - 16 |
| ctech_mux2x1_2 u_mux_level_00 ( .X (d00) , .A0 (clk_in), .A1(clk_d1), .S(sel[0])); |
| ctech_mux2x1_2 u_mux_level_01 ( .X (d01) , .A0 (clk_d2), .A1(clk_d3), .S(sel[0])); |
| ctech_mux2x1_2 u_mux_level_02 ( .X (d02) , .A0 (clk_d4), .A1(clk_d5), .S(sel[0])); |
| ctech_mux2x1_2 u_mux_level_03 ( .X (d03) , .A0 (clk_d6), .A1(clk_d7), .S(sel[0])); |
| ctech_mux2x1_2 u_mux_level_04 ( .X (d04) , .A0 (clk_d8), .A1(clk_d9), .S(sel[0])); |
| ctech_mux2x1_2 u_mux_level_05 ( .X (d05) , .A0 (clk_d10), .A1(clk_d11), .S(sel[0])); |
| ctech_mux2x1_2 u_mux_level_06 ( .X (d06) , .A0 (clk_d12), .A1(clk_d13), .S(sel[0])); |
| ctech_mux2x1_2 u_mux_level_07 ( .X (d07) , .A0 (clk_d14), .A1(clk_d15), .S(sel[0])); |
| ctech_mux2x1_2 u_mux_level_08 ( .X (d08) , .A0 (clk_d16), .A1(clk_d17), .S(sel[0])); |
| ctech_mux2x1_2 u_mux_level_09 ( .X (d09) , .A0 (clk_d18), .A1(clk_d19), .S(sel[0])); |
| ctech_mux2x1_2 u_mux_level_0a ( .X (d0a) , .A0 (clk_d20), .A1(clk_d21), .S(sel[0])); |
| ctech_mux2x1_2 u_mux_level_0b ( .X (d0b) , .A0 (clk_d22), .A1(clk_d23), .S(sel[0])); |
| ctech_mux2x1_2 u_mux_level_0c ( .X (d0c) , .A0 (clk_d24), .A1(clk_d25), .S(sel[0])); |
| ctech_mux2x1_2 u_mux_level_0d ( .X (d0d) , .A0 (clk_d26), .A1(clk_d27), .S(sel[0])); |
| ctech_mux2x1_2 u_mux_level_0e ( .X (d0e) , .A0 (clk_d28), .A1(clk_d29), .S(sel[0])); |
| ctech_mux2x1_2 u_mux_level_0f ( .X (d0f) , .A0 (clk_d30), .A1(clk_d31), .S(sel[0])); |
| |
| // second level mux - 8 |
| ctech_mux2x1_2 u_mux_level_10 ( .X (d10) , .A0 (d00), .A1(d01), .S(sel[1])); |
| ctech_mux2x1_2 u_mux_level_11 ( .X (d11) , .A0 (d02), .A1(d03), .S(sel[1])); |
| ctech_mux2x1_2 u_mux_level_12 ( .X (d12) , .A0 (d04), .A1(d05), .S(sel[1])); |
| ctech_mux2x1_2 u_mux_level_13 ( .X (d13) , .A0 (d06), .A1(d07), .S(sel[1])); |
| ctech_mux2x1_2 u_mux_level_14 ( .X (d14) , .A0 (d08), .A1(d09), .S(sel[1])); |
| ctech_mux2x1_2 u_mux_level_15 ( .X (d15) , .A0 (d0a), .A1(d0b), .S(sel[1])); |
| ctech_mux2x1_2 u_mux_level_16 ( .X (d16) , .A0 (d0c), .A1(d0d), .S(sel[1])); |
| ctech_mux2x1_2 u_mux_level_17 ( .X (d17) , .A0 (d0e), .A1(d0f), .S(sel[1])); |
| |
| // third level mux - 4 |
| ctech_mux2x1_2 u_mux_level_20 ( .X (d20) , .A0 (d10), .A1(d11), .S(sel[2])); |
| ctech_mux2x1_2 u_mux_level_21 ( .X (d21) , .A0 (d12), .A1(d13), .S(sel[2])); |
| ctech_mux2x1_2 u_mux_level_22 ( .X (d22) , .A0 (d14), .A1(d15), .S(sel[2])); |
| ctech_mux2x1_2 u_mux_level_23 ( .X (d23) , .A0 (d16), .A1(d17), .S(sel[2])); |
| |
| // fourth level mux - 2 |
| ctech_mux2x1_4 u_mux_level_30 ( .X (d30) , .A0 (d20), .A1(d21), .S(sel[3])); |
| ctech_mux2x1_4 u_mux_level_31 ( .X (d31) , .A0 (d22), .A1(d23), .S(sel[3])); |
| |
| // fifth level mux - 1 |
| ctech_mux2x1_4 u_mux_level_40 ( .X (d40) , .A0 (d30), .A1(d31), .S(sel[4])); |
| |
| assign clk_out = d40; |
| |
| endmodule |
