Add Whishbone register to control reset to Marmot
diff --git a/verilog/dv/marmot_test1/Makefile b/verilog/dv/marmot_test1/Makefile
new file mode 100644
index 0000000..3fd0b56
--- /dev/null
+++ b/verilog/dv/marmot_test1/Makefile
@@ -0,0 +1,32 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+
+
diff --git a/verilog/dv/marmot_test1/marmot_test1.c b/verilog/dv/marmot_test1/marmot_test1.c
new file mode 100644
index 0000000..3663169
--- /dev/null
+++ b/verilog/dv/marmot_test1/marmot_test1.c
@@ -0,0 +1,110 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include <defs.h>
+#include <stub.c>
+
+void main()
+{
+ /*
+ IO Control Registers
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
+ Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
+
+
+ Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
+ */
+
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ reg_spi_enable = 1;
+ reg_wb_enable = 1;
+ // reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+ // Configure LA[65] (reset to Marmot) as outputs from the mgmt_soc
+ // Configure other LA probes as inputs to the mgmt_soc
+ //reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
+ //reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
+ //reg_la2_oenb = reg_la2_iena = 0x00000002; // [95:64]
+ //reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
+
+ // Assert reset to Marmot
+ //reg_la2_data = 0x00000002;
+
+ // All GPIO pins are configured to be bi-directional
+ reg_mprj_io_37 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_36 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_35 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_34 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_33 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_32 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_31 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_30 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_29 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_28 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_24 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_23 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_22 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_20 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_3 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Negate reset to Marmot
+ //reg_la2_data = 0x00000000;
+
+ // Negate reset to Marmot
+ reg_mprj_slave = 0x00000001;
+
+ while (1) {}
+}
diff --git a/verilog/dv/marmot_test1/marmot_test1_tb.v b/verilog/dv/marmot_test1/marmot_test1_tb.v
new file mode 100644
index 0000000..90b9c31
--- /dev/null
+++ b/verilog/dv/marmot_test1/marmot_test1_tb.v
@@ -0,0 +1,138 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+module testbench;
+ reg clock;
+ wire clock_wire = clock;
+ reg RSTB;
+ reg CSB;
+
+ reg power1, power2;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+
+`ifdef PULLUP_IO
+ genvar gen_i;
+ generate
+ for (gen_i = 0; gen_i < 38; gen_i = gen_i + 1) begin
+ pullup(mprj_io[gen_i]);
+ end
+ endgenerate
+`endif
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("marmot_test1.vcd");
+ $dumpvars(0, testbench);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (75) begin
+ repeat (1000) @(posedge clock);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD1V8;
+ wire VDD3V3;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1; // Force CSB high.
+ assign mprj_io[0] = 0; // Disable debug mode
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vddio_2 (VDD3V3),
+ .vssio (VSS),
+ .vssio_2 (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda1_2 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa1_2 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock_wire),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("marmot_test1.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(),
+ .io3()
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/marmot/Marmot.v b/verilog/rtl/marmot/Marmot.v
index 4ef3209..3db80a6 100644
--- a/verilog/rtl/marmot/Marmot.v
+++ b/verilog/rtl/marmot/Marmot.v
@@ -135,21 +135,44 @@
wire [31:0] data_arrays_0_ext_ram_rdata7 = 32'd0;
//------------------------------------------------------------------------------
- // Wishbone Slave ports (WB MI A)
- reg wbs_ack_o;
- wire [31:0] wbs_dat_o;
+ // Clock and Reset to MarmotCaravelChip
+ wire clk;
+ wire rst_n;
+ reg [31:0] reg_val; // Wishbone register value
- always @(posedge wb_clk_i) begin
+ assign clk = wb_clk_i;
+ assign rst_n = reg_val[0];
+
+ //------------------------------------------------------------------------------
+ // Wishbone slave port & register
+ wire valid;
+ wire [3:0] wstrb;
+ reg ready;
+
+ assign valid = wbs_cyc_i & wbs_stb_i;
+ assign wstrb = wbs_sel_i & {4{wbs_we_i}};
+ assign wbs_ack_o = ready;
+ assign wbs_dat_o = reg_val;
+
+ always @(posedge clk) begin
if (wb_rst_i) begin
- wbs_ack_o <= 1'b0;
+ reg_val <= 32'h00000000;
+ ready <= 1'b0;
end
else begin
- wbs_ack_o <= wbs_stb_i & wbs_cyc_i;
+ if (valid && !ready) begin
+ ready <= 1'b1;
+ if (wstrb[0]) reg_val[7:0] <= wbs_dat_i[7:0];
+ if (wstrb[1]) reg_val[15:8] <= wbs_dat_i[15:8];
+ if (wstrb[2]) reg_val[23:16] <= wbs_dat_i[23:16];
+ if (wstrb[3]) reg_val[31:24] <= wbs_dat_i[31:24];
+ end
+ else begin
+ ready <= 1'b0;
+ end
end
end
- assign wbs_dat_o = 32'd0;
-
//------------------------------------------------------------------------------
// Logic Analyzer Signals
wire [127:0] la_data_out;
@@ -163,14 +186,6 @@
assign irq = 3'b000;
//------------------------------------------------------------------------------
- // Clock and Reset to MarmotCaravelChip
- wire clk;
- wire rst_n;
-
- assign clk = wb_clk_i;
- assign rst_n = ~wb_rst_i;
-
- //------------------------------------------------------------------------------
// MarmotCaravelChip
MarmotCaravelChip MarmotCaravelChip (
.clk(clk),
