openlane/marmot/pin_order.cfg

#BUS_SORT

#S
wb_.*
wbs_.*
la_.*
irq.*

#N
ram_clk_delay_sel\[.*\]
data_arrays_0_0_ext_ram_rdata2\[.*\]
data_arrays_0_0_ext_ram_addr02\[.*\]
data_arrays_0_0_ext_ram_wdata2\[.*\]
data_arrays_0_0_ext_ram_wmask2\[.*\]
data_arrays_0_0_ext_ram_csb\[2\]
data_arrays_0_0_ext_ram_web2
data_arrays_0_0_ext_ram_csb1\[2\]
data_arrays_0_0_ext_ram_addr12\[.*\]
tag_array_ext_ram_rdata0\[.*\]
tag_array_ext_ram_addr\[.*\]
tag_array_ext_ram_clk
tag_array_ext_ram_wdata\[.*\]
tag_array_ext_ram_wmask\[.*\]
tag_array_ext_ram_csb
tag_array_ext_ram_web
tag_array_ext_ram_csb1
tag_array_ext_ram_addr1\[.*\]
tag_array_ext_ram_rdata1\[.*\]
io_.*\[37\]
io_.*\[36\]
io_.*\[35\]
io_.*\[34\]
io_.*\[33\]
io_.*\[32\]
io_.*\[31\]
io_.*\[30\]
io_.*\[29\]
io_.*\[28\]
io_.*\[27\]
io_.*\[26\]
io_.*\[25\]
io_.*\[24\]
io_.*\[23\]
io_.*\[22\]
io_.*\[21\]
io_.*\[20\]
io_.*\[19\]
io_.*\[18\]
io_.*\[17\]
io_.*\[16\]
io_.*\[15\]
data_arrays_0_0_ext_ram_rdata3\[.*\]
data_arrays_0_0_ext_ram_addr03\[.*\]
data_arrays_0_0_ext_ram_wdata3\[.*\]
data_arrays_0_0_ext_ram_wmask3\[.*\]
data_arrays_0_0_ext_ram_csb\[3\]
data_arrays_0_0_ext_ram_web3
data_arrays_0_0_ext_ram_csb1\[3\]
data_arrays_0_0_ext_ram_addr13\[.*\]

#E
io_.*\[0\]
io_.*\[1\]
io_.*\[2\]
io_.*\[3\]
io_.*\[4\]
io_.*\[5\]
io_.*\[6\]
io_.*\[7\]
io_.*\[8\]
io_.*\[9\]
io_.*\[10\]
io_.*\[11\]
io_.*\[12\]
io_.*\[13\]
io_.*\[14\]

#W
data_arrays_0_0_ext_ram_clk
data_arrays_0_0_ext_ram_rdata0\[.*\]
data_arrays_0_0_ext_ram_addr00\[.*\]
data_arrays_0_0_ext_ram_wdata0\[.*\]
data_arrays_0_0_ext_ram_wmask0\[.*\]
data_arrays_0_0_ext_ram_csb\[0\]
data_arrays_0_0_ext_ram_web0
data_arrays_0_0_ext_ram_csb1\[0\]
data_arrays_0_0_ext_ram_addr10\[.*\]
data_arrays_0_0_ext_ram_rdata1\[.*\]
data_arrays_0_0_ext_ram_addr01\[.*\]
data_arrays_0_0_ext_ram_wdata1\[.*\]
data_arrays_0_0_ext_ram_wmask1\[.*\]
data_arrays_0_0_ext_ram_csb\[1\]
data_arrays_0_0_ext_ram_web1
data_arrays_0_0_ext_ram_csb1\[1\]
data_arrays_0_0_ext_ram_addr11\[.*\]