verilog/includes/includes.rtl.caravel_user_project

# Caravel user project includes
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
-v $(USER_PROJECT_VERILOG)/rtl/user_project.v	     
-v $(USER_PROJECT_VERILOG)/rtl/monitor.v
-v $(USER_PROJECT_VERILOG)/../thirdparty/bextdep/bextdep.v
-v $(USER_PROJECT_VERILOG)/../thirdparty/bextdep/bextdep_pps.v
-v $(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v