commit cc0df795fb3b3f25fc2fa65ea9d8220f125ca75c
author Ruediger Ehlers <mail(insert-current-4-digit-year-here)@ruediger-ehlers.de> Tue Mar 15 13:31:19 2022 +0100
committer Ruediger Ehlers <mail(insert-current-4-digit-year-here)@ruediger-ehlers.de> Tue Mar 15 13:31:19 2022 +0100
tree b2625697622f49239f72877bc11d2bb25f4c9940
parent b5c7f1beef452df5a849cbe9f3c71d7d3514172e

Updated README

README.md

diff --git a/README.md b/README.md
index 6aabd99..870ec4d 100644
--- a/README.md
+++ b/README.md
@@ -266,7 +266,7 @@
 
 # Ideas incorporated and submodules used
 
-The monitoring component uses the [BEXTDEP](https://github.com/cliffordwolf/bextdep Verilog modules for bit extraction by Claire Wolf, licensed under the ISC License.
+The monitoring component uses the [BEXTDEP](https://github.com/cliffordwolf/bextdep) Verilog modules for bit extraction by Claire Wolf, licensed under the ISC License.
 
 All SRAM output is read by a buffer in the monitoring component, which is an aspect whose implementation has been taken from the OpenSRAM test project by the following authors: