diff --git a/README.md b/README.md
index 6aabd99..870ec4d 100644
--- a/README.md
+++ b/README.md
@@ -266,7 +266,7 @@
 
 # Ideas incorporated and submodules used
 
-The monitoring component uses the [BEXTDEP](https://github.com/cliffordwolf/bextdep Verilog modules for bit extraction by Claire Wolf, licensed under the ISC License.
+The monitoring component uses the [BEXTDEP](https://github.com/cliffordwolf/bextdep) Verilog modules for bit extraction by Claire Wolf, licensed under the ISC License.
 
 All SRAM output is read by a buffer in the monitoring component, which is an aspect whose implementation has been taken from the OpenSRAM test project by the following authors: