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foss-eda-tools/third_party/shuttle/sky130/mpw-006/slot-023/b5c7f1beef452df5a849cbe9f3c71d7d3514172e^!/.
commit
b5c7f1beef452df5a849cbe9f3c71d7d3514172e
[log]
author
Ruediger Ehlers <mail(insert-current-4-digit-year-here)@ruediger-ehlers.de>
Tue Mar 15 13:30:41 2022 +0100
committer
Ruediger Ehlers <mail(insert-current-4-digit-year-here)@ruediger-ehlers.de>
Tue Mar 15 13:30:41 2022 +0100
tree
bf167c4a95f142faff142b851e31fd91940482b5
parent
679ede00cbf8db16ac0206ab3911b9356aee8c9a [diff]
Updated README

diff --git a/README.md b/README.md
index 76c1d3d..6aabd99 100644
--- a/README.md
+++ b/README.md

@@ -155,7 +155,7 @@
 
 The monitoring component has been designed under the assumption that it is not programmed directly, but rather the user uses a compiler to generate the content of the SRAMs of the component.
 
-The compiler can be found [https://github.com/progirep/monitor_compiler_for_caraval_monitor on Github] and is licensed under GPLv3. It takes specification files that are already in the form of Boolean formulas to be computed as input:
+The compiler can be found [on Github](https://github.com/progirep/monitor_compiler_for_caraval_monitor) and is licensed under GPLv3. It takes specification files that are already in the form of Boolean formulas to be computed as input:
 
 ```
 STATES a b c
@@ -266,7 +266,7 @@
 
 # Ideas incorporated and submodules used
 
-The monitoring component uses the [BEXTDEP https://github.com/cliffordwolf/bextdep] Verilog modules for bit extraction by Claire Wolf, licensed under the ISC License.
+The monitoring component uses the [BEXTDEP](https://github.com/cliffordwolf/bextdep Verilog modules for bit extraction by Claire Wolf, licensed under the ISC License.
 
 All SRAM output is read by a buffer in the monitoring component, which is an aspect whose implementation has been taken from the OpenSRAM test project by the following authors: