commit	36094f9ea4f83068dcebb4d8b5eb76e7782b5ec3	[log] [tgz]
author	getziadz <getziadz@pm.me>	Thu May 12 15:30:15 2022 -0400
committer	getziadz <getziadz@pm.me>	Thu May 12 15:30:15 2022 -0400
tree	a673f90e9fbec7758c74825f85f5ced65fe2c242
parent	fb87c6f241c1d7d708d69a0e101abd10768b3f5f [diff]

Updated user_project_wrapper gds and GL verilog; deleted user_proj_example files

gds/user_proj_example.gds[Deleted - diff]
gds/user_project_wrapper.gds[Deleted - diff]
gds/user_project_wrapper.gds.gz[Added - diff]
verilog/gl/user_proj_example.v[Deleted - diff]
verilog/gl/user_project_wrapper.v[diff]

5 files changed

tree: a673f90e9fbec7758c74825f85f5ced65fe2c242

README.md

ORDER PRGA Tapeout

This repository is a branch of the caravel_user_project repository, modified for the tapeout of a 512-LUT4 FPGA generated using PRGA.

A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array)

An 8x8 array of CLBs, each containing 8 LUT4s and 8 DFFs and a local programmable crossbar for intra-CLB routing
24-track routing channel with L1 tracks
Capable of implementing 16 out of 30 ISCAS'89 circuits

Design

We used a three level hierarchical design:

1x Caravel user project wrapper
- 1x PRGA top
  - 64x CLB tile