| // SPDX-FileCopyrightText: (c) 2022 Princeton University |
| // SPDX-License-Identifier: BSD-3-Clause |
| // All rights reserved. |
| // |
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| // modification, are permitted provided that the following conditions are met: |
| // |
| // 1. Redistributions of source code must retain the above copyright notice, this |
| // list of conditions and the following disclaimer. |
| // |
| // 2. Redistributions in binary form must reproduce the above copyright notice, |
| // this list of conditions and the following disclaimer in the documentation |
| // and/or other materials provided with the distribution. |
| // |
| // 3. Neither the name of the copyright holder nor the names of its |
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| // this software without specific prior written permission. |
| // |
| // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| |
| module tile_clb ( |
| `ifdef USE_POWER_PINS |
| inout vccd1, // User area 1 1.8V supply |
| inout vssd1, // User area 1 digital ground |
| `endif |
| output wire [11:0] cu_x0y0n_L1 |
| , output wire [11:0] cu_x0y0s_L1 |
| , input wire [11:0] bi_u1y0n_L1 |
| , input wire [11:0] bi_u1y0s_L1 |
| , input wire [0:0] clk |
| , input wire [0:0] prog_clk |
| , input wire [0:0] prog_rst |
| , input wire [0:0] prog_done |
| , input wire [0:0] prog_we |
| , input wire [0:0] prog_din |
| , output wire [0:0] prog_dout |
| , output wire [0:0] prog_we_o |
| ); |
| |
| endmodule |
