my second commit
diff --git a/.spiceinit b/.spiceinit
new file mode 100644
index 0000000..6bc157f
--- /dev/null
+++ b/.spiceinit
@@ -0,0 +1 @@
+set ngbehavior=hs
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..261eeb9
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,201 @@
+ Apache License
+ Version 2.0, January 2004
+ http://www.apache.org/licenses/
+
+ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+ 1. Definitions.
+
+ "License" shall mean the terms and conditions for use, reproduction,
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+ "Contribution" shall mean any work of authorship, including
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+ the conditions stated in this License.
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+ 5. Submission of Contributions. Unless You explicitly state otherwise,
+ any Contribution intentionally submitted for inclusion in the Work
+ by You to the Licensor shall be under the terms and conditions of
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+ 7. Disclaimer of Warranty. Unless required by applicable law or
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+ APPENDIX: How to apply the Apache License to your work.
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+
+ Unless required by applicable law or agreed to in writing, software
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+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..2ac486a
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,141 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+PDK_ROOT?=/usr/local/share/pdk/sky130A
+INPUT_DIRECTORY?=/home/krishna/Comparator_MPW6
+CARAVEL_ROOT?=/home/krishna/Comparator_MPW6
+PRECHECK_ROOT?=/home/krishna/mpw_precheck
+SIM ?= RTL
+
+# Install lite version of caravel, (1): caravel-lite, (0): caravel
+CARAVEL_LITE?=1
+
+ifeq ($(CARAVEL_LITE),1)
+ CARAVEL_NAME := caravel-lite
+ CARAVEL_REPO := https://github.com/efabless/caravel-lite
+ CARAVEL_TAG := 'mpw-5a'
+else
+ CARAVEL_NAME := caravel
+ CARAVEL_REPO := https://github.com/efabless/caravel
+ CARAVEL_TAG := 'mpw-5a'
+endif
+
+# Include Caravel Makefile Targets
+.PHONY: % : check-caravel
+%:
+ export CARAVEL_ROOT=$(CARAVEL_ROOT) && $(MAKE) -f $(CARAVEL_ROOT)/Makefile $@
+
+# Verify Target for running simulations
+.PHONY: verify
+verify:
+ cd ./verilog/dv/ && \
+ export SIM=${SIM} && \
+ $(MAKE) -j$(THREADS)
+
+# Install DV setup
+.PHONY: simenv
+simenv:
+ docker pull efabless/dv_setup:latest
+
+PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
+DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
+TARGET_PATH=$(shell pwd)
+VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
+$(DV_PATTERNS): verify-% : ./verilog/dv/%
+ docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
+ -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
+ -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
+ -e CARAVEL_ROOT=${CARAVEL_ROOT} \
+ -u $(id -u $$USER):$(id -g $$USER) efabless/dv_setup:latest \
+ sh -c $(VERIFY_COMMAND)
+
+# Openlane Makefile Targets
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+.PHONY: $(BLOCKS)
+$(BLOCKS): %:
+ cd openlane && $(MAKE) $*
+
+# Install caravel
+.PHONY: install
+install:
+ @echo "Installing $(CARAVEL_NAME).."
+ @git clone -b $(CARAVEL_TAG) $(CARAVEL_REPO) $(CARAVEL_ROOT)
+
+# Create symbolic links to caravel's main files
+.PHONY: simlink
+simlink: check-caravel
+### Symbolic links relative path to $CARAVEL_ROOT
+ $(eval MAKEFILE_PATH := $(shell realpath --relative-to=openlane $(CARAVEL_ROOT)/openlane/Makefile))
+ mkdir -p openlane
+ cd openlane &&\
+ ln -sf $(MAKEFILE_PATH) Makefile
+
+# Update Caravel
+.PHONY: update_caravel
+update_caravel: check-caravel
+ cd $(CARAVEL_ROOT)/ && git checkout $(CARAVEL_TAG) && git pull
+
+# Uninstall Caravel
+.PHONY: uninstall
+uninstall:
+ rm -rf $(CARAVEL_ROOT)
+
+# Install Openlane
+.PHONY: openlane
+openlane:
+ cd openlane && $(MAKE) openlane
+
+# Install Pre-check
+# Default installs to the user home directory, override by "export PRECHECK_ROOT=<precheck-installation-path>"
+.PHONY: precheck
+precheck:
+ @git clone --depth=1 --branch mpw-5a https://github.com/efabless/mpw_precheck.git $(PRECHECK_ROOT)
+ @docker pull efabless/mpw_precheck:latest
+
+.PHONY: run-precheck
+run-precheck: check-pdk check-precheck
+ $(eval INPUT_DIRECTORY := $(shell pwd))
+ cd $(PRECHECK_ROOT) && \
+ docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_root $(PDK_ROOT)"
+
+# Clean
+.PHONY: clean
+clean:
+ cd ./verilog/dv/ && \
+ $(MAKE) -j$(THREADS) clean
+
+check-caravel:
+ @if [ ! -d "$(CARAVEL_ROOT)" ]; then \
+ echo "Caravel Root: "$(CARAVEL_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+check-precheck:
+ @if [ ! -d "$(PRECHECK_ROOT)" ]; then \
+ echo "Pre-check Root: "$(PRECHECK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+check-pdk:
+ @if [ ! -d "$(PDK_ROOT)" ]; then \
+ echo "PDK Root: "$(PDK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+.PHONY: help
+help:
+ cd $(CARAVEL_ROOT) && $(MAKE) help
+ @$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..96b8e90
--- /dev/null
+++ b/README.md
@@ -0,0 +1,14 @@
+# CMOS dynamic Comparator
+This project is the implementation of a novel dynamic CMOS comparator using Skywater 130nm technology.
+The purpose of this project is to test the open source tools provided with the PDK and to go through all the steps of the analog design flow.
+
+## CMOS Comparator
+The schematic of the comparator test bench was deisgned as follows :
+
+
+
+
+## Simulation
+We simulated the comparator with reference at the negative input and a pulse at the positive input. The output is a digital signal that triggers at every clock pulse depending on the input amplitude.
+
+
diff --git a/docs/Makefile b/docs/Makefile
new file mode 100644
index 0000000..c715218
--- /dev/null
+++ b/docs/Makefile
@@ -0,0 +1,37 @@
+
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+# Minimal makefile for Sphinx documentation
+#
+
+# You can set these variables from the command line, and also
+# from the environment for the first two.
+SPHINXOPTS ?=
+SPHINXBUILD ?= sphinx-build
+SOURCEDIR = source
+BUILDDIR = build
+
+# Put it first so that "make" without argument is like "make help".
+help:
+ @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
+.PHONY: help Makefile
+
+# Catch-all target: route all unknown targets to Sphinx using the new
+# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
+%: Makefile
+ @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
diff --git a/docs/comparator.png b/docs/comparator.png
new file mode 100644
index 0000000..9ef455f
--- /dev/null
+++ b/docs/comparator.png
Binary files differ
diff --git a/docs/environment.yml b/docs/environment.yml
new file mode 100644
index 0000000..2bddf94
--- /dev/null
+++ b/docs/environment.yml
@@ -0,0 +1,23 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+name: caravel-docs
+channels:
+- defaults
+dependencies:
+- python>=3.8
+- pip:
+ - -r file:requirements.txt
diff --git a/docs/requirements.txt b/docs/requirements.txt
new file mode 100644
index 0000000..f5c5383
--- /dev/null
+++ b/docs/requirements.txt
@@ -0,0 +1,6 @@
+git+https://github.com/SymbiFlow/sphinx_materialdesign_theme.git#egg=sphinx-symbiflow-theme
+
+docutils
+sphinx
+sphinx-autobuild
+sphinxcontrib-wavedrom
diff --git a/docs/sim_result.png b/docs/sim_result.png
new file mode 100644
index 0000000..9953050
--- /dev/null
+++ b/docs/sim_result.png
Binary files differ
diff --git a/docs/source/conf.py b/docs/source/conf.py
new file mode 100644
index 0000000..f960f13
--- /dev/null
+++ b/docs/source/conf.py
@@ -0,0 +1,89 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Configuration file for the Sphinx documentation builder.
+#
+# This file only contains a selection of the most common options. For a full
+# list see the documentation:
+# https://www.sphinx-doc.org/en/master/usage/configuration.html
+
+# -- Path setup --------------------------------------------------------------
+
+# If extensions (or modules to document with autodoc) are in another directory,
+# add these directories to sys.path here. If the directory is relative to the
+# documentation root, use os.path.abspath to make it absolute, like shown here.
+#
+# import os
+# import sys
+# sys.path.insert(0, os.path.abspath('.'))
+
+
+# -- Project information -----------------------------------------------------
+
+project = 'CIIC Harness'
+copyright = '2020, efabless'
+author = 'efabless'
+
+
+# -- General configuration ---------------------------------------------------
+
+# Add any Sphinx extension module names here, as strings. They can be
+# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
+# ones.
+extensions = [
+ 'sphinxcontrib.wavedrom',
+ 'sphinx.ext.mathjax',
+ 'sphinx.ext.todo'
+]
+
+# Add any paths that contain templates here, relative to this directory.
+templates_path = ['_templates']
+
+# List of patterns, relative to source directory, that match files and
+# directories to ignore when looking for source files.
+# This pattern also affects html_static_path and html_extra_path.
+exclude_patterns = [
+ 'build',
+ 'Thumbs.db',
+ # Files included in other rst files.
+ 'introduction.rst',
+]
+
+
+# -- Options for HTML output -------------------------------------------------
+"""
+html_theme_options = {
+ 'header_links' : [
+ ("Home", 'index', False, 'home'),
+ ("GitHub", "https://github.com/efabless/caravel", True, 'code'),
+ ],
+ 'hide_symbiflow_links': True,
+ 'license_url' : 'https://www.apache.org/licenses/LICENSE-2.0',
+}
+"""
+# The theme to use for HTML and HTML Help pages. See the documentation for
+# a list of builtin themes.
+#
+html_theme = 'sphinx_rtd_theme'
+
+# Add any paths that contain custom static files (such as style sheets) here,
+# relative to this directory. They are copied after the builtin static files,
+# so a file named "default.css" will overwrite the builtin "default.css".
+html_static_path = ['_static']
+
+todo_include_todos = False
+
+numfig = True
diff --git a/docs/source/index.rst b/docs/source/index.rst
new file mode 100644
index 0000000..b5f711d
--- /dev/null
+++ b/docs/source/index.rst
@@ -0,0 +1,337 @@
+.. raw:: html
+
+ <!---
+ # SPDX-FileCopyrightText: 2020 Efabless Corporation
+ #
+ # Licensed under the Apache License, Version 2.0 (the "License");
+ # you may not use this file except in compliance with the License.
+ # You may obtain a copy of the License at
+ #
+ # http://www.apache.org/licenses/LICENSE-2.0
+ #
+ # Unless required by applicable law or agreed to in writing, software
+ # distributed under the License is distributed on an "AS IS" BASIS,
+ # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ # See the License for the specific language governing permissions and
+ # limitations under the License.
+ #
+ # SPDX-License-Identifier: Apache-2.0
+ -->
+
+Caravel Analog User Project
+===========================
+
+|License| |User CI| |Caravan Build|
+
+Table of contents
+=================
+
+- `Overview <#overview>`__
+- `Install Caravel <#install-caravel>`__
+- `Caravel Integration <#caravel-integration>`__
+
+ - `User Project: Power on Reset <#user-project-power-on-reset>`_
+ - `Verilog Integration <#verilog-integration>`__
+
+- `Running Full Chip Simulation <#running-full-chip-simulation>`__
+- `Analog Design Flow <#analog-design-flow>`__
+- `Other Miscellaneous Targets <#other-miscellaneous-targets>`_
+- `Checklist for Open-MPW
+ Submission <#checklist-for-open-mpw-submission>`__
+
+Overview
+========
+
+This repo contains a sample user project that utilizes the caravan chip (analog version of `caravel <https://github.com/efabless/caravel.git>`__) user space. The user project is a simple power-on-reset that showcases how to make use of caravan's user space utilities like IO pads, logic analyzer probes, and wishbone port. The repo also demonstrates the recommended structure for the open-mpw **analog** projects.
+
+Install Caravel
+===============
+
+To setup caravel, run the following:
+
+.. code:: bash
+
+ # By default, CARAVEL_ROOT is set to $(pwd)/caravel
+ # If you want to install caravel at a different location, run "export CARAVEL_ROOT=<caravel-path>"
+ # Disable submodule installation if needed by, run "export SUBMODULE=0"
+
+ git clone https://github.com/efabless/caravel_user_project_analog.git
+ cd caravel_user_project_analog
+ make install
+
+To update the installed caravel to the latest, run:
+
+.. code:: bash
+
+ make update_caravel
+
+To remove caravel, run
+
+.. code:: bash
+
+ make uninstall
+
+By default
+`caravel-lite <https://github.com/efabless/caravel-lite.git>`__ is
+installed. To install the full version of caravel, run this prior to
+calling make install.
+
+.. code:: bash
+
+ export CARAVEL_LITE=0
+
+Caravel Integration
+=====================
+
+
+User Project: Power on Reset
+----------------------------
+
+This is an example user analog project which breaks out the power-on-reset
+circuit used by the management SoC for power-up behavior so that the circuit
+input and output can be independently controlled and measured.
+
+The power-on-reset circuit itself is a simple, non-temperature-compensated
+analog delay calibrated to 15ms under nominal conditions, with a Schmitt
+trigger inverter to provide hysteresis around the trigger point to provide
+a clean output reset signal.
+
+The circuit provides a single high-voltage (3.3V domain) sense-inverted reset
+signal "porb_h" and complementary low-voltage (1.8V domain) reset signals
+"por_l" and "porb_l".
+
+The only input to the circuit is the 3.3V domain power supply itself.
+
+
+Verilog Integration
+-------------------
+
+You need to create a wrapper around your macro that adheres to the
+template at
+`user\_analog_project\_wrapper <https://github.com/efabless/caravel/blob/master/verilog/rtl/__user_analog_project_wrapper.v>`__.
+The wrapper top module must be named ``user_analog_project_wrapper`` and must
+have the same input and output ports as the analog wrapper template. The wrapper gives access to the
+user space utilities provided by caravel like IO ports, logic analyzer
+probes, and wishbone bus connection to the management SoC.
+
+The verilog modules instantiated in the wrapper module should represent
+the analog project; they need not be more than empty blocks, but it is
+encouraged to write a simple behavioral description of the analog circuit
+in standard verilog, using real-valued wires when necessary. This allows
+the whole system to be run in a verilog testbench and verify the connectivity
+to the padframe and management SoC, even if the testbench C code does nothing
+more than set the mode of each GPIO pin. The example top-level verilog code
+emulates the behavior of the power-on-reset delay after applying a valid
+power supply to the circuit.
+
+
+Building the PDK
+================
+
+You have two options for building the pdk:
+
+- Build the pdk natively.
+
+Make sure you have `Magic VLSI Layout Tool <http://opencircuitdesign.com/magic/index.html>`__ `version 8.3.160 <https://github.com/RTimothyEdwards/magic/tree/8.3.160>`__ installed on your machine before building the pdk.
+
+.. code:: bash
+
+ # set PDK_ROOT to the path you wish to use for the pdk
+ export PDK_ROOT=<pdk-installation-path>
+
+ # you can optionally specify skywater-pdk and open-pdks commit used
+ # by setting and exporting SKYWATER_COMMIT and OPEN_PDKS_COMMIT
+ # if you do not set them, they default to the last verfied commits tested for this project
+
+ make pdk
+
+- Build the pdk using openlane's docker image which has magic installed.
+
+.. code:: bash
+
+ # set PDK_ROOT to the path you wish to use for the pdk
+ export PDK_ROOT=<pdk-installation-path>
+
+ # you can optionally specify skywater-pdk and open-pdks commit used
+ # by setting and exporting SKYWATER_COMMIT and OPEN_PDKS_COMMIT
+ # if you do not set them, they default to the last verfied commits tested for this project
+
+ make pdk-nonnative
+
+Running Full Chip Simulation
+============================
+
+First, you will need to install the simulation environment, by
+
+.. code:: bash
+
+ make simenv
+
+This will pull a docker image with the needed tools installed.
+
+To install the simulation environment locally, refer to `README <https://github.com/efabless/caravel_user_project_analog/blob/main/verilog/dv/README.md>`__
+
+Then, run the RTL and GL simulation by
+
+.. code:: bash
+
+ export PDK_ROOT=<pdk-installation-path>
+ export CARAVEL_ROOT=$(pwd)/caravel
+ # specify simulation mode: RTL/GL
+ export SIM=RTL
+ # Run the mprj_por testbench, make verify-mprj_por
+ make verify-<testbench-name>
+
+The verilog test-benches are under this directory
+`verilog/dv <https://github.com/efabless/caravel_user_project_analog/tree/main/verilog/dv>`__.
+
+
+Analog Design Flow
+===================
+
+The example project uses a very simple analog design flow with schematics
+made with xschem, simulation done using ngspice, layout done with magic,
+and LVS verification done with netgen. Sources for the power-on-reset
+circuit are in the "xschem/" directory, which also includes a schematic
+representing the wrapper with all of its ports, for use in a testbench
+circuit. There are several testbenches in the example, starting from
+tests of the component devices to a full test of the completed project
+inside the wrapper.
+
+There is no automation in this project; the schematic and layout were
+done by hand, including both the power-on-reset block and the power and
+signal routing to the pins on the wrapper.
+
+The power-on-reset circuit itself is simple and is not compensated for
+temperature or voltage variation. When the power supply reaches a
+sufficient level, the voltage divider sets the gate voltage on an nFET
+device to draw a current of nominally 240nA. The testbench
+"threshold_test_tb.spice" does a DC sweep to find the gate voltage that
+produces this value. Next, a cascaded current mirror divides down the
+current by a factor of (roughly) 400. The testbench current_test.spice
+checks the current division value. Finally, the output ~600pA from the
+end of the current mirror is accumulated on a capacitor until the value
+trips the input of the 3.3V Schmitt trigger buffer from the
+sky130_fd_sd_hvl library. The capacitor is sized to peg the nominal
+time to trigger at 15ms. The schematic "example_por_tb.sch" sets up
+the testbench for this timing test.
+
+The output of the Schmitt trigger buffer becomes the high-voltage
+output, and is input to a standard buffer and inverter used as
+level shifters from the 3.3V domain to the 1.8V domain, producing
+complementary low-voltage outputs.
+
+The user project is formed from two power-on-reset circuits, one of
+which is connected to the user area VDDA1 power supply, and the other
+of which is connected to one of the analog I/O pads, used as a power
+supply input and connected to its voltage ESD clamp circuit. The
+3.3V domain outputs are connected directly to GPIO pads through the
+ESD (150 ohm series) connection. The 1.8V domain outputs are connected
+to GPIO pads through the usual I/O connections, with the corresponding
+user output enable (sense inverted) held low to keep the output always
+active.
+
+The C code testbench is in "verilog/dv/mprj_por/mprj_por.c" and only
+sets the GPIO pins used to the correct state (user output function).
+The POR circuit outputs are monitored by the testbench verilog file
+"mprj_por_tb.v" which will fail if the connections are wrong or if
+the behavioral POR verilog does not work as intended.
+
+Note that to properly test this circuit, the GPIO pins have to be
+configured for output to be seen and measured, implying that the
+management SoC power supply must be stable and the C program running
+off of the SPI flash before the user area power supplies are raised.
+
+**NOTE**
+
+ When running spice extraction on the user_analog_project_wrapper layout, it is recommended to use `ext2spice short resistor`.
+ This is to preserve all the different port names in the extracted netlist. In case you have two ports that are electrically shorted
+ in the layout, the `short resistor` option will tell magic not to merge the two shorted ports instead it adds zero-ohm ideal resistors
+ between the net names so that they can be kept as separate nets.
+
+
+Running Open-MPW Precheck Locally
+=================================
+
+You can install the precheck by running
+
+.. code:: bash
+
+ # By default, this install the precheck in your home directory
+ # To change the installtion path, run "export PRECHECK_ROOT=<precheck installation path>"
+ make precheck
+
+This will clone the precheck repo and pull the latest precheck docker image.
+
+
+Then, you can run the precheck by running
+Specify CARAVEL_ROOT before running any of the following,
+
+.. code:: bash
+
+ # export CARAVEL_ROOT=$(pwd)/caravel
+ export CARAVEL_ROOT=<path-to-caravel>
+ make run-precheck
+
+This will run all the precheck checks on your project and will retain the logs under the ``checks`` directory.
+
+Other Miscellaneous Targets
+============================
+
+The makefile provides a number of useful that targets that can run compress, uncompress, and run XOR checks on your design.
+
+Compress gds files and any file larger than 100MB (GH file size limit),
+
+.. code:: bash
+
+ make compress
+
+Uncompress files,
+
+.. code:: bash
+
+ make uncompress
+
+
+Specify ``CARAVEL_ROOT`` before running any of the following,
+
+.. code:: bash
+
+ # export CARAVEL_ROOT=$(pwd)/caravel
+ export CARAVEL_ROOT=<path-to-caravel>
+
+Run XOR check,
+
+.. code:: bash
+
+ make xor-analog-wrapper
+
+Checklist for Open-MPW Submission
+=================================
+
+
+|:heavy_check_mark:| The project repo adheres to the same directory structure in this repo.
+
+|:heavy_check_mark:| The project repo contain info.yaml at the project root.
+
+|:heavy_check_mark:| Top level macro is named ``user_analog_project_wrapper``.
+
+|:heavy_check_mark:| Full Chip Simulation passes for RTL and GL (gate-level)
+
+|:heavy_check_mark:| The project contains a spice netlist for the ``user_analog_project_wrapper`` at netgen/user_analog_project_wrapper.spice
+
+|:heavy_check_mark:| The hardened Macros are LVS and DRC clean
+
+|:heavy_check_mark:| The ``user_analog_project_wrapper`` adheres to empty wrapper template order specified at `user_analog_project_wrapper_empty <https://github.com/efabless/caravel/blob/master/mag/user_analog_project_wrapper_empty.mag>`__
+
+|:heavy_check_mark:| XOR check passes with zero total difference.
+
+|:heavy_check_mark:| Open-MPW-Precheck tool runs successfully.
+
+
+.. |License| image:: https://img.shields.io/badge/License-Apache%202.0-blue.svg
+ :target: https://opensource.org/licenses/Apache-2.0
+.. |User CI| image:: https://github.com/efabless/caravel_user_project_analog/actions/workflows/user_project_ci.yml/badge.svg
+ :target: https://github.com/efabless/caravel_user_project_analog/actions/workflows/user_project_ci.yml
+.. |Caravan Build| image:: https://github.com/efabless/caravel_user_project_analog/actions/workflows/caravan_build.yml/badge.svg
+ :target: https://github.com/efabless/caravel_user_project_analog/actions/workflows/caravan_build.yml
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
new file mode 100644
index 0000000..db23266
--- /dev/null
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/info.yaml b/info.yaml
new file mode 100644
index 0000000..05e4c09
--- /dev/null
+++ b/info.yaml
@@ -0,0 +1,19 @@
+---
+project:
+ description: "CMOS Rail-to-Rail Comparator"
+ foundry: "SkyWater"
+ git_url: "https://github.com/maherbenhouria/caravel_user_project_analog.git"
+ organization: "Efabless"
+ organization_url: "http://efabless.com"
+ owner: "Maher Benhouria"
+ process: "SKY130"
+ project_name: "Caravel"
+ project_id: "00000000"
+ tags:
+ - "Open MPW"
+ - "Comparator"
+ category: "Comparator"
+ top_level_netlist: "caravel/verilog/gl/caravel.v"
+ user_level_netlist: "verilog/rtl/user_project_wrapper.v"
+ version: "1.00"
+ cover_image: "docs/source/_static/caravel_harness.png"
diff --git a/mag/.magicrc b/mag/.magicrc
new file mode 100755
index 0000000..ea1e753
--- /dev/null
+++ b/mag/.magicrc
@@ -0,0 +1,87 @@
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+# Change this to a fixed number for repeatable behavior with GDS writes
+# e.g., "random seed 12345"
+catch {random seed}
+
+# Turn off the scale option on ext2spice or else it conflicts with the
+# scale in the model files.
+ext2spice scale off
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "/usr/local/share/pdk/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/sky130A.tech
+
+
+# load device generator
+source $PDKPATH/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE mag
+}
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_ml_xx_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_sram_macros
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_sram_macros/${MAGTYPE}
+}
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git "a/mag/buffer_1\0430.ext" "b/mag/buffer_1\0430.ext"
new file mode 100644
index 0000000..bedb2ee
--- /dev/null
+++ "b/mag/buffer_1\0430.ext"
@@ -0,0 +1,22 @@
+timestamp 1646324508
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use inv_W2 inv_W2_0 1 0 588 0 1 72
+use inv_W1 inv_W1_0 1 0 100 0 1 72
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "inv_W2_0/VDD" "inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" 116.829
+cap "inv_W2_0/Vin" "inv_W2_0/VDD" 33.1221
+cap "inv_W2_0/Vin" "inv_W2_0/GND" 32.2784
+cap "inv_W2_0/GND" "inv_W1_0/Vin" 2.90674
+cap "inv_W2_0/GND" "inv_W2_0/VDD" -1.77636e-15
+cap "inv_W2_0/Vin" "inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" 23.6443
+cap "inv_W2_0/Vin" "inv_W1_0/Vin" 11.0875
+merge "inv_W1_0/VSUBS" "inv_W2_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W2_0/VSUBS" "VSUBS"
+merge "inv_W1_0/Vout" "inv_W2_0/Vin" -32.196 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1120 -152 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W1_0/w_156_432#" "inv_W2_0/VDD" -52.545 0 0 0 0 -7640 -804 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1000 -140 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W2_0/VDD" "inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#"
+merge "inv_W1_0/GND" "inv_W2_0/GND" -30.482 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1040 -144 0 0 0 0 0 0 0 0 0 0 0 0
diff --git "a/mag/buffer_1\0430.mag" "b/mag/buffer_1\0430.mag"
new file mode 100755
index 0000000..77e1a0a
--- /dev/null
+++ "b/mag/buffer_1\0430.mag"
@@ -0,0 +1,12 @@
+magic
+tech sky130A
+timestamp 1653304099
+use inv_W1#0 inv_W1_0
+timestamp 1645263751
+transform 1 0 50 0 1 36
+box -50 -36 194 439
+use inv_W2#0 inv_W2_0
+timestamp 1653304099
+transform 1 0 294 0 1 36
+box -60 -36 202 439
+<< end >>
diff --git "a/mag/buffer_2\0430.ext" "b/mag/buffer_2\0430.ext"
new file mode 100644
index 0000000..4fd0fc2
--- /dev/null
+++ "b/mag/buffer_2\0430.ext"
@@ -0,0 +1,27 @@
+timestamp 1646326308
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use inv_W16 inv_W16_0 1 0 1708 0 1 0
+use inv_W8 inv_W8_0 1 0 -354 0 1 0
+node "Vout" 15 44.2028 4850 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2576 204 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_1666_500#" 1943 420 1666 500 nw 0 0 0 0 140000 1500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "inv_W16_0/a_82_816#" "inv_W8_0/a_466_816#" 1.35641
+cap "inv_W16_0/a_468_358#" "inv_W16_0/li_n14_902#" 15.1736
+cap "inv_W8_0/a_466_816#" "inv_W16_0/a_468_358#" 16.3371
+cap "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "inv_W16_0/li_n14_902#" 16.9157
+cap "inv_W16_0/li_n14_902#" "inv_W16_0/a_468_358#" 105.456
+cap "inv_W16_0/li_n14_902#" "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" 120.656
+cap "inv_W16_0/li_n14_0#" "inv_W16_0/a_468_358#" -0.171875
+cap "inv_W16_0/a_468_358#" "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" 48.7475
+merge "inv_W8_0/VSUBS" "inv_W16_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W16_0/VSUBS" "VSUBS"
+merge "inv_W8_0/li_512_546#" "inv_W16_0/a_468_358#" -8.3746 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15768 -112 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W8_0/li_354_0#" "inv_W16_0/li_n14_0#" -8.0948 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15184 -108 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W8_0/w_354_500#" "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" 271.488 0 0 0 0 90496 -2304 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "w_1666_500#"
+merge "inv_W8_0/li_354_902#" "inv_W16_0/li_n14_902#" -25.0105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15184 -108 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W16_0/li_128_546#" "Vout" -44.2028 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2576 -204 0 0 0 0 0 0 0 0 0 0 0 0
diff --git "a/mag/buffer_2\0430.mag" "b/mag/buffer_2\0430.mag"
new file mode 100755
index 0000000..12f4f9a
--- /dev/null
+++ "b/mag/buffer_2\0430.mag"
@@ -0,0 +1,18 @@
+magic
+tech sky130A
+timestamp 1646326308
+<< nwell >>
+rect 833 250 1008 450
+<< locali >>
+rect 2425 218 2448 246
+use inv_W8 inv_W8_0
+timestamp 1646325197
+transform 1 0 -177 0 1 0
+box 177 0 1025 477
+use inv_W16 inv_W16_0
+timestamp 1646325283
+transform 1 0 854 0 1 0
+box -7 0 1594 477
+<< labels >>
+rlabel locali 2448 232 2448 232 3 Vout
+<< end >>
diff --git "a/mag/buffer_2\0431.ext" "b/mag/buffer_2\0431.ext"
new file mode 100644
index 0000000..f2669d8
--- /dev/null
+++ "b/mag/buffer_2\0431.ext"
@@ -0,0 +1,27 @@
+timestamp 1646326308
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use inv_W16 inv_W16_0 1 0 1708 0 1 0
+use inv_W8 inv_W8_0 1 0 -354 0 1 0
+node "Vout" 15 44.2028 4850 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2576 204 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_1666_500#" 1943 420 1666 500 nw 0 0 0 0 140000 1500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "inv_W8_0/a_466_816#" "inv_W16_0/a_82_816#" 1.35641
+cap "inv_W16_0/li_n14_902#" "inv_W16_0/a_468_358#" 15.1736
+cap "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "inv_W16_0/li_n14_902#" 16.9157
+cap "inv_W16_0/li_n14_0#" "inv_W16_0/a_468_358#" -0.171875
+cap "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" "inv_W16_0/a_468_358#" 48.7475
+cap "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" "inv_W16_0/li_n14_902#" 120.656
+cap "inv_W8_0/a_466_816#" "inv_W16_0/a_468_358#" 16.3371
+cap "inv_W16_0/li_n14_902#" "inv_W16_0/a_468_358#" 105.456
+merge "inv_W8_0/VSUBS" "inv_W16_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W16_0/VSUBS" "VSUBS"
+merge "inv_W8_0/li_512_546#" "inv_W16_0/a_468_358#" -8.3746 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15768 -112 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W8_0/li_354_0#" "inv_W16_0/li_n14_0#" -8.0948 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15184 -108 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W8_0/w_354_500#" "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" 271.488 0 0 0 0 90496 -2304 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "w_1666_500#"
+merge "inv_W8_0/li_354_902#" "inv_W16_0/li_n14_902#" -25.0105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15184 -108 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W16_0/li_128_546#" "Vout" -44.2028 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2576 -204 0 0 0 0 0 0 0 0 0 0 0 0
diff --git "a/mag/buffer_2\0431.mag" "b/mag/buffer_2\0431.mag"
new file mode 100755
index 0000000..12f4f9a
--- /dev/null
+++ "b/mag/buffer_2\0431.mag"
@@ -0,0 +1,18 @@
+magic
+tech sky130A
+timestamp 1646326308
+<< nwell >>
+rect 833 250 1008 450
+<< locali >>
+rect 2425 218 2448 246
+use inv_W8 inv_W8_0
+timestamp 1646325197
+transform 1 0 -177 0 1 0
+box 177 0 1025 477
+use inv_W16 inv_W16_0
+timestamp 1646325283
+transform 1 0 854 0 1 0
+box -7 0 1594 477
+<< labels >>
+rlabel locali 2448 232 2448 232 3 Vout
+<< end >>
diff --git a/mag/comparator_v6.ext b/mag/comparator_v6.ext
new file mode 100644
index 0000000..02f556c
--- /dev/null
+++ b/mag/comparator_v6.ext
@@ -0,0 +1,226 @@
+timestamp 1653472115
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use preamp_part22 preamp_part22_0 1 0 136 0 1 1320
+use preamp_part12 preamp_part12_0 1 0 712 0 1 -464
+use latch_3 latch_3_0 1 0 88 0 1 2638
+use SR_latch SR_latch_0 1 0 394 0 1 4454
+node "m3_266_1458#" 0 77.49 266 1458 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13416 468 0 0 0 0 0 0
+node "Vp" 0 260.94 1116 -1242 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68400 1056 0 0 0 0 0 0 0 0 0 0
+node "Vn" 0 255.186 296 -1242 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65856 1036 0 0 0 0 0 0 0 0 0 0
+node "m1_544_166#" 5 993.214 544 166 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 122668 4456 0 0 0 0 0 0 0 0 0 0
+node "fp" 5 1460.66 1056 1316 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 265808 6416 0 0 0 0 0 0 0 0 0 0
+node "fn" 7 1269.02 -58 -580 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 163488 6048 0 0 0 0 0 0 0 0 0 0
+node "li_1370_1838#" 194 252.323 1370 1838 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18360 1148 0 0 0 0 0 0 0 0 0 0 0 0
+node "Outn" 16 78.185 1090 4862 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7400 348 0 0 0 0 0 0 0 0 0 0 0 0
+node "Outp" 47 151.78 514 4852 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17816 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "GND" 212 16605.9 -2592 -1934 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9525540 26780 1011624 9920 1011624 9920 1011624 9920 1011624 9920 9257604 17452 0 0
+node "a_1110_1656#" 241 20.277 1110 1656 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 180 72 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_528_1662#" 723 8.409 528 1662 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "CLK" 1202 13941.8 68 360 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 71380 2456 0 0 419052 6372 469332 6760 3973028 32208 2605540 17004 0 0 0 0 0 0
+node "a_1454_2710#" 60 31.608 1454 2710 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 720 108 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_348_2702#" 48 35.385 348 2702 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 900 120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "CLKBAR" 840 6878.66 380 1922 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 113980 2572 0 0 167600 3772 280484 4336 402468 7552 3118900 16536 0 0 0 0 0 0
+node "Dn" 883 3529.87 1048 4532 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32208 1552 0 0 10424 576 547076 13476 0 0 0 0 0 0 0 0 0 0
+node "Dp" 369 3414.05 366 4532 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18488 828 0 0 6068 312 539996 14248 0 0 0 0 0 0 0 0 0 0
+node "a_652_4812#" 181 21.536 652 4812 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 240 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_734_574#" 3613 118.934 734 574 nw 0 0 0 0 33264 768 0 0 11696 480 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14636 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_1110_1902#" 12114 47.244 1110 1902 nw 0 0 0 0 15748 764 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_64_1616#" 14044 1315.59 64 1616 nw 0 0 0 0 424236 4156 0 0 29264 732 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 71792 1720 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 9497 22226.6 -114 3130 nw 0 0 0 0 674228 4476 0 0 11696 480 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9377032 30660 1241164 14616 9215660 22244 1155620 12124 9053420 17424 0 0 0 0
+node "w_782_5052#" 3460 140.755 782 5052 nw 0 0 0 0 44872 884 0 0 17784 612 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21640 756 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "a_86_n1150#" 0 0 86 -1150 ppd 0 0 0 0 0 0 0 0 0 0 12672 496 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16760 636 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_64_1616#" "GND" 1.81319
+cap "fp" "Dn" 1004.44
+cap "fn" "CLK" 481.001
+cap "CLKBAR" "a_528_1662#" 3.41584
+cap "CLKBAR" "GND" 102.027
+cap "Dp" "a_652_4812#" 2.94872
+cap "a_528_1662#" "CLK" 0.242105
+cap "CLKBAR" "VDD" 1041.95
+cap "CLKBAR" "Dp" 334.887
+cap "CLK" "GND" 180.748
+cap "Vn" "CLK" 17.8378
+cap "VDD" "CLK" 282.77
+cap "CLKBAR" "w_64_1616#" 456.174
+cap "Dp" "CLK" 359.008
+cap "CLKBAR" "w_1110_1902#" 232.043
+cap "w_64_1616#" "CLK" 25.3904
+cap "VDD" "fp" 83.6888
+cap "w_782_5052#" "VDD" 88.3518
+cap "VDD" "li_1370_1838#" 198
+cap "CLKBAR" "a_1110_1656#" 2.875
+cap "m3_266_1458#" "CLK" 71.7444
+cap "CLK" "a_1110_1656#" 0.489362
+cap "Vp" "CLK" 19.2233
+cap "VDD" "Dn" 337.145
+cap "Dp" "Dn" 2.89071
+cap "m1_544_166#" "CLK" 74.6341
+cap "CLKBAR" "CLK" 43.913
+cap "m1_544_166#" "fp" 162.117
+cap "fp" "CLK" 535.142
+cap "CLKBAR" "li_1370_1838#" 85.2332
+cap "fn" "Dp" 506.654
+cap "li_1370_1838#" "CLK" 4.34884
+cap "fn" "w_64_1616#" 77.088
+cap "Outn" "Outp" 6.09554
+cap "CLKBAR" "Dn" 340.023
+cap "Dp" "GND" 195.677
+cap "CLK" "Dn" 347.603
+cap "Dp" "VDD" 72.2468
+cap "a_528_1662#" "w_64_1616#" 9.35
+cap "preamp_part12_0/li_n720_n474#" "preamp_part12_0/a_n434_n660#" 12.75
+cap "preamp_part12_0/a_n656_n132#" "preamp_part12_0/li_n718_n356#" 9.40738
+cap "preamp_part12_0/li_n720_n474#" "preamp_part12_0/li_n718_n356#" 8.06358
+cap "preamp_part12_0/li_n720_n474#" "preamp_part12_0/a_n434_n660#" 12.75
+cap "preamp_part12_0/a_n168_604#" "preamp_part12_0/li_954_n358#" 1.07713
+cap "preamp_part12_0/a_80_n658#" "preamp_part12_0/a_388_n660#" -17.4051
+cap "preamp_part12_0/sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n474#" "preamp_part12_0/a_n168_604#" 0.0142912
+cap "preamp_part12_0/a_n434_n660#" "preamp_part12_0/a_80_n658#" -16.2825
+cap "preamp_part12_0/li_n720_n474#" "preamp_part12_0/li_954_n358#" 0.692308
+cap "preamp_part12_0/sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n474#" "preamp_part12_0/a_n434_n660#" 0.692308
+cap "preamp_part12_0/a_n168_604#" "preamp_part12_0/li_954_n358#" 21.7941
+cap "preamp_part12_0/li_954_n358#" "preamp_part12_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n500#" 0.692308
+cap "preamp_part12_0/a_n506_870#" "preamp_part12_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" 7.30889
+cap "preamp_part12_0/a_n506_870#" "preamp_part12_0/a_n656_n132#" 37.3171
+cap "preamp_part12_0/a_n656_n132#" "preamp_part12_0/li_n718_n356#" -4.40089
+cap "preamp_part12_0/w_n720_994#" "preamp_part12_0/a_n656_n132#" 69.7726
+cap "preamp_part12_0/a_n656_n132#" "preamp_part12_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" 33.3
+cap "preamp_part12_0/w_n720_994#" "preamp_part12_0/a_n656_n132#" 16.3235
+cap "preamp_part12_0/a_n656_n132#" "preamp_part12_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" -0.121863
+cap "preamp_part12_0/w_n720_994#" "preamp_part12_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 66.6084
+cap "preamp_part12_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "preamp_part12_0/li_954_n358#" 0.837766
+cap "preamp_part12_0/a_n656_n132#" "preamp_part12_0/a_n506_870#" 80.5263
+cap "preamp_part12_0/a_n656_n132#" "preamp_part12_0/a_706_862#" 1.82456
+cap "preamp_part12_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "preamp_part12_0/sky130_fd_pr__nfet_01v8_RURP52_0/a_n125_n348#" 25.3554
+cap "preamp_part12_0/w_n720_994#" "preamp_part12_0/a_706_862#" 6.08017
+cap "preamp_part12_0/w_n720_994#" "preamp_part12_0/a_n506_870#" 3.31259
+cap "preamp_part12_0/a_706_862#" "preamp_part12_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 44.99
+cap "preamp_part12_0/sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n474#" "preamp_part12_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 4.2676
+cap "preamp_part12_0/a_706_862#" "preamp_part12_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 1.49202
+cap "preamp_part12_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "preamp_part12_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 11.6434
+cap "preamp_part12_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "preamp_part12_0/li_954_n358#" 1.85294
+cap "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_15_n100#" "preamp_part12_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" 26.455
+cap "CLK" "preamp_part12_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" 5.88032
+cap "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_15_n100#" "preamp_part22_0/w_78_306#" 0.942857
+cap "preamp_part12_0/w_n720_994#" "CLK" 4.6516
+cap "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n15_n126#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_15_n100#" 22.3092
+cap "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_15_n100#" "preamp_part22_0/w_78_306#" -19.417
+cap "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_15_n100#" "preamp_part22_0/a_392_716#" 13.1013
+cap "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_15_n100#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#" 16.8442
+cap "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_15_n100#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126#" 160.099
+cap "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126#" "preamp_part22_0/a_392_716#" 23.507
+cap "preamp_part22_0/w_78_306#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_n15_n126#" 29.9521
+cap "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_15_n100#" "latch_3_0/inv_W12_1/GND" 1.49202
+cap "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_15_n100#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126#" 40.233
+cap "preamp_part22_0/w_78_306#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n15_n126#" 8.62731
+cap "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n15_n126#" 0.242105
+cap "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_15_n100#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_n15_n126#" 22.7509
+cap "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_n15_n126#" -0.244681
+cap "preamp_part22_0/w_78_306#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_15_n100#" 84.1635
+cap "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_15_n100#" 153.083
+cap "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_15_n100#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_15_n100#" 12.5837
+cap "latch_3_0/inv_W12_1/GND" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_15_n100#" 1.49202
+cap "preamp_part22_0/w_78_306#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#" 350.005
+cap "preamp_part12_0/w_n720_994#" "CLK" 0.087766
+cap "preamp_part22_0/w_78_306#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_15_n100#" 70.7327
+cap "preamp_part22_0/w_78_306#" "preamp_part22_0/a_392_716#" 66.9678
+cap "preamp_part22_0/w_78_306#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126#" 191.461
+cap "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#" "preamp_part22_0/a_392_716#" 4.97835
+cap "preamp_part12_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" "CLK" 1.49202
+cap "preamp_part12_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" "fp" 1.42109e-14
+cap "preamp_part22_0/w_78_306#" "latch_3_0/inv_W12_1/GND" 5.6958
+cap "latch_3_0/w_n16_492#" "latch_3_0/inv_W12_1/Vin" -16.739
+cap "latch_3_0/inv_W12_1/GND" "latch_3_0/inv_W12_1/Vout" 0.261905
+cap "latch_3_0/inv_W12_1/GND" "latch_3_0/inv_W12_1/Vin" 0.991587
+cap "latch_3_0/w_n16_492#" "latch_3_0/inv_W12_1/VDD" 44.5794
+cap "latch_3_0/w_n16_492#" "latch_3_0/inv_W12_1/Vout" 5.71154
+cap "latch_3_0/inv_W12_1/GND" "latch_3_0/inv_W12_1/Vout" 0.261905
+cap "latch_3_0/inv_W12_1/VDD" "latch_3_0/w_n16_492#" 44.5742
+cap "latch_3_0/inv_W12_1/VDD" "latch_3_0/inv_W12_1/Vout" 1.43617
+cap "latch_3_0/inv_W12_1/VDD" "latch_3_0/a_646_808#" 192.149
+cap "latch_3_0/inv_W12_1/Vout" "latch_3_0/w_n16_492#" -21.7885
+cap "latch_3_0/inv_W12_1/GND" "preamp_part22_0/w_78_306#" 199.078
+cap "latch_3_0/inv_W12_1/GND" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" 1.49202
+cap "latch_3_0/a_646_808#" "latch_3_0/w_n16_492#" -30.386
+cap "latch_3_0/inv_W12_1/Vin" "latch_3_0/w_n16_492#" -152.501
+cap "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#" "preamp_part22_0/w_78_306#" 0.559322
+cap "latch_3_0/inv_W12_1/Vin" "latch_3_0/inv_W12_1/Vout" 12.4717
+cap "latch_3_0/inv_W12_1/GND" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 1.49202
+cap "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126#" "preamp_part22_0/w_78_306#" 4.59725
+cap "latch_3_0/inv_W12_1/Vout" "preamp_part22_0/w_78_306#" 3.20571
+cap "latch_3_0/inv_W12_1/Vin" "preamp_part22_0/w_78_306#" 3.22414
+cap "latch_3_0/inv_W12_0/pmos_2uf2_0/a_33_n130#" "latch_3_0/sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" -32.82
+cap "latch_3_0/inv_W12_0/pmos_2uf2_0/a_33_n130#" "latch_3_0/inv_W12_0/Vout" 28.9979
+cap "latch_3_0/inv_W12_0/pmos_2uf2_0/a_33_n130#" "latch_3_0/inv_W12_0/pmos_2uf2_0/a_n139_n100#" 14.5665
+cap "latch_3_0/inv_W12_0/nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n73_n69#" "li_1370_1838#" 11.5789
+cap "SR_latch_0/GND" "SR_latch_0/a_518_392#" 8.77457
+cap "SR_latch_0/a_518_392#" "SR_latch_0/a_262_508#" -6.09554
+cap "SR_latch_0/a_262_508#" "SR_latch_0/VDD" 33.2791
+cap "SR_latch_0/GND" "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#" 8.2
+cap "SR_latch_0/GND" "SR_latch_0/a_262_508#" 5.93258
+cap "latch_3_0/w_n16_492#" "latch_3_0/a_646_808#" 0.763006
+cap "SR_latch_0/a_518_392#" "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 0.402439
+cap "latch_3_0/a_646_808#" "latch_3_0/inv_W12_1/VDD" 16.3447
+cap "SR_latch_0/GND" "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 26.4556
+cap "SR_latch_0/a_518_392#" "SR_latch_0/VDD" 11.4371
+cap "VDD" "Dn" -26.8
+cap "SR_latch_0/VDD" "SR_latch_0/a_518_392#" 46.8405
+cap "SR_latch_0/VDD" "SR_latch_0/a_262_508#" 63.5933
+cap "SR_latch_0/a_262_508#" "SR_latch_0/a_518_392#" 8.88178e-16
+merge "latch_3_0/a_646_808#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126#" -4082.38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -636128 -812 0 0 -831388 0 -643856 0 336716 -1158 -89784 -2812 0 0 0 0 0 0
+merge "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126#" "a_1110_1656#"
+merge "a_1110_1656#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#"
+merge "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#" "a_528_1662#"
+merge "a_528_1662#" "CLKBAR"
+merge "SR_latch_0/a_518_392#" "Outp" -286.964 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -204740 -476 0 0 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "a_652_4812#" -972.702 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 46120 -260 0 0 55836 0 -230108 -6168 0 0 0 0 0 0 0 0 0 0
+merge "a_652_4812#" "latch_3_0/inv_W12_1/Vin"
+merge "latch_3_0/inv_W12_1/Vin" "a_348_2702#"
+merge "a_348_2702#" "preamp_part12_0/li_n718_n356#"
+merge "preamp_part12_0/li_n718_n356#" "Dp"
+merge "SR_latch_0/VSUBS" "SR_latch_0/GND" -295.861 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 87048 -1836 0 0 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/GND" "latch_3_0/inv_W12_1/GND"
+merge "latch_3_0/inv_W12_1/GND" "latch_3_0/VSUBS"
+merge "latch_3_0/VSUBS" "preamp_part22_0/VSUBS"
+merge "preamp_part22_0/VSUBS" "preamp_part12_0/VSUBS"
+merge "preamp_part12_0/VSUBS" "preamp_part12_0/li_n720_n474#"
+merge "preamp_part12_0/li_n720_n474#" "a_86_n1150#"
+merge "a_86_n1150#" "GND"
+merge "SR_latch_0/VDD" "SR_latch_0/w_0_524#" -2262.53 0 0 0 0 -213908 -9532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 94626 -5228 -35228 -688 -33858 -1092 0 0 0 0 0 0 0 0
+merge "SR_latch_0/w_0_524#" "w_782_5052#"
+merge "w_782_5052#" "latch_3_0/m1_686_734#"
+merge "latch_3_0/m1_686_734#" "latch_3_0/w_n16_492#"
+merge "latch_3_0/w_n16_492#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n73_n100#"
+merge "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n73_n100#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_15_n100#"
+merge "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_15_n100#" "li_1370_1838#"
+merge "li_1370_1838#" "preamp_part12_0/li_n720_1336#"
+merge "preamp_part12_0/li_n720_1336#" "VDD"
+merge "VDD" "preamp_part12_0/w_n720_994#"
+merge "preamp_part12_0/w_n720_994#" "w_734_574#"
+merge "w_734_574#" "w_1110_1902#"
+merge "w_1110_1902#" "preamp_part22_0/li_116_1034#"
+merge "preamp_part22_0/li_116_1034#" "preamp_part22_0/w_78_306#"
+merge "preamp_part22_0/w_78_306#" "w_64_1616#"
+merge "preamp_part12_0/a_388_n660#" "Vp" -100.485 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13208 -784 0 0 0 0 0 0 0 0 0 0
+merge "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_n15_n126#" "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n15_n126#" -812.06 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 109552 -384 0 0 103600 0 95716 -372 525020 -2800 -341600 -2800 0 0 0 0 0 0
+merge "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n15_n126#" "preamp_part12_0/a_706_862#"
+merge "preamp_part12_0/a_706_862#" "preamp_part12_0/a_n506_870#"
+merge "preamp_part12_0/a_n506_870#" "preamp_part12_0/a_80_n658#"
+merge "preamp_part12_0/a_80_n658#" "CLK"
+merge "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#" "latch_3_0/inv_W12_0/pmos_2uf2_0/a_33_n130#" -880.152 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34784 -268 0 0 52520 0 188972 -5770 0 0 0 0 0 0 0 0 0 0
+merge "latch_3_0/inv_W12_0/pmos_2uf2_0/a_33_n130#" "latch_3_0/inv_W12_1/Vout"
+merge "latch_3_0/inv_W12_1/Vout" "a_1454_2710#"
+merge "a_1454_2710#" "preamp_part12_0/li_954_n358#"
+merge "preamp_part12_0/li_954_n358#" "Dn"
+merge "preamp_part22_0/sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_15_n100#" "preamp_part12_0/a_n656_n132#" -75.2968 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30872 -312 0 0 0 0 0 0 0 0 0 0
+merge "preamp_part12_0/a_n656_n132#" "fn"
+merge "preamp_part22_0/a_392_716#" "preamp_part12_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" -1188.36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77556 -6150 0 0 0 0 0 0 0 0 0 0
+merge "preamp_part12_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "preamp_part12_0/a_n168_604#"
+merge "preamp_part12_0/a_n168_604#" "fp"
+merge "fp" "m1_544_166#"
+merge "preamp_part12_0/a_n434_n660#" "Vn" -117.877 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -19400 -776 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/a_262_508#" "Outn" -54.3574 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10008 -220 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/comparator_v6.mag b/mag/comparator_v6.mag
new file mode 100644
index 0000000..7fca7d0
--- /dev/null
+++ b/mag/comparator_v6.mag
@@ -0,0 +1,954 @@
+magic
+tech sky130A
+timestamp 1653472115
+<< nwell >>
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+<< metal5 >>
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+rect -1296 2319 -677 2536
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+rect -1131 2146 -856 2319
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+rect -1296 -669 -677 -522
+rect -1296 -967 -675 -669
+use SR_latch SR_latch_0 ~/mycomparator_copy1/layout/latch
+timestamp 1646810677
+transform 1 0 197 0 1 2227
+box 0 0 436 474
+use latch_3 latch_3_0
+timestamp 1653304099
+transform 1 0 44 0 1 1319
+box -8 0 813 511
+use preamp_part12 preamp_part12_0 ~/Documents/Comparator_MPW6/mag/preamp
+timestamp 1652163895
+transform 1 0 356 0 1 -232
+box -360 -330 510 693
+use preamp_part22 preamp_part22_0 ~/Documents/Comparator_MPW6/mag/preamp
+timestamp 1652012215
+transform 1 0 68 0 1 660
+box 39 151 658 544
+<< labels >>
+rlabel poly 483 1945 483 1945 1 CLKBAR
+rlabel locali 595 2448 595 2448 3 Outn
+rlabel locali 257 2431 257 2431 7 Outp
+rlabel metal1 640 -621 640 -621 5 Vp
+rlabel metal1 220 -621 220 -621 5 Vn
+rlabel metal1 -29 669 -29 669 7 fn
+rlabel metal5 -910 -967 -910 -967 5 GND
+rlabel metal4 1885 -965 1885 -965 5 VDD
+rlabel metal3 395 -965 395 -965 5 CLK
+rlabel metal1 1029 2281 1029 2281 3 Dn
+rlabel metal1 941 672 941 672 3 fp
+rlabel metal1 -159 2279 -159 2279 7 Dp
+<< end >>
diff --git a/mag/comparator_v6.spice b/mag/comparator_v6.spice
new file mode 100644
index 0000000..095097a
--- /dev/null
+++ b/mag/comparator_v6.spice
@@ -0,0 +1,155 @@
+* SPICE3 file created from comparator_v6.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_GJYUB2 a_207_n100# a_81_n126# a_n207_n128# a_15_n100#
++ a_n177_n100# a_111_n100# a_n15_n128# a_n111_n126# w_n305_n200# a_n81_n100# a_177_n128#
++ a_n269_n100# VSUBS
+X0 a_207_n100# a_177_n128# a_111_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=3.1e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_15_n100# a_n15_n128# a_n81_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_111_n100# a_81_n126# a_15_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n81_n100# a_n111_n126# a_n177_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_n177_n100# a_n207_n128# a_n269_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n15_n89# a_15_n69# VSUBS
+X0 a_15_n69# a_n15_n89# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u#0 sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89# sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n73_n69# VSUBS
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n73_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# VSUBS sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2#0 a_n139_n100# a_63_n100# a_33_n130# a_n33_n100# w_n319_n202# a_n63_n130#
++ VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n319_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n139_n100# w_n319_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W12 Vout Vin VDD GND pmos_2uf2_0/w_n319_n202# nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ VSUBS
+Xnmos_1u_0 Vin nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# GND VSUBS nmos_1u#0
+Xpmos_2uf2_0 VDD VDD Vin Vout pmos_2uf2_0/w_n319_n202# Vin VSUBS pmos_2uf2#0
+.ends
+
+.subckt latch_3 a_646_808# inv_W12_1/GND m1_686_734# w_n16_492# inv_W12_1/Vin VSUBS
++ inv_W12_0/Vin
+Xsky130_fd_pr__pfet_01v8_GJYUB2_0 m1_686_734# a_646_808# a_646_808# m1_686_734# m1_686_734#
++ inv_W12_1/VDD a_646_808# a_646_808# w_n16_492# inv_W12_1/VDD a_646_808# inv_W12_1/VDD
++ VSUBS sky130_fd_pr__pfet_01v8_GJYUB2
+Xinv_W12_0 inv_W12_1/Vin inv_W12_0/Vin inv_W12_1/VDD inv_W12_1/GND w_n16_492# inv_W12_1/Vin
++ VSUBS inv_W12
+Xinv_W12_1 inv_W12_0/Vin inv_W12_1/Vin inv_W12_1/VDD inv_W12_1/GND w_n16_492# inv_W12_0/Vin
++ VSUBS inv_W12
+C0 w_n16_492# VSUBS 2.44fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_G6PLX8 a_n129_n500# a_63_n500# a_n221_n474# a_n33_n500#
++ a_n159_n522# a_159_n500# VSUBS
+X0 a_n33_n500# a_n159_n522# a_n129_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_159_n500# a_n159_n522# a_63_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_63_n500# a_n159_n522# a_n33_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n500# a_n159_n522# a_n221_n474# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_RFM3CD#0 a_n73_n100# w_n109_n162# a_15_n100# a_n15_n126#
++ VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# w_n109_n162# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#1 a_15_n500# a_n15_n526# a_n73_n500# VSUBS
+X0 a_15_n500# a_n15_n526# a_n73_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_RURP52 a_33_n370# a_63_n348# a_n63_n370# a_n33_n348#
++ a_n125_n348# VSUBS
+X0 a_n33_n348# a_n63_n370# a_n125_n348# VSUBS sky130_fd_pr__nfet_01v8 ad=4.95e+11p pd=3.66e+06u as=4.65e+11p ps=3.62e+06u w=1.5e+06u l=150000u
+X1 a_63_n348# a_33_n370# a_n33_n348# VSUBS sky130_fd_pr__nfet_01v8 ad=4.65e+11p pd=3.62e+06u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8FHE5N a_n125_n439# a_63_n450# a_n63_n476# a_n33_n450#
++ a_33_n476# VSUBS
+X0 a_63_n450# a_33_n476# a_n33_n450# VSUBS sky130_fd_pr__nfet_01v8 ad=1.528e+11p pd=1.62e+06u as=1.65e+11p ps=1.66e+06u w=500000u l=150000u
+X1 a_n33_n450# a_n63_n476# a_n125_n439# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.528e+11p ps=1.62e+06u w=500000u l=150000u
+.ends
+
+.subckt preamp_part12 li_n720_1336# a_n72_236# a_80_n658# a_n434_n660# m1_n692_n210#
++ a_n506_870# a_388_n660# w_n720_994# li_n720_n474# a_414_256# a_706_862# li_954_n358#
++ VSUBS
+Xsky130_fd_pr__nfet_01v8_G6PLX8_0 a_414_256# a_414_256# m1_n128_n164# m1_n128_n164#
++ a_n434_n660# m1_n128_n164# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__nfet_01v8_G6PLX8_1 a_n72_236# a_n72_236# m1_338_n220# m1_338_n220#
++ a_388_n660# m1_338_n220# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 li_n720_1336# w_n720_994# a_414_256# a_n506_870#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 a_n72_236# w_n720_994# li_n720_1336# a_706_862#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 li_n720_n474# a_414_256# m1_n692_n210# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 li_954_n358# a_n72_236# li_n720_n474# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_RURP52_0 a_n72_236# li_n218_192# a_n72_236# m1_n128_n164#
++ li_n218_192# VSUBS sky130_fd_pr__nfet_01v8_RURP52
+Xsky130_fd_pr__nfet_01v8_RURP52_1 a_414_256# li_n218_192# a_414_256# m1_338_n220#
++ li_n218_192# VSUBS sky130_fd_pr__nfet_01v8_RURP52
+Xsky130_fd_pr__nfet_01v8_8FHE5N_0 li_n720_n474# li_n720_n474# a_80_n658# li_n218_192#
++ a_80_n658# VSUBS sky130_fd_pr__nfet_01v8_8FHE5N
+C0 w_n720_994# VSUBS 2.08fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5E9B w_n161_n200# a_33_n126# a_63_n100# a_n125_n74#
++ a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n126# a_n33_n100# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n125_n74# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt SR_latch a_648_848# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ a_262_508# VDD w_0_524# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 a_648_848# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND a_262_508# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__pfet_01v8_AC5E9B_0 w_0_524# a_262_508# VDD VDD a_648_848# a_262_508#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+Xsky130_fd_pr__pfet_01v8_AC5E9B_1 w_0_524# a_648_848# VDD VDD a_262_508# a_648_848#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+.ends
+
+.subckt preamp_part22 w_78_306# a_392_716# sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#
++ sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126# sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n15_n126#
++ sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_n15_n126# a_810_594# li_116_1034# sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_15_n100#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n73_n100#
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_0 li_214_402# w_78_306# a_810_594# sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_1 a_392_716# w_78_306# li_1016_536# sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_2 sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n73_n100#
++ w_78_306# li_214_402# sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_3 li_1016_536# w_78_306# sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_15_n100#
++ sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 li_214_402# w_78_306# li_116_1034# a_392_716# VSUBS
++ sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 li_116_1034# w_78_306# li_1016_536# a_810_594# VSUBS
++ sky130_fd_pr__pfet_01v8_RFM3CD#0
+C0 w_78_306# VSUBS 2.70fF
+.ends
+
+
+* Top level circuit comparator_v6
+
+Xlatch_3_0 CLKBAR GND VDD VDD Dp GND Dn latch_3
+Xpreamp_part12_0 VDD fp CLK Vn Dp CLK Vp VDD GND fn CLK Dn GND preamp_part12
+XSR_latch_0 Outp Dn Dp Outn VDD VDD GND GND SR_latch
+Xpreamp_part22_0 VDD fp CLKBAR CLKBAR CLK CLK fn VDD VDD GND VDD preamp_part22
+C0 CLKBAR VDD 2.34fF
+C1 VDD GND 29.75fF
+C2 CLK GND 14.11fF
+C3 fp GND 2.32fF
+C4 fn GND 2.31fF
+C5 Dp GND 3.77fF
+C6 Dn GND 3.24fF
+C7 CLKBAR GND 3.04fF
+.end
+
diff --git "a/mag/inv_W2\0430.ext" "b/mag/inv_W2\0430.ext"
new file mode 100644
index 0000000..f3de1ff
--- /dev/null
+++ "b/mag/inv_W2\0430.ext"
@@ -0,0 +1,51 @@
+timestamp 1647355571
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_AC5Z8B#0 sky130_fd_pr__pfet_01v8_AC5Z8B_0 1 0 141 0 1 654
+use sky130_fd_pr__nfet_01v8_XJTKXQ#1 sky130_fd_pr__nfet_01v8_XJTKXQ_0 1 0 219 0 1 182
+node "GND" 207 364.064 -100 -72 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34556 1620 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vout" 91 169.775 202 260 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15108 760 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 120 244.033 -100 828 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24468 1080 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_156_12#" 127 111.727 156 12 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6048 348 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_252_300#" 56 32.867 252 300 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vin" 251 302.04 84 352 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10728 516 0 0 17360 704 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "Vin" "Vout" 81.5294
+cap "a_156_12#" "Vin" 2.89916
+cap "GND" "Vin" 24.9623
+cap "VDD" "Vin" 7.08611
+cap "a_252_300#" "Vin" 9.06061
+cap "GND" "Vout" 18.672
+cap "VDD" "Vout" 3
+cap "a_252_300#" "a_156_12#" 2.875
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" -7.15
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" 6.10637
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" 14.0899
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" 30.4523
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" 11.1195
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" 67.2375
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" 12.3374
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" 42.0143
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/VSUBS" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/VSUBS" "VSUBS"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_63_n100#" "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" -104.04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2828 -468 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_225_n726#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_225_n726#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" "GND"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_33_n122#" "a_252_300#" -117.03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -540 -336 0 0 -896 -144 0 0 0 0 0 0 0 0 0 0 0 0
+merge "a_252_300#" "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n122#"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n122#" "a_156_12#"
+merge "a_156_12#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n290#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n290#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "Vin"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_229_174#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_159_n100#" -147.998 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2968 -560 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_159_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n33_n100#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" "VDD"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_217_n290#" -76.2649 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2360 -348 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_217_n290#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "Vout"
diff --git "a/mag/inv_W2\0430.mag" "b/mag/inv_W2\0430.mag"
new file mode 100755
index 0000000..61116f5
--- /dev/null
+++ "b/mag/inv_W2\0430.mag"
@@ -0,0 +1,44 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647355571
+<< poly >>
+rect 156 436 186 454
+rect 84 416 186 436
+rect 84 370 100 416
+rect 150 370 186 416
+rect 84 352 186 370
+rect 156 298 186 352
+rect 252 300 282 326
+rect 156 12 282 60
+<< polycont >>
+rect 100 370 150 416
+<< locali >>
+rect -100 828 388 878
+rect 106 826 140 828
+rect 84 420 168 436
+rect -100 416 168 420
+rect -100 370 100 416
+rect 150 370 168 416
+rect -100 364 168 370
+rect 84 352 168 364
+rect 202 420 236 454
+rect 202 364 388 420
+rect 202 260 236 364
+rect 106 -20 140 114
+rect 298 -20 332 116
+rect -100 -72 388 -20
+use sky130_fd_pr__nfet_01v8_XJTKXQ#1 sky130_fd_pr__nfet_01v8_XJTKXQ_0
+timestamp 1646324451
+transform 1 0 219 0 1 182
+box -125 -126 125 126
+use sky130_fd_pr__pfet_01v8_AC5Z8B#0 sky130_fd_pr__pfet_01v8_AC5Z8B_0
+timestamp 1646324451
+transform 1 0 141 0 1 654
+box -261 -726 263 224
+<< labels >>
+rlabel locali -100 390 -100 390 7 Vin
+rlabel locali 388 392 388 392 3 Vout
+rlabel locali -100 -46 -100 -46 7 GND
+rlabel locali -100 854 -100 854 7 VDD
+<< end >>
diff --git a/mag/inv_W2.ext b/mag/inv_W2.ext
new file mode 100755
index 0000000..2d1cdde
--- /dev/null
+++ b/mag/inv_W2.ext
@@ -0,0 +1,51 @@
+timestamp 1646324451
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_AC5Z8B sky130_fd_pr__pfet_01v8_AC5Z8B_0 1 0 141 0 1 654
+use sky130_fd_pr__nfet_01v8_XJTKXQ sky130_fd_pr__nfet_01v8_XJTKXQ_0 1 0 219 0 1 182
+node "GND" 217 364.064 -100 -72 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34556 1620 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vout" 95 169.775 202 260 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15108 760 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 126 244.033 -100 828 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24468 1080 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_156_12#" 127 111.727 156 12 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6048 348 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_252_300#" 56 32.867 252 300 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vin" 254 302.04 84 352 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10728 516 0 0 17360 704 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "Vin" "GND" 24.9623
+cap "Vin" "VDD" 7.08611
+cap "Vin" "a_252_300#" 9.06061
+cap "Vout" "GND" 18.672
+cap "VDD" "Vout" 3
+cap "a_252_300#" "a_156_12#" 2.875
+cap "Vin" "Vout" 81.5294
+cap "Vin" "a_156_12#" 2.89916
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" 11.1195
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" 14.0899
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" 6.10637
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" 42.0143
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" 30.4523
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" 12.3374
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" 67.2375
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" -7.15
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/VSUBS" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/VSUBS" "VSUBS"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_63_n100#" "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" -104.04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2828 -468 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_225_n726#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_225_n726#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" "GND"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_33_n122#" "a_252_300#" -117.03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -540 -336 0 0 -896 -144 0 0 0 0 0 0 0 0 0 0 0 0
+merge "a_252_300#" "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n122#"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n122#" "a_156_12#"
+merge "a_156_12#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n290#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n290#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "Vin"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_229_174#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_159_n100#" -147.998 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2968 -560 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_159_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n33_n100#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" "VDD"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_217_n290#" -76.2649 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2360 -348 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_217_n290#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "Vout"
diff --git a/mag/inv_W2.mag b/mag/inv_W2.mag
new file mode 100755
index 0000000..a22a50b
--- /dev/null
+++ b/mag/inv_W2.mag
@@ -0,0 +1,44 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1653304099
+<< poly >>
+rect 156 436 186 454
+rect 84 416 186 436
+rect 84 370 100 416
+rect 150 370 186 416
+rect 84 352 186 370
+rect 156 298 186 352
+rect 252 300 282 326
+rect 156 12 282 60
+<< polycont >>
+rect 100 370 150 416
+<< locali >>
+rect -100 828 388 878
+rect 106 826 140 828
+rect 84 420 168 436
+rect -100 416 168 420
+rect -100 370 100 416
+rect 150 370 168 416
+rect -100 364 168 370
+rect 84 352 168 364
+rect 202 420 236 454
+rect 202 364 388 420
+rect 202 260 236 364
+rect 106 -20 140 114
+rect 298 -20 332 116
+rect -100 -72 388 -20
+use sky130_fd_pr__nfet_01v8_XJTKXQ#0 sky130_fd_pr__nfet_01v8_XJTKXQ_0
+timestamp 1646324451
+transform 1 0 219 0 1 182
+box -125 -126 125 126
+use sky130_fd_pr__pfet_01v8_AC5Z8B#0 sky130_fd_pr__pfet_01v8_AC5Z8B_0
+timestamp 1646324451
+transform 1 0 141 0 1 654
+box -261 -726 263 224
+<< labels >>
+rlabel locali -100 390 -100 390 7 Vin
+rlabel locali 388 392 388 392 3 Vout
+rlabel locali -100 -46 -100 -46 7 GND
+rlabel locali -100 854 -100 854 7 VDD
+<< end >>
diff --git a/mag/latch/.magicrc b/mag/latch/.magicrc
new file mode 100755
index 0000000..ea1e753
--- /dev/null
+++ b/mag/latch/.magicrc
@@ -0,0 +1,87 @@
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+# Change this to a fixed number for repeatable behavior with GDS writes
+# e.g., "random seed 12345"
+catch {random seed}
+
+# Turn off the scale option on ext2spice or else it conflicts with the
+# scale in the model files.
+ext2spice scale off
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "/usr/local/share/pdk/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/sky130A.tech
+
+
+# load device generator
+source $PDKPATH/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE mag
+}
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_ml_xx_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_sram_macros
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_sram_macros/${MAGTYPE}
+}
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/mag/latch/SR_latch.ext b/mag/latch/SR_latch.ext
new file mode 100644
index 0000000..535dc50
--- /dev/null
+++ b/mag/latch/SR_latch.ext
@@ -0,0 +1,67 @@
+timestamp 1646810677
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_AC5E9B sky130_fd_pr__pfet_01v8_AC5E9B_1 1 0 711 0 1 726
+use sky130_fd_pr__pfet_01v8_AC5E9B sky130_fd_pr__pfet_01v8_AC5E9B_0 1 0 229 0 1 724
+use sky130_fd_pr__nfet_01v8_F5U58G sky130_fd_pr__nfet_01v8_F5U58G_1 1 0 669 0 1 250
+use sky130_fd_pr__nfet_01v8_F5U58G sky130_fd_pr__nfet_01v8_F5U58G_0 1 0 273 0 1 248
+node "GND" 289 542.754 0 0 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 55756 2396 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 364 159.564 2 896 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63484 2844 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_518_392#" 532 438.835 518 392 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13888 748 0 0 40980 1532 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_262_508#" 297 224.078 262 508 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9044 440 0 0 44880 1612 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_648_848#" 112 18.0306 648 848 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6804 360 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_166_848#" 112 18.0306 166 848 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6804 360 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_0_524#" 3688 1051.63 0 524 nw 0 0 0 0 350544 2548 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_648_848#" "a_518_392#" 2.85124
+cap "a_648_848#" "VDD" 51.7866
+cap "a_262_508#" "a_518_392#" 404.208
+cap "VDD" "a_262_508#" 52.2896
+cap "VDD" "a_518_392#" 8.97418
+cap "a_648_848#" "w_0_524#" 99
+cap "a_262_508#" "w_0_524#" 259.748
+cap "a_648_848#" "a_166_848#" 3.48876
+cap "w_0_524#" "a_518_392#" 117.472
+cap "a_166_848#" "a_262_508#" 2.89916
+cap "VDD" "w_0_524#" 429.12
+cap "a_166_848#" "VDD" 51.7866
+cap "a_166_848#" "w_0_524#" 99
+cap "GND" "a_262_508#" 11.6389
+cap "GND" "a_518_392#" 41.7112
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#" "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 3.01639
+cap "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n33_n100#" "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 4.46269
+cap "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n63_n130#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 50.8278
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n33_n100#" 43.4924
+cap "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n63_n130#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#" 9.51724
+cap "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n63_n130#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/w_n161_n200#" -78.9324
+cap "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n33_n100#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/w_n161_n200#" -95.631
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n125_n74#" 15.3087
+cap "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n63_n130#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n33_n100#" 2.58427
+cap "sky130_fd_pr__pfet_01v8_AC5E9B_1/w_n161_n200#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n125_n74#" -115.525
+cap "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n63_n130#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n125_n74#" 44.4318
+cap "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n33_n100#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n125_n74#" 66.447
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/VSUBS" "sky130_fd_pr__nfet_01v8_F5U58G_1/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/VSUBS" "sky130_fd_pr__pfet_01v8_AC5E9B_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_0/VSUBS" "sky130_fd_pr__pfet_01v8_AC5E9B_1/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_1/VSUBS" "VSUBS"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/a_15_n100#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" -52.832 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1224 -208 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "GND"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n73_n100#" "sky130_fd_pr__pfet_01v8_AC5E9B_0/a_n33_n100#" -46.0998 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -660 -224 0 0 -2040 -256 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_33_n126#"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_33_n126#" "a_518_392#"
+merge "a_518_392#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n63_n130#"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n63_n130#" "a_648_848#"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_0/a_63_n100#" "sky130_fd_pr__pfet_01v8_AC5E9B_0/a_n125_n74#" -12.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4352 -528 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_0/a_n125_n74#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_63_n100#"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_63_n100#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n125_n74#"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n125_n74#" "VDD"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_0/w_n161_n200#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/w_n161_n200#" -729.024 0 0 0 0 -243008 -2888 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_1/w_n161_n200#" "w_0_524#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "sky130_fd_pr__pfet_01v8_AC5E9B_0/a_33_n126#" -28.5522 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -600 -220 0 0 -1944 -252 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_0/a_33_n126#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n33_n100#"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n33_n100#" "a_262_508#"
+merge "a_262_508#" "sky130_fd_pr__pfet_01v8_AC5E9B_0/a_n63_n130#"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_0/a_n63_n130#" "a_166_848#"
diff --git a/mag/latch/SR_latch.mag b/mag/latch/SR_latch.mag
new file mode 100755
index 0000000..3aa0bc6
--- /dev/null
+++ b/mag/latch/SR_latch.mag
@@ -0,0 +1,64 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646810677
+<< nwell >>
+rect 0 524 872 926
+<< poly >>
+rect 166 848 292 902
+rect 648 848 774 902
+rect 262 576 292 610
+rect 262 566 380 576
+rect 262 520 318 566
+rect 364 520 380 566
+rect 262 508 380 520
+rect 648 474 678 606
+rect 518 450 678 474
+rect 518 410 540 450
+rect 582 434 678 450
+rect 582 410 602 434
+rect 518 392 602 410
+<< polycont >>
+rect 318 520 364 566
+rect 540 410 582 450
+<< locali >>
+rect 2 896 872 948
+rect 114 774 152 896
+rect 308 776 344 896
+rect 596 766 632 896
+rect 790 768 826 896
+rect 212 470 248 652
+rect 696 584 732 696
+rect 306 566 732 584
+rect 306 520 318 566
+rect 364 520 732 566
+rect 306 504 732 520
+rect 212 450 598 470
+rect 212 410 540 450
+rect 582 410 598 450
+rect 212 392 598 410
+rect 212 272 248 392
+rect 696 316 732 504
+rect 298 52 336 184
+rect 606 52 644 194
+rect 0 0 872 52
+use sky130_fd_pr__nfet_01v8_F5U58G sky130_fd_pr__nfet_01v8_F5U58G_0
+timestamp 1646507701
+transform 1 0 273 0 1 248
+box -73 -126 73 126
+use sky130_fd_pr__nfet_01v8_F5U58G sky130_fd_pr__nfet_01v8_F5U58G_1
+timestamp 1646507701
+transform 1 0 669 0 1 250
+box -73 -126 73 126
+use sky130_fd_pr__pfet_01v8_AC5E9B sky130_fd_pr__pfet_01v8_AC5E9B_0
+timestamp 1646507701
+transform 1 0 229 0 1 724
+box -161 -200 161 200
+use sky130_fd_pr__pfet_01v8_AC5E9B sky130_fd_pr__pfet_01v8_AC5E9B_1
+timestamp 1646507701
+transform 1 0 711 0 1 726
+box -161 -200 161 200
+<< labels >>
+rlabel locali 872 934 872 934 3 VDD
+rlabel locali 870 26 870 26 3 GND
+<< end >>
diff --git a/mag/latch/comparator_v5.spice b/mag/latch/comparator_v5.spice
new file mode 100644
index 0000000..f66c2a8
--- /dev/null
+++ b/mag/latch/comparator_v5.spice
@@ -0,0 +1,159 @@
+* SPICE3 file created from comparator_v5.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_G6PLX8 a_n129_n500# a_63_n500# a_n221_n474# a_n33_n500#
++ a_n159_n522# a_159_n500# VSUBS
+X0 a_n33_n500# a_n159_n522# a_n129_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_159_n500# a_n159_n522# a_63_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_63_n500# a_n159_n522# a_n33_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n500# a_n159_n522# a_n221_n474# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_RFM3CD#0 a_n73_n100# w_n109_n162# a_15_n100# a_n15_n126#
++ VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# w_n109_n162# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#1 a_15_n500# a_n15_n526# a_n73_n500# VSUBS
+X0 a_15_n500# a_n15_n526# a_n73_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_RURP52 a_33_n370# a_63_n348# a_n63_n370# a_n33_n348#
++ a_n125_n348# VSUBS
+X0 a_n33_n348# a_n63_n370# a_n125_n348# VSUBS sky130_fd_pr__nfet_01v8 ad=4.95e+11p pd=3.66e+06u as=4.65e+11p ps=3.62e+06u w=1.5e+06u l=150000u
+X1 a_63_n348# a_33_n370# a_n33_n348# VSUBS sky130_fd_pr__nfet_01v8 ad=4.65e+11p pd=3.62e+06u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8FHE5N a_n125_n439# a_63_n450# a_n63_n476# a_n33_n450#
++ a_33_n476# VSUBS
+X0 a_63_n450# a_33_n476# a_n33_n450# VSUBS sky130_fd_pr__nfet_01v8 ad=1.528e+11p pd=1.62e+06u as=1.65e+11p ps=1.66e+06u w=500000u l=150000u
+X1 a_n33_n450# a_n63_n476# a_n125_n439# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.528e+11p ps=1.62e+06u w=500000u l=150000u
+.ends
+
+.subckt preamp_part12 a_n72_236# li_n720_1336# a_80_n658# a_n434_n660# m1_n692_n210#
++ a_n506_870# a_388_n660# w_n720_994# li_n720_n474# a_414_600# a_706_862# li_954_n358#
++ VSUBS
+Xsky130_fd_pr__nfet_01v8_G6PLX8_0 a_414_600# a_414_600# m1_n128_n164# m1_n128_n164#
++ a_n434_n660# m1_n128_n164# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__nfet_01v8_G6PLX8_1 a_n72_236# a_n72_236# m1_338_n220# m1_338_n220#
++ a_388_n660# m1_338_n220# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 li_n720_1336# w_n720_994# a_414_600# a_n506_870#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 a_n72_236# w_n720_994# li_n720_1336# a_706_862#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 li_n720_n474# a_414_600# m1_n692_n210# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 li_954_n358# a_n72_236# li_n720_n474# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_RURP52_0 a_n72_236# li_n218_192# a_n72_236# m1_n128_n164#
++ li_n218_192# VSUBS sky130_fd_pr__nfet_01v8_RURP52
+Xsky130_fd_pr__nfet_01v8_RURP52_1 a_414_600# li_n218_192# a_414_600# m1_338_n220#
++ li_n218_192# VSUBS sky130_fd_pr__nfet_01v8_RURP52
+Xsky130_fd_pr__nfet_01v8_8FHE5N_0 li_n720_n474# li_n720_n474# a_80_n658# li_n218_192#
++ a_80_n658# VSUBS sky130_fd_pr__nfet_01v8_8FHE5N
+C0 w_n720_994# VSUBS 2.08fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5E9B w_n161_n200# a_33_n126# a_63_n100# a_n125_n74#
++ a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n126# a_n33_n100# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n125_n74# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt SR_latch a_648_848# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ a_262_508# VDD w_0_524# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 a_648_848# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND a_262_508# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__pfet_01v8_AC5E9B_0 w_0_524# a_262_508# VDD VDD a_648_848# a_262_508#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+Xsky130_fd_pr__pfet_01v8_AC5E9B_1 w_0_524# a_648_848# VDD VDD a_262_508# a_648_848#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+.ends
+
+.subckt preamp_part22 w_78_306# a_392_716# sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#
++ sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126# sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n15_n126#
++ sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_n15_n126# a_810_594# li_116_1034# sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_15_n100#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n73_n100#
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_0 li_214_402# w_78_306# a_810_594# sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_1 a_392_716# w_78_306# li_1016_536# sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_2 sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n73_n100#
++ w_78_306# li_214_402# sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_3 li_1016_536# w_78_306# sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_15_n100#
++ sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 li_214_402# w_78_306# li_116_1034# a_392_716# VSUBS
++ sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 li_116_1034# w_78_306# li_1016_536# a_810_594# VSUBS
++ sky130_fd_pr__pfet_01v8_RFM3CD#0
+C0 w_78_306# VSUBS 2.70fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_GJYUB2 a_207_n100# a_81_n126# a_n207_n128# a_15_n100#
++ a_n177_n100# a_111_n100# a_n15_n128# a_n111_n126# w_n305_n200# a_n81_n100# a_177_n128#
++ a_n269_n100# VSUBS
+X0 a_207_n100# a_177_n128# a_111_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=3.1e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_15_n100# a_n15_n128# a_n81_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_111_n100# a_81_n126# a_15_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n81_n100# a_n111_n126# a_n177_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_n177_n100# a_n207_n128# a_n269_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n15_n89# a_15_n69# VSUBS
+X0 a_15_n69# a_n15_n89# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89# sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n73_n69# VSUBS
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n73_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# VSUBS sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2 a_n139_n100# a_63_n100# a_33_n130# a_n33_n100# w_n319_n202# a_n63_n130#
++ VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n319_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n139_n100# w_n319_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W12 Vout Vin VDD GND pmos_2uf2_0/w_n319_n202# nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ VSUBS
+Xnmos_1u_0 Vin nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# GND VSUBS nmos_1u
+Xpmos_2uf2_0 VDD VDD Vin Vout pmos_2uf2_0/w_n319_n202# Vin VSUBS pmos_2uf2
+.ends
+
+.subckt latch_2 m1_686_734# a_646_796# inv_W12_1/GND inv_W12_1/Vin w_416_492# VSUBS
++ inv_W12_0/Vin
+Xsky130_fd_pr__pfet_01v8_GJYUB2_0 m1_686_734# a_646_796# a_646_796# m1_686_734# m1_686_734#
++ inv_W12_1/VDD a_646_796# a_646_796# w_416_492# inv_W12_1/VDD a_646_796# inv_W12_1/VDD
++ VSUBS sky130_fd_pr__pfet_01v8_GJYUB2
+Xinv_W12_0 inv_W12_1/Vin inv_W12_0/Vin inv_W12_1/VDD inv_W12_1/GND w_416_492# inv_W12_1/Vin
++ VSUBS inv_W12
+Xinv_W12_1 inv_W12_0/Vin inv_W12_1/Vin inv_W12_1/VDD inv_W12_1/GND w_416_492# inv_W12_0/Vin
++ VSUBS inv_W12
+C0 w_416_492# VSUBS 2.45fF
+.ends
+
+
+* Top level circuit comparator_v5
+
+Xpreamp_part12_0 m1_1056_1316# SR_latch_0/VDD a_68_360# Vn Dp a_68_360# Vp SR_latch_0/VDD
++ SR_latch_0/GND m1_n58_n580# a_68_360# Dn SR_latch_0/GND preamp_part12
+XSR_latch_0 Outp Dn Dp Outn SR_latch_0/VDD SR_latch_0/VDD SR_latch_0/GND SR_latch_0/GND
++ SR_latch
+Xpreamp_part22_0 SR_latch_0/VDD m1_1056_1316# CLKBAR CLKBAR a_68_360# a_68_360# m1_n58_n580#
++ SR_latch_0/VDD SR_latch_0/VDD SR_latch_0/GND SR_latch_0/VDD preamp_part22
+Xlatch_2_0 SR_latch_0/VDD CLKBAR SR_latch_0/GND Dp SR_latch_0/VDD SR_latch_0/GND Dn
++ latch_2
+C0 SR_latch_0/VDD CLKBAR 2.33fF
+C1 Dn SR_latch_0/GND 3.20fF
+C2 Dp SR_latch_0/GND 3.54fF
+C3 CLKBAR SR_latch_0/GND 3.08fF
+C4 SR_latch_0/VDD SR_latch_0/GND 28.97fF
+C5 a_68_360# SR_latch_0/GND 15.50fF
+C6 m1_1056_1316# SR_latch_0/GND 2.18fF
+C7 m1_n58_n580# SR_latch_0/GND 2.56fF
+.end
+
diff --git a/mag/latch/latch.ext b/mag/latch/latch.ext
new file mode 100644
index 0000000..46f2912
--- /dev/null
+++ b/mag/latch/latch.ext
@@ -0,0 +1,38 @@
+timestamp 1652082276
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use inv_W12 inv_W12_0 1 0 624 0 1 72
+use inv_W12 inv_W12_1 1 0 136 0 1 72
+node "GND" 15 51.5546 -12 0 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3432 236 0 0 0 0 0 0 0 0 0 0 0 0
+node "outp" 81 695.319 2 436 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10864 612 96264 2460 0 0 0 0 0 0 0 0 0 0
+node "outn" 118 234.647 2 544 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13908 808 5520 304 0 0 0 0 0 0 0 0 0 0
+node "VDD" 13 45.1375 -12 900 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2700 208 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "outp" "GND" 4.46875
+cap "outp" "outn" 188.769
+cap "outn" "VDD" 4.15094
+cap "inv_W12_0/VDD" "inv_W12_0/Vin" 109.18
+cap "inv_W12_1/nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#" "inv_W12_0/GND" 41.2926
+cap "inv_W12_0/Vout" "inv_W12_0/pmos_2uf2_0/w_n319_n202#" 206.414
+cap "inv_W12_0/Vout" "inv_W12_0/GND" 34.7689
+cap "inv_W12_0/Vout" "inv_W12_0/Vin" 548.805
+cap "inv_W12_0/Vout" "inv_W12_0/VDD" 77.1154
+cap "inv_W12_0/Vout" "inv_W12_0/nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#" 18.1579
+cap "inv_W12_0/Vout" "inv_W12_1/nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#" 18.1579
+cap "inv_W12_0/pmos_2uf2_0/w_n319_n202#" "inv_W12_0/Vin" 156.905
+cap "inv_W12_0/GND" "inv_W12_0/Vin" 4.52419
+cap "inv_W12_0/GND" "inv_W12_0/VDD" -1.77636e-15
+merge "inv_W12_1/VSUBS" "inv_W12_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_0/VSUBS" "VSUBS"
+merge "inv_W12_1/VDD" "inv_W12_0/VDD" -43.7375 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -300 -212 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_0/VDD" "VDD"
+merge "inv_W12_1/GND" "inv_W12_0/GND" -50.8858 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -936 -244 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_0/GND" "GND"
+merge "inv_W12_1/Vin" "inv_W12_0/Vout" -434.638 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3248 -340 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_0/Vout" "outp"
+merge "inv_W12_1/Vout" "inv_W12_0/Vin" -218.968 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1140 -248 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_0/Vin" "outn"
+merge "inv_W12_1/pmos_2uf2_0/w_n319_n202#" "inv_W12_0/pmos_2uf2_0/w_n319_n202#" 0 0 0 0 0 0 -812 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/latch/latch.mag b/mag/latch/latch.mag
new file mode 100755
index 0000000..2b759b2
--- /dev/null
+++ b/mag/latch/latch.mag
@@ -0,0 +1,40 @@
+magic
+tech sky130A
+timestamp 1652082276
+<< error_s >>
+rect 148 41 163 44
+rect 392 41 407 44
+<< locali >>
+rect -6 450 21 475
+rect 1 272 7 291
+rect 35 272 184 291
+rect 500 218 517 246
+rect -6 0 27 26
+<< viali >>
+rect 7 272 35 291
+rect 1 218 41 246
+rect 517 218 557 246
+<< metal1 >>
+rect -5 291 41 298
+rect -5 272 7 291
+rect 35 272 41 291
+rect -5 268 41 272
+rect -6 246 567 253
+rect -6 218 1 246
+rect 41 218 517 246
+rect 557 218 567 246
+rect -6 211 567 218
+use inv_W12 inv_W12_0 ~/Documents/Comparator_MPW6/mag/myinv_layout2
+timestamp 1651483715
+transform 1 0 312 0 1 36
+box -50 -36 194 439
+use inv_W12 inv_W12_1
+timestamp 1651483715
+transform 1 0 68 0 1 36
+box -50 -36 194 439
+<< labels >>
+rlabel metal1 -6 232 -6 232 7 outp
+rlabel locali -6 463 -6 463 7 VDD
+rlabel locali -6 14 -6 14 7 GND
+rlabel metal1 -5 283 -5 283 7 outn
+<< end >>
diff --git a/mag/latch/latch_1u.mag b/mag/latch/latch_1u.mag
new file mode 100644
index 0000000..a784f5e
--- /dev/null
+++ b/mag/latch/latch_1u.mag
@@ -0,0 +1,36 @@
+magic
+tech sky130A
+timestamp 1651469404
+<< locali >>
+rect -6 450 11 475
+rect 0 286 6 305
+rect 34 286 91 305
+rect -6 0 6 26
+<< viali >>
+rect 6 286 34 305
+rect 1 218 41 246
+rect 517 218 557 246
+<< metal1 >>
+rect -6 305 40 312
+rect -6 286 6 305
+rect 34 286 40 305
+rect -6 282 40 286
+rect -6 246 567 253
+rect -6 218 1 246
+rect 41 218 517 246
+rect 557 218 567 246
+rect -6 211 567 218
+use inv_W2 inv_W2_0 ~/mycomparator/layout/myinv_layout2
+timestamp 1647332453
+transform 1 0 60 0 1 36
+box -60 -36 202 439
+use inv_W2 inv_W2_1
+timestamp 1647332453
+transform 1 0 322 0 1 36
+box -60 -36 202 439
+<< labels >>
+rlabel metal1 -6 297 -6 297 7 outn
+rlabel metal1 -6 232 -6 232 7 outp
+rlabel locali -6 463 -6 463 7 VDD
+rlabel locali -6 14 -6 14 7 GND
+<< end >>
diff --git a/mag/latch/latch_2.ext b/mag/latch/latch_2.ext
new file mode 100644
index 0000000..3cc60b7
--- /dev/null
+++ b/mag/latch/latch_2.ext
@@ -0,0 +1,95 @@
+timestamp 1652089661
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_GJYUB2 sky130_fd_pr__pfet_01v8_GJYUB2_0 1 0 853 0 1 690
+use inv_W12 inv_W12_1 1 0 100 0 1 72
+use inv_W12 inv_W12_0 1 0 1206 0 1 72
+node "m1_686_734#" 3 183.32 686 734 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 52592 2412 0 0 0 0 0 0 0 0 0 0
+node "li_474_0#" 157 328.247 474 0 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34840 1444 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1408_254#" 44 67.7969 1408 254 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4148 312 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_302_244#" 37 59.8508 302 244 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3536 276 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_480_436#" 139 187.312 480 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35840 1392 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_192_434#" 75 778.97 192 434 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7224 480 87784 3440 0 0 0 0 0 0 0 0 0 0
+node "li_452_900#" 326 161.747 452 900 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50108 2400 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_1366_66#" 56 32.867 1366 66 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_260_64#" 55 37.903 260 64 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1020 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_646_528#" 554 39.4956 646 528 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14904 900 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_646_808#" 554 39.4956 646 808 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14904 900 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n16_492#" 11438 1959.6 -16 492 nw 0 0 0 0 653200 4816 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "m1_686_734#" "li_452_900#" 156.465
+cap "m1_686_734#" "a_646_808#" 53.206
+cap "li_452_900#" "li_480_436#" 13.252
+cap "a_646_528#" "a_646_808#" 39.0246
+cap "m1_686_734#" "w_n16_492#" 247.667
+cap "li_192_434#" "w_n16_492#" 68.8525
+cap "a_646_528#" "w_n16_492#" 247.5
+cap "li_1408_254#" "li_192_434#" 31.1746
+cap "li_480_436#" "w_n16_492#" 131.2
+cap "li_452_900#" "a_646_808#" 60.1928
+cap "li_452_900#" "w_n16_492#" 344.818
+cap "m1_686_734#" "li_192_434#" 18.1579
+cap "a_646_808#" "w_n16_492#" 247.5
+cap "li_302_244#" "li_192_434#" 18.6614
+cap "li_480_436#" "li_192_434#" 12.6212
+cap "li_474_0#" "li_480_436#" 55
+cap "inv_W12_1/Vin" "inv_W12_1/GND" 123.372
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#" "inv_W12_1/Vout" 46.1642
+cap "inv_W12_1/Vin" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n207_n128#" 12.4249
+cap "inv_W12_1/Vout" "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" -3.3815
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n177_n100#" 196.5
+cap "inv_W12_1/Vin" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#" 68.5137
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n177_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" -98.7684
+cap "inv_W12_1/Vout" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n177_n100#" 53.0501
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#" "inv_W12_1/GND" -1.77636e-15
+cap "inv_W12_1/Vin" "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" -17.0349
+cap "inv_W12_1/Vin" "inv_W12_1/Vout" 86.8557
+cap "inv_W12_1/Vout" "inv_W12_1/GND" -5.89777
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n207_n128#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" -153.45
+cap "inv_W12_1/Vin" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n177_n100#" 19.864
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n207_n128#" "inv_W12_1/Vout" 10.1115
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" -17.0554
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" "inv_W12_0/Vout" -1.06581e-14
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" "inv_W12_0/Vin" -12.1
+cap "inv_W12_0/VDD" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_207_n100#" 14.0512
+cap "inv_W12_0/Vin" "inv_W12_0/Vout" -87.3484
+cap "inv_W12_0/GND" "inv_W12_0/Vout" -4.00714
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" "inv_W12_0/VDD" -38.3565
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_177_n128#" "inv_W12_0/Vin" 4.22145
+cap "inv_W12_0/VDD" "inv_W12_0/Vout" 24.5687
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_207_n100#" "inv_W12_0/Vout" 10.2987
+merge "inv_W12_0/Vout" "inv_W12_0/nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#" -210.297 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -300 -80 0 0 -17084 -788 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_0/nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#" "li_1408_254#"
+merge "li_1408_254#" "inv_W12_1/Vin"
+merge "inv_W12_1/Vin" "a_260_64#"
+merge "a_260_64#" "li_192_434#"
+merge "inv_W12_0/VSUBS" "inv_W12_1/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/VSUBS" "sky130_fd_pr__pfet_01v8_GJYUB2_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/VSUBS" "VSUBS"
+merge "inv_W12_0/VDD" "inv_W12_1/VDD" -95.2014 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21564 -832 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/VDD" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_111_n100#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_111_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n81_n100#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n81_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#" "li_452_900#"
+merge "inv_W12_0/Vin" "a_1366_66#" -109.137 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -120 -68 0 0 11240 -540 0 0 0 0 0 0 0 0 0 0 0 0
+merge "a_1366_66#" "inv_W12_1/Vout"
+merge "inv_W12_1/Vout" "li_480_436#"
+merge "li_480_436#" "inv_W12_1/nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#"
+merge "inv_W12_1/nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#" "li_302_244#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_207_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_15_n100#" 22.446 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3900 -456 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n177_n100#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n177_n100#" "m1_686_734#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_177_n128#" "a_646_528#" -36.957 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1620 -708 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "a_646_528#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_81_n126#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_81_n126#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n15_n128#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n15_n128#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n111_n126#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n111_n126#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n207_n128#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n207_n128#" "a_646_808#"
+merge "inv_W12_0/GND" "inv_W12_1/GND" -54.9172 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9776 -312 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/GND" "li_474_0#"
+merge "inv_W12_0/pmos_2uf2_0/w_n319_n202#" "inv_W12_1/pmos_2uf2_0/w_n319_n202#" -1194.76 0 0 0 0 -398252 -7572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/pmos_2uf2_0/w_n319_n202#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" "w_n16_492#"
diff --git a/mag/latch/latch_2.mag b/mag/latch/latch_2.mag
new file mode 100755
index 0000000..b531bd2
--- /dev/null
+++ b/mag/latch/latch_2.mag
@@ -0,0 +1,58 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1652089661
+<< nwell >>
+rect -16 838 1626 902
+rect -16 552 1178 838
+rect 1248 552 1626 838
+rect -16 492 1626 552
+<< poly >>
+rect 646 808 1060 844
+rect 646 528 1060 564
+rect 260 64 290 98
+rect 1366 66 1396 92
+<< locali >>
+rect 452 900 1140 950
+rect 596 746 630 900
+rect 788 746 822 900
+rect 980 746 1014 900
+rect 480 436 1120 492
+rect 302 244 336 348
+rect 1408 254 1442 376
+rect 474 0 1144 52
+<< viali >>
+rect 192 434 258 498
+rect 1504 438 1564 488
+<< metal1 >>
+rect 686 978 1116 1022
+rect 686 734 732 978
+rect 878 734 924 978
+rect 1070 734 1116 978
+rect 180 498 272 510
+rect 180 434 192 498
+rect 258 434 272 498
+rect 180 420 272 434
+rect 1486 488 1578 506
+rect 1486 438 1504 488
+rect 1564 438 1578 488
+rect 1486 420 1578 438
+rect 198 392 250 420
+rect 1504 392 1566 420
+rect 198 342 1566 392
+use inv_W12 inv_W12_0 ~/Documents/Comparator_MPW6/mag/myinv_layout2
+timestamp 1651483715
+transform 1 0 1206 0 1 72
+box -100 -72 388 878
+use inv_W12 inv_W12_1
+timestamp 1651483715
+transform 1 0 100 0 1 72
+box -100 -72 388 878
+use sky130_fd_pr__pfet_01v8_GJYUB2 sky130_fd_pr__pfet_01v8_GJYUB2_0
+timestamp 1652082874
+transform 1 0 853 0 1 690
+box -439 -200 467 162
+<< labels >>
+rlabel space 1602 26 1602 26 3 GND
+rlabel space 1602 936 1602 936 3 VDD
+<< end >>
diff --git a/mag/latch/latch_22.ext b/mag/latch/latch_22.ext
new file mode 100644
index 0000000..22856eb
--- /dev/null
+++ b/mag/latch/latch_22.ext
@@ -0,0 +1,94 @@
+timestamp 1652081936
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_GJYUB2 sky130_fd_pr__pfet_01v8_GJYUB2_0 1 0 853 0 1 678
+use inv_W12 inv_W12_1 1 0 100 0 1 72
+use inv_W12 inv_W12_0 1 0 1206 0 1 72
+node "m1_686_734#" 3 185.78 686 734 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 52592 2412 0 0 0 0 0 0 0 0 0 0
+node "li_474_0#" 157 328.247 474 0 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34840 1444 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1408_254#" 44 67.7969 1408 254 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4148 312 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_302_244#" 37 59.8508 302 244 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3536 276 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_480_436#" 139 187.312 480 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35840 1392 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_192_434#" 75 847.822 192 434 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7224 480 87784 3440 0 0 0 0 0 0 0 0 0 0
+node "li_452_900#" 326 163.84 452 900 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50108 2400 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_1366_66#" 56 32.867 1366 66 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_260_64#" 55 37.903 260 64 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1020 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_646_518#" 554 39.4956 646 518 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14904 900 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_646_796#" 554 39.4956 646 796 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14904 900 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_416_492#" 3693 917.052 416 492 nw 0 0 0 0 305684 2380 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n76_492#" 4317 243.84 -76 492 nw 0 0 0 0 93580 1336 0 0 20520 636 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21212 656 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_646_796#" "a_646_518#" 39.3471
+cap "li_192_434#" "li_480_436#" 12.6212
+cap "li_474_0#" "li_480_436#" 55
+cap "w_416_492#" "m1_686_734#" 245.207
+cap "a_646_518#" "w_416_492#" 247.5
+cap "a_646_796#" "w_416_492#" 247.5
+cap "li_452_900#" "m1_686_734#" 156.465
+cap "w_416_492#" "li_480_436#" 131.2
+cap "li_452_900#" "a_646_796#" 60.1928
+cap "li_302_244#" "li_192_434#" 18.6614
+cap "li_452_900#" "li_480_436#" 13.252
+cap "m1_686_734#" "li_192_434#" 18.1579
+cap "li_1408_254#" "li_192_434#" 31.1746
+cap "li_452_900#" "w_416_492#" 342.725
+cap "a_646_796#" "m1_686_734#" 53.206
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#" "inv_W12_1/Vout" 52.9276
+cap "inv_W12_1/pmos_2uf2_0/w_n319_n202#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n177_n100#" 454.103
+cap "inv_W12_1/Vin" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n177_n100#" 22.0976
+cap "inv_W12_1/GND" "inv_W12_1/Vin" 75.7248
+cap "inv_W12_1/Vin" "inv_W12_1/pmos_2uf2_0/w_n319_n202#" 50.7717
+cap "inv_W12_1/Vout" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n177_n100#" 59.4027
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n177_n100#" 187.24
+cap "inv_W12_1/Vout" "inv_W12_1/GND" -5.89777
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#" "inv_W12_1/GND" 8.88178e-16
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n207_n124#" "inv_W12_1/pmos_2uf2_0/w_n319_n202#" 33
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#" "inv_W12_1/pmos_2uf2_0/w_n319_n202#" 551.119
+cap "inv_W12_1/Vout" "inv_W12_1/pmos_2uf2_0/w_n319_n202#" 22.0028
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n207_n124#" "inv_W12_1/Vin" 10.3644
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#" "inv_W12_1/Vin" 65.4635
+cap "inv_W12_1/Vout" "inv_W12_1/Vin" 74.1532
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n207_n124#" "inv_W12_1/Vout" 4.77735
+cap "inv_W12_0/pmos_2uf2_0/w_n319_n202#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_111_n100#" -2.46
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_81_n124#" "inv_W12_0/Vin" 4.77735
+cap "inv_W12_0/GND" "inv_W12_0/Vout" 43.6399
+cap "inv_W12_0/pmos_2uf2_0/w_n319_n202#" "inv_W12_0/Vout" 25.4372
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_207_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_111_n100#" 19.3831
+cap "inv_W12_0/Vout" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_207_n100#" 10.9631
+cap "inv_W12_0/Vout" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_111_n100#" 30.1932
+cap "inv_W12_0/Vout" "inv_W12_0/Vin" 22.1391
+merge "inv_W12_0/Vout" "inv_W12_0/nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#" -359.356 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -300 -80 0 0 -14924 -788 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_0/nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#" "li_1408_254#"
+merge "li_1408_254#" "inv_W12_1/Vin"
+merge "inv_W12_1/Vin" "a_260_64#"
+merge "a_260_64#" "li_192_434#"
+merge "inv_W12_0/VSUBS" "inv_W12_1/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/VSUBS" "sky130_fd_pr__pfet_01v8_GJYUB2_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/VSUBS" "VSUBS"
+merge "inv_W12_0/VDD" "inv_W12_1/VDD" -598.519 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13188 -760 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/VDD" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_111_n100#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_111_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n81_n100#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n81_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#" "li_452_900#"
+merge "inv_W12_0/Vin" "a_1366_66#" -47.7412 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 -68 0 0 7880 -540 0 0 0 0 0 0 0 0 0 0 0 0
+merge "a_1366_66#" "inv_W12_1/Vout"
+merge "inv_W12_1/Vout" "li_480_436#"
+merge "li_480_436#" "inv_W12_1/nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#"
+merge "inv_W12_1/nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#" "li_302_244#"
+merge "inv_W12_0/pmos_2uf2_0/w_n319_n202#" "inv_W12_1/pmos_2uf2_0/w_n319_n202#" -192.984 0 0 0 0 -64328 -3136 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/pmos_2uf2_0/w_n319_n202#" "w_416_492#"
+merge "w_416_492#" "w_n76_492#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_207_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_15_n100#" -512.701 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8460 -384 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n177_n100#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n177_n100#" "m1_686_734#"
+merge "inv_W12_0/GND" "inv_W12_1/GND" -57.8032 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6656 -312 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/GND" "li_474_0#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_177_n124#" "a_646_518#" -198 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -600 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "a_646_518#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_81_n124#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_81_n124#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n15_n124#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n15_n124#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n111_n124#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n111_n124#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n207_n124#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n207_n124#" "a_646_796#"
diff --git a/mag/latch/latch_22.mag b/mag/latch/latch_22.mag
new file mode 100644
index 0000000..c5de4a2
--- /dev/null
+++ b/mag/latch/latch_22.mag
@@ -0,0 +1,69 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1652081936
+<< nwell >>
+rect -76 882 124 898
+rect -76 868 98 882
+rect -76 514 160 868
+rect 450 522 1198 900
+rect -76 492 124 514
+rect 416 512 1198 522
+rect 416 492 1172 512
+<< nsubdiff >>
+rect -22 780 68 804
+rect -22 576 68 600
+<< nsubdiffcont >>
+rect -22 600 68 780
+<< poly >>
+rect 646 796 1060 832
+rect 646 518 1060 554
+rect 260 64 290 98
+rect 1366 66 1396 92
+<< locali >>
+rect 452 900 1140 950
+rect -22 780 68 796
+rect -48 642 -22 724
+rect 596 746 630 900
+rect 788 746 822 900
+rect 980 746 1014 900
+rect -22 584 68 600
+rect 480 436 1120 492
+rect 302 244 336 348
+rect 1408 254 1442 376
+rect 474 0 1144 52
+<< viali >>
+rect 192 434 258 498
+rect 1504 438 1564 488
+<< metal1 >>
+rect 686 978 1116 1022
+rect 686 734 732 978
+rect 878 734 924 978
+rect 1070 734 1116 978
+rect 180 498 272 510
+rect 180 434 192 498
+rect 258 434 272 498
+rect 180 420 272 434
+rect 1486 488 1578 506
+rect 1486 438 1504 488
+rect 1564 438 1578 488
+rect 1486 420 1578 438
+rect 198 392 250 420
+rect 1504 392 1566 420
+rect 198 342 1566 392
+use inv_W12 inv_W12_0 ~/Documents/Comparator_MPW6/mag/myinv_layout2
+timestamp 1651483715
+transform 1 0 1206 0 1 72
+box -100 -72 388 878
+use inv_W12 inv_W12_1
+timestamp 1651483715
+transform 1 0 100 0 1 72
+box -100 -72 388 878
+use sky130_fd_pr__pfet_01v8_GJYUB2 sky130_fd_pr__pfet_01v8_GJYUB2_0
+timestamp 1651918812
+transform 1 0 853 0 1 678
+box -305 -136 305 136
+<< labels >>
+rlabel space 1602 26 1602 26 3 GND
+rlabel space 1602 936 1602 936 3 VDD
+<< end >>
diff --git a/mag/latch/sky130A.magicrc b/mag/latch/sky130A.magicrc
new file mode 100755
index 0000000..ea1e753
--- /dev/null
+++ b/mag/latch/sky130A.magicrc
@@ -0,0 +1,87 @@
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+# Change this to a fixed number for repeatable behavior with GDS writes
+# e.g., "random seed 12345"
+catch {random seed}
+
+# Turn off the scale option on ext2spice or else it conflicts with the
+# scale in the model files.
+ext2spice scale off
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "/usr/local/share/pdk/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/sky130A.tech
+
+
+# load device generator
+source $PDKPATH/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE mag
+}
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_ml_xx_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_sram_macros
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_sram_macros/${MAGTYPE}
+}
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.ext b/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.ext
new file mode 100644
index 0000000..431a549
--- /dev/null
+++ b/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.ext
@@ -0,0 +1,13 @@
+timestamp 1646507701
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n100#" 470 -13.94 15 -100 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n100#" 470 -13.94 -73 -100 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n126#" 405 49.234 -15 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7560 564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n100#" "a_n73_n100#" 253.905
+device msubckt sky130_fd_pr__nfet_01v8 -15 -100 -14 -99 l=30 w=200 "VSUBS" "a_n15_n126#" 60 0 "a_n73_n100#" 200 0 "a_15_n100#" 200 0
diff --git a/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.mag b/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.mag
new file mode 100755
index 0000000..88fc7a8
--- /dev/null
+++ b/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646507701
+<< nmos >>
+rect -15 -100 15 100
+<< ndiff >>
+rect -73 62 -15 100
+rect -73 -62 -61 62
+rect -27 -62 -15 62
+rect -73 -100 -15 -62
+rect 15 62 73 100
+rect 15 -62 27 62
+rect 61 -62 73 62
+rect 15 -100 73 -62
+<< ndiffc >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< poly >>
+rect -15 100 15 126
+rect -15 -126 15 -100
+<< locali >>
+rect -61 62 -27 78
+rect -61 -78 -27 -62
+rect 27 62 61 78
+rect 27 -78 61 -62
+<< viali >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< metal1 >>
+rect -67 62 -21 74
+rect -67 -62 -61 62
+rect -27 -62 -21 62
+rect -67 -74 -21 -62
+rect 21 62 67 74
+rect 21 -62 27 62
+rect 61 -62 67 62
+rect 21 -74 67 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 1 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git "a/mag/latch/sky130_fd_pr__nfet_01v8_XJTKXQ\0431.ext" "b/mag/latch/sky130_fd_pr__nfet_01v8_XJTKXQ\0431.ext"
new file mode 100755
index 0000000..150e91a
--- /dev/null
+++ "b/mag/latch/sky130_fd_pr__nfet_01v8_XJTKXQ\0431.ext"
@@ -0,0 +1,19 @@
+timestamp 1646324451
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n100#" 456 -13.94 63 -100 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 420 -13.94 -33 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n125_n74#" 456 -13.94 -125 -74 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_33_n122#" 392 44.198 33 -122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7320 548 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n63_n122#" 392 44.198 -63 -122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7320 548 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n100#" "a_63_n100#" 216.232
+cap "a_n125_n74#" "a_63_n100#" 78.1987
+cap "a_n125_n74#" "a_n33_n100#" 216.232
+cap "a_n63_n122#" "a_33_n122#" 15.3333
+device msubckt sky130_fd_pr__nfet_01v8 33 -100 34 -99 l=30 w=200 "VSUBS" "a_33_n122#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -63 -100 -62 -99 l=30 w=200 "VSUBS" "a_n63_n122#" 60 0 "a_n125_n74#" 200 0 "a_n33_n100#" 200 0
diff --git "a/mag/latch/sky130_fd_pr__nfet_01v8_XJTKXQ\0431.mag" "b/mag/latch/sky130_fd_pr__nfet_01v8_XJTKXQ\0431.mag"
new file mode 100755
index 0000000..9e1b853
--- /dev/null
+++ "b/mag/latch/sky130_fd_pr__nfet_01v8_XJTKXQ\0431.mag"
@@ -0,0 +1,67 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646324451
+<< error_p >>
+rect -63 122 -33 126
+rect 33 122 63 126
+rect -63 -126 -33 -122
+rect 33 -126 63 -122
+<< nmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< ndiff >>
+rect -121 74 -63 100
+rect -125 62 -63 74
+rect -125 -62 -113 62
+rect -79 -62 -63 62
+rect -125 -74 -63 -62
+rect -121 -100 -63 -74
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 74 121 100
+rect 63 62 125 74
+rect 63 -62 79 62
+rect 113 -62 125 62
+rect 63 -74 125 -62
+rect 63 -100 121 -74
+<< ndiffc >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< poly >>
+rect -63 100 -33 122
+rect 33 100 63 122
+rect -63 -122 -33 -100
+rect 33 -122 63 -100
+<< locali >>
+rect -113 62 -79 78
+rect -113 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+<< viali >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< metal1 >>
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.ext b/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.ext
new file mode 100644
index 0000000..0985d14
--- /dev/null
+++ b/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.ext
@@ -0,0 +1,28 @@
+timestamp 1646503715
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_111_n100#" 711 -177.94 111 -100 pdif 0 0 0 0 0 0 0 0 0 0 12400 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_15_n100#" 672 -177.94 15 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n81_n100#" 672 -177.94 -81 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n173_n100#" 711 -177.94 -173 -100 pdif 0 0 0 0 0 0 0 0 0 0 12400 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n111_n158#" 1654 51.4524 -111 -158 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37416 2332 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n789_n196#" 6483 1998.88 -789 -196 nw 0 0 0 0 666292 4024 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_n789_n196#" "a_111_n100#" 200.332
+cap "a_n111_n158#" "w_n789_n196#" 311.3
+cap "a_n173_n100#" "a_n81_n100#" 290.71
+cap "a_n173_n100#" "w_n789_n196#" 200.332
+cap "a_n81_n100#" "w_n789_n196#" 200.332
+cap "a_15_n100#" "a_111_n100#" 290.71
+cap "a_15_n100#" "a_n173_n100#" 105.087
+cap "a_15_n100#" "a_n81_n100#" 290.71
+cap "a_15_n100#" "w_n789_n196#" 200.332
+cap "a_n173_n100#" "a_111_n100#" 64.2137
+cap "a_n81_n100#" "a_111_n100#" 105.087
+device msubckt sky130_fd_pr__pfet_01v8 81 -100 82 -99 l=30 w=200 "w_n789_n196#" "a_n111_n158#" 60 0 "a_15_n100#" 200 0 "a_111_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -15 -100 -14 -99 l=30 w=200 "w_n789_n196#" "a_n111_n158#" 60 0 "a_n81_n100#" 200 0 "a_15_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -111 -100 -110 -99 l=30 w=200 "w_n789_n196#" "a_n111_n158#" 60 0 "a_n173_n100#" 200 0 "a_n81_n100#" 200 0
diff --git a/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.mag b/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.mag
new file mode 100755
index 0000000..f6c91f5
--- /dev/null
+++ b/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.mag
@@ -0,0 +1,77 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646503715
+<< nwell >>
+rect -789 -196 805 222
+<< pmos >>
+rect -111 -100 -81 100
+rect -15 -100 15 100
+rect 81 -100 111 100
+<< pdiff >>
+rect -173 88 -111 100
+rect -173 -88 -161 88
+rect -127 -88 -111 88
+rect -173 -100 -111 -88
+rect -81 88 -15 100
+rect -81 -88 -65 88
+rect -31 -88 -15 88
+rect -81 -100 -15 -88
+rect 15 88 81 100
+rect 15 -88 31 88
+rect 65 -88 81 88
+rect 15 -100 81 -88
+rect 111 88 173 100
+rect 111 -88 127 88
+rect 161 -88 173 88
+rect 111 -100 173 -88
+<< pdiffc >>
+rect -161 -88 -127 88
+rect -65 -88 -31 88
+rect 31 -88 65 88
+rect 127 -88 161 88
+<< poly >>
+rect -111 124 111 158
+rect -111 100 -81 124
+rect -15 100 15 124
+rect 81 100 111 124
+rect -111 -124 -81 -100
+rect -15 -124 15 -100
+rect 81 -124 111 -100
+rect -111 -158 111 -124
+<< locali >>
+rect -161 88 -127 104
+rect -161 -104 -127 -88
+rect -65 88 -31 104
+rect -65 -104 -31 -88
+rect 31 88 65 104
+rect 31 -104 65 -88
+rect 127 88 161 104
+rect 127 -104 161 -88
+<< viali >>
+rect -161 -88 -127 88
+rect -65 -88 -31 88
+rect 31 -88 65 88
+rect 127 -88 161 88
+<< metal1 >>
+rect -167 88 -121 100
+rect -167 -88 -161 88
+rect -127 -88 -121 88
+rect -167 -100 -121 -88
+rect -71 88 -25 100
+rect -71 -88 -65 88
+rect -31 -88 -25 88
+rect -71 -100 -25 -88
+rect 25 88 71 100
+rect 25 -88 31 88
+rect 65 -88 71 88
+rect 25 -100 71 -88
+rect 121 88 167 100
+rect 121 -88 127 88
+rect 161 -88 167 88
+rect 121 -100 167 -88
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 3 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.ext b/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.ext
new file mode 100644
index 0000000..66ae58c
--- /dev/null
+++ b/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.ext
@@ -0,0 +1,25 @@
+timestamp 1646507701
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n100#" 712 -171.38 63 -100 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 653 -171.38 -33 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n125_n74#" 712 -171.38 -125 -74 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_33_n126#" 411 4.452 33 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7680 572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n63_n130#" 411 4.452 -63 -130 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7680 572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n161_n200#" 2895 364.512 -161 -200 nw 0 0 0 0 121504 1444 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n125_n74#" "a_n33_n100#" 216.232
+cap "a_63_n100#" "a_n125_n74#" 78.1987
+cap "a_63_n100#" "a_n33_n100#" 216.232
+cap "a_33_n126#" "w_n161_n200#" 47.3
+cap "a_n125_n74#" "w_n161_n200#" 157.44
+cap "a_33_n126#" "a_n63_n130#" 18.1212
+cap "w_n161_n200#" "a_n33_n100#" 157.44
+cap "a_63_n100#" "w_n161_n200#" 157.44
+cap "a_n63_n130#" "w_n161_n200#" 47.3
+device msubckt sky130_fd_pr__pfet_01v8 33 -100 34 -99 l=30 w=200 "w_n161_n200#" "a_33_n126#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -63 -100 -62 -99 l=30 w=200 "w_n161_n200#" "a_n63_n130#" 60 0 "a_n125_n74#" 200 0 "a_n33_n100#" 200 0
diff --git a/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.mag b/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.mag
new file mode 100755
index 0000000..99c3b1d
--- /dev/null
+++ b/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.mag
@@ -0,0 +1,66 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646507701
+<< nwell >>
+rect -65 162 161 200
+rect -161 -162 161 162
+rect -161 -200 65 -162
+<< pmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< pdiff >>
+rect -121 74 -63 100
+rect -125 62 -63 74
+rect -125 -62 -113 62
+rect -79 -62 -63 62
+rect -125 -74 -63 -62
+rect -121 -100 -63 -74
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 74 121 100
+rect 63 62 125 74
+rect 63 -62 79 62
+rect 113 -62 125 62
+rect 63 -74 125 -62
+rect 63 -100 121 -74
+<< pdiffc >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< poly >>
+rect -63 100 -33 126
+rect 33 100 63 130
+rect -63 -130 -33 -100
+rect 33 -126 63 -100
+<< locali >>
+rect -113 62 -79 78
+rect -113 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+<< viali >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< metal1 >>
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git "a/mag/latch/sky130_fd_pr__pfet_01v8_AC5Z8B\0430.ext" "b/mag/latch/sky130_fd_pr__pfet_01v8_AC5Z8B\0430.ext"
new file mode 100755
index 0000000..7d564af
--- /dev/null
+++ "b/mag/latch/sky130_fd_pr__pfet_01v8_AC5Z8B\0430.ext"
@@ -0,0 +1,44 @@
+timestamp 1646324451
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "li_225_n726#" 17 38.7278 225 -726 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1976 180 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n261_n726#" 17 38.7278 -261 -726 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1976 180 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_217_n290#" 15 44.2028 217 -290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2576 204 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n261_n290#" 19 39.5848 -261 -290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2016 184 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_229_174#" 18 22.8948 229 174 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1700 168 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n261_174#" 25 20.6228 -261 174 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1200 148 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_159_n100#" 753 -173.43 159 -100 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9180 608 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 694 -173.43 -33 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9180 608 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n129_n100#" 1931 -368.685 -129 -100 pdif 0 0 0 0 0 0 0 0 0 0 26400 1064 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24300 1440 13616 776 0 0 0 0 0 0 0 0 0 0
+node "a_n221_n74#" 753 -173.43 -221 -74 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9180 608 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n159_n152#" 2233 50.032 -159 -152 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42880 2880 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n261_n210#" 2173 644.52 -261 -210 nw 0 0 0 0 214840 1868 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_229_174#" "a_n33_n100#" 2.80189
+cap "li_n261_n726#" "li_n261_n290#" 3.09375
+cap "a_159_n100#" "li_229_174#" 29.7
+cap "li_n261_174#" "a_n33_n100#" 2.7
+cap "a_n129_n100#" "a_n33_n100#" 462.239
+cap "a_n221_n74#" "a_n33_n100#" 102.009
+cap "a_159_n100#" "a_n129_n100#" 264.021
+cap "a_n221_n74#" "a_159_n100#" 45.1613
+cap "w_n261_n210#" "a_n33_n100#" 207.073
+cap "li_217_n290#" "li_225_n726#" 3.26562
+cap "w_n261_n210#" "a_159_n100#" 207.073
+cap "a_n221_n74#" "li_n261_174#" 21.2143
+cap "a_n221_n74#" "a_n129_n100#" 264.212
+cap "w_n261_n210#" "li_229_174#" 13.1177
+cap "w_n261_n210#" "li_n261_174#" 10.8272
+cap "w_n261_n210#" "a_n129_n100#" 447.025
+cap "w_n261_n210#" "a_n221_n74#" 207.073
+cap "a_n129_n100#" "a_n159_n152#" 106.141
+cap "w_n261_n210#" "a_n159_n152#" 352
+cap "a_159_n100#" "a_n33_n100#" 102.009
+device msubckt sky130_fd_pr__pfet_01v8 129 -100 130 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n129_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 33 -100 34 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n33_n100#" 200 0 "a_n129_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -63 -100 -62 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -159 -100 -158 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n221_n74#" 200 0 "a_n129_n100#" 200 0
diff --git "a/mag/latch/sky130_fd_pr__pfet_01v8_AC5Z8B\0430.mag" "b/mag/latch/sky130_fd_pr__pfet_01v8_AC5Z8B\0430.mag"
new file mode 100755
index 0000000..dced6c3
--- /dev/null
+++ "b/mag/latch/sky130_fd_pr__pfet_01v8_AC5Z8B\0430.mag"
@@ -0,0 +1,114 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646324451
+<< error_p >>
+rect -261 174 -227 224
+rect -209 140 -203 192
+rect 195 140 209 192
+rect 229 174 263 224
+rect -261 -290 -225 -234
+rect -261 -726 -223 -674
+rect 225 -726 263 -674
+<< nwell >>
+rect -261 -210 263 200
+<< pmos >>
+rect -159 -100 -129 100
+rect -63 -100 -33 100
+rect 33 -100 63 100
+rect 129 -100 159 100
+<< pdiff >>
+rect -217 74 -159 100
+rect -221 62 -159 74
+rect -221 -62 -209 62
+rect -175 -62 -159 62
+rect -221 -74 -159 -62
+rect -217 -100 -159 -74
+rect -129 62 -63 100
+rect -129 -62 -113 62
+rect -79 -62 -63 62
+rect -129 -100 -63 -62
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 62 129 100
+rect 63 -62 79 62
+rect 113 -62 129 62
+rect 63 -100 129 -62
+rect 159 74 217 100
+rect 159 62 221 74
+rect 159 -62 175 62
+rect 209 -62 221 62
+rect 159 -74 221 -62
+rect 159 -100 217 -74
+<< pdiffc >>
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+<< poly >>
+rect -159 100 -129 138
+rect -63 100 -33 138
+rect 33 100 63 138
+rect 129 100 159 138
+rect -159 -120 -129 -100
+rect -63 -120 -33 -100
+rect 33 -120 63 -100
+rect 129 -120 159 -100
+rect -159 -152 161 -120
+rect 15 -208 45 -152
+<< locali >>
+rect -261 174 -237 224
+rect -209 62 -175 192
+rect -209 -78 -175 -62
+rect -113 62 -79 78
+rect -113 -68 -79 -62
+rect -115 -116 -79 -68
+rect -17 62 17 192
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -64 113 -62
+rect 77 -116 113 -64
+rect 175 62 209 192
+rect 229 174 263 224
+rect 175 -78 209 -62
+rect -115 -154 113 -116
+rect 61 -220 95 -154
+rect -261 -290 -225 -234
+rect 217 -290 263 -234
+rect -261 -726 -223 -674
+rect 225 -726 263 -674
+<< viali >>
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+<< metal1 >>
+rect -215 62 -169 74
+rect -215 -62 -209 62
+rect -175 -62 -169 62
+rect -215 -74 -169 -62
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+rect 169 62 215 74
+rect 169 -62 175 62
+rect 209 -62 215 62
+rect 169 -74 215 -62
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 4 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/latch/sky130_fd_pr__pfet_01v8_GJYUB2.ext b/mag/latch/sky130_fd_pr__pfet_01v8_GJYUB2.ext
new file mode 100644
index 0000000..e3ea7e9
--- /dev/null
+++ b/mag/latch/sky130_fd_pr__pfet_01v8_GJYUB2.ext
@@ -0,0 +1,60 @@
+timestamp 1652082874
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_207_n100#" 711 -175.48 207 -100 pdif 0 0 0 0 0 0 0 0 0 0 12400 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_111_n100#" 672 -175.48 111 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_15_n100#" 672 -175.48 15 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n81_n100#" 672 -175.48 -81 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n177_n100#" 672 -175.48 -177 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n269_n100#" 711 -175.48 -269 -100 pdif 0 0 0 0 0 0 0 0 0 0 12400 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_177_n128#" 408 12.543 177 -128 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7620 568 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_81_n126#" 411 12.702 81 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7680 572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n128#" 408 12.543 -15 -128 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7620 568 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n111_n126#" 411 12.702 -111 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7680 572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n207_n128#" 408 12.543 -207 -128 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7620 568 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n305_n200#" 24582 490.536 -305 -200 nw 0 0 0 0 163512 3288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_111_n100#" "a_207_n100#" 243.91
+cap "a_n177_n100#" "a_n269_n100#" 243.91
+cap "w_n305_n200#" "a_n207_n128#" 37.95
+cap "w_n305_n200#" "a_15_n100#" 179.012
+cap "a_n81_n100#" "a_15_n100#" 243.91
+cap "a_n177_n100#" "a_111_n100#" 54.5443
+cap "a_n111_n126#" "a_81_n126#" 7.95062
+cap "a_n207_n128#" "a_177_n128#" 3.50847
+cap "w_n305_n200#" "a_n269_n100#" 179.012
+cap "w_n305_n200#" "a_n111_n126#" 39.05
+cap "a_n81_n100#" "a_n269_n100#" 89.0595
+cap "w_n305_n200#" "a_111_n100#" 179.012
+cap "a_n81_n100#" "a_111_n100#" 89.0595
+cap "a_n177_n100#" "a_207_n100#" 39.3156
+cap "a_n15_n128#" "a_81_n126#" 18.1212
+cap "a_n111_n126#" "a_177_n128#" 4.63566
+cap "a_15_n100#" "a_n269_n100#" 54.5443
+cap "w_n305_n200#" "a_n15_n128#" 37.95
+cap "a_n207_n128#" "a_n111_n126#" 18.1212
+cap "w_n305_n200#" "a_207_n100#" 179.012
+cap "a_15_n100#" "a_111_n100#" 243.91
+cap "a_n81_n100#" "a_207_n100#" 54.5443
+cap "a_n15_n128#" "a_177_n128#" 7.66667
+cap "w_n305_n200#" "a_n177_n100#" 179.012
+cap "a_n177_n100#" "a_n81_n100#" 243.91
+cap "w_n305_n200#" "a_81_n126#" 39.05
+cap "a_n207_n128#" "a_n15_n128#" 7.66667
+cap "a_111_n100#" "a_n269_n100#" 39.3156
+cap "a_15_n100#" "a_207_n100#" 89.0595
+cap "a_81_n126#" "a_177_n128#" 18.1212
+cap "w_n305_n200#" "a_n81_n100#" 179.012
+cap "a_n177_n100#" "a_15_n100#" 89.0595
+cap "w_n305_n200#" "a_177_n128#" 37.95
+cap "a_n111_n126#" "a_n15_n128#" 18.1212
+cap "a_n207_n128#" "a_81_n126#" 4.63566
+device msubckt sky130_fd_pr__pfet_01v8 177 -100 178 -99 l=30 w=200 "w_n305_n200#" "a_177_n128#" 60 0 "a_111_n100#" 200 0 "a_207_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 81 -100 82 -99 l=30 w=200 "w_n305_n200#" "a_81_n126#" 60 0 "a_15_n100#" 200 0 "a_111_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -15 -100 -14 -99 l=30 w=200 "w_n305_n200#" "a_n15_n128#" 60 0 "a_n81_n100#" 200 0 "a_15_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -111 -100 -110 -99 l=30 w=200 "w_n305_n200#" "a_n111_n126#" 60 0 "a_n177_n100#" 200 0 "a_n81_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -207 -100 -206 -99 l=30 w=200 "w_n305_n200#" "a_n207_n128#" 60 0 "a_n269_n100#" 200 0 "a_n177_n100#" 200 0
diff --git a/mag/latch/sky130_fd_pr__pfet_01v8_GJYUB2.mag b/mag/latch/sky130_fd_pr__pfet_01v8_GJYUB2.mag
new file mode 100644
index 0000000..072dbf0
--- /dev/null
+++ b/mag/latch/sky130_fd_pr__pfet_01v8_GJYUB2.mag
@@ -0,0 +1,118 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1652082874
+<< error_p >>
+rect -247 136 -137 162
+rect -247 130 297 136
+rect 305 130 465 162
+rect -269 94 269 100
+rect -439 -128 -305 40
+rect -271 -198 299 56
+rect 305 -198 467 40
+<< nwell >>
+rect -305 130 -247 162
+rect 297 130 305 162
+rect -305 -128 305 130
+rect -305 -198 -271 -128
+rect 299 -198 305 -128
+rect -305 -200 305 -198
+<< pmos >>
+rect -207 -100 -177 100
+rect -111 -100 -81 100
+rect -15 -100 15 100
+rect 81 -100 111 100
+rect 177 -100 207 100
+<< pdiff >>
+rect -269 88 -207 100
+rect -269 -88 -257 88
+rect -223 -88 -207 88
+rect -269 -100 -207 -88
+rect -177 88 -111 100
+rect -177 -88 -161 88
+rect -127 -88 -111 88
+rect -177 -100 -111 -88
+rect -81 88 -15 100
+rect -81 -88 -65 88
+rect -31 -88 -15 88
+rect -81 -100 -15 -88
+rect 15 88 81 100
+rect 15 -88 31 88
+rect 65 -88 81 88
+rect 15 -100 81 -88
+rect 111 88 177 100
+rect 111 -88 127 88
+rect 161 -88 177 88
+rect 111 -100 177 -88
+rect 207 88 269 100
+rect 207 -88 223 88
+rect 257 -88 269 88
+rect 207 -100 269 -88
+<< pdiffc >>
+rect -257 -88 -223 88
+rect -161 -88 -127 88
+rect -65 -88 -31 88
+rect 31 -88 65 88
+rect 127 -88 161 88
+rect 223 -88 257 88
+<< poly >>
+rect -207 100 -177 126
+rect -111 100 -81 130
+rect -15 100 15 126
+rect 81 100 111 130
+rect 177 100 207 126
+rect -207 -128 -177 -100
+rect -111 -126 -81 -100
+rect -15 -128 15 -100
+rect 81 -126 111 -100
+rect 177 -128 207 -100
+<< locali >>
+rect -257 88 -223 104
+rect -257 -104 -223 -88
+rect -161 88 -127 104
+rect -161 -104 -127 -88
+rect -65 88 -31 104
+rect -65 -104 -31 -88
+rect 31 88 65 104
+rect 31 -104 65 -88
+rect 127 88 161 104
+rect 127 -104 161 -88
+rect 223 88 257 104
+rect 223 -104 257 -88
+<< viali >>
+rect -257 -62 -223 62
+rect -161 -62 -127 62
+rect -65 -62 -31 62
+rect 31 -62 65 62
+rect 127 -62 161 62
+rect 223 -62 257 62
+<< metal1 >>
+rect -263 62 -217 74
+rect -263 -62 -257 62
+rect -223 -62 -217 62
+rect -263 -74 -217 -62
+rect -167 62 -121 74
+rect -167 -62 -161 62
+rect -127 -62 -121 62
+rect -167 -74 -121 -62
+rect -71 62 -25 74
+rect -71 -62 -65 62
+rect -31 -62 -25 62
+rect -71 -74 -25 -62
+rect 25 62 71 74
+rect 25 -62 31 62
+rect 65 -62 71 62
+rect 25 -74 71 -62
+rect 121 62 167 74
+rect 121 -62 127 62
+rect 161 -62 167 62
+rect 121 -74 167 -62
+rect 217 62 263 74
+rect 217 -62 223 62
+rect 257 -62 263 62
+rect 217 -74 263 -62
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 5 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/latch/sky130_fd_pr__pfet_01v8_KKZUBC.mag b/mag/latch/sky130_fd_pr__pfet_01v8_KKZUBC.mag
new file mode 100644
index 0000000..5408667
--- /dev/null
+++ b/mag/latch/sky130_fd_pr__pfet_01v8_KKZUBC.mag
@@ -0,0 +1,61 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1651918812
+<< nwell >>
+rect -351 74 337 460
+rect -161 -356 163 74
+<< pmos >>
+rect -63 -250 -33 250
+rect 33 -250 63 250
+<< pdiff >>
+rect -125 238 -63 250
+rect -125 -238 -113 238
+rect -79 -238 -63 238
+rect -125 -250 -63 -238
+rect -33 238 33 250
+rect -33 -238 -17 238
+rect 17 -238 33 238
+rect -33 -250 33 -238
+rect 63 238 125 250
+rect 63 -238 79 238
+rect 113 -238 125 238
+rect 63 -250 125 -238
+<< pdiffc >>
+rect -113 -238 -79 238
+rect -17 -238 17 238
+rect 79 -238 113 238
+<< poly >>
+rect -63 250 -33 276
+rect 33 250 63 278
+rect -63 -280 -33 -250
+rect 33 -276 63 -250
+<< locali >>
+rect -113 238 -79 254
+rect -113 -254 -79 -238
+rect -17 238 17 254
+rect -17 -254 17 -238
+rect 79 238 113 254
+rect 79 -254 113 -238
+<< viali >>
+rect -113 -167 -79 167
+rect -17 -167 17 167
+rect 79 -167 113 167
+<< metal1 >>
+rect -119 167 -73 179
+rect -119 -167 -113 167
+rect -79 -167 -73 167
+rect -119 -179 -73 -167
+rect -23 167 23 179
+rect -23 -167 -17 167
+rect 17 -167 23 167
+rect -23 -179 23 -167
+rect 73 167 119 179
+rect 73 -167 79 167
+rect 113 -167 119 167
+rect 73 -179 119 -167
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 2.5 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/latch_2.ext b/mag/latch_2.ext
new file mode 100644
index 0000000..29f3f1f
--- /dev/null
+++ b/mag/latch_2.ext
@@ -0,0 +1,47 @@
+timestamp 1651483715
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_5SVZDE sky130_fd_pr__pfet_01v8_5SVZDE_0 1 0 789 0 1 712
+use inv_W12 inv_W12_1 1 0 100 0 1 72
+use inv_W12 inv_W12_0 1 0 1206 0 1 72
+node "m1_718_782#" 2 233.662 718 782 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25988 1272 0 0 0 0 0 0 0 0 0 0
+node "li_474_0#" 157 328.247 474 0 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34840 1444 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_480_436#" 139 187.312 480 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35840 1392 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_452_900#" 236 423.573 452 900 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41268 1880 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_416_492#" 42840 68.04 416 492 nw 0 0 0 0 22680 1572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_480_436#" "w_416_492#" 131.2
+cap "li_452_900#" "li_480_436#" 7.31014
+cap "li_474_0#" "li_480_436#" 55
+cap "li_452_900#" "m1_718_782#" 104.31
+cap "inv_W12_1/GND" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#" -1.77636e-15
+cap "inv_W12_1/Vin" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" 5.95932
+cap "inv_W12_1/Vout" "sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" -4.51
+cap "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" 28.8966
+cap "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" 25.5595
+cap "inv_W12_1/Vout" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#" 30.5689
+cap "inv_W12_1/Vout" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" 33.2933
+cap "sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#" 364.07
+cap "inv_W12_1/GND" "inv_W12_1/Vout" -1.89062
+cap "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" 85.249
+cap "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#" 114.896
+cap "inv_W12_0/pmos_2uf2_0/w_n319_n202#" "inv_W12_0/VDD" -36.3337
+merge "inv_W12_0/VSUBS" "inv_W12_1/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/VSUBS" "sky130_fd_pr__pfet_01v8_5SVZDE_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_5SVZDE_0/VSUBS" "VSUBS"
+merge "inv_W12_0/VDD" "inv_W12_1/VDD" -446.547 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8344 -544 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/VDD" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_15_n100#"
+merge "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#"
+merge "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#" "li_452_900#"
+merge "inv_W12_0/pmos_2uf2_0/w_n319_n202#" "inv_W12_1/pmos_2uf2_0/w_n319_n202#" -1121.52 0 0 0 0 -373840 -5100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/pmos_2uf2_0/w_n319_n202#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#"
+merge "sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "w_416_492#"
+merge "inv_W12_0/GND" "inv_W12_1/GND" -54.1476 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10608 -312 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/GND" "li_474_0#"
+merge "inv_W12_0/Vin" "inv_W12_1/Vout" -37.0656 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14448 -268 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/Vout" "li_480_436#"
+merge "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_111_n100#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" -149.677 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2668 -300 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" "m1_718_782#"
diff --git a/mag/latch_2.mag b/mag/latch_2.mag
new file mode 100755
index 0000000..a14aab3
--- /dev/null
+++ b/mag/latch_2.mag
@@ -0,0 +1,35 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1651483715
+<< error_s >>
+rect 260 82 290 88
+rect 1366 82 1396 88
+<< nwell >>
+rect 416 492 1172 522
+<< locali >>
+rect 452 900 1140 950
+rect 628 796 662 900
+rect 820 802 854 900
+rect 480 436 1120 492
+rect 474 0 1144 52
+<< metal1 >>
+rect 718 962 956 1002
+rect 718 782 764 962
+rect 910 784 956 962
+use inv_W12 inv_W12_0 ~/Documents/Comparator_MPW6/mag/myinv_layout2
+timestamp 1651483715
+transform 1 0 1206 0 1 72
+box -100 -72 388 878
+use inv_W12 inv_W12_1
+timestamp 1651483715
+transform 1 0 100 0 1 72
+box -100 -72 388 878
+use sky130_fd_pr__pfet_01v8_5SVZDE sky130_fd_pr__pfet_01v8_5SVZDE_0 ~/Documents/Comparator_MPW6/mag/latch
+timestamp 1646503715
+transform 1 0 789 0 1 712
+box -789 -196 805 222
+<< labels >>
+rlabel space 1602 26 1602 26 3 GND
+rlabel space 1602 936 1602 936 3 VDD
+<< end >>
diff --git a/mag/latch_22.ext b/mag/latch_22.ext
new file mode 100644
index 0000000..1eff89c
--- /dev/null
+++ b/mag/latch_22.ext
@@ -0,0 +1,47 @@
+timestamp 1651483715
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_5SVZDE sky130_fd_pr__pfet_01v8_5SVZDE_0 1 0 789 0 1 712
+use inv_W12 inv_W12_1 1 0 100 0 1 72
+use inv_W12 inv_W12_0 1 0 1206 0 1 72
+node "m1_718_782#" 2 233.662 718 782 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25988 1272 0 0 0 0 0 0 0 0 0 0
+node "li_474_0#" 157 328.247 474 0 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34840 1444 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_480_436#" 139 187.312 480 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35840 1392 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_452_900#" 236 423.573 452 900 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41268 1880 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_416_492#" 42840 68.04 416 492 nw 0 0 0 0 22680 1572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_480_436#" "li_474_0#" 55
+cap "li_480_436#" "w_416_492#" 131.2
+cap "li_452_900#" "m1_718_782#" 104.31
+cap "li_452_900#" "li_480_436#" 7.31014
+cap "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" "inv_W12_1/Vout" 33.2933
+cap "inv_W12_1/Vout" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#" 30.5689
+cap "inv_W12_1/GND" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#" -1.77636e-15
+cap "inv_W12_1/GND" "inv_W12_1/Vout" -1.89062
+cap "sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" 85.249
+cap "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "inv_W12_1/Vin" 5.95932
+cap "sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#" 364.07
+cap "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" 25.5595
+cap "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#" 28.8966
+cap "sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "inv_W12_1/Vout" -4.51
+cap "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#" 114.896
+cap "inv_W12_0/VDD" "inv_W12_0/pmos_2uf2_0/w_n319_n202#" -36.3337
+merge "inv_W12_0/VSUBS" "inv_W12_1/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/VSUBS" "sky130_fd_pr__pfet_01v8_5SVZDE_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_5SVZDE_0/VSUBS" "VSUBS"
+merge "inv_W12_0/VDD" "inv_W12_1/VDD" -446.547 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8344 -544 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/VDD" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_15_n100#"
+merge "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#"
+merge "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#" "li_452_900#"
+merge "inv_W12_0/pmos_2uf2_0/w_n319_n202#" "inv_W12_1/pmos_2uf2_0/w_n319_n202#" -1121.52 0 0 0 0 -373840 -5100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/pmos_2uf2_0/w_n319_n202#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#"
+merge "sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "w_416_492#"
+merge "inv_W12_0/GND" "inv_W12_1/GND" -54.1476 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10608 -312 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/GND" "li_474_0#"
+merge "inv_W12_0/Vin" "inv_W12_1/Vout" -37.0656 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14448 -268 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/Vout" "li_480_436#"
+merge "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_111_n100#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" -149.677 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2668 -300 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" "m1_718_782#"
diff --git a/mag/latch_22.mag b/mag/latch_22.mag
new file mode 100644
index 0000000..a14aab3
--- /dev/null
+++ b/mag/latch_22.mag
@@ -0,0 +1,35 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1651483715
+<< error_s >>
+rect 260 82 290 88
+rect 1366 82 1396 88
+<< nwell >>
+rect 416 492 1172 522
+<< locali >>
+rect 452 900 1140 950
+rect 628 796 662 900
+rect 820 802 854 900
+rect 480 436 1120 492
+rect 474 0 1144 52
+<< metal1 >>
+rect 718 962 956 1002
+rect 718 782 764 962
+rect 910 784 956 962
+use inv_W12 inv_W12_0 ~/Documents/Comparator_MPW6/mag/myinv_layout2
+timestamp 1651483715
+transform 1 0 1206 0 1 72
+box -100 -72 388 878
+use inv_W12 inv_W12_1
+timestamp 1651483715
+transform 1 0 100 0 1 72
+box -100 -72 388 878
+use sky130_fd_pr__pfet_01v8_5SVZDE sky130_fd_pr__pfet_01v8_5SVZDE_0 ~/Documents/Comparator_MPW6/mag/latch
+timestamp 1646503715
+transform 1 0 789 0 1 712
+box -789 -196 805 222
+<< labels >>
+rlabel space 1602 26 1602 26 3 GND
+rlabel space 1602 936 1602 936 3 VDD
+<< end >>
diff --git a/mag/latch_3.ext b/mag/latch_3.ext
new file mode 100644
index 0000000..0f20da5
--- /dev/null
+++ b/mag/latch_3.ext
@@ -0,0 +1,95 @@
+timestamp 1653304099
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_GJYUB2 sky130_fd_pr__pfet_01v8_GJYUB2_0 1 0 853 0 1 690
+use inv_W12 inv_W12_1 1 0 100 0 1 72
+use inv_W12 inv_W12_0 1 0 1206 0 1 72
+node "m1_686_734#" 3 183.32 686 734 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 52592 2412 0 0 0 0 0 0 0 0 0 0
+node "li_474_0#" 157 328.247 474 0 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34840 1444 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1408_254#" 44 67.7969 1408 254 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4148 312 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_302_244#" 37 59.8508 302 244 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3536 276 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_480_436#" 139 187.312 480 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35840 1392 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_192_434#" 75 778.97 192 434 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7224 480 87784 3440 0 0 0 0 0 0 0 0 0 0
+node "li_452_900#" 326 161.747 452 900 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50108 2400 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_1366_66#" 56 32.867 1366 66 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_260_64#" 55 37.903 260 64 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1020 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_646_528#" 554 39.4956 646 528 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14904 900 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_646_808#" 554 39.4956 646 808 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14904 900 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n16_492#" 11438 1959.6 -16 492 nw 0 0 0 0 653200 4816 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_n16_492#" "li_452_900#" 344.818
+cap "li_192_434#" "li_480_436#" 12.6212
+cap "w_n16_492#" "a_646_808#" 247.5
+cap "w_n16_492#" "m1_686_734#" 247.667
+cap "a_646_808#" "li_452_900#" 60.1928
+cap "li_452_900#" "m1_686_734#" 156.465
+cap "li_192_434#" "li_302_244#" 18.6614
+cap "w_n16_492#" "a_646_528#" 247.5
+cap "a_646_808#" "m1_686_734#" 53.206
+cap "li_192_434#" "w_n16_492#" 68.8525
+cap "li_192_434#" "li_1408_254#" 31.1746
+cap "w_n16_492#" "li_480_436#" 131.2
+cap "a_646_808#" "a_646_528#" 39.0246
+cap "li_452_900#" "li_480_436#" 13.252
+cap "li_192_434#" "m1_686_734#" 18.1579
+cap "li_480_436#" "li_474_0#" 55
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#" "inv_W12_1/GND" -1.77636e-15
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n207_n128#" "inv_W12_1/Vin" 12.4249
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" "inv_W12_1/Vin" -17.0349
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#" "inv_W12_1/Vin" 68.5137
+cap "inv_W12_1/Vout" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n177_n100#" 53.0501
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n207_n128#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" -153.45
+cap "inv_W12_1/Vout" "inv_W12_1/GND" -5.89777
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" -17.0554
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n177_n100#" "inv_W12_1/Vin" 19.864
+cap "inv_W12_1/Vout" "inv_W12_1/Vin" 86.8557
+cap "inv_W12_1/GND" "inv_W12_1/Vin" 123.372
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n177_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" -98.7684
+cap "inv_W12_1/Vout" "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" -3.3815
+cap "inv_W12_1/Vout" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n207_n128#" 10.1115
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n177_n100#" 196.5
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#" "inv_W12_1/Vout" 46.1642
+cap "inv_W12_0/Vout" "inv_W12_0/VDD" 24.5687
+cap "inv_W12_0/Vout" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_207_n100#" 10.2987
+cap "inv_W12_0/Vout" "inv_W12_0/GND" -4.00714
+cap "inv_W12_0/Vout" "inv_W12_0/Vin" -87.3484
+cap "inv_W12_0/VDD" "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" -38.3565
+cap "inv_W12_0/Vin" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_177_n128#" 4.22145
+cap "inv_W12_0/Vout" "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" -1.06581e-14
+cap "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_207_n100#" "inv_W12_0/VDD" 14.0512
+cap "inv_W12_0/Vin" "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" -12.1
+merge "inv_W12_0/Vout" "inv_W12_0/nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#" -210.297 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -300 -80 0 0 -17084 -788 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_0/nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#" "li_1408_254#"
+merge "li_1408_254#" "inv_W12_1/Vin"
+merge "inv_W12_1/Vin" "a_260_64#"
+merge "a_260_64#" "li_192_434#"
+merge "inv_W12_0/VSUBS" "inv_W12_1/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/VSUBS" "sky130_fd_pr__pfet_01v8_GJYUB2_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/VSUBS" "VSUBS"
+merge "inv_W12_0/VDD" "inv_W12_1/VDD" -95.2014 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21564 -832 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/VDD" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_111_n100#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_111_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n81_n100#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n81_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n269_n100#" "li_452_900#"
+merge "inv_W12_0/Vin" "a_1366_66#" -109.137 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -120 -68 0 0 11240 -540 0 0 0 0 0 0 0 0 0 0 0 0
+merge "a_1366_66#" "inv_W12_1/Vout"
+merge "inv_W12_1/Vout" "li_480_436#"
+merge "li_480_436#" "inv_W12_1/nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#"
+merge "inv_W12_1/nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#" "li_302_244#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_207_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_15_n100#" 22.446 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3900 -456 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n177_n100#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n177_n100#" "m1_686_734#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_177_n128#" "a_646_528#" -36.957 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1620 -708 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "a_646_528#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_81_n126#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_81_n126#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n15_n128#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n15_n128#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n111_n126#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n111_n126#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n207_n128#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/a_n207_n128#" "a_646_808#"
+merge "inv_W12_0/GND" "inv_W12_1/GND" -54.9172 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9776 -312 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/GND" "li_474_0#"
+merge "inv_W12_0/pmos_2uf2_0/w_n319_n202#" "inv_W12_1/pmos_2uf2_0/w_n319_n202#" -1194.76 0 0 0 0 -398252 -7572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W12_1/pmos_2uf2_0/w_n319_n202#" "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#"
+merge "sky130_fd_pr__pfet_01v8_GJYUB2_0/w_n305_n200#" "w_n16_492#"
diff --git a/mag/latch_3.mag b/mag/latch_3.mag
new file mode 100644
index 0000000..fd7083a
--- /dev/null
+++ b/mag/latch_3.mag
@@ -0,0 +1,58 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1653304099
+<< nwell >>
+rect -16 838 1626 902
+rect -16 552 1178 838
+rect 1248 552 1626 838
+rect -16 492 1626 552
+<< poly >>
+rect 646 808 1060 844
+rect 646 528 1060 564
+rect 260 64 290 98
+rect 1366 66 1396 92
+<< locali >>
+rect 452 900 1140 950
+rect 596 746 630 900
+rect 788 746 822 900
+rect 980 746 1014 900
+rect 480 436 1120 492
+rect 302 244 336 348
+rect 1408 254 1442 376
+rect 474 0 1144 52
+<< viali >>
+rect 192 434 258 498
+rect 1504 438 1564 488
+<< metal1 >>
+rect 686 978 1116 1022
+rect 686 734 732 978
+rect 878 734 924 978
+rect 1070 734 1116 978
+rect 180 498 272 510
+rect 180 434 192 498
+rect 258 434 272 498
+rect 180 420 272 434
+rect 1486 488 1578 506
+rect 1486 438 1504 488
+rect 1564 438 1578 488
+rect 1486 420 1578 438
+rect 198 392 250 420
+rect 1504 392 1566 420
+rect 198 342 1566 392
+use inv_W12 inv_W12_0 ~/Documents/Comparator_MPW6/mag/myinv_layout2
+timestamp 1653304099
+transform 1 0 1206 0 1 72
+box -100 -72 388 878
+use inv_W12 inv_W12_1
+timestamp 1653304099
+transform 1 0 100 0 1 72
+box -100 -72 388 878
+use sky130_fd_pr__pfet_01v8_GJYUB2 sky130_fd_pr__pfet_01v8_GJYUB2_0 ~/Documents/Comparator_MPW6/mag/latch
+timestamp 1652082874
+transform 1 0 853 0 1 690
+box -439 -200 467 162
+<< labels >>
+rlabel space 1602 26 1602 26 3 GND
+rlabel space 1602 936 1602 936 3 VDD
+<< end >>
diff --git a/mag/myinv_layout2/.magicrc b/mag/myinv_layout2/.magicrc
new file mode 100755
index 0000000..ea1e753
--- /dev/null
+++ b/mag/myinv_layout2/.magicrc
@@ -0,0 +1,87 @@
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+# Change this to a fixed number for repeatable behavior with GDS writes
+# e.g., "random seed 12345"
+catch {random seed}
+
+# Turn off the scale option on ext2spice or else it conflicts with the
+# scale in the model files.
+ext2spice scale off
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "/usr/local/share/pdk/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/sky130A.tech
+
+
+# load device generator
+source $PDKPATH/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE mag
+}
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_ml_xx_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_sram_macros
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_sram_macros/${MAGTYPE}
+}
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/mag/myinv_layout2/.spiceinit b/mag/myinv_layout2/.spiceinit
new file mode 100755
index 0000000..6bc157f
--- /dev/null
+++ b/mag/myinv_layout2/.spiceinit
@@ -0,0 +1 @@
+set ngbehavior=hs
diff --git a/mag/myinv_layout2/PLS_INV1.raw b/mag/myinv_layout2/PLS_INV1.raw
new file mode 100755
index 0000000..accab2f
--- /dev/null
+++ b/mag/myinv_layout2/PLS_INV1.raw
Binary files differ
diff --git a/mag/myinv_layout2/buffer_1.ext b/mag/myinv_layout2/buffer_1.ext
new file mode 100755
index 0000000..8808168
--- /dev/null
+++ b/mag/myinv_layout2/buffer_1.ext
@@ -0,0 +1,22 @@
+timestamp 1646324508
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use inv_W2 inv_W2_0 1 0 588 0 1 72
+use inv_W1 inv_W1_0 1 0 100 0 1 72
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "inv_W1_0/Vin" "inv_W2_0/Vin" 11.0875
+cap "inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "inv_W2_0/Vin" 23.6443
+cap "inv_W1_0/Vin" "inv_W2_0/GND" 2.90674
+cap "inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "inv_W2_0/VDD" 116.829
+cap "inv_W2_0/GND" "inv_W2_0/Vin" 32.2784
+cap "inv_W2_0/Vin" "inv_W2_0/VDD" 33.1221
+cap "inv_W2_0/GND" "inv_W2_0/VDD" -1.77636e-15
+merge "inv_W1_0/VSUBS" "inv_W2_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W2_0/VSUBS" "VSUBS"
+merge "inv_W1_0/Vout" "inv_W2_0/Vin" -32.196 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1120 -152 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W1_0/w_156_432#" "inv_W2_0/VDD" -52.545 0 0 0 0 -7640 -804 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1000 -140 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W2_0/VDD" "inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#"
+merge "inv_W1_0/GND" "inv_W2_0/GND" -30.482 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1040 -144 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/myinv_layout2/buffer_1.mag b/mag/myinv_layout2/buffer_1.mag
new file mode 100755
index 0000000..9a3422f
--- /dev/null
+++ b/mag/myinv_layout2/buffer_1.mag
@@ -0,0 +1,12 @@
+magic
+tech sky130A
+timestamp 1646324508
+use inv_W1 inv_W1_0
+timestamp 1645263751
+transform 1 0 50 0 1 36
+box -50 -36 194 439
+use inv_W2 inv_W2_0
+timestamp 1646324451
+transform 1 0 294 0 1 36
+box -60 -36 202 439
+<< end >>
diff --git a/mag/myinv_layout2/buffer_1.spice b/mag/myinv_layout2/buffer_1.spice
new file mode 100755
index 0000000..8dd610a
--- /dev/null
+++ b/mag/myinv_layout2/buffer_1.spice
@@ -0,0 +1,48 @@
+* SPICE3 file created from buffer_1.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_AC5Z8B a_159_n100# a_n221_n74# a_n129_n100# a_63_n100#
++ a_n63_n126# a_n159_n130# a_33_n130# w_n257_n200# a_n33_n100# a_129_n126# VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n257_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n126# a_n129_n100# w_n257_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_159_n100# a_129_n126# a_63_n100# w_n257_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n159_n130# a_n221_n74# w_n257_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ a_33_n142# a_63_n100# a_n63_n142# a_n125_n74#
++ a_n33_n100# VSUBS
+X0 a_63_n100# a_33_n142# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n142# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W2 Vin VDD GND w_n106_454# VSUBS
+Xsky130_fd_pr__pfet_01v8_AC5Z8B_0 VDD VDD VDD VDD Vin Vin Vin w_n106_454# VDD Vin
++ VSUBS sky130_fd_pr__pfet_01v8_AC5Z8B
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 Vin GND Vin GND VDD VSUBS sky130_fd_pr__nfet_01v8_XJTKXQ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n33_n157# a_15_n69# VSUBS
+X0 a_15_n69# a_n33_n157# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ m1_n86_2#
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS m1_n86_2#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS
++ sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2 a_63_n100# a_33_n130# w_n317_n202# a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# w_n317_n202# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W1 Vout Vin VDD GND
+Xnmos_1u_0 GND Vout Vin nmos_1u
+Xpmos_2uf2_0 VDD Vin VDD Vout Vin GND pmos_2uf2
+.ends
+
+.subckt buffer_1
+Xinv_W2_0 inv_W2_0/Vin inv_W2_0/VDD VSUBS inv_W2_0/VDD VSUBS inv_W2
+Xinv_W1_0 inv_W2_0/Vin inv_W2_0/Vin inv_W2_0/VDD VSUBS inv_W1
+.ends
+
diff --git a/mag/myinv_layout2/buffer_12.ext b/mag/myinv_layout2/buffer_12.ext
new file mode 100755
index 0000000..efa80fe
--- /dev/null
+++ b/mag/myinv_layout2/buffer_12.ext
@@ -0,0 +1,30 @@
+timestamp 1646326465
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use buffer_2 buffer_2_0 1 0 990 0 1 0
+use buffer_1 buffer_1_0 1 0 0 0 1 0
+node "GND" 18 37.8116 0 0 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1872 176 0 0 0 0 0 0 0 0 0 0 0 0
+node "buf_out" 13 49.7444 5828 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3248 228 0 0 0 0 0 0 0 0 0 0 0 0
+node "buf_in" 13 46.9736 0 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2912 216 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 14 40.575 0 900 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2200 188 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "GND" "buf_in" 3.09375
+cap "buffer_2_0/inv_W8_0/w_354_500#" "buffer_2_0/inv_W8_0/a_804_430#" 83.8408
+cap "buffer_2_0/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" "buffer_2_0/inv_W8_0/a_804_430#" 43.2725
+cap "buffer_1_0/inv_W2_0/Vin" "buffer_2_0/inv_W8_0/a_466_816#" 11.4029
+cap "buffer_2_0/inv_W8_0/a_804_430#" "buffer_2_0/inv_W8_0/li_354_0#" -0.171875
+cap "buffer_2_0/inv_W8_0/w_354_500#" "buffer_2_0/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" 75.6961
+cap "buffer_1_0/inv_W1_0/Vin" "buffer_2_0/inv_W8_0/li_354_0#" -3.09375
+merge "buffer_1_0/VSUBS" "buffer_2_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "buffer_2_0/VSUBS" "VSUBS"
+merge "buffer_1_0/inv_W2_0/GND" "buffer_2_0/inv_W8_0/li_354_0#" -60.0478 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1976 -284 0 0 0 0 0 0 0 0 0 0 0 0
+merge "buffer_2_0/inv_W8_0/li_354_0#" "GND"
+merge "buffer_2_0/Vout" "buf_out" -37.934 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9520 -228 0 0 0 0 0 0 0 0 0 0 0 0
+merge "buffer_1_0/inv_W2_0/VDD" "buffer_2_0/inv_W8_0/li_354_902#" -63.5794 0 0 0 0 -820 -824 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2296 -288 0 0 0 0 0 0 0 0 0 0 0 0
+merge "buffer_2_0/inv_W8_0/li_354_902#" "VDD"
+merge "VDD" "buffer_2_0/inv_W8_0/w_354_500#"
+merge "buffer_1_0/inv_W2_0/Vout" "buffer_2_0/inv_W8_0/a_804_430#" -23.0599 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -108 -112 0 0 0 0 0 0 0 0 0 0 0 0
+merge "buffer_1_0/inv_W1_0/Vin" "buf_in" -46.9736 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2912 -216 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/myinv_layout2/buffer_12.mag b/mag/myinv_layout2/buffer_12.mag
new file mode 100755
index 0000000..ea42762
--- /dev/null
+++ b/mag/myinv_layout2/buffer_12.mag
@@ -0,0 +1,22 @@
+magic
+tech sky130A
+timestamp 1646326465
+<< locali >>
+rect 0 450 22 475
+rect 0 218 26 246
+rect 2914 218 2943 246
+rect 0 0 18 26
+use buffer_1 buffer_1_0
+timestamp 1646324508
+transform 1 0 0 0 1 0
+box 0 0 496 475
+use buffer_2 buffer_2_0
+timestamp 1646326308
+transform 1 0 495 0 1 0
+box 0 0 2448 477
+<< labels >>
+rlabel locali 0 20 0 20 7 GND
+rlabel locali 2943 238 2943 238 3 buf_out
+rlabel locali 0 238 0 238 7 buf_in
+rlabel locali 0 469 0 469 7 VDD
+<< end >>
diff --git a/mag/myinv_layout2/buffer_12.spice b/mag/myinv_layout2/buffer_12.spice
new file mode 100755
index 0000000..ef46354
--- /dev/null
+++ b/mag/myinv_layout2/buffer_12.spice
@@ -0,0 +1,201 @@
+* SPICE3 file created from buffer_12.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_AC5Z8B a_159_n100# li_217_n290# li_n261_n290# li_229_174#
++ a_n221_n74# a_n129_n100# a_n159_n152# li_225_n726# a_n33_n100# w_n261_n210# li_n261_174#
++ li_n261_n726# VSUBS
+X0 a_n129_n100# a_n159_n152# a_n33_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5.32e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n159_n152# a_n221_n74# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ a_33_n122# a_n63_n122# a_63_n100# a_n125_n74#
++ a_n33_n100# VSUBS
+X0 a_63_n100# a_33_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n122# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W2 sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210# Vout Vin VDD GND VSUBS
+Xsky130_fd_pr__pfet_01v8_AC5Z8B_0 VDD Vout Vin VDD VDD Vout Vin GND VDD sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#
++ VDD GND VSUBS sky130_fd_pr__pfet_01v8_AC5Z8B
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 Vin Vin GND GND Vout VSUBS sky130_fd_pr__nfet_01v8_XJTKXQ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n33_n157# a_15_n69# VSUBS
+X0 a_15_n69# a_n33_n157# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ m1_n86_2#
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS m1_n86_2#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS
++ sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2 a_63_n100# a_33_n130# w_n317_n202# a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# w_n317_n202# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W1 Vout VDD Vin GND
+Xnmos_1u_0 GND Vout Vin nmos_1u
+Xpmos_2uf2_0 VDD Vin VDD Vout Vin GND pmos_2uf2
+.ends
+
+.subckt buffer_1 inv_W2_0/VDD inv_W2_0/Vout inv_W1_0/Vin VSUBS
+Xinv_W2_0 inv_W2_0/VDD inv_W2_0/Vout inv_W2_0/Vin inv_W2_0/VDD VSUBS VSUBS inv_W2
+Xinv_W1_0 inv_W2_0/Vin inv_W2_0/VDD inv_W1_0/Vin VSUBS inv_W1
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KZU588 a_159_n100# a_255_n100# a_351_n100# a_n129_n100#
++ a_63_n100# li_321_116# a_n353_n162# a_n225_n100# a_n413_n74# a_n321_n100# a_n33_n100#
++ VSUBS
+X0 a_n321_n100# a_n353_n162# a_n413_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_n225_n100# a_n353_n162# a_n321_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n129_n100# a_n353_n162# a_n225_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_63_n100# a_n353_n162# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_n33_n100# a_n353_n162# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_351_n100# a_n353_n162# a_255_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X6 a_159_n100# a_n353_n162# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_255_n100# a_n353_n162# a_159_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_RL4NCG a_543_n100# a_159_n100# a_n609_n100# a_321_n126#
++ a_n705_n100# a_255_n100# a_n159_n128# a_n543_n128# a_n255_n126# a_351_n100# a_n417_n100#
++ a_33_n128# a_n129_n100# a_n513_n100# a_n351_n128# a_63_n100# w_n833_n200# a_n225_n100#
++ a_609_n128# a_n63_n126# a_n797_n74# a_705_n126# a_n321_n100# a_639_n100# a_417_n128#
++ a_n639_n126# a_735_n100# a_n33_n100# a_513_n126# a_129_n126# a_447_n100# a_n735_n128#
++ a_n447_n126# a_225_n128# VSUBS
+X0 a_63_n100# a_33_n128# a_n33_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n126# a_n129_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_255_n100# a_225_n128# a_159_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X3 a_351_n100# a_321_n126# a_255_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X4 a_543_n100# a_513_n126# a_447_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X5 a_159_n100# a_129_n126# a_63_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_447_n100# a_417_n128# a_351_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_639_n100# a_609_n128# a_543_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 a_735_n100# a_705_n126# a_639_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n513_n100# a_n543_n128# a_n609_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_n321_n100# a_n351_n128# a_n417_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X11 a_n225_n100# a_n255_n126# a_n321_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n705_n100# a_n735_n128# a_n797_n74# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X13 a_n609_n100# a_n639_n126# a_n705_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n417_n100# a_n447_n126# a_n513_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_n129_n100# a_n159_n128# a_n225_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W8 li_354_902# w_354_500# li_354_0# li_512_546# a_804_430# VSUBS
+Xsky130_fd_pr__nfet_01v8_KZU588_0 li_354_0# li_512_546# li_354_0# li_512_546# li_512_546#
++ li_512_546# a_804_430# li_354_0# li_354_0# li_512_546# li_354_0# VSUBS sky130_fd_pr__nfet_01v8_KZU588
+Xsky130_fd_pr__pfet_01v8_RL4NCG_0 li_354_902# li_354_902# li_354_902# a_804_430# li_512_546#
++ li_512_546# a_804_430# a_804_430# a_804_430# li_354_902# li_354_902# a_804_430#
++ li_512_546# li_512_546# a_804_430# li_512_546# w_354_500# li_354_902# a_804_430#
++ a_804_430# li_354_902# a_804_430# li_512_546# li_512_546# a_804_430# a_804_430#
++ li_354_902# li_354_902# a_804_430# a_804_430# li_512_546# a_804_430# a_804_430#
++ a_804_430# VSUBS sky130_fd_pr__pfet_01v8_RL4NCG
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_VJWT33 a_543_n100# a_159_n100# a_n609_n100# a_n705_n100#
++ a_255_n100# a_351_n100# a_n417_n100# a_n129_n100# a_n513_n100# a_63_n100# a_n225_n100#
++ a_n797_n74# a_n735_n176# a_n321_n100# a_639_n100# a_735_n100# a_n33_n100# a_447_n100#
++ VSUBS
+X0 a_n513_n100# a_n735_n176# a_n609_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n321_n100# a_n735_n176# a_n417_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n225_n100# a_n735_n176# a_n321_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n705_n100# a_n735_n176# a_n797_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X4 a_n609_n100# a_n735_n176# a_n705_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n417_n100# a_n735_n176# a_n513_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n129_n100# a_n735_n176# a_n225_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_63_n100# a_n735_n176# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X8 a_n33_n100# a_n735_n176# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_351_n100# a_n735_n176# a_255_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_159_n100# a_n735_n176# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X11 a_255_n100# a_n735_n176# a_159_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_447_n100# a_n735_n176# a_351_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X13 a_543_n100# a_n735_n176# a_447_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X14 a_639_n100# a_n735_n176# a_543_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X15 a_735_n100# a_n735_n176# a_639_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_3M44SC a_543_n100# a_159_n100# a_n609_n100# a_321_n126#
++ a_1473_n126# a_1089_n126# a_n1407_n126# a_n705_n100# a_255_n100# a_n159_n128# a_n543_n128#
++ a_1407_n100# a_1185_n128# a_n255_n126# a_351_n100# a_n417_n100# a_n801_n100# a_n1119_n128#
++ a_n1503_n128# a_1281_n126# a_897_n126# a_33_n128# w_n1601_n200# a_1503_n100# a_1119_n100#
++ a_n1377_n100# a_n1215_n126# a_n129_n100# a_n513_n100# a_n351_n128# a_n1565_n74#
++ a_1215_n100# a_63_n100# a_n1089_n100# a_n1473_n100# a_993_n128# a_n225_n100# a_609_n128#
++ a_n63_n126# a_n1311_n128# a_1311_n100# a_927_n100# a_n1185_n100# a_705_n126# a_n1023_n126#
++ a_n321_n100# a_1023_n100# a_639_n100# a_n1281_n100# a_n927_n128# a_801_n128# a_417_n128#
++ a_n639_n126# a_735_n100# a_n33_n100# a_513_n126# a_129_n126# a_n897_n100# a_831_n100#
++ a_447_n100# a_n735_n128# a_n993_n100# a_n447_n126# a_n831_n126# a_1377_n128# a_225_n128#
++ VSUBS
+X0 a_63_n100# a_33_n128# a_n33_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_927_n100# a_897_n126# a_831_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_1023_n100# a_993_n128# a_927_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_1311_n100# a_1281_n126# a_1215_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_1119_n100# a_1089_n126# a_1023_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n100# a_1185_n128# a_1119_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_1407_n100# a_1377_n128# a_1311_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_1503_n100# a_1473_n126# a_1407_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n33_n100# a_n63_n126# a_n129_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X9 a_255_n100# a_225_n128# a_159_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_351_n100# a_321_n126# a_255_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X11 a_543_n100# a_513_n126# a_447_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X12 a_831_n100# a_801_n128# a_735_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X13 a_159_n100# a_129_n126# a_63_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_447_n100# a_417_n128# a_351_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_639_n100# a_609_n128# a_543_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X16 a_735_n100# a_705_n126# a_639_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_n1281_n100# a_n1311_n128# a_n1377_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X18 a_n993_n100# a_n1023_n126# a_n1089_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X19 a_n1473_n100# a_n1503_n128# a_n1565_n74# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X20 a_n1377_n100# a_n1407_n126# a_n1473_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_n1185_n100# a_n1215_n126# a_n1281_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X22 a_n1089_n100# a_n1119_n128# a_n1185_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_n801_n100# a_n831_n126# a_n897_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X24 a_n513_n100# a_n543_n128# a_n609_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X25 a_n321_n100# a_n351_n128# a_n417_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X26 a_n225_n100# a_n255_n126# a_n321_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X27 a_n897_n100# a_n927_n128# a_n993_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_n705_n100# a_n735_n128# a_n801_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X29 a_n609_n100# a_n639_n126# a_n705_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_n417_n100# a_n447_n126# a_n513_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_n129_n100# a_n159_n128# a_n225_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 w_n1601_n200# VSUBS 3.82fF
+.ends
+
+.subckt inv_W16 li_128_546# li_n14_902# a_82_816# w_82_814# li_n14_0# VSUBS
+Xsky130_fd_pr__nfet_01v8_VJWT33_0 li_n14_0# li_n14_0# li_n14_0# li_128_546# li_128_546#
++ li_n14_0# li_n14_0# li_128_546# li_128_546# li_128_546# li_n14_0# li_n14_0# a_82_816#
++ li_128_546# li_128_546# li_n14_0# li_n14_0# li_128_546# VSUBS sky130_fd_pr__nfet_01v8_VJWT33
+Xsky130_fd_pr__pfet_01v8_3M44SC_0 li_n14_902# li_n14_902# li_n14_902# a_82_816# a_82_816#
++ a_82_816# a_82_816# li_128_546# li_128_546# a_82_816# a_82_816# li_128_546# a_82_816#
++ a_82_816# li_n14_902# li_n14_902# li_n14_902# a_82_816# a_82_816# a_82_816# a_82_816#
++ a_82_816# w_82_814# li_n14_902# li_n14_902# li_n14_902# a_82_816# li_128_546# li_128_546#
++ a_82_816# li_n14_902# li_128_546# li_128_546# li_128_546# li_128_546# a_82_816#
++ li_n14_902# a_82_816# a_82_816# a_82_816# li_n14_902# li_n14_902# li_n14_902# a_82_816#
++ a_82_816# li_128_546# li_128_546# li_128_546# li_128_546# a_82_816# a_82_816# a_82_816#
++ a_82_816# li_n14_902# li_n14_902# a_82_816# a_82_816# li_128_546# li_128_546# li_128_546#
++ a_82_816# li_n14_902# a_82_816# a_82_816# a_82_816# a_82_816# VSUBS sky130_fd_pr__pfet_01v8_3M44SC
+C0 a_82_816# VSUBS 3.17fF
+C1 w_82_814# VSUBS 3.92fF
+.ends
+
+.subckt buffer_2 Vout inv_W8_0/li_354_902# w_1666_500# inv_W8_0/a_804_430# inv_W8_0/li_354_0#
++ VSUBS
+Xinv_W8_0 inv_W8_0/li_354_902# w_1666_500# inv_W8_0/li_354_0# inv_W16_0/a_82_816#
++ inv_W8_0/a_804_430# VSUBS inv_W8
+Xinv_W16_0 Vout inv_W8_0/li_354_902# inv_W16_0/a_82_816# w_1666_500# inv_W8_0/li_354_0#
++ VSUBS inv_W16
+C0 inv_W16_0/a_82_816# VSUBS 3.68fF
+C1 w_1666_500# VSUBS 6.52fF
+C2 inv_W8_0/li_354_0# VSUBS 2.31fF
+.ends
+
+.subckt buffer_12
+Xbuffer_1_0 VDD buffer_1_0/inv_W2_0/Vout buf_in GND buffer_1
+Xbuffer_2_0 buf_out VDD VDD buffer_1_0/inv_W2_0/Vout GND GND buffer_2
+C0 VDD 0 9.85fF
+C1 buffer_2_0/inv_W16_0/a_82_816# 0 3.68fF
+C2 GND 0 2.85fF
+.ends
+
diff --git a/mag/myinv_layout2/buffer_2.ext b/mag/myinv_layout2/buffer_2.ext
new file mode 100755
index 0000000..6a8155a
--- /dev/null
+++ b/mag/myinv_layout2/buffer_2.ext
@@ -0,0 +1,27 @@
+timestamp 1646326308
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use inv_W16 inv_W16_0 1 0 1708 0 1 0
+use inv_W8 inv_W8_0 1 0 -354 0 1 0
+node "Vout" 15 44.2028 4850 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2576 204 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_1666_500#" 1943 420 1666 500 nw 0 0 0 0 140000 1500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "inv_W16_0/li_n14_902#" "inv_W16_0/a_468_358#" 15.1736
+cap "inv_W8_0/a_466_816#" "inv_W16_0/a_82_816#" 1.35641
+cap "inv_W16_0/a_468_358#" "inv_W8_0/a_466_816#" 16.3371
+cap "inv_W16_0/a_468_358#" "inv_W16_0/li_n14_0#" -0.171875
+cap "inv_W16_0/a_468_358#" "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" 48.7475
+cap "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "inv_W16_0/li_n14_902#" 16.9157
+cap "inv_W16_0/li_n14_902#" "inv_W16_0/a_468_358#" 105.456
+cap "inv_W16_0/li_n14_902#" "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" 120.656
+merge "inv_W8_0/VSUBS" "inv_W16_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W16_0/VSUBS" "VSUBS"
+merge "inv_W8_0/li_512_546#" "inv_W16_0/a_468_358#" -8.3746 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15768 -112 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W8_0/li_354_0#" "inv_W16_0/li_n14_0#" -8.0948 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15184 -108 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W8_0/w_354_500#" "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" 271.488 0 0 0 0 90496 -2304 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "w_1666_500#"
+merge "inv_W8_0/li_354_902#" "inv_W16_0/li_n14_902#" -25.0105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15184 -108 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W16_0/li_128_546#" "Vout" -44.2028 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2576 -204 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/myinv_layout2/buffer_2.mag b/mag/myinv_layout2/buffer_2.mag
new file mode 100755
index 0000000..12f4f9a
--- /dev/null
+++ b/mag/myinv_layout2/buffer_2.mag
@@ -0,0 +1,18 @@
+magic
+tech sky130A
+timestamp 1646326308
+<< nwell >>
+rect 833 250 1008 450
+<< locali >>
+rect 2425 218 2448 246
+use inv_W8 inv_W8_0
+timestamp 1646325197
+transform 1 0 -177 0 1 0
+box 177 0 1025 477
+use inv_W16 inv_W16_0
+timestamp 1646325283
+transform 1 0 854 0 1 0
+box -7 0 1594 477
+<< labels >>
+rlabel locali 2448 232 2448 232 3 Vout
+<< end >>
diff --git a/mag/myinv_layout2/buffer_sample_lay.ext b/mag/myinv_layout2/buffer_sample_lay.ext
new file mode 100755
index 0000000..3c5ab2f
--- /dev/null
+++ b/mag/myinv_layout2/buffer_sample_lay.ext
@@ -0,0 +1,29 @@
+timestamp 1645264122
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use inv_W1 inv_W1_1 1 0 588 0 1 72
+use inv_W1 inv_W1_0 1 0 100 0 1 72
+node "GND" 14 41.4764 0 2 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2288 192 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vout" 26 34.9668 950 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1456 164 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vin" 16 42.3556 0 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2352 196 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 16 36.0384 -2 902 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1728 168 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "GND" "Vin" 3.62827
+cap "inv_W1_1/Vin" "inv_W1_1/GND" 47.9354
+cap "inv_W1_1/GND" "inv_W1_0/Vin" 0.314602
+cap "inv_W1_1/VDD" "inv_W1_1/Vout" 14.3882
+cap "inv_W1_1/Vin" "inv_W1_0/Vin" 15.2675
+cap "inv_W1_1/VDD" "inv_W1_1/GND" -1.42109e-14
+cap "inv_W1_1/Vin" "inv_W1_1/VDD" 31.3824
+merge "inv_W1_0/VDD" "VDD" -55.6296 0 0 0 0 0 -812 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1632 -264 0 0 0 0 0 0 0 0 0 0 0 0
+merge "VDD" "inv_W1_1/VDD"
+merge "inv_W1_0/VSUBS" "inv_W1_1/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W1_1/VSUBS" "VSUBS"
+merge "inv_W1_0/GND" "inv_W1_1/GND" -61.895 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2200 -292 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W1_1/GND" "GND"
+merge "inv_W1_0/Vin" "Vin" -42.3556 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2352 -196 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W1_0/Vout" "inv_W1_1/Vin" -22.96 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -112 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W1_1/Vout" "Vout" -34.9668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1456 -164 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/myinv_layout2/buffer_sample_lay.mag b/mag/myinv_layout2/buffer_sample_lay.mag
new file mode 100755
index 0000000..28edf44
--- /dev/null
+++ b/mag/myinv_layout2/buffer_sample_lay.mag
@@ -0,0 +1,22 @@
+magic
+tech sky130A
+timestamp 1645264122
+<< locali >>
+rect -1 451 17 475
+rect 0 218 21 246
+rect 475 218 488 246
+rect 0 1 22 27
+use inv_W1 inv_W1_0
+timestamp 1645263751
+transform 1 0 50 0 1 36
+box -50 -36 194 439
+use inv_W1 inv_W1_1
+timestamp 1645263751
+transform 1 0 294 0 1 36
+box -50 -36 194 439
+<< labels >>
+rlabel locali 0 6 0 6 7 GND
+rlabel locali 0 227 0 227 7 Vin
+rlabel locali -1 456 -1 456 7 VDD
+rlabel locali 488 227 488 227 3 Vout
+<< end >>
diff --git a/mag/myinv_layout2/buffer_sample_lay.spice b/mag/myinv_layout2/buffer_sample_lay.spice
new file mode 100755
index 0000000..ac80db0
--- /dev/null
+++ b/mag/myinv_layout2/buffer_sample_lay.spice
@@ -0,0 +1,32 @@
+* SPICE3 file created from buffer_sample_lay.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n33_n157# a_15_n69# VSUBS
+X0 a_15_n69# a_n33_n157# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ m1_n86_2#
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS m1_n86_2#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS
++ sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2 a_63_n100# a_33_n130# w_n317_n202# a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# w_n317_n202# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W1 Vout Vin VDD GND
+Xnmos_1u_0 GND Vout Vin nmos_1u
+Xpmos_2uf2_0 VDD Vin VDD Vout Vin GND pmos_2uf2
+.ends
+
+
+* Top level circuit buffer_sample_lay
+
+Xinv_W1_0 inv_W1_1/Vin Vin VDD GND inv_W1
+Xinv_W1_1 Vout inv_W1_1/Vin VDD GND inv_W1
+.global VDD
+.global GND
+.end
+
diff --git a/mag/myinv_layout2/inv.ext b/mag/myinv_layout2/inv.ext
new file mode 100755
index 0000000..4754063
--- /dev/null
+++ b/mag/myinv_layout2/inv.ext
@@ -0,0 +1,41 @@
+timestamp 1644846380
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_5YYKDE sky130_fd_pr__pfet_01v8_5YYKDE_0 1 0 21 0 1 730
+use sky130_fd_pr__nfet_01v8_QQ4XG9 sky130_fd_pr__nfet_01v8_QQ4XG9_0 1 0 71 0 1 141
+node "m1_18_0#" 0 51.1006 18 0 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2924 240 0 0 0 0 0 0 0 0 0 0
+node "m1_n100_448#" 0 -7.38 -100 448 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3816 284 0 0 0 0 0 0 0 0 0 0
+node "m1_36_976#" 0 0 36 976 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3816 284 0 0 0 0 0 0 0 0 0 0
+node "a_n46_72#" 545 8.14 -46 72 ndif 0 0 0 0 0 0 0 0 8800 488 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_6_442#" 385 94.535 6 442 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8900 600 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n254_408#" 2764 923.34 -254 408 nw 0 0 0 0 304964 2232 0 0 42400 1012 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48144 1052 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "a_n160_72#" 0 0 -160 72 ppd 0 0 0 0 0 0 0 0 0 0 22800 628 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34528 748 0 0 0 0 0 0 0 0 0 0 0 0
+cap "m1_n100_448#" "a_6_442#" 11.52
+cap "m1_n100_448#" "w_n254_408#" 60.7004
+cap "w_n254_408#" "m1_36_976#" 60.7004
+cap "a_6_442#" "w_n254_408#" 94.05
+cap "sky130_fd_pr__nfet_01v8_QQ4XG9_0/a_n73_n69#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/w_n161_n300#" 4.488
+cap "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_15_231#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_63_n200#" 41.087
+cap "sky130_fd_pr__nfet_01v8_QQ4XG9_0/a_n73_n69#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_15_231#" 41.522
+cap "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_15_231#" "sky130_fd_pr__nfet_01v8_QQ4XG9_0/a_15_n69#" 4.73684
+cap "sky130_fd_pr__nfet_01v8_QQ4XG9_0/a_n73_n69#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_n33_n200#" 11.4647
+cap "sky130_fd_pr__pfet_01v8_5YYKDE_0/w_n161_n300#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_15_231#" -86.3818
+cap "sky130_fd_pr__pfet_01v8_5YYKDE_0/w_n161_n300#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_n33_n200#" -5.68434e-14
+cap "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_63_n200#" "sky130_fd_pr__nfet_01v8_QQ4XG9_0/a_15_n69#" 11.8984
+cap "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_15_231#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_n33_n200#" 7.82609
+cap "sky130_fd_pr__pfet_01v8_5YYKDE_0/w_n161_n300#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_63_n200#" -1.13687e-13
+merge "sky130_fd_pr__nfet_01v8_QQ4XG9_0/a_n33_n157#" "m1_18_0#" 9.4784 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -420 -240 0 0 0 0 -6148 -560 0 0 0 0 0 0 0 0 0 0
+merge "m1_18_0#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_n81_n297#"
+merge "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_n81_n297#" "m1_n100_448#"
+merge "m1_n100_448#" "m1_36_976#"
+merge "m1_36_976#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_15_231#"
+merge "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_15_231#" "a_6_442#"
+merge "sky130_fd_pr__nfet_01v8_QQ4XG9_0/VSUBS" "sky130_fd_pr__nfet_01v8_QQ4XG9_0/a_n73_n69#" -89.96 0 0 0 0 0 0 0 0 0 -400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -416 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_QQ4XG9_0/a_n73_n69#" "a_n46_72#"
+merge "a_n46_72#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_5YYKDE_0/VSUBS" "a_n160_72#"
+merge "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_n125_n200#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/w_n161_n300#" -560.172 0 0 0 0 -185904 -1844 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -816 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_5YYKDE_0/w_n161_n300#" "w_n254_408#"
diff --git a/mag/myinv_layout2/inv.mag b/mag/myinv_layout2/inv.mag
new file mode 100755
index 0000000..88cc41a
--- /dev/null
+++ b/mag/myinv_layout2/inv.mag
@@ -0,0 +1,48 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1644851365
+<< nwell >>
+rect -254 408 224 1046
+<< ndiff >>
+rect -46 72 -2 272
+<< psubdiff >>
+rect -160 248 -46 272
+rect -160 92 -126 248
+rect -76 92 -46 248
+rect -160 72 -46 92
+<< nsubdiff >>
+rect -210 896 -104 930
+rect -210 556 -180 896
+rect -138 556 -104 896
+rect -210 530 -104 556
+<< psubdiffcont >>
+rect -126 92 -76 248
+<< nsubdiffcont >>
+rect -180 556 -138 896
+<< poly >>
+rect 54 488 84 514
+rect 6 442 86 488
+rect 56 294 86 442
+<< locali >>
+rect -210 896 -92 934
+rect -210 556 -180 896
+rect -138 556 -92 896
+rect -210 526 -92 556
+rect -156 248 10 276
+rect -156 92 -126 248
+rect -76 92 10 248
+rect -156 68 10 92
+<< metal1 >>
+rect 36 976 142 1012
+rect -100 448 6 484
+rect 18 0 104 34
+use sky130_fd_pr__nfet_01v8_QQ4XG9 sky130_fd_pr__nfet_01v8_QQ4XG9_0
+timestamp 1644851365
+transform 1 0 71 0 1 141
+box -73 -157 73 157
+use sky130_fd_pr__pfet_01v8_5YYKDE sky130_fd_pr__pfet_01v8_5YYKDE_0
+timestamp 1644851365
+transform 1 0 21 0 1 730
+box -161 -300 161 300
+<< end >>
diff --git a/mag/myinv_layout2/inv.spice b/mag/myinv_layout2/inv.spice
new file mode 100755
index 0000000..4c427c4
--- /dev/null
+++ b/mag/myinv_layout2/inv.spice
@@ -0,0 +1,21 @@
+* SPICE3 file created from inv.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_5YYKDE a_15_231# a_n81_n297# w_n161_n300# a_n125_n200#
++ VSUBS
+X0 a_63_n200# a_15_231# a_n33_n200# w_n161_n300# sky130_fd_pr__pfet_01v8 ad=6.2e+11p pd=4.62e+06u as=6.6e+11p ps=4.66e+06u w=2e+06u l=150000u
+X1 a_n33_n200# a_n81_n297# a_n125_n200# w_n161_n300# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=6.2e+11p ps=4.62e+06u w=2e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_QQ4XG9 a_n73_n69# a_n33_n157# VSUBS
+X0 a_15_n69# a_n33_n157# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+
+* Top level circuit inv
+
+Xsky130_fd_pr__pfet_01v8_5YYKDE_0 m1_18_0# m1_18_0# w_n254_408# w_n254_408# sky130_fd_pr__pfet_01v8_5YYKDE_0/VSUBS
++ sky130_fd_pr__pfet_01v8_5YYKDE
+Xsky130_fd_pr__nfet_01v8_QQ4XG9_0 sky130_fd_pr__pfet_01v8_5YYKDE_0/VSUBS m1_18_0#
++ sky130_fd_pr__pfet_01v8_5YYKDE_0/VSUBS sky130_fd_pr__nfet_01v8_QQ4XG9
+.end
+
diff --git a/mag/myinv_layout2/inv_W1.ext b/mag/myinv_layout2/inv_W1.ext
new file mode 100755
index 0000000..4752a17
--- /dev/null
+++ b/mag/myinv_layout2/inv_W1.ext
@@ -0,0 +1,43 @@
+timestamp 1645263751
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use pmos_2uf2 pmos_2uf2_0 1 0 219 0 1 622
+use nmos_1u nmos_1u_0 1 0 112 0 1 14
+node "GND" 130 309.233 -100 -72 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35560 1348 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vout" 127 170.655 202 260 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18576 964 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 295 464.724 -100 828 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42548 2112 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vin" 437 361.439 84 352 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16584 812 0 0 17360 704 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_156_432#" 3455 23.436 156 432 nw 0 0 0 0 7812 376 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_106_758#" 10767 24.624 106 758 nw 0 0 0 0 8208 528 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n100_420#" 345100 2.436 -100 420 nw 0 0 0 0 812 816 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "GND" "Vin" 26.7649
+cap "w_156_432#" "Vin" 37.93
+cap "GND" "Vout" 17.0696
+cap "VDD" "Vin" 14.9802
+cap "w_156_432#" "Vout" 26.4893
+cap "Vout" "Vin" 114.025
+cap "w_n100_420#" "Vin" 0.41
+cap "VDD" "Vout" 20.2327
+cap "VDD" "w_106_758#" 7.5924
+cap "pmos_2uf2_0/a_n33_n100#" "nmos_1u_0/a_n112_74#" 5.34286
+cap "pmos_2uf2_0/a_n63_n130#" "nmos_1u_0/a_n112_74#" 180.654
+cap "pmos_2uf2_0/w_n317_n202#" "nmos_1u_0/a_n112_74#" 23.3428
+cap "pmos_2uf2_0/w_n317_n202#" "pmos_2uf2_0/a_n33_n100#" 81.4607
+cap "pmos_2uf2_0/w_n317_n202#" "pmos_2uf2_0/a_n63_n130#" 156.497
+merge "nmos_1u_0/a_n112_74#" "GND" -28.0678 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1064 -180 0 0 0 0 0 0 0 0 0 0 0 0
+merge "GND" "pmos_2uf2_0/VSUBS"
+merge "pmos_2uf2_0/VSUBS" "VSUBS"
+merge "nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#" "pmos_2uf2_0/a_n33_n100#" -98.7705 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -952 -192 0 0 0 0 0 0 0 0 0 0 0 0
+merge "pmos_2uf2_0/a_n33_n100#" "Vout"
+merge "pmos_2uf2_0/a_63_n100#" "pmos_2uf2_0/w_n317_n202#" -280.232 0 0 0 0 -16020 -1716 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4692 -412 0 0 0 0 0 0 0 0 0 0 0 0
+merge "pmos_2uf2_0/w_n317_n202#" "VDD"
+merge "VDD" "w_156_432#"
+merge "w_156_432#" "w_106_758#"
+merge "w_106_758#" "w_n100_420#"
+merge "nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n33_n157#" "pmos_2uf2_0/a_33_n130#" -210.176 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1320 -268 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "pmos_2uf2_0/a_33_n130#" "pmos_2uf2_0/a_n63_n130#"
+merge "pmos_2uf2_0/a_n63_n130#" "Vin"
diff --git a/mag/myinv_layout2/inv_W1.mag b/mag/myinv_layout2/inv_W1.mag
new file mode 100755
index 0000000..0fa9a17
--- /dev/null
+++ b/mag/myinv_layout2/inv_W1.mag
@@ -0,0 +1,49 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645263751
+<< nwell >>
+rect -100 420 -98 826
+rect 106 758 334 794
+rect 156 432 282 494
+<< poly >>
+rect 156 466 282 506
+rect 156 436 190 466
+rect 84 416 190 436
+rect 84 370 100 416
+rect 150 370 190 416
+rect 84 352 190 370
+rect 160 298 190 352
+<< polycont >>
+rect 100 370 150 416
+<< locali >>
+rect -100 828 388 878
+rect 106 794 140 828
+rect 106 758 334 794
+rect 106 578 140 758
+rect 298 684 334 758
+rect 84 420 168 436
+rect -100 416 168 420
+rect -100 370 100 416
+rect 150 370 168 416
+rect -100 364 168 370
+rect 84 352 168 364
+rect 202 420 236 556
+rect 202 364 388 420
+rect 202 260 236 364
+rect 6 -20 82 114
+rect -100 -72 388 -20
+use nmos_1u nmos_1u_0
+timestamp 1644925353
+transform 1 0 112 0 1 14
+box -112 -14 136 300
+use pmos_2uf2 pmos_2uf2_0
+timestamp 1645079724
+transform 1 0 219 0 1 622
+box -317 -202 169 204
+<< labels >>
+rlabel locali -100 390 -100 390 7 Vin
+rlabel locali 388 392 388 392 3 Vout
+rlabel locali -100 854 -100 854 7 VDD
+rlabel locali -100 -46 -100 -46 7 GND
+<< end >>
diff --git a/mag/myinv_layout2/inv_W1.spice b/mag/myinv_layout2/inv_W1.spice
new file mode 100755
index 0000000..2a48770
--- /dev/null
+++ b/mag/myinv_layout2/inv_W1.spice
@@ -0,0 +1,40 @@
+* SPICE3 file created from inv_W1.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n33_n157# a_15_n69# VSUBS
+X0 a_15_n69# a_n33_n157# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ m1_n86_2#
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS m1_n86_2#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS
++ sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2 a_63_n100# a_33_n130# w_n317_n202# a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# w_n317_n202# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+**** begin user architecture code
+
+** opencircuitdesign pdks install
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+Vdd Vdd gnd 1.8
+Vin Vin gnd 0
+
+.control
+dc Vin 0 1.8 0.01
+plot Vin Vout
+save all
+write PLS_INV1.raw
+.endc
+
+**** end user architecture code
+* Top level circuit inv_W1
+
+Xnmos_1u_0 gnd Vout Vin nmos_1u
+Xpmos_2uf2_0 Vdd Vin Vdd Vout Vin gnd pmos_2uf2
+.end
+
diff --git a/mag/myinv_layout2/inv_W12.ext b/mag/myinv_layout2/inv_W12.ext
new file mode 100644
index 0000000..9d776c5
--- /dev/null
+++ b/mag/myinv_layout2/inv_W12.ext
@@ -0,0 +1,39 @@
+timestamp 1653304099
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use pmos_2uf2#0 pmos_2uf2_0 1 0 219 0 1 622
+use nmos_1u#0 nmos_1u_0 1 0 112 0 1 -38
+node "GND" 161 304.91 -100 -72 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30000 1352 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vout" 127 197.145 202 260 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18576 964 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 295 472.317 -100 828 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42548 2112 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_160_62#" 241 20.277 160 62 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 180 72 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vin" 522 435.031 84 352 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18264 924 0 0 17360 704 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "VDD" "Vout" 20.2327
+cap "Vin" "GND" 25.0022
+cap "Vin" "a_160_62#" 3.96552
+cap "Vin" "VDD" 14.9802
+cap "Vout" "GND" 17.0696
+cap "Vin" "Vout" 114.025
+cap "pmos_2uf2_0/a_n63_n130#" "pmos_2uf2_0/a_n139_n100#" 10.2742
+cap "pmos_2uf2_0/w_n319_n202#" "pmos_2uf2_0/a_n33_n100#" 76.9799
+cap "pmos_2uf2_0/a_n33_n100#" "nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#" 31.1667
+cap "nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n73_n69#" "nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#" 16.5
+cap "pmos_2uf2_0/a_n63_n130#" "nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n73_n69#" 4.01139
+cap "pmos_2uf2_0/a_n139_n100#" "pmos_2uf2_0/a_n33_n100#" 23.2294
+cap "pmos_2uf2_0/w_n319_n202#" "pmos_2uf2_0/a_n63_n130#" 140.15
+cap "pmos_2uf2_0/a_n139_n100#" "nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n73_n69#" 7.86307
+cap "pmos_2uf2_0/w_n319_n202#" "pmos_2uf2_0/a_n139_n100#" 145
+merge "nmos_1u_0/VSUBS" "pmos_2uf2_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "pmos_2uf2_0/VSUBS" "VSUBS"
+merge "pmos_2uf2_0/a_n33_n100#" "Vout" -98.9592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -408 -92 0 0 0 0 0 0 0 0 0 0 0 0
+merge "nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n73_n69#" "GND" -49.256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2312 -204 0 0 0 0 0 0 0 0 0 0 0 0
+merge "pmos_2uf2_0/a_63_n100#" "pmos_2uf2_0/a_n139_n100#" -239.764 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4692 -412 0 0 0 0 0 0 0 0 0 0 0 0
+merge "pmos_2uf2_0/a_n139_n100#" "VDD"
+merge "nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89#" "a_160_62#" -240.143 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1620 -348 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "a_160_62#" "pmos_2uf2_0/a_33_n130#"
+merge "pmos_2uf2_0/a_33_n130#" "pmos_2uf2_0/a_n63_n130#"
+merge "pmos_2uf2_0/a_n63_n130#" "Vin"
diff --git a/mag/myinv_layout2/inv_W12.mag b/mag/myinv_layout2/inv_W12.mag
new file mode 100644
index 0000000..2c8da09
--- /dev/null
+++ b/mag/myinv_layout2/inv_W12.mag
@@ -0,0 +1,48 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1653304099
+<< error_s >>
+rect 160 10 190 16
+<< poly >>
+rect 156 466 282 506
+rect 156 436 190 466
+rect 84 416 190 436
+rect 84 370 100 416
+rect 150 370 190 416
+rect 84 352 190 370
+rect 160 242 190 352
+rect 160 62 190 68
+<< polycont >>
+rect 100 370 150 416
+<< locali >>
+rect -100 828 388 878
+rect 106 794 140 828
+rect 106 758 334 794
+rect 106 578 140 758
+rect 298 684 334 758
+rect 84 420 168 436
+rect -100 416 168 420
+rect -100 370 100 416
+rect 150 370 168 416
+rect -100 364 168 370
+rect 84 352 168 364
+rect 202 420 236 556
+rect 202 364 388 420
+rect 202 260 236 364
+rect 114 -20 148 116
+rect -100 -72 388 -20
+use nmos_1u#0 nmos_1u_0
+timestamp 1653304099
+transform 1 0 112 0 1 -38
+box -10 48 136 300
+use pmos_2uf2#0 pmos_2uf2_0
+timestamp 1651470485
+transform 1 0 219 0 1 622
+box -319 -202 169 204
+<< labels >>
+rlabel locali -100 390 -100 390 7 Vin
+rlabel locali 388 392 388 392 3 Vout
+rlabel locali -100 854 -100 854 7 VDD
+rlabel locali -100 -46 -100 -46 7 GND
+<< end >>
diff --git a/mag/myinv_layout2/inv_W16.ext b/mag/myinv_layout2/inv_W16.ext
new file mode 100755
index 0000000..f7c7033
--- /dev/null
+++ b/mag/myinv_layout2/inv_W16.ext
@@ -0,0 +1,141 @@
+timestamp 1646325283
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_3M44SC sky130_fd_pr__pfet_01v8_3M44SC_0 1 0 1587 0 1 700
+use sky130_fd_pr__nfet_01v8_VJWT33 sky130_fd_pr__nfet_01v8_VJWT33_0 1 0 1205 0 1 242
+node "li_n14_0#" 751 1488.16 -14 0 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 166504 6508 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_128_546#" 1950 2770.04 128 546 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 255720 12868 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n14_902#" 1454 1915.55 -14 902 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 253448 11084 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_468_358#" 214 496.36 468 358 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27648 688 0 0 32192 1292 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_82_816#" 3150 1218.38 82 816 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 138276 6104 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_598_546#" 77300 157.692 598 546 nw 0 0 0 0 52564 3160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_82_814#" 111091 414.828 82 814 nw 0 0 0 0 138276 6104 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_128_546#" "w_598_546#" 48.6217
+cap "li_n14_902#" "a_468_358#" 13.4357
+cap "li_n14_902#" "w_82_814#" 283.954
+cap "li_n14_902#" "li_128_546#" 310.984
+cap "a_468_358#" "li_n14_0#" 50.7778
+cap "li_n14_902#" "a_82_816#" 562.917
+cap "li_128_546#" "li_n14_0#" 272.424
+cap "li_128_546#" "a_468_358#" 425.592
+cap "a_468_358#" "a_82_816#" 12.1653
+cap "w_82_814#" "a_82_816#" 826.65
+cap "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n513_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n797_n74#" 155.797
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n797_n74#" 29.6436
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n513_n100#" 31.9355
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1503_n128#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n797_n74#" 7.08629
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1565_n74#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n513_n100#" 7.90745
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1565_n74#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n797_n74#" 51.8165
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1565_n74#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" 166.618
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1503_n128#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n513_n100#" 151.576
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1503_n128#" 163.354
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1565_n74#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1503_n128#" 13.4786
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" 553.099
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1503_n128#" 89.65
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1565_n74#" "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" 194.847
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n513_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n225_n100#" 154.243
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_927_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n225_n100#" 37.1376
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n513_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_927_n100#" 143.63
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n513_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" 463.472
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n513_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n735_n176#" 110.965
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n543_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n513_n100#" 96.875
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_927_n100#" 197.821
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n543_n128#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n735_n176#" 19.5829
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n543_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_927_n100#" -52.725
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n543_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" -225.775
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_801_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" -95.425
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_831_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_927_n100#" 19.6471
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_831_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" 92.39
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_927_n100#" 74.2228
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_639_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1407_n100#" -1832.37 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12172 -2084 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1407_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1215_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1215_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1023_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1023_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_831_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_831_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_639_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_639_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_447_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_447_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_255_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_255_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_447_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_447_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_63_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_63_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n705_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n705_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_255_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_255_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n129_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n129_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n321_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n321_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n513_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n513_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_63_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_63_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n129_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n129_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n321_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n321_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n513_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n513_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n705_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n705_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n897_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n897_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1089_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1089_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1281_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1281_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" "li_128_546#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/VSUBS" "sky130_fd_pr__pfet_01v8_3M44SC_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/VSUBS" "VSUBS"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1503_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1311_n100#" -821.67 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13020 -1516 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1311_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1119_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1119_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_735_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_735_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_543_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_543_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_351_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_351_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_927_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_927_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_159_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_159_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n33_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n225_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n225_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n417_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n417_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n609_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n609_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n801_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n801_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n993_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n993_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1185_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1185_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1377_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1377_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1565_n74#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1565_n74#" "li_n14_902#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1473_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1377_n128#" -530.201 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21792 -2980 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1377_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1281_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1281_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1185_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1185_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1089_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1089_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_993_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_993_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_897_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_897_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_801_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_801_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_705_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_705_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_609_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_609_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_513_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_513_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_417_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_417_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_321_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_321_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_225_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_225_n128#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n735_n176#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n735_n176#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_129_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_129_n126#" "a_468_358#"
+merge "a_468_358#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_33_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_33_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n63_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n63_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n159_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n159_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n255_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n255_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n351_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n351_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n447_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n447_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n543_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n543_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n639_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n639_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n735_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n735_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n831_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n831_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n927_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n927_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1023_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1023_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1119_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1119_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1215_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1215_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1311_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1311_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1407_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1407_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1503_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1503_n128#" "a_82_816#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_735_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_543_n100#" -410.172 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -13040 -1948 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_543_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_351_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_351_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_159_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_159_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n33_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n33_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n225_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n225_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n417_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n417_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n609_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n609_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n797_n74#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n797_n74#" "li_n14_0#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "w_598_546#" -472.248 0 0 0 0 -157416 -9264 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "w_598_546#" "w_82_814#"
diff --git a/mag/myinv_layout2/inv_W16.mag b/mag/myinv_layout2/inv_W16.mag
new file mode 100755
index 0000000..2bc4e67
--- /dev/null
+++ b/mag/myinv_layout2/inv_W16.mag
@@ -0,0 +1,83 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646325283
+<< nwell >>
+rect 82 814 3088 860
+rect 706 580 740 630
+rect 898 580 932 626
+rect 1090 580 1124 630
+rect 1282 580 1316 626
+rect 1474 580 1508 628
+rect 1666 580 1700 626
+rect 598 546 1858 580
+<< poly >>
+rect 82 816 3088 862
+rect 468 490 596 574
+rect 468 436 498 490
+rect 560 436 596 490
+rect 468 358 596 436
+<< polycont >>
+rect 498 436 560 490
+<< locali >>
+rect -14 902 3188 954
+rect 32 770 70 902
+rect 224 770 262 902
+rect 416 770 454 902
+rect 608 768 646 902
+rect 800 766 838 902
+rect 992 768 1030 902
+rect 1186 770 1224 902
+rect 1376 766 1414 902
+rect 1568 768 1606 902
+rect 1760 766 1798 902
+rect 1954 768 1992 902
+rect 2146 768 2184 902
+rect 2336 766 2374 902
+rect 2528 760 2566 902
+rect 2720 766 2758 902
+rect 2912 768 2950 902
+rect 3104 768 3142 902
+rect 130 580 164 628
+rect 322 580 356 630
+rect 514 580 548 626
+rect 706 580 740 630
+rect 898 580 932 626
+rect 1090 580 1124 630
+rect 1282 580 1316 626
+rect 1474 580 1508 628
+rect 1666 580 1700 626
+rect 1858 580 1892 628
+rect 2050 580 2084 632
+rect 128 546 2084 580
+rect 2050 494 2084 546
+rect 1944 492 2084 494
+rect 2242 492 2276 634
+rect 2434 492 2468 632
+rect 2626 492 2660 630
+rect 2818 492 2852 628
+rect 3010 492 3044 632
+rect -14 436 498 490
+rect 560 436 576 490
+rect 1944 436 3188 492
+rect -14 434 152 436
+rect 1944 390 2062 436
+rect 512 354 2062 390
+rect 514 314 552 354
+rect 706 300 744 354
+rect 900 304 938 354
+rect 1090 302 1128 354
+rect 1282 308 1320 354
+rect 1476 304 1514 354
+rect 1666 308 1704 354
+rect 1858 308 1896 354
+rect -14 0 3188 52
+use sky130_fd_pr__nfet_01v8_VJWT33 sky130_fd_pr__nfet_01v8_VJWT33_0
+timestamp 1646295505
+transform 1 0 1205 0 1 242
+box -797 -218 797 138
+use sky130_fd_pr__pfet_01v8_3M44SC sky130_fd_pr__pfet_01v8_3M44SC_0
+timestamp 1646261959
+transform 1 0 1587 0 1 700
+box -1601 -200 1601 200
+<< end >>
diff --git a/mag/myinv_layout2/inv_W2.ext b/mag/myinv_layout2/inv_W2.ext
new file mode 100755
index 0000000..8ce7a59
--- /dev/null
+++ b/mag/myinv_layout2/inv_W2.ext
@@ -0,0 +1,51 @@
+timestamp 1646324451
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_AC5Z8B sky130_fd_pr__pfet_01v8_AC5Z8B_0 1 0 141 0 1 654
+use sky130_fd_pr__nfet_01v8_XJTKXQ sky130_fd_pr__nfet_01v8_XJTKXQ_0 1 0 219 0 1 182
+node "GND" 207 364.064 -100 -72 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34556 1620 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vout" 91 169.775 202 260 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15108 760 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 120 244.033 -100 828 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24468 1080 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_156_12#" 127 111.727 156 12 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6048 348 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_252_300#" 56 32.867 252 300 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vin" 251 302.04 84 352 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10728 516 0 0 17360 704 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "Vin" "a_252_300#" 9.06061
+cap "a_156_12#" "a_252_300#" 2.875
+cap "a_156_12#" "Vin" 2.89916
+cap "Vout" "Vin" 81.5294
+cap "Vin" "VDD" 7.08611
+cap "Vin" "GND" 24.9623
+cap "Vout" "VDD" 3
+cap "Vout" "GND" 18.672
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" 6.10637
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" 11.1195
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" 12.3374
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" 42.0143
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" 30.4523
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" 67.2375
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" -7.15
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" 14.0899
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/VSUBS" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/VSUBS" "VSUBS"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_63_n100#" "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" -104.04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2828 -468 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_225_n726#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_225_n726#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" "GND"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_33_n122#" "a_252_300#" -117.03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -540 -336 0 0 -896 -144 0 0 0 0 0 0 0 0 0 0 0 0
+merge "a_252_300#" "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n122#"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n122#" "a_156_12#"
+merge "a_156_12#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n290#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n290#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "Vin"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_229_174#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_159_n100#" -147.998 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2968 -560 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_159_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n33_n100#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" "VDD"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_217_n290#" -76.2649 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2360 -348 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_217_n290#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "Vout"
diff --git a/mag/myinv_layout2/inv_W2.mag b/mag/myinv_layout2/inv_W2.mag
new file mode 100755
index 0000000..66c19e1
--- /dev/null
+++ b/mag/myinv_layout2/inv_W2.mag
@@ -0,0 +1,44 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646324451
+<< poly >>
+rect 156 436 186 454
+rect 84 416 186 436
+rect 84 370 100 416
+rect 150 370 186 416
+rect 84 352 186 370
+rect 156 298 186 352
+rect 252 300 282 326
+rect 156 12 282 60
+<< polycont >>
+rect 100 370 150 416
+<< locali >>
+rect -100 828 388 878
+rect 106 826 140 828
+rect 84 420 168 436
+rect -100 416 168 420
+rect -100 370 100 416
+rect 150 370 168 416
+rect -100 364 168 370
+rect 84 352 168 364
+rect 202 420 236 454
+rect 202 364 388 420
+rect 202 260 236 364
+rect 106 -20 140 114
+rect 298 -20 332 116
+rect -100 -72 388 -20
+use sky130_fd_pr__nfet_01v8_XJTKXQ sky130_fd_pr__nfet_01v8_XJTKXQ_0
+timestamp 1646324451
+transform 1 0 219 0 1 182
+box -125 -126 125 126
+use sky130_fd_pr__pfet_01v8_AC5Z8B sky130_fd_pr__pfet_01v8_AC5Z8B_0
+timestamp 1646324451
+transform 1 0 141 0 1 654
+box -261 -726 263 224
+<< labels >>
+rlabel locali -100 390 -100 390 7 Vin
+rlabel locali 388 392 388 392 3 Vout
+rlabel locali -100 -46 -100 -46 7 GND
+rlabel locali -100 854 -100 854 7 VDD
+<< end >>
diff --git a/mag/myinv_layout2/inv_W8.ext b/mag/myinv_layout2/inv_W8.ext
new file mode 100755
index 0000000..d9d0f4c
--- /dev/null
+++ b/mag/myinv_layout2/inv_W8.ext
@@ -0,0 +1,88 @@
+timestamp 1646325197
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_RL4NCG sky130_fd_pr__pfet_01v8_RL4NCG_0 1 0 1203 0 1 700
+use sky130_fd_pr__nfet_01v8_KZU588 sky130_fd_pr__nfet_01v8_KZU588_0 1 0 1207 0 1 240
+node "li_354_0#" 593 1060.48 354 0 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 108388 4684 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_512_546#" 863 631.918 512 546 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 140104 6384 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_354_902#" 770 236.98 354 902 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 134096 5912 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_804_430#" 376 362.728 804 430 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12672 616 0 0 28836 1176 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_466_816#" 1544 179.681 466 816 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67804 3040 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_354_500#" 6351 2309.95 354 500 nw 0 0 0 0 769984 4300 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_804_430#" "w_354_500#" 58.3
+cap "w_354_500#" "a_466_816#" 836
+cap "a_804_430#" "a_466_816#" 7.54446
+cap "w_354_500#" "li_354_902#" 955.68
+cap "a_466_816#" "li_354_902#" 262.695
+cap "a_804_430#" "li_354_902#" 13.5328
+cap "w_354_500#" "li_512_546#" 786.974
+cap "a_804_430#" "li_512_546#" 256.467
+cap "a_804_430#" "li_354_0#" 47.1553
+cap "li_512_546#" "li_354_902#" 185.517
+cap "li_354_0#" "li_512_546#" 141.711
+cap "sky130_fd_pr__nfet_01v8_KZU588_0/a_n413_n74#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" 132.841
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/w_n833_n200#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n735_n128#" -346.5
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n797_n74#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n735_n128#" 13.3917
+cap "sky130_fd_pr__nfet_01v8_KZU588_0/a_n413_n74#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n735_n128#" 106.409
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n735_n128#" 282.814
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n797_n74#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/w_n833_n200#" -134.154
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/w_n833_n200#" -121.474
+cap "sky130_fd_pr__nfet_01v8_KZU588_0/a_n413_n74#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n797_n74#" 46.5714
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n797_n74#" 167.333
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_255_n100#" "w_354_500#" -17.5026
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_255_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_225_n128#" 14.114
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_225_n128#" "w_354_500#" -46.2
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_255_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_159_n100#" 35.0677
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_159_n100#" "w_354_500#" -39.2199
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_351_n100#" "sky130_fd_pr__nfet_01v8_KZU588_0/a_159_n100#" -153.624 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3728 -428 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_159_n100#" "sky130_fd_pr__nfet_01v8_KZU588_0/a_n33_n100#"
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_n33_n100#" "sky130_fd_pr__nfet_01v8_KZU588_0/a_n225_n100#"
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_n225_n100#" "sky130_fd_pr__nfet_01v8_KZU588_0/a_n413_n74#"
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_n413_n74#" "li_354_0#"
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/VSUBS" "sky130_fd_pr__pfet_01v8_RL4NCG_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/VSUBS" "VSUBS"
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_n353_n162#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_705_n126#" -0.161601 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8656 -1512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_705_n126#" "a_804_430#"
+merge "a_804_430#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_609_n128#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_609_n128#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_513_n126#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_513_n126#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_417_n128#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_417_n128#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_321_n126#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_321_n126#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_225_n128#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_225_n128#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_129_n126#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_129_n126#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_33_n128#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_33_n128#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n63_n126#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n63_n126#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n159_n128#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n159_n128#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n255_n126#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n255_n126#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n351_n128#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n351_n128#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n447_n126#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n447_n126#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n543_n128#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n543_n128#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n639_n126#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n639_n126#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n735_n128#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n735_n128#" "a_466_816#"
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_255_n100#" "sky130_fd_pr__nfet_01v8_KZU588_0/a_63_n100#" -246.038 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5360 -1108 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_63_n100#" "sky130_fd_pr__nfet_01v8_KZU588_0/a_n321_n100#"
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_n321_n100#" "sky130_fd_pr__nfet_01v8_KZU588_0/li_321_116#"
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/li_321_116#" "sky130_fd_pr__nfet_01v8_KZU588_0/a_n129_n100#"
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_n129_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_639_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_639_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_447_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_447_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_255_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_255_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_63_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_63_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n129_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n129_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n321_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n321_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n513_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n513_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" "li_512_546#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_735_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_543_n100#" -26.0875 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4572 -796 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_543_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_351_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_351_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_159_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_159_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n33_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n225_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n225_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n417_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n417_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n609_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n609_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n797_n74#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n797_n74#" "li_354_902#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/w_n833_n200#" "w_354_500#" -2380.46 0 0 0 0 -793488 -5178 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/myinv_layout2/inv_W8.mag b/mag/myinv_layout2/inv_W8.mag
new file mode 100755
index 0000000..e2886a7
--- /dev/null
+++ b/mag/myinv_layout2/inv_W8.mag
@@ -0,0 +1,63 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646325197
+<< nwell >>
+rect 354 500 2050 954
+<< poly >>
+rect 466 816 1940 862
+rect 848 498 892 584
+rect 804 482 892 498
+rect 804 446 820 482
+rect 856 446 892 482
+rect 804 430 892 446
+rect 848 364 892 430
+<< polycont >>
+rect 820 446 856 482
+<< locali >>
+rect 354 902 2050 954
+rect 416 770 454 902
+rect 608 768 646 902
+rect 800 766 838 902
+rect 992 768 1030 902
+rect 1186 770 1224 902
+rect 1376 766 1414 902
+rect 1568 768 1606 902
+rect 1760 766 1798 902
+rect 1954 768 1992 902
+rect 514 580 548 626
+rect 706 580 740 630
+rect 898 580 932 626
+rect 1090 580 1124 630
+rect 1282 580 1316 626
+rect 1474 580 1508 628
+rect 1666 580 1700 626
+rect 1858 580 1892 628
+rect 512 546 1898 580
+rect 1516 492 1664 546
+rect 354 482 888 490
+rect 354 446 820 482
+rect 856 446 888 482
+rect 354 436 888 446
+rect 1516 436 2050 492
+rect 1516 390 1668 436
+rect 900 354 1668 390
+rect 900 304 938 354
+rect 1090 302 1128 354
+rect 1282 308 1320 354
+rect 1476 304 1514 354
+rect 806 52 840 168
+rect 998 52 1032 174
+rect 1190 52 1224 168
+rect 1382 52 1416 174
+rect 1574 52 1608 170
+rect 354 0 2050 52
+use sky130_fd_pr__nfet_01v8_KZU588 sky130_fd_pr__nfet_01v8_KZU588_0
+timestamp 1646318752
+transform 1 0 1207 0 1 240
+box -413 -162 413 150
+use sky130_fd_pr__pfet_01v8_RL4NCG sky130_fd_pr__pfet_01v8_RL4NCG_0
+timestamp 1646319668
+transform 1 0 1203 0 1 700
+box -833 -200 833 200
+<< end >>
diff --git "a/mag/myinv_layout2/nmos_1u\0430.ext" "b/mag/myinv_layout2/nmos_1u\0430.ext"
new file mode 100755
index 0000000..4997c06
--- /dev/null
+++ "b/mag/myinv_layout2/nmos_1u\0430.ext"
@@ -0,0 +1,9 @@
+timestamp 1653304099
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__nfet_01v8_7RYEVP sky130_fd_pr__nfet_01v8_7RYEVP_0 1 0 63 0 1 143
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS" "VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
diff --git "a/mag/myinv_layout2/nmos_1u\0430.mag" "b/mag/myinv_layout2/nmos_1u\0430.mag"
new file mode 100755
index 0000000..43e26b7
--- /dev/null
+++ "b/mag/myinv_layout2/nmos_1u\0430.mag"
@@ -0,0 +1,11 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1653304099
+<< error_p >>
+rect 48 48 78 54
+use sky130_fd_pr__nfet_01v8_7RYEVP sky130_fd_pr__nfet_01v8_7RYEVP_0 ~/my_sky130_project/mag/myinv_layout2
+timestamp 1651470485
+transform 1 0 63 0 1 143
+box -73 -95 73 157
+<< end >>
diff --git a/mag/myinv_layout2/pmos_2u.mag b/mag/myinv_layout2/pmos_2u.mag
new file mode 100755
index 0000000..28c9b08
--- /dev/null
+++ b/mag/myinv_layout2/pmos_2u.mag
@@ -0,0 +1,66 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645075726
+<< error_s >>
+rect 890 113 948 119
+rect 890 79 902 113
+rect 890 73 948 79
+<< nwell >>
+rect -156 418 314 800
+<< pmos >>
+rect 46 480 76 680
+rect 134 480 164 680
+<< pdiff >>
+rect -20 644 46 680
+rect -20 520 0 644
+rect 34 520 46 644
+rect -20 480 46 520
+rect 76 644 134 680
+rect 76 520 88 644
+rect 122 520 134 644
+rect 76 480 134 520
+rect 164 644 222 680
+rect 164 520 176 644
+rect 210 520 222 644
+rect 164 480 222 520
+<< pdiffc >>
+rect 0 520 34 644
+rect 88 520 122 644
+rect 176 520 210 644
+<< nsubdiff >>
+rect -114 644 -20 680
+rect -114 520 -78 644
+rect -44 520 -20 644
+rect -114 480 -20 520
+<< nsubdiffcont >>
+rect -78 520 -44 644
+<< poly >>
+rect 46 680 76 730
+rect 134 680 164 730
+rect 46 428 76 480
+rect 134 428 164 480
+<< locali >>
+rect -106 644 40 680
+rect -106 520 -78 644
+rect -44 520 0 644
+rect 34 520 40 644
+rect -106 482 40 520
+rect -6 480 40 482
+rect 82 644 128 680
+rect 82 520 88 644
+rect 122 520 128 644
+rect 82 480 128 520
+rect 170 644 216 680
+rect 170 520 176 644
+rect 210 520 216 644
+rect 170 480 216 520
+use pmos_2uf2 sky130_fd_pr__pfet_01v8_SBMASV_0
+timestamp 1645025748
+transform 1 0 871 0 1 -68
+box -317 -202 169 204
+use sky130_fd_pr__pfet_01v8_U9MAPM sky130_fd_pr__pfet_01v8_U9MAPM_0
+timestamp 1645025748
+transform 1 0 1355 0 1 -78
+box 0 0 1 1
+<< end >>
diff --git "a/mag/myinv_layout2/pmos_2uf2\0430.ext" "b/mag/myinv_layout2/pmos_2uf2\0430.ext"
new file mode 100755
index 0000000..51cf1c7
--- /dev/null
+++ "b/mag/myinv_layout2/pmos_2uf2\0430.ext"
@@ -0,0 +1,25 @@
+timestamp 1651470485
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n100#" 712 -156.62 63 -100 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 5152 316 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 653 -77.9 -33 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n139_n100#" 550 -160.72 -139 -100 pdif 0 0 0 0 0 0 0 0 0 0 15200 552 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9360 432 5152 316 0 0 0 0 0 0 0 0 0 0
+node "a_33_n130#" 411 4.452 33 -130 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7680 572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n63_n130#" 411 4.452 -63 -130 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7680 572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n319_n202#" 2043 594.384 -319 -202 nw 0 0 0 0 198128 1788 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_n319_n202#" "a_n33_n100#" 77.9
+cap "w_n319_n202#" "a_n63_n130#" 47.3
+cap "a_n139_n100#" "a_63_n100#" 67.1028
+cap "w_n319_n202#" "a_33_n130#" 47.3
+cap "a_n139_n100#" "a_n33_n100#" 83.0323
+cap "w_n319_n202#" "a_n139_n100#" 153.34
+cap "a_n63_n130#" "a_33_n130#" 19.5152
+cap "a_n33_n100#" "a_63_n100#" 83.0323
+cap "w_n319_n202#" "a_63_n100#" 142.68
+device msubckt sky130_fd_pr__pfet_01v8 33 -100 34 -99 l=30 w=200 "w_n319_n202#" "a_33_n130#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -63 -100 -62 -99 l=30 w=200 "w_n319_n202#" "a_n63_n130#" 60 0 "a_n139_n100#" 200 0 "a_n33_n100#" 200 0
diff --git "a/mag/myinv_layout2/pmos_2uf2\0430.mag" "b/mag/myinv_layout2/pmos_2uf2\0430.mag"
new file mode 100755
index 0000000..8ec261d
--- /dev/null
+++ "b/mag/myinv_layout2/pmos_2uf2\0430.mag"
@@ -0,0 +1,58 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1651470485
+<< nwell >>
+rect -319 -202 169 204
+<< pmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< pdiff >>
+rect -139 62 -63 100
+rect -139 -62 -113 62
+rect -79 -62 -63 62
+rect -139 -100 -63 -62
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 74 121 100
+rect 63 62 125 74
+rect 63 -62 79 62
+rect 113 -62 125 62
+rect 63 -74 125 -62
+rect 63 -100 121 -74
+<< pdiffc >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< poly >>
+rect -63 100 -33 126
+rect 33 100 63 126
+rect -63 -130 -33 -100
+rect 33 -130 63 -100
+<< locali >>
+rect -139 62 -79 78
+rect -139 -62 -113 62
+rect -139 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+<< viali >>
+rect -113 -44 -79 44
+rect 79 -44 113 44
+<< metal1 >>
+rect -119 44 -73 56
+rect -119 -44 -113 44
+rect -79 -44 -73 44
+rect -119 -56 -73 -44
+rect 73 44 119 56
+rect 73 -44 79 44
+rect 113 -44 119 44
+rect 73 -56 119 -44
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 50 viadrn 50 viagate 50 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130A.magicrc b/mag/myinv_layout2/sky130A.magicrc
new file mode 100755
index 0000000..ea1e753
--- /dev/null
+++ b/mag/myinv_layout2/sky130A.magicrc
@@ -0,0 +1,87 @@
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+# Change this to a fixed number for repeatable behavior with GDS writes
+# e.g., "random seed 12345"
+catch {random seed}
+
+# Turn off the scale option on ext2spice or else it conflicts with the
+# scale in the model files.
+ext2spice scale off
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "/usr/local/share/pdk/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/sky130A.tech
+
+
+# load device generator
+source $PDKPATH/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE mag
+}
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_ml_xx_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_sram_macros
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_sram_macros/${MAGTYPE}
+}
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.ext b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.ext
new file mode 100755
index 0000000..24a493e
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.ext
@@ -0,0 +1,15 @@
+timestamp 1644925353
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n69#" 481 18.86 15 -69 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5984 420 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n69#" 481 18.86 -73 -69 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5984 420 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n157#" 514 144.799 -33 -157 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11796 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n69#" "a_15_n69#" 321.841
+cap "a_n73_n69#" "a_n33_n157#" 15.21
+cap "a_n33_n157#" "a_15_n69#" 15.21
+device msubckt sky130_fd_pr__nfet_01v8 -15 -69 -14 -68 l=30 w=200 "VSUBS" "a_n33_n157#" 60 0 "a_n73_n69#" 200 0 "a_15_n69#" 200 0
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.mag
new file mode 100755
index 0000000..c8b66a6
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.mag
@@ -0,0 +1,62 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1644925353
+<< error_p >>
+rect -73 -69 -15 131
+rect 15 -69 73 131
+rect -29 -107 29 -101
+rect -29 -141 -17 -107
+rect -29 -147 29 -141
+<< nmos >>
+rect -15 -69 15 131
+<< ndiff >>
+rect -73 93 -15 131
+rect -73 -31 -61 93
+rect -27 -31 -15 93
+rect -73 -69 -15 -31
+rect 15 93 73 131
+rect 15 -31 27 93
+rect 61 -31 73 93
+rect 15 -69 73 -31
+<< ndiffc >>
+rect -61 -31 -27 93
+rect 27 -31 61 93
+<< poly >>
+rect -15 131 15 157
+rect -15 -91 15 -69
+rect -33 -107 33 -91
+rect -33 -141 -17 -107
+rect 17 -141 33 -107
+rect -33 -157 33 -141
+<< polycont >>
+rect -17 -141 17 -107
+<< locali >>
+rect -33 -141 -17 -107
+rect 17 -141 33 -107
+<< viali >>
+rect -61 93 -27 119
+rect -61 -31 -27 93
+rect -61 -57 -27 -31
+rect 27 93 61 119
+rect 27 -31 61 93
+rect 27 -57 61 -31
+rect -17 -141 17 -107
+<< metal1 >>
+rect -67 119 -21 131
+rect -67 -57 -61 119
+rect -27 -57 -21 119
+rect -67 -69 -21 -57
+rect 21 119 67 131
+rect 21 -57 27 119
+rect 61 -57 67 119
+rect 21 -69 67 -57
+rect -29 -107 29 -101
+rect -29 -141 -17 -107
+rect 17 -141 29 -107
+rect -29 -147 29 -141
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 1 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_8P2286.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_8P2286.mag
new file mode 100755
index 0000000..4f08242
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_8P2286.mag
@@ -0,0 +1,94 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646248588
+<< error_p >>
+rect 19 272 77 278
+rect 19 238 31 272
+rect 19 232 77 238
+rect -77 -238 -19 -232
+rect -77 -272 -65 -238
+rect -77 -278 -19 -272
+<< nmos >>
+rect -63 -200 -33 200
+rect 33 -200 63 200
+<< ndiff >>
+rect -121 144 -63 200
+rect -125 132 -63 144
+rect -125 -132 -113 132
+rect -79 -132 -63 132
+rect -125 -144 -63 -132
+rect -121 -200 -63 -144
+rect -33 132 33 200
+rect -33 -132 -17 132
+rect 17 -132 33 132
+rect -33 -200 33 -132
+rect 63 144 121 200
+rect 63 132 125 144
+rect 63 -132 79 132
+rect 113 -132 125 132
+rect 63 -144 125 -132
+rect 63 -200 121 -144
+<< ndiffc >>
+rect -113 -132 -79 132
+rect -17 -132 17 132
+rect 79 -132 113 132
+<< poly >>
+rect 15 272 81 288
+rect 15 238 31 272
+rect 65 238 81 272
+rect -63 200 -33 226
+rect 15 222 81 238
+rect 33 200 63 222
+rect -63 -222 -33 -200
+rect -81 -238 -15 -222
+rect 33 -226 63 -200
+rect -81 -272 -65 -238
+rect -31 -272 -15 -238
+rect -81 -288 -15 -272
+<< polycont >>
+rect 31 238 65 272
+rect -65 -272 -31 -238
+<< locali >>
+rect 15 238 31 272
+rect 65 238 81 272
+rect -113 132 -79 148
+rect -113 -148 -79 -132
+rect -17 132 17 148
+rect -17 -148 17 -132
+rect 79 132 113 148
+rect 79 -148 113 -132
+rect -81 -272 -65 -238
+rect -31 -272 -15 -238
+<< viali >>
+rect 31 238 65 272
+rect -113 -132 -79 132
+rect -17 -132 17 132
+rect 79 -132 113 132
+rect -65 -272 -31 -238
+<< metal1 >>
+rect 19 272 77 278
+rect 19 238 31 272
+rect 65 238 77 272
+rect 19 232 77 238
+rect -119 132 -73 144
+rect -119 -132 -113 132
+rect -79 -132 -73 132
+rect -119 -144 -73 -132
+rect -23 132 23 144
+rect -23 -132 -17 132
+rect 17 -132 23 132
+rect -23 -144 23 -132
+rect 73 132 119 144
+rect 73 -132 79 132
+rect 113 -132 119 132
+rect 73 -144 119 -132
+rect -77 -238 -19 -232
+rect -77 -272 -65 -238
+rect -31 -272 -19 -238
+rect -77 -278 -19 -272
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 2 l 0.150 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_A2RL69.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_A2RL69.mag
new file mode 100755
index 0000000..0a0b357
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_A2RL69.mag
@@ -0,0 +1,90 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646248588
+<< error_p >>
+rect 19 172 77 178
+rect 19 138 31 172
+rect 19 132 77 138
+rect -77 -138 -19 -132
+rect -77 -172 -65 -138
+rect -77 -178 -19 -172
+<< nmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< ndiff >>
+rect -125 88 -63 100
+rect -125 -88 -113 88
+rect -79 -88 -63 88
+rect -125 -100 -63 -88
+rect -33 88 33 100
+rect -33 -88 -17 88
+rect 17 -88 33 88
+rect -33 -100 33 -88
+rect 63 88 125 100
+rect 63 -88 79 88
+rect 113 -88 125 88
+rect 63 -100 125 -88
+<< ndiffc >>
+rect -113 -88 -79 88
+rect -17 -88 17 88
+rect 79 -88 113 88
+<< poly >>
+rect 15 172 81 188
+rect 15 138 31 172
+rect 65 138 81 172
+rect -63 100 -33 126
+rect 15 122 81 138
+rect 33 100 63 122
+rect -63 -122 -33 -100
+rect -81 -138 -15 -122
+rect 33 -126 63 -100
+rect -81 -172 -65 -138
+rect -31 -172 -15 -138
+rect -81 -188 -15 -172
+<< polycont >>
+rect 31 138 65 172
+rect -65 -172 -31 -138
+<< locali >>
+rect 15 138 31 172
+rect 65 138 81 172
+rect -113 88 -79 104
+rect -113 -104 -79 -88
+rect -17 88 17 104
+rect -17 -104 17 -88
+rect 79 88 113 104
+rect 79 -104 113 -88
+rect -81 -172 -65 -138
+rect -31 -172 -15 -138
+<< viali >>
+rect 31 138 65 172
+rect -113 -88 -79 88
+rect -17 -88 17 88
+rect 79 -88 113 88
+rect -65 -172 -31 -138
+<< metal1 >>
+rect 19 172 77 178
+rect 19 138 31 172
+rect 65 138 77 172
+rect 19 132 77 138
+rect -119 88 -73 100
+rect -119 -88 -113 88
+rect -79 -88 -73 88
+rect -119 -100 -73 -88
+rect -23 88 23 100
+rect -23 -88 -17 88
+rect 17 -88 23 88
+rect -23 -100 23 -88
+rect 73 88 119 100
+rect 73 -88 79 88
+rect 113 -88 119 88
+rect 73 -100 119 -88
+rect -77 -138 -19 -132
+rect -77 -172 -65 -138
+rect -31 -172 -19 -138
+rect -77 -178 -19 -172
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 2 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_CJHXAH.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_CJHXAH.mag
new file mode 100755
index 0000000..4e90e0a
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_CJHXAH.mag
@@ -0,0 +1,119 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646248588
+<< error_p >>
+rect 19 272 77 278
+rect 19 238 31 272
+rect 19 232 77 238
+rect -77 -238 -19 -232
+rect -77 -272 -65 -238
+rect -77 -278 -19 -272
+<< pwell >>
+rect -263 -410 263 410
+<< nmos >>
+rect -63 -200 -33 200
+rect 33 -200 63 200
+<< ndiff >>
+rect -121 144 -63 200
+rect -125 132 -63 144
+rect -125 -132 -113 132
+rect -79 -132 -63 132
+rect -125 -144 -63 -132
+rect -121 -200 -63 -144
+rect -33 132 33 200
+rect -33 -132 -17 132
+rect 17 -132 33 132
+rect -33 -200 33 -132
+rect 63 144 121 200
+rect 63 132 125 144
+rect 63 -132 79 132
+rect 113 -132 125 132
+rect 63 -144 125 -132
+rect 63 -200 121 -144
+<< ndiffc >>
+rect -113 -132 -79 132
+rect -17 -132 17 132
+rect 79 -132 113 132
+<< psubdiff >>
+rect -227 340 -92 374
+rect 92 340 227 374
+rect -227 195 -193 340
+rect -227 -340 -193 -195
+rect 193 195 227 340
+rect 193 -340 227 -195
+rect -227 -374 -92 -340
+rect 92 -374 227 -340
+<< psubdiffcont >>
+rect -92 340 92 374
+rect -227 -195 -193 195
+rect 193 -195 227 195
+rect -92 -374 92 -340
+<< poly >>
+rect 15 272 81 288
+rect 15 238 31 272
+rect 65 238 81 272
+rect -63 200 -33 226
+rect 15 222 81 238
+rect 33 200 63 222
+rect -63 -222 -33 -200
+rect -81 -238 -15 -222
+rect 33 -226 63 -200
+rect -81 -272 -65 -238
+rect -31 -272 -15 -238
+rect -81 -288 -15 -272
+<< polycont >>
+rect 31 238 65 272
+rect -65 -272 -31 -238
+<< locali >>
+rect -227 340 -92 374
+rect 92 340 227 374
+rect -227 195 -193 340
+rect 15 238 31 272
+rect 65 238 81 272
+rect 193 195 227 340
+rect -113 132 -79 148
+rect -113 -148 -79 -132
+rect -17 132 17 148
+rect -17 -148 17 -132
+rect 79 132 113 148
+rect 79 -148 113 -132
+rect -227 -340 -193 -195
+rect -81 -272 -65 -238
+rect -31 -272 -15 -238
+rect 193 -340 227 -195
+rect -227 -374 -92 -340
+rect 92 -374 227 -340
+<< viali >>
+rect 31 238 65 272
+rect -113 -132 -79 132
+rect -17 -132 17 132
+rect 79 -132 113 132
+rect -65 -272 -31 -238
+<< metal1 >>
+rect 19 272 77 278
+rect 19 238 31 272
+rect 65 238 77 272
+rect 19 232 77 238
+rect -119 132 -73 144
+rect -119 -132 -113 132
+rect -79 -132 -73 132
+rect -119 -144 -73 -132
+rect -23 132 23 144
+rect -23 -132 -17 132
+rect 17 -132 23 132
+rect -23 -144 23 -132
+rect 73 132 119 144
+rect 73 -132 79 132
+rect 113 -132 119 132
+rect 73 -144 119 -132
+rect -77 -238 -19 -232
+rect -77 -272 -65 -238
+rect -31 -272 -19 -238
+rect -77 -278 -19 -272
+<< properties >>
+string FIXED_BBOX -210 -357 210 357
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 2 l 0.150 m 1 nf 2 diffcov 70 polycov 70 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 70 rlcov 70 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.ext b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.ext
new file mode 100755
index 0000000..f01472d
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.ext
@@ -0,0 +1,54 @@
+timestamp 1646318752
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "li_321_116#" 20 13.53 321 116 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 540 96 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_351_n100#" 456 -13.94 351 -100 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_255_n100#" 420 -13.94 255 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_159_n100#" 420 -13.94 159 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_63_n100#" 420 -13.94 63 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 420 -13.94 -33 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n129_n100#" 420 -13.94 -129 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n225_n100#" 420 -13.94 -225 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n321_n100#" 420 -13.94 -321 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n413_n74#" 456 -13.94 -413 -74 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n353_n162#" 4022 764.376 -353 -162 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90708 5568 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_159_n100#" "a_255_n100#" 216.232
+cap "a_255_n100#" "a_351_n100#" 216.232
+cap "a_159_n100#" "a_351_n100#" 78.1987
+cap "a_255_n100#" "a_63_n100#" 78.1987
+cap "a_159_n100#" "a_63_n100#" 216.232
+cap "a_351_n100#" "a_63_n100#" 47.7884
+cap "a_n225_n100#" "a_159_n100#" 34.4127
+cap "a_n129_n100#" "a_159_n100#" 47.7884
+cap "a_255_n100#" "a_n33_n100#" 47.7884
+cap "a_159_n100#" "a_n33_n100#" 78.1987
+cap "a_n129_n100#" "a_255_n100#" 34.4127
+cap "a_n225_n100#" "a_63_n100#" 47.7884
+cap "a_n321_n100#" "a_63_n100#" 34.4127
+cap "a_351_n100#" "a_n33_n100#" 34.4127
+cap "a_n33_n100#" "a_63_n100#" 216.232
+cap "a_n129_n100#" "a_63_n100#" 78.1987
+cap "a_n225_n100#" "a_n321_n100#" 216.232
+cap "a_n225_n100#" "a_n33_n100#" 78.1987
+cap "a_n129_n100#" "a_n225_n100#" 216.232
+cap "a_n33_n100#" "a_n321_n100#" 47.7884
+cap "a_n129_n100#" "a_n321_n100#" 78.1987
+cap "a_n129_n100#" "a_n33_n100#" 216.232
+cap "li_321_116#" "a_n353_n162#" 9.069
+cap "a_n413_n74#" "a_n321_n100#" 216.232
+cap "a_n225_n100#" "a_n413_n74#" 78.1987
+cap "a_n129_n100#" "a_n413_n74#" 47.7884
+cap "a_n413_n74#" "a_n33_n100#" 34.4127
+device msubckt sky130_fd_pr__nfet_01v8 321 -100 322 -99 l=30 w=200 "VSUBS" "a_n353_n162#" 60 0 "a_255_n100#" 200 0 "a_351_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 225 -100 226 -99 l=30 w=200 "VSUBS" "a_n353_n162#" 60 0 "a_159_n100#" 200 0 "a_255_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 129 -100 130 -99 l=30 w=200 "VSUBS" "a_n353_n162#" 60 0 "a_63_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 33 -100 34 -99 l=30 w=200 "VSUBS" "a_n353_n162#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -63 -100 -62 -99 l=30 w=200 "VSUBS" "a_n353_n162#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -159 -100 -158 -99 l=30 w=200 "VSUBS" "a_n353_n162#" 60 0 "a_n225_n100#" 200 0 "a_n129_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -255 -100 -254 -99 l=30 w=200 "VSUBS" "a_n353_n162#" 60 0 "a_n321_n100#" 200 0 "a_n225_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -351 -100 -350 -99 l=30 w=200 "VSUBS" "a_n353_n162#" 60 0 "a_n413_n74#" 200 0 "a_n321_n100#" 200 0
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.mag
new file mode 100755
index 0000000..b7232f5
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.mag
@@ -0,0 +1,157 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646318752
+<< error_p >>
+rect 321 134 351 150
+rect 321 116 355 134
+<< nmos >>
+rect -351 -100 -321 100
+rect -255 -100 -225 100
+rect -159 -100 -129 100
+rect -63 -100 -33 100
+rect 33 -100 63 100
+rect 129 -100 159 100
+rect 225 -100 255 100
+rect 321 -100 351 100
+<< ndiff >>
+rect -409 74 -351 100
+rect -413 62 -351 74
+rect -413 -62 -401 62
+rect -367 -62 -351 62
+rect -413 -74 -351 -62
+rect -409 -100 -351 -74
+rect -321 62 -255 100
+rect -321 -62 -305 62
+rect -271 -62 -255 62
+rect -321 -100 -255 -62
+rect -225 62 -159 100
+rect -225 -62 -209 62
+rect -175 -62 -159 62
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+<< ndiffc >>
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+<< poly >>
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+rect 321 -120 351 -100
+rect -353 -162 351 -120
+<< locali >>
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+<< viali >>
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+rect 79 -62 113 62
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+rect 271 -62 305 62
+rect 367 -62 401 62
+<< metal1 >>
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+rect -311 62 -265 74
+rect -311 -62 -305 62
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+rect 305 -62 311 62
+rect 265 -74 311 -62
+rect 361 62 407 74
+rect 361 -62 367 62
+rect 401 -62 407 62
+rect 361 -74 407 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 8 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.ext b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.ext
new file mode 100755
index 0000000..b0142d4
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.ext
@@ -0,0 +1,15 @@
+timestamp 0
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n69#" 489 22.3916 15 -69 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n69#" 489 22.3916 -73 -69 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n157#" 513 114.359 -33 -157 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11796 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n69#" "a_15_n69#" 341.397
+cap "a_n33_n157#" "a_15_n69#" 17.0735
+cap "a_n73_n69#" "a_n33_n157#" 17.0735
+device msubckt sky130_fd_pr__nfet_01v8 -15 -69 -14 -68 l=30 w=200 "VSUBS" "a_n33_n157#" 60 0 "a_n73_n69#" 200 0 "a_15_n69#" 200 0
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.mag
new file mode 100755
index 0000000..30b7f23
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.mag
@@ -0,0 +1,60 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1644851365
+<< error_p >>
+rect -29 -107 29 -101
+rect -29 -141 -17 -107
+rect -29 -147 29 -141
+<< nmos >>
+rect -15 -69 15 131
+<< ndiff >>
+rect -73 119 -15 131
+rect -73 -57 -61 119
+rect -27 -57 -15 119
+rect -73 -69 -15 -57
+rect 15 119 73 131
+rect 15 -57 27 119
+rect 61 -57 73 119
+rect 15 -69 73 -57
+<< ndiffc >>
+rect -61 -57 -27 119
+rect 27 -57 61 119
+<< poly >>
+rect -15 131 15 157
+rect -15 -91 15 -69
+rect -33 -107 33 -91
+rect -33 -141 -17 -107
+rect 17 -141 33 -107
+rect -33 -157 33 -141
+<< polycont >>
+rect -17 -141 17 -107
+<< locali >>
+rect -61 119 -27 135
+rect -61 -73 -27 -57
+rect 27 119 61 135
+rect 27 -73 61 -57
+rect -33 -141 -17 -107
+rect 17 -141 33 -107
+<< viali >>
+rect -61 -57 -27 119
+rect 27 -57 61 119
+rect -17 -141 17 -107
+<< metal1 >>
+rect -67 119 -21 131
+rect -67 -57 -61 119
+rect -27 -57 -21 119
+rect -67 -69 -21 -57
+rect 21 119 67 131
+rect 21 -57 27 119
+rect 61 -57 67 119
+rect 21 -69 67 -57
+rect -29 -107 29 -101
+rect -29 -141 -17 -107
+rect 17 -141 29 -107
+rect -29 -147 29 -141
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ7V57.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ7V57.mag
new file mode 100755
index 0000000..92bd77e
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ7V57.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646248588
+<< nmos >>
+rect -15 -100 15 100
+<< ndiff >>
+rect -73 88 -15 100
+rect -73 -88 -61 88
+rect -27 -88 -15 88
+rect -73 -100 -15 -88
+rect 15 88 73 100
+rect 15 -88 27 88
+rect 61 -88 73 88
+rect 15 -100 73 -88
+<< ndiffc >>
+rect -61 -88 -27 88
+rect 27 -88 61 88
+<< poly >>
+rect -15 100 15 126
+rect -15 -126 15 -100
+<< locali >>
+rect -61 88 -27 104
+rect -61 -104 -27 -88
+rect 27 88 61 104
+rect 27 -104 61 -88
+<< viali >>
+rect -61 -88 -27 88
+rect 27 -88 61 88
+<< metal1 >>
+rect -67 88 -21 100
+rect -67 -88 -61 88
+rect -27 -88 -21 88
+rect -67 -100 -21 -88
+rect 21 88 67 100
+rect 21 -88 27 88
+rect 61 -88 67 88
+rect 21 -100 67 -88
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.ext b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.ext
new file mode 100755
index 0000000..0004cc1
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.ext
@@ -0,0 +1,107 @@
+timestamp 1646295505
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_735_n100#" 495 42.4035 735 -100 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10960 660 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_639_n100#" 420 -13.94 639 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_543_n100#" 457 13.6771 543 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10756 648 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_447_n100#" 420 -13.94 447 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_351_n100#" 457 13.6771 351 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10756 648 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_255_n100#" 420 -13.94 255 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_159_n100#" 459 15.4725 159 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10892 656 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_63_n100#" 420 -13.94 63 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 459 15.4725 -33 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10892 656 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n129_n100#" 420 -13.94 -129 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n225_n100#" 456 12.7794 -225 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10688 644 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n321_n100#" 420 -13.94 -321 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n417_n100#" 461 18.1656 -417 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11096 668 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n513_n100#" 420 -13.94 -513 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n609_n100#" 462 19.961 -609 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11232 676 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n705_n100#" 420 -13.94 -705 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n797_n74#" 495 42.4035 -797 -74 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10960 660 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n735_n176#" 7099 1578.9 -735 -176 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 205736 11084 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_159_n100#" "a_n33_n100#" 106.977
+cap "a_447_n100#" "a_255_n100#" 78.1987
+cap "a_543_n100#" "a_639_n100#" 217.373
+cap "a_n609_n100#" "a_n321_n100#" 47.8072
+cap "a_255_n100#" "a_159_n100#" 216.82
+cap "a_n225_n100#" "a_n33_n100#" 106.123
+cap "a_n705_n100#" "a_n321_n100#" 34.4127
+cap "a_n609_n100#" "a_n513_n100#" 216.574
+cap "a_n321_n100#" "a_n33_n100#" 47.8216
+cap "a_447_n100#" "a_735_n100#" 47.8028
+cap "a_351_n100#" "a_n735_n176#" 46.3846
+cap "a_351_n100#" "a_447_n100#" 217.373
+cap "a_n129_n100#" "a_n417_n100#" 47.8092
+cap "a_351_n100#" "a_159_n100#" 105.697
+cap "a_447_n100#" "a_63_n100#" 34.4127
+cap "a_n705_n100#" "a_n513_n100#" 78.1987
+cap "a_n797_n74#" "a_n417_n100#" 47.0941
+cap "a_639_n100#" "a_255_n100#" 34.4127
+cap "a_63_n100#" "a_159_n100#" 216.82
+cap "a_n129_n100#" "a_159_n100#" 47.8216
+cap "a_n705_n100#" "a_n609_n100#" 216.339
+cap "a_543_n100#" "a_255_n100#" 47.809
+cap "a_n129_n100#" "a_n225_n100#" 217.487
+cap "a_63_n100#" "a_n225_n100#" 47.8575
+cap "a_639_n100#" "a_735_n100#" 216.481
+cap "a_63_n100#" "a_n321_n100#" 34.4127
+cap "a_n129_n100#" "a_n321_n100#" 78.1987
+cap "a_351_n100#" "a_639_n100#" 47.8512
+cap "a_n735_n176#" "a_n417_n100#" 46.3846
+cap "a_543_n100#" "a_735_n100#" 106.124
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+cap "a_447_n100#" "a_159_n100#" 47.8216
+cap "a_n225_n100#" "a_n417_n100#" 105.234
+cap "a_n225_n100#" "a_n735_n176#" 46.3846
+cap "a_n797_n74#" "a_n513_n100#" 47.8028
+cap "a_n417_n100#" "a_n321_n100#" 216.599
+cap "a_n225_n100#" "a_159_n100#" 46.5022
+cap "a_351_n100#" "a_n33_n100#" 46.5284
+cap "a_n797_n74#" "a_n609_n100#" 106.538
+cap "a_63_n100#" "a_n33_n100#" 216.82
+cap "a_n129_n100#" "a_n33_n100#" 216.82
+cap "a_n417_n100#" "a_n513_n100#" 216.599
+cap "a_447_n100#" "a_639_n100#" 78.1987
+cap "a_351_n100#" "a_255_n100#" 216.587
+cap "a_63_n100#" "a_255_n100#" 78.1987
+cap "a_n129_n100#" "a_255_n100#" 34.4127
+cap "a_n705_n100#" "a_n797_n74#" 216.481
+cap "a_543_n100#" "a_n735_n176#" 46.3846
+cap "a_447_n100#" "a_543_n100#" 216.587
+cap "a_n225_n100#" "a_n321_n100#" 216.623
+cap "a_n609_n100#" "a_n417_n100#" 108.629
+cap "a_543_n100#" "a_159_n100#" 46.5284
+cap "a_n609_n100#" "a_n735_n176#" 46.3846
+cap "a_351_n100#" "a_735_n100#" 46.6114
+cap "a_n225_n100#" "a_n513_n100#" 47.8111
+cap "a_n705_n100#" "a_n417_n100#" 47.8092
+cap "a_n417_n100#" "a_n33_n100#" 46.9852
+cap "a_351_n100#" "a_63_n100#" 47.809
+cap "a_n735_n176#" "a_n33_n100#" 46.3846
+cap "a_n321_n100#" "a_n513_n100#" 78.1987
+cap "a_n225_n100#" "a_n609_n100#" 46.3995
+cap "a_n129_n100#" "a_63_n100#" 78.1987
+device msubckt sky130_fd_pr__nfet_01v8 705 -100 706 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_639_n100#" 200 0 "a_735_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 609 -100 610 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_543_n100#" 200 0 "a_639_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 513 -100 514 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_447_n100#" 200 0 "a_543_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 417 -100 418 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_351_n100#" 200 0 "a_447_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 321 -100 322 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_255_n100#" 200 0 "a_351_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 225 -100 226 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_159_n100#" 200 0 "a_255_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 129 -100 130 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_63_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 33 -100 34 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -63 -100 -62 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -159 -100 -158 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_n225_n100#" 200 0 "a_n129_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -255 -100 -254 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_n321_n100#" 200 0 "a_n225_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -351 -100 -350 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_n417_n100#" 200 0 "a_n321_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -447 -100 -446 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_n513_n100#" 200 0 "a_n417_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -543 -100 -542 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_n609_n100#" 200 0 "a_n513_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -639 -100 -638 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_n705_n100#" 200 0 "a_n609_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -735 -100 -734 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_n797_n74#" 200 0 "a_n705_n100#" 200 0
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.mag
new file mode 100755
index 0000000..a79051d
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.mag
@@ -0,0 +1,283 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646295505
+<< nmos >>
+rect -735 -100 -705 100
+rect -639 -100 -609 100
+rect -543 -100 -513 100
+rect -447 -100 -417 100
+rect -351 -100 -321 100
+rect -255 -100 -225 100
+rect -159 -100 -129 100
+rect -63 -100 -33 100
+rect 33 -100 63 100
+rect 129 -100 159 100
+rect 225 -100 255 100
+rect 321 -100 351 100
+rect 417 -100 447 100
+rect 513 -100 543 100
+rect 609 -100 639 100
+rect 705 -100 735 100
+<< ndiff >>
+rect -793 74 -735 100
+rect -797 62 -735 74
+rect -797 -62 -785 62
+rect -751 -62 -735 62
+rect -797 -74 -735 -62
+rect -793 -100 -735 -74
+rect -705 62 -639 100
+rect -705 -62 -689 62
+rect -655 -62 -639 62
+rect -705 -100 -639 -62
+rect -609 62 -543 100
+rect -609 -62 -593 62
+rect -559 -62 -543 62
+rect -609 -100 -543 -62
+rect -513 62 -447 100
+rect -513 -62 -497 62
+rect -463 -62 -447 62
+rect -513 -100 -447 -62
+rect -417 62 -351 100
+rect -417 -62 -401 62
+rect -367 -62 -351 62
+rect -417 -100 -351 -62
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+rect 639 62 705 100
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+rect 735 74 793 100
+rect 735 62 797 74
+rect 735 -62 751 62
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+rect 735 -74 797 -62
+rect 735 -100 793 -74
+<< ndiffc >>
+rect -785 -62 -751 62
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+rect -305 -62 -271 62
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+rect 271 -62 305 62
+rect 367 -62 401 62
+rect 463 -62 497 62
+rect 559 -62 593 62
+rect 655 -62 689 62
+rect 751 -62 785 62
+<< poly >>
+rect -735 100 -705 126
+rect -639 100 -609 132
+rect -543 100 -513 134
+rect -447 100 -417 134
+rect -351 100 -321 134
+rect -255 100 -225 132
+rect -159 100 -129 132
+rect -63 100 -33 132
+rect 33 100 63 134
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+rect 225 100 255 132
+rect 321 100 351 132
+rect 417 100 447 132
+rect 513 100 543 134
+rect 609 100 639 134
+rect 705 100 735 138
+rect -735 -118 -705 -100
+rect -639 -118 -609 -100
+rect -543 -118 -513 -100
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+rect -351 -118 -321 -100
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+rect 417 -118 447 -100
+rect 513 -118 543 -100
+rect 609 -118 639 -100
+rect 705 -118 735 -100
+rect -735 -176 737 -118
+<< locali >>
+rect -785 62 -751 78
+rect -785 -64 -751 -62
+rect -689 62 -655 78
+rect -791 -210 -749 -64
+rect -689 -78 -655 -62
+rect -593 62 -559 78
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+rect -305 -78 -271 -62
+rect -211 -62 -209 -56
+rect -113 62 -79 78
+rect -175 -62 -169 -56
+rect -211 -202 -169 -62
+rect -17 62 17 78
+rect 79 62 113 78
+rect 175 62 209 78
+rect 271 62 305 78
+rect 367 62 401 78
+rect -113 -78 -79 -62
+rect -21 -208 21 -62
+rect 79 -78 113 -62
+rect 171 -208 213 -62
+rect 271 -78 305 -62
+rect 365 -62 367 -58
+rect 463 62 497 78
+rect 401 -62 407 -58
+rect 365 -204 407 -62
+rect 559 62 593 78
+rect 463 -78 497 -62
+rect 557 -62 559 -58
+rect 655 62 689 78
+rect 593 -62 599 -58
+rect 557 -204 599 -62
+rect 655 -78 689 -62
+rect 751 62 785 78
+rect 751 -64 785 -62
+rect 749 -210 791 -64
+<< viali >>
+rect -785 -62 -751 62
+rect -689 -62 -655 62
+rect -593 -62 -559 62
+rect -497 -62 -463 62
+rect -401 -62 -367 62
+rect -305 -62 -271 62
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+rect -17 -62 17 62
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+rect 271 -62 305 62
+rect 367 -62 401 62
+rect 463 -62 497 62
+rect 559 -62 593 62
+rect 655 -62 689 62
+rect 751 -62 785 62
+<< metal1 >>
+rect -791 62 -745 74
+rect -791 -62 -785 62
+rect -751 -62 -745 62
+rect -791 -74 -745 -62
+rect -695 62 -649 74
+rect -695 -62 -689 62
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+rect -407 62 -361 74
+rect -407 -62 -401 62
+rect -367 -62 -361 62
+rect -407 -74 -361 -62
+rect -311 62 -265 74
+rect -311 -62 -305 62
+rect -271 -62 -265 62
+rect -311 -74 -265 -62
+rect -215 62 -169 74
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+rect -175 -62 -169 62
+rect -215 -74 -169 -62
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+rect 169 62 215 74
+rect 169 -62 175 62
+rect 209 -62 215 62
+rect 169 -74 215 -62
+rect 265 62 311 74
+rect 265 -62 271 62
+rect 305 -62 311 62
+rect 265 -74 311 -62
+rect 361 62 407 74
+rect 361 -62 367 62
+rect 401 -62 407 62
+rect 361 -74 407 -62
+rect 457 62 503 74
+rect 457 -62 463 62
+rect 497 -62 503 62
+rect 457 -74 503 -62
+rect 553 62 599 74
+rect 553 -62 559 62
+rect 593 -62 599 62
+rect 553 -74 599 -62
+rect 649 62 695 74
+rect 649 -62 655 62
+rect 689 -62 695 62
+rect 649 -74 695 -62
+rect 745 62 791 74
+rect 745 -62 751 62
+rect 785 -62 791 62
+rect 745 -74 791 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 16 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_W9PLXN.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_W9PLXN.mag
new file mode 100755
index 0000000..8390e40
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_W9PLXN.mag
@@ -0,0 +1,110 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646259600
+<< error_p >>
+rect -159 222 -129 226
+rect -63 222 -33 226
+rect 33 222 63 226
+rect 129 222 159 226
+rect -217 144 -159 200
+rect -221 -144 -159 144
+rect -217 -200 -159 -144
+rect -129 -200 -63 200
+rect -33 -200 33 200
+rect 63 -200 129 200
+rect 159 144 217 200
+rect 159 -144 221 144
+rect 159 -200 217 -144
+rect -159 -226 -129 -222
+rect -63 -226 -33 -222
+rect 33 -226 63 -222
+rect 129 -226 159 -222
+<< nmos >>
+rect -159 -200 -129 200
+rect -63 -200 -33 200
+rect 33 -200 63 200
+rect 129 -200 159 200
+<< ndiff >>
+rect -217 144 -159 200
+rect -221 132 -159 144
+rect -221 -132 -209 132
+rect -175 -132 -159 132
+rect -221 -144 -159 -132
+rect -217 -200 -159 -144
+rect -129 132 -63 200
+rect -129 -132 -113 132
+rect -79 -132 -63 132
+rect -129 -200 -63 -132
+rect -33 132 33 200
+rect -33 -132 -17 132
+rect 17 -132 33 132
+rect -33 -200 33 -132
+rect 63 132 129 200
+rect 63 -132 79 132
+rect 113 -132 129 132
+rect 63 -200 129 -132
+rect 159 144 217 200
+rect 159 132 221 144
+rect 159 -132 175 132
+rect 209 -132 221 132
+rect 159 -144 221 -132
+rect 159 -200 217 -144
+<< ndiffc >>
+rect -209 -132 -175 132
+rect -113 -132 -79 132
+rect -17 -132 17 132
+rect 79 -132 113 132
+rect 175 -132 209 132
+<< poly >>
+rect -159 200 -129 222
+rect -63 200 -33 222
+rect 33 200 63 222
+rect 129 200 159 222
+rect -159 -222 -129 -200
+rect -63 -222 -33 -200
+rect 33 -222 63 -200
+rect 129 -222 159 -200
+<< locali >>
+rect -209 132 -175 148
+rect -209 -148 -175 -132
+rect -113 132 -79 148
+rect -113 -148 -79 -132
+rect -17 132 17 148
+rect -17 -148 17 -132
+rect 79 132 113 148
+rect 79 -148 113 -132
+rect 175 132 209 148
+rect 175 -148 209 -132
+<< viali >>
+rect -209 -132 -175 132
+rect -113 -132 -79 132
+rect -17 -132 17 132
+rect 79 -132 113 132
+rect 175 -132 209 132
+<< metal1 >>
+rect -215 132 -169 144
+rect -215 -132 -209 132
+rect -175 -132 -169 132
+rect -215 -144 -169 -132
+rect -119 132 -73 144
+rect -119 -132 -113 132
+rect -79 -132 -73 132
+rect -119 -144 -73 -132
+rect -23 132 23 144
+rect -23 -132 -17 132
+rect 17 -132 23 132
+rect -23 -144 23 -132
+rect 73 132 119 144
+rect 73 -132 79 132
+rect 113 -132 119 132
+rect 73 -144 119 -132
+rect 169 132 215 144
+rect 169 -132 175 132
+rect 209 -132 215 132
+rect 169 -144 215 -132
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 2 l 0.150 m 1 nf 4 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.ext b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
new file mode 100755
index 0000000..bc7e422
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
@@ -0,0 +1,19 @@
+timestamp 1646324451
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n100#" 456 -13.94 63 -100 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 420 -13.94 -33 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n125_n74#" 456 -13.94 -125 -74 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_33_n122#" 392 44.198 33 -122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7320 548 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n63_n122#" 392 44.198 -63 -122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7320 548 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n100#" "a_63_n100#" 216.232
+cap "a_n33_n100#" "a_n125_n74#" 216.232
+cap "a_n125_n74#" "a_63_n100#" 78.1987
+cap "a_33_n122#" "a_n63_n122#" 15.3333
+device msubckt sky130_fd_pr__nfet_01v8 33 -100 34 -99 l=30 w=200 "VSUBS" "a_33_n122#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -63 -100 -62 -99 l=30 w=200 "VSUBS" "a_n63_n122#" 60 0 "a_n125_n74#" 200 0 "a_n33_n100#" 200 0
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.mag
new file mode 100755
index 0000000..9e1b853
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.mag
@@ -0,0 +1,67 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646324451
+<< error_p >>
+rect -63 122 -33 126
+rect 33 122 63 126
+rect -63 -126 -33 -122
+rect 33 -126 63 -122
+<< nmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< ndiff >>
+rect -121 74 -63 100
+rect -125 62 -63 74
+rect -125 -62 -113 62
+rect -79 -62 -63 62
+rect -125 -74 -63 -62
+rect -121 -100 -63 -74
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 74 121 100
+rect 63 62 125 74
+rect 63 -62 79 62
+rect 113 -62 125 62
+rect 63 -74 125 -62
+rect 63 -100 121 -74
+<< ndiffc >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< poly >>
+rect -63 100 -33 122
+rect 33 100 63 122
+rect -63 -122 -33 -100
+rect 33 -122 63 -100
+<< locali >>
+rect -113 62 -79 78
+rect -113 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+<< viali >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< metal1 >>
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.ext b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.ext
new file mode 100755
index 0000000..731757e
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.ext
@@ -0,0 +1,411 @@
+timestamp 1646261959
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_1503_n100#" 712 -171.38 1503 -100 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_1407_n100#" 653 -171.38 1407 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_1311_n100#" 653 -171.38 1311 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_1215_n100#" 653 -171.38 1215 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_1119_n100#" 653 -171.38 1119 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_1023_n100#" 653 -171.38 1023 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_927_n100#" 653 -171.38 927 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_831_n100#" 653 -171.38 831 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_735_n100#" 653 -171.38 735 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_639_n100#" 653 -171.38 639 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_543_n100#" 653 -171.38 543 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
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+cap "a_927_n100#" "a_543_n100#" 34.4127
+cap "a_447_n100#" "w_n1601_n200#" 157.44
+cap "a_255_n100#" "a_n33_n100#" 47.7884
+cap "w_n1601_n200#" "a_735_n100#" 157.44
+cap "a_n1089_n100#" "a_n1281_n100#" 78.1987
+cap "a_513_n126#" "w_n1601_n200#" 47.3
+cap "a_831_n100#" "a_1023_n100#" 78.1987
+cap "a_897_n126#" "a_609_n128#" 4.63566
+cap "a_n63_n126#" "a_33_n128#" 18.1212
+cap "a_1119_n100#" "a_1215_n100#" 216.232
+cap "a_831_n100#" "a_639_n100#" 78.1987
+cap "a_n1119_n128#" "a_n927_n128#" 7.66667
+cap "a_n1185_n100#" "w_n1601_n200#" 157.44
+cap "a_1377_n128#" "a_1281_n126#" 18.1212
+cap "a_129_n126#" "a_513_n126#" 3.63842
+cap "a_1377_n128#" "w_n1601_n200#" 46.2
+cap "w_n1601_n200#" "a_417_n128#" 46.2
+cap "w_n1601_n200#" "a_n1023_n126#" 47.3
+cap "a_n513_n100#" "a_n609_n100#" 216.232
+cap "a_n1185_n100#" "a_n801_n100#" 34.4127
+cap "a_n897_n100#" "w_n1601_n200#" 157.44
+cap "a_n1565_n74#" "a_n1377_n100#" 78.1987
+cap "a_n1311_n128#" "a_n1215_n126#" 18.1212
+cap "a_n993_n100#" "a_n1377_n100#" 34.4127
+cap "a_321_n126#" "w_n1601_n200#" 47.3
+cap "a_129_n126#" "a_417_n128#" 4.63566
+cap "a_351_n100#" "a_543_n100#" 78.1987
+cap "a_n897_n100#" "a_n801_n100#" 216.232
+cap "a_n159_n128#" "a_n63_n126#" 18.1212
+cap "a_n543_n128#" "a_n447_n126#" 18.1212
+cap "a_n609_n100#" "a_n321_n100#" 47.7884
+cap "a_n1185_n100#" "a_n1089_n100#" 216.232
+cap "a_513_n126#" "a_801_n128#" 4.63566
+cap "a_1023_n100#" "a_927_n100#" 216.232
+cap "a_255_n100#" "a_n129_n100#" 34.4127
+cap "a_129_n126#" "a_321_n126#" 7.95062
+cap "a_n447_n126#" "a_n255_n126#" 7.95062
+cap "a_639_n100#" "a_927_n100#" 47.7884
+cap "a_993_n128#" "a_609_n128#" 3.50847
+cap "a_n897_n100#" "a_n1089_n100#" 78.1987
+cap "a_447_n100#" "a_831_n100#" 34.4127
+cap "a_n609_n100#" "a_n225_n100#" 34.4127
+cap "a_417_n128#" "a_801_n128#" 3.50847
+cap "a_831_n100#" "a_735_n100#" 216.232
+cap "a_1281_n126#" "a_1185_n128#" 18.1212
+cap "w_n1601_n200#" "a_33_n128#" 46.2
+cap "a_n735_n128#" "w_n1601_n200#" 46.2
+cap "a_n1119_n128#" "a_n1311_n128#" 7.66667
+cap "a_n1281_n100#" "a_n1377_n100#" 216.232
+cap "w_n1601_n200#" "a_1185_n128#" 46.2
+cap "a_1119_n100#" "a_1023_n100#" 216.232
+cap "a_1377_n128#" "a_1089_n126#" 4.63566
+cap "a_513_n126#" "a_705_n126#" 7.95062
+cap "a_1311_n100#" "a_1407_n100#" 216.232
+cap "a_129_n126#" "a_33_n128#" 18.1212
+cap "a_n1119_n128#" "a_n1215_n126#" 18.1212
+cap "a_159_n100#" "w_n1601_n200#" 157.44
+cap "a_1281_n126#" "a_897_n126#" 3.63842
+cap "w_n1601_n200#" "a_897_n126#" 47.3
+cap "a_705_n126#" "a_417_n128#" 4.63566
+cap "a_n159_n128#" "w_n1601_n200#" 46.2
+cap "a_n543_n128#" "a_n351_n128#" 7.66667
+cap "a_351_n100#" "a_639_n100#" 47.7884
+cap "w_n1601_n200#" "a_n639_n126#" 47.3
+cap "a_n1311_n128#" "a_n1503_n128#" 7.66667
+cap "a_321_n126#" "a_705_n126#" 3.63842
+cap "a_n351_n128#" "a_n255_n126#" 18.1212
+cap "a_1473_n126#" "a_1281_n126#" 7.95062
+cap "a_927_n100#" "a_735_n100#" 78.1987
+cap "a_1473_n126#" "w_n1601_n200#" 47.3
+cap "a_129_n126#" "a_n159_n128#" 4.63566
+cap "a_1023_n100#" "a_1215_n100#" 78.1987
+cap "a_159_n100#" "a_n33_n100#" 78.1987
+cap "a_1185_n128#" "a_801_n128#" 3.50847
+cap "a_n1185_n100#" "a_n1377_n100#" 78.1987
+cap "a_n1503_n128#" "a_n1215_n126#" 4.63566
+cap "a_639_n100#" "a_543_n100#" 216.232
+cap "a_351_n100#" "a_255_n100#" 216.232
+cap "a_63_n100#" "w_n1601_n200#" 157.44
+cap "a_1089_n126#" "a_1185_n128#" 18.1212
+cap "a_225_n128#" "a_513_n126#" 4.63566
+cap "a_n1023_n126#" "a_n927_n128#" 18.1212
+cap "a_1119_n100#" "a_735_n100#" 34.4127
+cap "a_801_n128#" "a_897_n126#" 18.1212
+cap "a_1281_n126#" "a_993_n128#" 4.63566
+cap "w_n1601_n200#" "a_993_n128#" 46.2
+cap "a_n1407_n126#" "a_n1311_n128#" 18.1212
+cap "a_1311_n100#" "w_n1601_n200#" 157.44
+cap "w_n1601_n200#" "a_n831_n126#" 47.3
+cap "a_n513_n100#" "a_n897_n100#" 34.4127
+cap "a_255_n100#" "a_543_n100#" 47.7884
+cap "a_n705_n100#" "w_n1601_n200#" 157.44
+cap "a_225_n128#" "a_417_n128#" 7.66667
+cap "a_63_n100#" "a_n33_n100#" 216.232
+cap "a_1089_n126#" "a_897_n126#" 7.95062
+cap "a_447_n100#" "a_351_n100#" 216.232
+cap "a_n1407_n126#" "a_n1215_n126#" 7.95062
+cap "a_n1119_n128#" "a_n1503_n128#" 3.50847
+cap "a_n705_n100#" "a_n801_n100#" 216.232
+cap "a_n993_n100#" "a_n609_n100#" 34.4127
+cap "a_351_n100#" "a_735_n100#" 34.4127
+cap "a_225_n128#" "a_321_n126#" 18.1212
+cap "a_705_n126#" "a_897_n126#" 7.95062
+cap "a_1473_n126#" "a_1089_n126#" 3.63842
+cap "a_n705_n100#" "a_n417_n100#" 47.7884
+cap "a_447_n100#" "a_543_n100#" 216.232
+cap "a_159_n100#" "a_n129_n100#" 47.7884
+cap "a_n705_n100#" "a_n1089_n100#" 34.4127
+cap "a_n447_n126#" "a_n351_n128#" 18.1212
+cap "a_n735_n128#" "a_n927_n128#" 7.66667
+cap "a_543_n100#" "a_735_n100#" 78.1987
+cap "w_n1601_n200#" "a_609_n128#" 46.2
+cap "a_639_n100#" "a_1023_n100#" 34.4127
+cap "a_993_n128#" "a_801_n128#" 7.66667
+cap "a_n1023_n126#" "a_n1311_n128#" 4.63566
+cap "a_n1473_n100#" "w_n1601_n200#" 157.44
+cap "a_n1407_n126#" "a_n1119_n128#" 4.63566
+cap "a_1089_n126#" "a_993_n128#" 18.1212
+cap "a_225_n128#" "a_33_n128#" 7.66667
+cap "a_n1023_n126#" "a_n1215_n126#" 7.95062
+cap "a_1407_n100#" "w_n1601_n200#" 157.44
+cap "a_n63_n126#" "w_n1601_n200#" 47.3
+cap "a_n735_n128#" "a_n543_n128#" 7.66667
+cap "a_n1565_n74#" "a_n1281_n100#" 47.7884
+cap "a_n927_n128#" "a_n639_n126#" 4.63566
+cap "a_255_n100#" "a_639_n100#" 34.4127
+cap "a_63_n100#" "a_n129_n100#" 78.1987
+cap "a_705_n126#" "a_993_n128#" 4.63566
+cap "a_n993_n100#" "a_n1281_n100#" 47.7884
+cap "a_33_n128#" "a_n255_n126#" 4.63566
+cap "a_129_n126#" "a_n63_n126#" 7.95062
+cap "a_n1473_n100#" "a_n1089_n100#" 34.4127
+cap "a_1311_n100#" "a_1503_n100#" 78.1987
+cap "a_801_n128#" "a_609_n128#" 7.66667
+cap "a_n1407_n126#" "a_n1503_n128#" 18.1212
+cap "a_225_n128#" "a_n159_n128#" 3.50847
+cap "a_447_n100#" "a_639_n100#" 78.1987
+cap "a_n159_n128#" "a_n543_n128#" 3.50847
+cap "a_159_n100#" "a_n225_n100#" 34.4127
+cap "a_n543_n128#" "a_n639_n126#" 18.1212
+cap "a_n1119_n128#" "a_n1023_n126#" 18.1212
+cap "a_1023_n100#" "a_735_n100#" 47.7884
+cap "a_n159_n128#" "a_n255_n126#" 18.1212
+cap "a_639_n100#" "a_735_n100#" 216.232
+cap "a_n639_n126#" "a_n255_n126#" 3.63842
+cap "a_n831_n126#" "a_n927_n128#" 18.1212
+cap "a_159_n100#" "a_351_n100#" 78.1987
+cap "a_n897_n100#" "a_n609_n100#" 47.7884
+cap "a_705_n126#" "a_609_n128#" 18.1212
+cap "a_1311_n100#" "a_927_n100#" 34.4127
+cap "a_n1185_n100#" "a_n1565_n74#" 34.4127
+cap "a_63_n100#" "a_n321_n100#" 34.4127
+cap "a_n1185_n100#" "a_n993_n100#" 78.1987
+cap "a_447_n100#" "a_255_n100#" 78.1987
+cap "a_n513_n100#" "a_n705_n100#" 78.1987
+cap "a_1281_n126#" "w_n1601_n200#" 47.3
+cap "a_159_n100#" "a_543_n100#" 34.4127
+cap "a_n993_n100#" "a_n897_n100#" 216.232
+cap "a_63_n100#" "a_n225_n100#" 47.7884
+cap "a_n801_n100#" "w_n1601_n200#" 157.44
+device msubckt sky130_fd_pr__pfet_01v8 1473 -100 1474 -99 l=30 w=200 "w_n1601_n200#" "a_1473_n126#" 60 0 "a_1407_n100#" 200 0 "a_1503_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 1377 -100 1378 -99 l=30 w=200 "w_n1601_n200#" "a_1377_n128#" 60 0 "a_1311_n100#" 200 0 "a_1407_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 1281 -100 1282 -99 l=30 w=200 "w_n1601_n200#" "a_1281_n126#" 60 0 "a_1215_n100#" 200 0 "a_1311_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 1185 -100 1186 -99 l=30 w=200 "w_n1601_n200#" "a_1185_n128#" 60 0 "a_1119_n100#" 200 0 "a_1215_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 1089 -100 1090 -99 l=30 w=200 "w_n1601_n200#" "a_1089_n126#" 60 0 "a_1023_n100#" 200 0 "a_1119_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 993 -100 994 -99 l=30 w=200 "w_n1601_n200#" "a_993_n128#" 60 0 "a_927_n100#" 200 0 "a_1023_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 897 -100 898 -99 l=30 w=200 "w_n1601_n200#" "a_897_n126#" 60 0 "a_831_n100#" 200 0 "a_927_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 801 -100 802 -99 l=30 w=200 "w_n1601_n200#" "a_801_n128#" 60 0 "a_735_n100#" 200 0 "a_831_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 705 -100 706 -99 l=30 w=200 "w_n1601_n200#" "a_705_n126#" 60 0 "a_639_n100#" 200 0 "a_735_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 609 -100 610 -99 l=30 w=200 "w_n1601_n200#" "a_609_n128#" 60 0 "a_543_n100#" 200 0 "a_639_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 513 -100 514 -99 l=30 w=200 "w_n1601_n200#" "a_513_n126#" 60 0 "a_447_n100#" 200 0 "a_543_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 417 -100 418 -99 l=30 w=200 "w_n1601_n200#" "a_417_n128#" 60 0 "a_351_n100#" 200 0 "a_447_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 321 -100 322 -99 l=30 w=200 "w_n1601_n200#" "a_321_n126#" 60 0 "a_255_n100#" 200 0 "a_351_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 225 -100 226 -99 l=30 w=200 "w_n1601_n200#" "a_225_n128#" 60 0 "a_159_n100#" 200 0 "a_255_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 129 -100 130 -99 l=30 w=200 "w_n1601_n200#" "a_129_n126#" 60 0 "a_63_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 33 -100 34 -99 l=30 w=200 "w_n1601_n200#" "a_33_n128#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -63 -100 -62 -99 l=30 w=200 "w_n1601_n200#" "a_n63_n126#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -159 -100 -158 -99 l=30 w=200 "w_n1601_n200#" "a_n159_n128#" 60 0 "a_n225_n100#" 200 0 "a_n129_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -255 -100 -254 -99 l=30 w=200 "w_n1601_n200#" "a_n255_n126#" 60 0 "a_n321_n100#" 200 0 "a_n225_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -351 -100 -350 -99 l=30 w=200 "w_n1601_n200#" "a_n351_n128#" 60 0 "a_n417_n100#" 200 0 "a_n321_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -447 -100 -446 -99 l=30 w=200 "w_n1601_n200#" "a_n447_n126#" 60 0 "a_n513_n100#" 200 0 "a_n417_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -543 -100 -542 -99 l=30 w=200 "w_n1601_n200#" "a_n543_n128#" 60 0 "a_n609_n100#" 200 0 "a_n513_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -639 -100 -638 -99 l=30 w=200 "w_n1601_n200#" "a_n639_n126#" 60 0 "a_n705_n100#" 200 0 "a_n609_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -735 -100 -734 -99 l=30 w=200 "w_n1601_n200#" "a_n735_n128#" 60 0 "a_n801_n100#" 200 0 "a_n705_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -831 -100 -830 -99 l=30 w=200 "w_n1601_n200#" "a_n831_n126#" 60 0 "a_n897_n100#" 200 0 "a_n801_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -927 -100 -926 -99 l=30 w=200 "w_n1601_n200#" "a_n927_n128#" 60 0 "a_n993_n100#" 200 0 "a_n897_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -1023 -100 -1022 -99 l=30 w=200 "w_n1601_n200#" "a_n1023_n126#" 60 0 "a_n1089_n100#" 200 0 "a_n993_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -1119 -100 -1118 -99 l=30 w=200 "w_n1601_n200#" "a_n1119_n128#" 60 0 "a_n1185_n100#" 200 0 "a_n1089_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -1215 -100 -1214 -99 l=30 w=200 "w_n1601_n200#" "a_n1215_n126#" 60 0 "a_n1281_n100#" 200 0 "a_n1185_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -1311 -100 -1310 -99 l=30 w=200 "w_n1601_n200#" "a_n1311_n128#" 60 0 "a_n1377_n100#" 200 0 "a_n1281_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -1407 -100 -1406 -99 l=30 w=200 "w_n1601_n200#" "a_n1407_n126#" 60 0 "a_n1473_n100#" 200 0 "a_n1377_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -1503 -100 -1502 -99 l=30 w=200 "w_n1601_n200#" "a_n1503_n128#" 60 0 "a_n1565_n74#" 200 0 "a_n1473_n100#" 200 0
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.mag b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.mag
new file mode 100755
index 0000000..889bd28
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.mag
@@ -0,0 +1,520 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646261959
+<< error_p >>
+rect -1505 162 1601 200
+rect -1601 -162 1601 162
+rect -1601 -200 1505 -162
+<< nwell >>
+rect -1505 162 1601 200
+rect -1601 -162 1601 162
+rect -1601 -200 1505 -162
+<< pmos >>
+rect -1503 -100 -1473 100
+rect -1407 -100 -1377 100
+rect -1311 -100 -1281 100
+rect -1215 -100 -1185 100
+rect -1119 -100 -1089 100
+rect -1023 -100 -993 100
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+rect -831 -100 -801 100
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+rect -639 -100 -609 100
+rect -543 -100 -513 100
+rect -447 -100 -417 100
+rect -351 -100 -321 100
+rect -255 -100 -225 100
+rect -159 -100 -129 100
+rect -63 -100 -33 100
+rect 33 -100 63 100
+rect 129 -100 159 100
+rect 225 -100 255 100
+rect 321 -100 351 100
+rect 417 -100 447 100
+rect 513 -100 543 100
+rect 609 -100 639 100
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+rect 801 -100 831 100
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+rect 1089 -100 1119 100
+rect 1185 -100 1215 100
+rect 1281 -100 1311 100
+rect 1377 -100 1407 100
+rect 1473 -100 1503 100
+<< pdiff >>
+rect -1561 74 -1503 100
+rect -1565 62 -1503 74
+rect -1565 -62 -1553 62
+rect -1519 -62 -1503 62
+rect -1565 -74 -1503 -62
+rect -1561 -100 -1503 -74
+rect -1473 62 -1407 100
+rect -1473 -62 -1457 62
+rect -1423 -62 -1407 62
+rect -1473 -100 -1407 -62
+rect -1377 62 -1311 100
+rect -1377 -62 -1361 62
+rect -1327 -62 -1311 62
+rect -1377 -100 -1311 -62
+rect -1281 62 -1215 100
+rect -1281 -62 -1265 62
+rect -1231 -62 -1215 62
+rect -1281 -100 -1215 -62
+rect -1185 62 -1119 100
+rect -1185 -62 -1169 62
+rect -1135 -62 -1119 62
+rect -1185 -100 -1119 -62
+rect -1089 62 -1023 100
+rect -1089 -62 -1073 62
+rect -1039 -62 -1023 62
+rect -1089 -100 -1023 -62
+rect -993 62 -927 100
+rect -993 -62 -977 62
+rect -943 -62 -927 62
+rect -993 -100 -927 -62
+rect -897 62 -831 100
+rect -897 -62 -881 62
+rect -847 -62 -831 62
+rect -897 -100 -831 -62
+rect -801 62 -735 100
+rect -801 -62 -785 62
+rect -751 -62 -735 62
+rect -801 -100 -735 -62
+rect -705 62 -639 100
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+rect 1503 -62 1519 62
+rect 1553 -62 1565 62
+rect 1503 -74 1565 -62
+rect 1503 -100 1561 -74
+<< pdiffc >>
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+rect -1457 -62 -1423 62
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+rect -1265 -62 -1231 62
+rect -1169 -62 -1135 62
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+rect 1231 -62 1265 62
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+rect 1519 -62 1553 62
+<< poly >>
+rect -1503 100 -1473 126
+rect -1407 100 -1377 130
+rect -1311 100 -1281 126
+rect -1215 100 -1185 130
+rect -1119 100 -1089 126
+rect -1023 100 -993 130
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+rect 1185 100 1215 126
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+rect 1377 100 1407 126
+rect 1473 100 1503 130
+rect -1503 -128 -1473 -100
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+rect -1311 -128 -1281 -100
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+rect -447 -126 -417 -100
+rect -351 -128 -321 -100
+rect -255 -126 -225 -100
+rect -159 -128 -129 -100
+rect -63 -126 -33 -100
+rect 33 -128 63 -100
+rect 129 -126 159 -100
+rect 225 -128 255 -100
+rect 321 -126 351 -100
+rect 417 -128 447 -100
+rect 513 -126 543 -100
+rect 609 -128 639 -100
+rect 705 -126 735 -100
+rect 801 -128 831 -100
+rect 897 -126 927 -100
+rect 993 -128 1023 -100
+rect 1089 -126 1119 -100
+rect 1185 -128 1215 -100
+rect 1281 -126 1311 -100
+rect 1377 -128 1407 -100
+rect 1473 -126 1503 -100
+<< locali >>
+rect -1553 62 -1519 78
+rect -1553 -78 -1519 -62
+rect -1457 62 -1423 78
+rect -1457 -78 -1423 -62
+rect -1361 62 -1327 78
+rect -1361 -78 -1327 -62
+rect -1265 62 -1231 78
+rect -1265 -78 -1231 -62
+rect -1169 62 -1135 78
+rect -1169 -78 -1135 -62
+rect -1073 62 -1039 78
+rect -1073 -78 -1039 -62
+rect -977 62 -943 78
+rect -977 -78 -943 -62
+rect -881 62 -847 78
+rect -881 -78 -847 -62
+rect -785 62 -751 78
+rect -785 -78 -751 -62
+rect -689 62 -655 78
+rect -689 -78 -655 -62
+rect -593 62 -559 78
+rect -593 -78 -559 -62
+rect -497 62 -463 78
+rect -497 -78 -463 -62
+rect -401 62 -367 78
+rect -401 -78 -367 -62
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+rect -305 -78 -271 -62
+rect -209 62 -175 78
+rect -209 -78 -175 -62
+rect -113 62 -79 78
+rect -113 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+rect 175 62 209 78
+rect 175 -78 209 -62
+rect 271 62 305 78
+rect 271 -78 305 -62
+rect 367 62 401 78
+rect 367 -78 401 -62
+rect 463 62 497 78
+rect 463 -78 497 -62
+rect 559 62 593 78
+rect 559 -78 593 -62
+rect 655 62 689 78
+rect 655 -78 689 -62
+rect 751 62 785 78
+rect 751 -78 785 -62
+rect 847 62 881 78
+rect 847 -78 881 -62
+rect 943 62 977 78
+rect 943 -78 977 -62
+rect 1039 62 1073 78
+rect 1039 -78 1073 -62
+rect 1135 62 1169 78
+rect 1135 -78 1169 -62
+rect 1231 62 1265 78
+rect 1231 -78 1265 -62
+rect 1327 62 1361 78
+rect 1327 -78 1361 -62
+rect 1423 62 1457 78
+rect 1423 -78 1457 -62
+rect 1519 62 1553 78
+rect 1519 -78 1553 -62
+<< viali >>
+rect -1553 -62 -1519 62
+rect -1457 -62 -1423 62
+rect -1361 -62 -1327 62
+rect -1265 -62 -1231 62
+rect -1169 -62 -1135 62
+rect -1073 -62 -1039 62
+rect -977 -62 -943 62
+rect -881 -62 -847 62
+rect -785 -62 -751 62
+rect -689 -62 -655 62
+rect -593 -62 -559 62
+rect -497 -62 -463 62
+rect -401 -62 -367 62
+rect -305 -62 -271 62
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
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+rect 367 -62 401 62
+rect 463 -62 497 62
+rect 559 -62 593 62
+rect 655 -62 689 62
+rect 751 -62 785 62
+rect 847 -62 881 62
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+rect 1135 -62 1169 62
+rect 1231 -62 1265 62
+rect 1327 -62 1361 62
+rect 1423 -62 1457 62
+rect 1519 -62 1553 62
+<< metal1 >>
+rect -1559 62 -1513 74
+rect -1559 -62 -1553 62
+rect -1519 -62 -1513 62
+rect -1559 -74 -1513 -62
+rect -1463 62 -1417 74
+rect -1463 -62 -1457 62
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+rect -1327 -62 -1321 62
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+rect -1079 62 -1033 74
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+rect 649 62 695 74
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+rect 841 -74 887 -62
+rect 937 62 983 74
+rect 937 -62 943 62
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+rect 937 -74 983 -62
+rect 1033 62 1079 74
+rect 1033 -62 1039 62
+rect 1073 -62 1079 62
+rect 1033 -74 1079 -62
+rect 1129 62 1175 74
+rect 1129 -62 1135 62
+rect 1169 -62 1175 62
+rect 1129 -74 1175 -62
+rect 1225 62 1271 74
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+rect 1321 -74 1367 -62
+rect 1417 62 1463 74
+rect 1417 -62 1423 62
+rect 1457 -62 1463 62
+rect 1417 -74 1463 -62
+rect 1513 62 1559 74
+rect 1513 -62 1519 62
+rect 1553 -62 1559 62
+rect 1513 -74 1559 -62
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 32 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.ext b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.ext
new file mode 100755
index 0000000..83b67cb
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.ext
@@ -0,0 +1,29 @@
+timestamp 0
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n200#" 1418 -341.94 63 -200 pdif 0 0 0 0 0 0 0 0 0 0 24800 924 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 18400 892 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n200#" 1341 -341.94 -33 -200 pdif 0 0 0 0 0 0 0 0 0 0 26400 932 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 18400 892 0 0 0 0 0 0 0 0 0 0
+node "a_n125_n200#" 1418 -341.94 -125 -200 pdif 0 0 0 0 0 0 0 0 0 0 24800 924 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 18400 892 0 0 0 0 0 0 0 0 0 0
+node "a_n81_n297#" 850 -67.5651 -81 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18066 1178 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_15_231#" 850 -67.5651 15 231 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18066 1178 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "w_n161_n300#" 3562 557.712 -161 -300 nw 0 0 0 0 185904 1844 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n200#" "a_63_n200#" 577.161
+cap "a_15_231#" "a_n81_n297#" 18.1212
+cap "a_n33_n200#" "a_15_231#" 5.92513
+cap "w_n161_n300#" "a_n81_n297#" 187.59
+cap "a_n33_n200#" "w_n161_n300#" 364.332
+cap "a_63_n200#" "a_n125_n200#" 208.503
+cap "a_15_231#" "a_63_n200#" 5.92513
+cap "w_n161_n300#" "a_n125_n200#" 364.332
+cap "w_n161_n300#" "a_63_n200#" 364.332
+cap "a_n33_n200#" "a_n81_n297#" 5.92513
+cap "a_15_231#" "w_n161_n300#" 187.59
+cap "a_n81_n297#" "a_n125_n200#" 5.92513
+cap "a_n33_n200#" "a_n125_n200#" 577.161
+device msubckt sky130_fd_pr__pfet_01v8 33 -200 34 -199 l=30 w=400 "w_n161_n300#" "a_15_231#" 60 0 "a_n33_n200#" 400 0 "a_63_n200#" 400 0
+device msubckt sky130_fd_pr__pfet_01v8 -63 -200 -62 -199 l=30 w=400 "w_n161_n300#" "a_n81_n297#" 60 0 "a_n125_n200#" 400 0 "a_n33_n200#" 400 0
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.mag b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.mag
new file mode 100755
index 0000000..fb63d39
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.mag
@@ -0,0 +1,94 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1644851365
+<< error_p >>
+rect 19 281 77 287
+rect 19 247 31 281
+rect 19 241 77 247
+rect -77 -247 -19 -241
+rect -77 -281 -65 -247
+rect -77 -287 -19 -281
+<< nwell >>
+rect -65 262 161 300
+rect -161 -262 161 262
+rect -161 -300 65 -262
+<< pmos >>
+rect -63 -200 -33 200
+rect 33 -200 63 200
+<< pdiff >>
+rect -125 188 -63 200
+rect -125 -188 -113 188
+rect -79 -188 -63 188
+rect -125 -200 -63 -188
+rect -33 188 33 200
+rect -33 -188 -17 188
+rect 17 -188 33 188
+rect -33 -200 33 -188
+rect 63 188 125 200
+rect 63 -188 79 188
+rect 113 -188 125 188
+rect 63 -200 125 -188
+<< pdiffc >>
+rect -113 -188 -79 188
+rect -17 -188 17 188
+rect 79 -188 113 188
+<< poly >>
+rect 15 281 81 297
+rect 15 247 31 281
+rect 65 247 81 281
+rect 15 231 81 247
+rect -63 200 -33 226
+rect 33 200 63 231
+rect -63 -231 -33 -200
+rect 33 -226 63 -200
+rect -81 -247 -15 -231
+rect -81 -281 -65 -247
+rect -31 -281 -15 -247
+rect -81 -297 -15 -281
+<< polycont >>
+rect 31 247 65 281
+rect -65 -281 -31 -247
+<< locali >>
+rect 15 247 31 281
+rect 65 247 81 281
+rect -113 188 -79 204
+rect -113 -204 -79 -188
+rect -17 188 17 204
+rect -17 -204 17 -188
+rect 79 188 113 204
+rect 79 -204 113 -188
+rect -81 -281 -65 -247
+rect -31 -281 -15 -247
+<< viali >>
+rect 31 247 65 281
+rect -113 -188 -79 188
+rect -17 -188 17 188
+rect 79 -188 113 188
+rect -65 -281 -31 -247
+<< metal1 >>
+rect 19 281 77 287
+rect 19 247 31 281
+rect 65 247 77 281
+rect 19 241 77 247
+rect -119 188 -73 200
+rect -119 -188 -113 188
+rect -79 -188 -73 188
+rect -119 -200 -73 -188
+rect -23 188 23 200
+rect -23 -188 -17 188
+rect 17 -188 23 188
+rect -23 -200 23 -188
+rect 73 188 119 200
+rect 73 -188 79 188
+rect 113 -188 119 188
+rect 73 -200 119 -188
+rect -77 -247 -19 -241
+rect -77 -281 -65 -247
+rect -31 -281 -19 -247
+rect -77 -287 -19 -281
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 2 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_66F9W7.mag b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_66F9W7.mag
new file mode 100755
index 0000000..42981d0
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_66F9W7.mag
@@ -0,0 +1,44 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645005148
+<< nwell >>
+rect -109 -162 109 162
+<< pmos >>
+rect -15 -100 15 100
+<< pdiff >>
+rect -73 62 -15 100
+rect -73 -62 -61 62
+rect -27 -62 -15 62
+rect -73 -100 -15 -62
+rect 15 62 73 100
+rect 15 -62 27 62
+rect 61 -62 73 62
+rect 15 -100 73 -62
+<< pdiffc >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< poly >>
+rect -15 100 15 126
+rect -15 -126 15 -100
+<< viali >>
+rect -61 62 -27 88
+rect -61 -62 -27 62
+rect -61 -88 -27 -62
+rect 27 62 61 88
+rect 27 -62 61 62
+rect 27 -88 61 -62
+<< metal1 >>
+rect -67 88 -21 100
+rect -67 -88 -61 88
+rect -27 -88 -21 88
+rect -67 -100 -21 -88
+rect 21 88 67 100
+rect 21 -88 27 88
+rect 61 -88 67 88
+rect 21 -100 67 -88
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 1 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.ext b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
new file mode 100755
index 0000000..d102d21
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
@@ -0,0 +1,44 @@
+timestamp 1646324451
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "li_225_n726#" 17 38.7278 225 -726 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1976 180 0 0 0 0 0 0 0 0 0 0 0 0
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+cap "a_n33_n100#" "li_229_174#" 2.80189
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+cap "a_159_n100#" "a_n33_n100#" 102.009
+cap "a_n129_n100#" "a_n159_n152#" 106.141
+cap "a_159_n100#" "a_n221_n74#" 45.1613
+cap "a_n221_n74#" "a_n33_n100#" 102.009
+cap "a_159_n100#" "w_n261_n210#" 207.073
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+cap "a_n221_n74#" "w_n261_n210#" 207.073
+cap "a_n159_n152#" "w_n261_n210#" 352
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+device msubckt sky130_fd_pr__pfet_01v8 33 -100 34 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n33_n100#" 200 0 "a_n129_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -63 -100 -62 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -159 -100 -158 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n221_n74#" 200 0 "a_n129_n100#" 200 0
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.mag b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.mag
new file mode 100755
index 0000000..dced6c3
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.mag
@@ -0,0 +1,114 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646324451
+<< error_p >>
+rect -261 174 -227 224
+rect -209 140 -203 192
+rect 195 140 209 192
+rect 229 174 263 224
+rect -261 -290 -225 -234
+rect -261 -726 -223 -674
+rect 225 -726 263 -674
+<< nwell >>
+rect -261 -210 263 200
+<< pmos >>
+rect -159 -100 -129 100
+rect -63 -100 -33 100
+rect 33 -100 63 100
+rect 129 -100 159 100
+<< pdiff >>
+rect -217 74 -159 100
+rect -221 62 -159 74
+rect -221 -62 -209 62
+rect -175 -62 -159 62
+rect -221 -74 -159 -62
+rect -217 -100 -159 -74
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+rect 159 -62 175 62
+rect 209 -62 221 62
+rect 159 -74 221 -62
+rect 159 -100 217 -74
+<< pdiffc >>
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+<< poly >>
+rect -159 100 -129 138
+rect -63 100 -33 138
+rect 33 100 63 138
+rect 129 100 159 138
+rect -159 -120 -129 -100
+rect -63 -120 -33 -100
+rect 33 -120 63 -100
+rect 129 -120 159 -100
+rect -159 -152 161 -120
+rect 15 -208 45 -152
+<< locali >>
+rect -261 174 -237 224
+rect -209 62 -175 192
+rect -209 -78 -175 -62
+rect -113 62 -79 78
+rect -113 -68 -79 -62
+rect -115 -116 -79 -68
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+rect 229 174 263 224
+rect 175 -78 209 -62
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+rect 61 -220 95 -154
+rect -261 -290 -225 -234
+rect 217 -290 263 -234
+rect -261 -726 -223 -674
+rect 225 -726 263 -674
+<< viali >>
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+<< metal1 >>
+rect -215 62 -169 74
+rect -215 -62 -209 62
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+rect 113 -62 119 62
+rect 73 -74 119 -62
+rect 169 62 215 74
+rect 169 -62 175 62
+rect 209 -62 215 62
+rect 169 -74 215 -62
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 4 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.ext b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.ext
new file mode 100755
index 0000000..5f8954f
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.ext
@@ -0,0 +1,203 @@
+timestamp 1646319668
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
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+cap "a_n639_n126#" "a_n255_n126#" 3.63842
+cap "w_n833_n200#" "a_n735_n128#" 46.2
+cap "a_n447_n126#" "w_n833_n200#" 47.3
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+cap "a_n639_n126#" "a_n735_n128#" 18.1212
+cap "w_n833_n200#" "a_n351_n128#" 46.2
+cap "a_n543_n128#" "a_n447_n126#" 18.1212
+cap "a_n639_n126#" "a_n447_n126#" 7.95062
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+cap "a_639_n100#" "a_447_n100#" 78.1987
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+cap "a_n321_n100#" "a_n609_n100#" 47.7884
+cap "a_n797_n74#" "a_n705_n100#" 216.232
+device msubckt sky130_fd_pr__pfet_01v8 705 -100 706 -99 l=30 w=200 "w_n833_n200#" "a_705_n126#" 60 0 "a_639_n100#" 200 0 "a_735_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 609 -100 610 -99 l=30 w=200 "w_n833_n200#" "a_609_n128#" 60 0 "a_543_n100#" 200 0 "a_639_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 513 -100 514 -99 l=30 w=200 "w_n833_n200#" "a_513_n126#" 60 0 "a_447_n100#" 200 0 "a_543_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 417 -100 418 -99 l=30 w=200 "w_n833_n200#" "a_417_n128#" 60 0 "a_351_n100#" 200 0 "a_447_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 321 -100 322 -99 l=30 w=200 "w_n833_n200#" "a_321_n126#" 60 0 "a_255_n100#" 200 0 "a_351_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 225 -100 226 -99 l=30 w=200 "w_n833_n200#" "a_225_n128#" 60 0 "a_159_n100#" 200 0 "a_255_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 129 -100 130 -99 l=30 w=200 "w_n833_n200#" "a_129_n126#" 60 0 "a_63_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 33 -100 34 -99 l=30 w=200 "w_n833_n200#" "a_33_n128#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -63 -100 -62 -99 l=30 w=200 "w_n833_n200#" "a_n63_n126#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -159 -100 -158 -99 l=30 w=200 "w_n833_n200#" "a_n159_n128#" 60 0 "a_n225_n100#" 200 0 "a_n129_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -255 -100 -254 -99 l=30 w=200 "w_n833_n200#" "a_n255_n126#" 60 0 "a_n321_n100#" 200 0 "a_n225_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -351 -100 -350 -99 l=30 w=200 "w_n833_n200#" "a_n351_n128#" 60 0 "a_n417_n100#" 200 0 "a_n321_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -447 -100 -446 -99 l=30 w=200 "w_n833_n200#" "a_n447_n126#" 60 0 "a_n513_n100#" 200 0 "a_n417_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -543 -100 -542 -99 l=30 w=200 "w_n833_n200#" "a_n543_n128#" 60 0 "a_n609_n100#" 200 0 "a_n513_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -639 -100 -638 -99 l=30 w=200 "w_n833_n200#" "a_n639_n126#" 60 0 "a_n705_n100#" 200 0 "a_n609_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -735 -100 -734 -99 l=30 w=200 "w_n833_n200#" "a_n735_n128#" 60 0 "a_n797_n74#" 200 0 "a_n705_n100#" 200 0
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.mag b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.mag
new file mode 100755
index 0000000..bc38771
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.mag
@@ -0,0 +1,276 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646319668
+<< nwell >>
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+<< pmos >>
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+<< pdiff >>
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+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 16 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RP57DD.mag b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RP57DD.mag
new file mode 100755
index 0000000..2b87be0
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RP57DD.mag
@@ -0,0 +1,257 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646259600
+<< error_p >>
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+<< nwell >>
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+rect 223 -281 257 -247
+<< metal1 >>
+rect -269 281 -211 287
+rect -269 247 -257 281
+rect -223 247 -211 281
+rect -269 241 -211 247
+rect -77 281 -19 287
+rect -77 247 -65 281
+rect -31 247 -19 281
+rect -77 241 -19 247
+rect 115 281 173 287
+rect 115 247 127 281
+rect 161 247 173 281
+rect 115 241 173 247
+rect 307 281 365 287
+rect 307 247 319 281
+rect 353 247 365 281
+rect 307 241 365 247
+rect -407 132 -361 144
+rect -407 -132 -401 132
+rect -367 -132 -361 132
+rect -407 -144 -361 -132
+rect -311 132 -265 144
+rect -311 -132 -305 132
+rect -271 -132 -265 132
+rect -311 -144 -265 -132
+rect -215 132 -169 144
+rect -215 -132 -209 132
+rect -175 -132 -169 132
+rect -215 -144 -169 -132
+rect -119 132 -73 144
+rect -119 -132 -113 132
+rect -79 -132 -73 132
+rect -119 -144 -73 -132
+rect -23 132 23 144
+rect -23 -132 -17 132
+rect 17 -132 23 132
+rect -23 -144 23 -132
+rect 73 132 119 144
+rect 73 -132 79 132
+rect 113 -132 119 132
+rect 73 -144 119 -132
+rect 169 132 215 144
+rect 169 -132 175 132
+rect 209 -132 215 132
+rect 169 -144 215 -132
+rect 265 132 311 144
+rect 265 -132 271 132
+rect 305 -132 311 132
+rect 265 -144 311 -132
+rect 361 132 407 144
+rect 361 -132 367 132
+rect 401 -132 407 132
+rect 361 -144 407 -132
+rect -365 -247 -307 -241
+rect -365 -281 -353 -247
+rect -319 -281 -307 -247
+rect -365 -287 -307 -281
+rect -173 -247 -115 -241
+rect -173 -281 -161 -247
+rect -127 -281 -115 -247
+rect -173 -287 -115 -281
+rect 19 -247 77 -241
+rect 19 -281 31 -247
+rect 65 -281 77 -247
+rect 19 -287 77 -281
+rect 211 -247 269 -241
+rect 211 -281 223 -247
+rect 257 -281 269 -247
+rect 211 -287 269 -281
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 2 l 0.15 m 1 nf 8 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_SBMASV.mag b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_SBMASV.mag
new file mode 100755
index 0000000..b6f661d
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_SBMASV.mag
@@ -0,0 +1,87 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645025748
+<< error_p >>
+rect 19 181 77 187
+rect 19 147 31 181
+rect 19 141 77 147
+<< nwell >>
+rect -317 -202 169 204
+<< pmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< pdiff >>
+rect -139 62 -63 100
+rect -139 -62 -113 62
+rect -79 -62 -63 62
+rect -139 -100 -63 -62
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 74 121 100
+rect 63 62 125 74
+rect 63 -62 79 62
+rect 113 -62 125 62
+rect 63 -74 125 -62
+rect 63 -100 121 -74
+<< pdiffc >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< nsubdiff >>
+rect -267 100 -179 124
+rect -179 -100 -139 100
+rect -267 -124 -179 -100
+<< nsubdiffcont >>
+rect -267 -100 -179 100
+<< poly >>
+rect 15 181 81 197
+rect 15 147 31 181
+rect 65 147 81 181
+rect 15 131 81 147
+rect -63 100 -33 126
+rect 33 100 63 131
+rect -63 -130 -33 -100
+rect 33 -126 63 -100
+<< polycont >>
+rect 31 147 65 181
+<< locali >>
+rect 15 147 31 181
+rect 65 147 81 181
+rect -267 100 -179 116
+rect -113 62 -79 78
+rect -113 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+rect -267 -116 -179 -100
+<< viali >>
+rect 31 147 65 181
+rect -113 -44 -79 44
+rect -17 -44 17 44
+rect 79 -44 113 44
+<< metal1 >>
+rect 19 181 77 187
+rect 19 147 31 181
+rect 65 147 77 181
+rect 19 141 77 147
+rect -119 44 -73 56
+rect -119 -44 -113 44
+rect -79 -44 -73 44
+rect -119 -56 -73 -44
+rect -23 44 23 56
+rect -23 -44 -17 44
+rect 17 -44 23 44
+rect -23 -56 23 -44
+rect 73 44 119 56
+rect 73 -44 79 44
+rect 113 -44 119 44
+rect 73 -56 119 -44
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 50 viadrn 50 viagate 50 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_U9MAPM.mag b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_U9MAPM.mag
new file mode 100755
index 0000000..6d34b43
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_U9MAPM.mag
@@ -0,0 +1,8 @@
+magic
+tech sky130A
+timestamp 1645025748
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 20 viadrn 20 viagate 20 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_YHFVVH.mag b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_YHFVVH.mag
new file mode 100755
index 0000000..aaf2415
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_YHFVVH.mag
@@ -0,0 +1,337 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646261223
+<< error_p >>
+rect -737 162 833 200
+rect -833 -162 833 162
+rect -833 -200 737 -162
+rect -637 -412 -625 -384
+rect -637 -414 -607 -412
+<< nwell >>
+rect -737 162 833 200
+rect -833 -162 833 162
+rect -833 -200 737 -162
+<< pmos >>
+rect -735 -100 -705 100
+rect -639 -100 -609 100
+rect -543 -100 -513 100
+rect -447 -100 -417 100
+rect -351 -100 -321 100
+rect -255 -100 -225 100
+rect -159 -100 -129 100
+rect -63 -100 -33 100
+rect 33 -100 63 100
+rect 129 -100 159 100
+rect 225 -100 255 100
+rect 321 -100 351 100
+rect 417 -100 447 100
+rect 513 -100 543 100
+rect 609 -100 639 100
+rect 705 -100 735 100
+<< ndiff >>
+rect -637 -414 -625 -412
+<< pdiff >>
+rect -793 74 -735 100
+rect -797 62 -735 74
+rect -797 -62 -785 62
+rect -751 -62 -735 62
+rect -797 -74 -735 -62
+rect -793 -100 -735 -74
+rect -705 62 -639 100
+rect -705 -62 -689 62
+rect -655 -62 -639 62
+rect -705 -100 -639 -62
+rect -609 62 -543 100
+rect -609 -62 -593 62
+rect -559 -62 -543 62
+rect -609 -100 -543 -62
+rect -513 62 -447 100
+rect -513 -62 -497 62
+rect -463 -62 -447 62
+rect -513 -100 -447 -62
+rect -417 62 -351 100
+rect -417 -62 -401 62
+rect -367 -62 -351 62
+rect -417 -100 -351 -62
+rect -321 62 -255 100
+rect -321 -62 -305 62
+rect -271 -62 -255 62
+rect -321 -100 -255 -62
+rect -225 62 -159 100
+rect -225 -62 -209 62
+rect -175 -62 -159 62
+rect -225 -100 -159 -62
+rect -129 62 -63 100
+rect -129 -62 -113 62
+rect -79 -62 -63 62
+rect -129 -100 -63 -62
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 62 129 100
+rect 63 -62 79 62
+rect 113 -62 129 62
+rect 63 -100 129 -62
+rect 159 62 225 100
+rect 159 -62 175 62
+rect 209 -62 225 62
+rect 159 -100 225 -62
+rect 255 62 321 100
+rect 255 -62 271 62
+rect 305 -62 321 62
+rect 255 -100 321 -62
+rect 351 62 417 100
+rect 351 -62 367 62
+rect 401 -62 417 62
+rect 351 -100 417 -62
+rect 447 62 513 100
+rect 447 -62 463 62
+rect 497 -62 513 62
+rect 447 -100 513 -62
+rect 543 62 609 100
+rect 543 -62 559 62
+rect 593 -62 609 62
+rect 543 -100 609 -62
+rect 639 62 705 100
+rect 639 -62 655 62
+rect 689 -62 705 62
+rect 639 -100 705 -62
+rect 735 74 793 100
+rect 735 62 797 74
+rect 735 -62 751 62
+rect 785 -62 797 62
+rect 735 -74 797 -62
+rect 735 -100 793 -74
+<< pdiffc >>
+rect -785 -62 -751 62
+rect -689 -62 -655 62
+rect -593 -62 -559 62
+rect -497 -62 -463 62
+rect -401 -62 -367 62
+rect -305 -62 -271 62
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+rect 271 -62 305 62
+rect 367 -62 401 62
+rect 463 -62 497 62
+rect 559 -62 593 62
+rect 655 -62 689 62
+rect 751 -62 785 62
+<< poly >>
+rect -735 100 -705 126
+rect -639 100 -609 130
+rect -543 100 -513 126
+rect -447 100 -417 130
+rect -351 100 -321 126
+rect -255 100 -225 130
+rect -159 100 -129 126
+rect -63 100 -33 130
+rect 33 100 63 126
+rect 129 100 159 130
+rect 225 100 255 126
+rect 321 100 351 130
+rect 417 100 447 126
+rect 513 100 543 130
+rect 609 100 639 126
+rect 705 100 735 130
+rect -735 -116 -705 -100
+rect -639 -116 -609 -100
+rect -543 -116 -513 -100
+rect -447 -116 -417 -100
+rect -351 -116 -321 -100
+rect -255 -116 -225 -100
+rect -159 -116 -129 -100
+rect -63 -116 -33 -100
+rect 33 -116 63 -100
+rect 129 -116 159 -100
+rect 225 -116 255 -100
+rect 321 -116 351 -100
+rect 417 -116 447 -100
+rect 513 -116 543 -100
+rect 609 -116 639 -100
+rect 705 -116 735 -100
+rect -737 -168 735 -116
+rect -603 -216 -543 -168
+rect -667 -236 -543 -216
+rect -667 -282 -651 -236
+rect -601 -282 -543 -236
+rect -667 -300 -543 -282
+rect -603 -366 -543 -300
+<< polycont >>
+rect -651 -282 -601 -236
+<< locali >>
+rect -333 226 893 228
+rect -883 176 893 226
+rect -785 88 -751 176
+rect -593 88 -559 176
+rect -401 88 -367 176
+rect -211 88 -177 176
+rect -17 88 17 176
+rect 175 88 209 176
+rect 367 88 401 176
+rect 559 88 593 176
+rect 751 88 785 176
+rect -691 -88 -689 -78
+rect -211 68 -209 88
+rect 497 -88 499 -84
+rect 689 -88 691 -84
+rect -691 -118 -655 -88
+rect -497 -118 -463 -88
+rect -305 -118 -271 -88
+rect -113 -118 -79 -88
+rect 79 -118 113 -88
+rect 271 -118 305 -88
+rect 463 -118 499 -88
+rect 655 -118 691 -88
+rect -691 -156 691 -118
+rect -667 -232 -583 -216
+rect -925 -236 -583 -232
+rect -925 -282 -651 -236
+rect -601 -282 -583 -236
+rect -925 -288 -583 -282
+rect -667 -300 -583 -288
+rect -63 -232 25 -156
+rect -63 -288 869 -232
+rect -63 -340 25 -288
+rect -637 -374 25 -340
+rect -637 -376 -23 -374
+rect -637 -414 -603 -376
+rect -445 -424 -409 -376
+rect -255 -422 -219 -376
+rect -61 -416 -25 -376
+rect -733 -698 -699 -556
+rect -541 -684 -507 -542
+rect -349 -688 -315 -546
+rect -155 -694 -121 -552
+rect 35 -698 69 -556
+<< viali >>
+rect -785 62 -751 88
+rect -785 -62 -751 62
+rect -785 -88 -751 -62
+rect -689 62 -655 88
+rect -689 -62 -655 62
+rect -689 -88 -655 -62
+rect -593 62 -559 88
+rect -593 -62 -559 62
+rect -593 -88 -559 -62
+rect -497 62 -463 88
+rect -497 -62 -463 62
+rect -497 -88 -463 -62
+rect -401 62 -367 88
+rect -401 -62 -367 62
+rect -401 -88 -367 -62
+rect -305 62 -271 88
+rect -305 -62 -271 62
+rect -305 -88 -271 -62
+rect -209 62 -175 88
+rect -209 -62 -175 62
+rect -209 -88 -175 -62
+rect -113 62 -79 88
+rect -113 -62 -79 62
+rect -113 -88 -79 -62
+rect -17 62 17 88
+rect -17 -62 17 62
+rect -17 -88 17 -62
+rect 79 62 113 88
+rect 79 -62 113 62
+rect 79 -88 113 -62
+rect 175 62 209 88
+rect 175 -62 209 62
+rect 175 -88 209 -62
+rect 271 62 305 88
+rect 271 -62 305 62
+rect 271 -88 305 -62
+rect 367 62 401 88
+rect 367 -62 401 62
+rect 367 -88 401 -62
+rect 463 62 497 88
+rect 463 -62 497 62
+rect 463 -88 497 -62
+rect 559 62 593 88
+rect 559 -62 593 62
+rect 559 -88 593 -62
+rect 655 62 689 88
+rect 655 -62 689 62
+rect 655 -88 689 -62
+rect 751 62 785 88
+rect 751 -62 785 62
+rect 751 -88 785 -62
+<< metal1 >>
+rect -791 88 -745 100
+rect -791 -88 -785 88
+rect -751 -88 -745 88
+rect -791 -100 -745 -88
+rect -695 88 -649 100
+rect -695 -88 -689 88
+rect -655 -88 -649 88
+rect -695 -100 -649 -88
+rect -599 88 -553 100
+rect -599 -88 -593 88
+rect -559 -88 -553 88
+rect -599 -100 -553 -88
+rect -503 88 -457 100
+rect -503 -88 -497 88
+rect -463 -88 -457 88
+rect -503 -100 -457 -88
+rect -407 88 -361 100
+rect -407 -88 -401 88
+rect -367 -88 -361 88
+rect -407 -100 -361 -88
+rect -311 88 -265 100
+rect -311 -88 -305 88
+rect -271 -88 -265 88
+rect -311 -100 -265 -88
+rect -215 88 -169 100
+rect -215 -88 -209 88
+rect -175 -88 -169 88
+rect -215 -100 -169 -88
+rect -119 88 -73 100
+rect -119 -88 -113 88
+rect -79 -88 -73 88
+rect -119 -100 -73 -88
+rect -23 88 23 100
+rect -23 -88 -17 88
+rect 17 -88 23 88
+rect -23 -100 23 -88
+rect 73 88 119 100
+rect 73 -88 79 88
+rect 113 -88 119 88
+rect 73 -100 119 -88
+rect 169 88 215 100
+rect 169 -88 175 88
+rect 209 -88 215 88
+rect 169 -100 215 -88
+rect 265 88 311 100
+rect 265 -88 271 88
+rect 305 -88 311 88
+rect 265 -100 311 -88
+rect 361 88 407 100
+rect 361 -88 367 88
+rect 401 -88 407 88
+rect 361 -100 407 -88
+rect 457 88 503 100
+rect 457 -88 463 88
+rect 497 -88 503 88
+rect 457 -100 503 -88
+rect 553 88 599 100
+rect 553 -88 559 88
+rect 593 -88 599 88
+rect 553 -100 599 -88
+rect 649 88 695 100
+rect 649 -88 655 88
+rect 689 -88 695 88
+rect 649 -100 695 -88
+rect 745 88 791 100
+rect 745 -88 751 88
+rect 785 -88 791 88
+rect 745 -100 791 -88
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 16 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/preamp/.magicrc b/mag/preamp/.magicrc
new file mode 100755
index 0000000..ea1e753
--- /dev/null
+++ b/mag/preamp/.magicrc
@@ -0,0 +1,87 @@
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+# Change this to a fixed number for repeatable behavior with GDS writes
+# e.g., "random seed 12345"
+catch {random seed}
+
+# Turn off the scale option on ext2spice or else it conflicts with the
+# scale in the model files.
+ext2spice scale off
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "/usr/local/share/pdk/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/sky130A.tech
+
+
+# load device generator
+source $PDKPATH/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE mag
+}
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_ml_xx_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_sram_macros
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_sram_macros/${MAGTYPE}
+}
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/mag/preamp/preamp_part1.ext b/mag/preamp/preamp_part1.ext
new file mode 100644
index 0000000..2f1d4ac
--- /dev/null
+++ b/mag/preamp/preamp_part1.ext
@@ -0,0 +1,216 @@
+timestamp 1651643300
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_1 1 0 721 0 1 1160
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_0 1 0 -447 0 1 1160
+use sky130_fd_pr__nfet_01v8_RURP52 sky130_fd_pr__nfet_01v8_RURP52_1 1 0 381 0 1 630
+use sky130_fd_pr__nfet_01v8_RURP52 sky130_fd_pr__nfet_01v8_RURP52_0 1 0 -105 0 1 630
+use sky130_fd_pr__nfet_01v8_G6PLX8 sky130_fd_pr__nfet_01v8_G6PLX8_1 1 0 547 0 1 122
+use sky130_fd_pr__nfet_01v8_G6PLX8 sky130_fd_pr__nfet_01v8_G6PLX8_0 1 0 -275 0 1 122
+use sky130_fd_pr__nfet_01v8_F5U58G#1 sky130_fd_pr__nfet_01v8_F5U58G_1 1 0 897 0 1 120
+use sky130_fd_pr__nfet_01v8_F5U58G#1 sky130_fd_pr__nfet_01v8_F5U58G_0 1 0 -625 0 1 116
+use sky130_fd_pr__nfet_01v8_8FHE5N sky130_fd_pr__nfet_01v8_8FHE5N_0 1 0 143 0 1 126
+node "m1_338_180#" 1 122.121 338 180 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13376 848 0 0 0 0 0 0 0 0 0 0
+node "m1_n128_236#" 2 208.781 -128 236 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19420 1184 0 0 0 0 0 0 0 0 0 0
+node "m1_n692_190#" 0 17.1792 -692 190 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 968 132 0 0 0 0 0 0 0 0 0 0
+node "li_954_42#" 29 100.544 954 42 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10296 444 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_122_87#" 17 45.5327 122 87 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2684 210 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n720_n74#" 442 605.241 -720 -74 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 114132 4180 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_338_192#" 199 258.503 338 192 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18836 1176 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n718_44#" 29 100.544 -718 44 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10296 444 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n484_188#" 201 261.152 -484 188 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19040 1188 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n218_392#" 649 917.393 -218 392 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 72510 3998 20044 880 0 0 0 0 0 0 0 0 0 0
+node "li_n720_1336#" 508 779.211 -720 1336 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95636 4088 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_388_n260#" 122 549.325 388 -260 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82764 1200 0 0 30396 800 30396 800 0 0 0 0 0 0 0 0 0 0
+node "a_80_n258#" 135 463.845 80 -258 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39816 884 0 0 13824 472 13568 468 0 0 0 0 0 0 0 0 0 0
+node "a_n434_n260#" 105 547.609 -434 -260 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 84192 1180 0 0 29988 792 30576 796 0 0 0 0 0 0 0 0 0 0
+node "a_n656_268#" 664 1385.51 -656 268 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32496 1176 0 0 39600 1884 74764 3348 0 0 0 0 0 0 0 0 0 0
+node "a_n72_436#" 48 35.385 -72 436 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 900 120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n168_434#" 48 35.385 -168 434 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 900 120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_414_798#" 121 24.054 414 798 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 360 84 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_318_800#" 121 24.054 318 800 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 360 84 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n170_802#" 386 1281.62 -170 802 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19236 812 0 0 13012 644 117060 5044 0 0 0 0 0 0 0 0 0 0
+node "a_688_1452#" 368 272.18 688 1452 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10800 640 0 0 5168 288 5168 288 0 0 0 0 0 0 0 0 0 0
+node "a_n482_1452#" 400 273.412 -482 1452 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10748 660 0 0 5168 288 5168 288 0 0 0 0 0 0 0 0 0 0
+node "w_n720_994#" 8846 1741.48 -720 994 nw 0 0 0 0 580492 4144 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_n484_188#" "a_n656_268#" 402.207
+cap "li_122_87#" "a_80_n258#" 6.07531
+cap "a_80_n258#" "a_n434_n260#" 69.5567
+cap "li_954_42#" "li_n720_n74#" 38.7455
+cap "li_n218_392#" "li_n720_n74#" 22.6759
+cap "a_n72_436#" "a_n656_268#" 2.28244
+cap "li_n720_1336#" "a_688_1452#" 66.9
+cap "w_n720_994#" "a_688_1452#" 37.4
+cap "a_n170_802#" "w_n720_994#" 70.7256
+cap "m1_338_180#" "a_n656_268#" 43.817
+cap "m1_n128_236#" "a_n170_802#" 10.2
+cap "a_388_n260#" "li_338_192#" 25.8506
+cap "li_n218_392#" "a_n168_434#" 11.55
+cap "a_n482_1452#" "a_n656_268#" 1.81034
+cap "li_n484_188#" "a_n434_n260#" 25.375
+cap "a_n170_802#" "li_338_192#" 72.9079
+cap "li_122_87#" "a_n656_268#" 9.075
+cap "a_n434_n260#" "a_n656_268#" 11.325
+cap "li_n718_44#" "li_n720_n74#" 37.8889
+cap "a_388_n260#" "li_n720_n74#" 350.111
+cap "a_n170_802#" "li_n720_n74#" 7.24543
+cap "a_n170_802#" "li_n218_392#" 44.5573
+cap "m1_n128_236#" "li_n484_188#" 45.889
+cap "a_n170_802#" "a_n168_434#" 2.04142
+cap "w_n720_994#" "a_n656_268#" 58.372
+cap "m1_n128_236#" "a_n656_268#" 314.8
+cap "a_80_n258#" "li_n720_n74#" 186.298
+cap "li_338_192#" "a_n656_268#" 5.21053
+cap "li_n218_392#" "a_80_n258#" 7.72388
+cap "li_n720_1336#" "a_n482_1452#" 65.625
+cap "a_n482_1452#" "w_n720_994#" 42.35
+cap "a_318_800#" "a_n170_802#" 0.638889
+cap "m1_338_180#" "li_338_192#" 41.3766
+cap "li_n718_44#" "m1_n692_190#" 24.64
+cap "a_318_800#" "a_414_798#" 3.48485
+cap "a_n170_802#" "a_388_n260#" 9.58613
+cap "li_n484_188#" "li_n720_n74#" 55.9374
+cap "a_n170_802#" "a_688_1452#" 1.96875
+cap "li_n218_392#" "li_n484_188#" 41.8
+cap "li_n720_n74#" "a_n656_268#" 88.6242
+cap "li_n218_392#" "a_n656_268#" 677.907
+cap "m1_338_180#" "li_n218_392#" 108.194
+cap "a_n168_434#" "a_n656_268#" 1.79888
+cap "a_80_n258#" "a_388_n260#" 73.7878
+cap "a_n72_436#" "a_n168_434#" 9.75758
+cap "li_122_87#" "li_n720_n74#" 37.8201
+cap "li_n720_n74#" "a_n434_n260#" 344.877
+cap "li_n718_44#" "li_n484_188#" 2.90714
+cap "li_n720_1336#" "w_n720_994#" 119.005
+cap "li_n218_392#" "li_122_87#" 36.3936
+cap "li_n718_44#" "a_n656_268#" 1.94118
+cap "a_318_800#" "a_n656_268#" 2.04142
+cap "a_388_n260#" "a_n656_268#" 3.48418
+cap "a_n170_802#" "a_n656_268#" 19.7143
+cap "a_n72_436#" "a_n170_802#" 2.05357
+cap "m1_338_180#" "a_388_n260#" 0.932642
+cap "a_414_798#" "a_n656_268#" 2.05357
+cap "m1_338_180#" "a_n170_802#" 219.311
+cap "m1_n692_190#" "a_n656_268#" 32.7658
+cap "m1_n128_236#" "li_n218_392#" 114.747
+cap "li_n720_n74#" "li_338_192#" 55.7881
+cap "li_954_42#" "li_338_192#" 1.33846
+cap "li_n218_392#" "li_338_192#" 42.9
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n159_n122#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 77.3742
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n150#" 42.7168
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n150#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" 16.3288
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n150#" 83.8503
+cap "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n150#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n125_n150#" 132.636
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n150#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 202.444
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n73_n100#" -3.18889
+cap "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n63_n76#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n125_n150#" 1.01711
+cap "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n63_n76#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n122#" 4.87089
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n122#" 71.0899
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n125_n150#" 199.694
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 2.55556
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 0.964286
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n122#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 11.6631
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n125_n150#" 129.7
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n150#" 372.168
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n150#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n150#" 16.9898
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 22.6607
+cap "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n73_n100#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n150#" 103.84
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n159_n122#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n150#" 118.85
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" -0.775862
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 170.488
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n150#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 128.302
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 245.966
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n125_n150#" 11.2131
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n150#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n125_n150#" 146.944
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" -21.7168
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n150#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n122#" 97.2439
+cap "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n63_n76#" "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n159_n122#" 4.08628
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n159_n122#" 4.25926
+cap "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 46.0275
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" -27.6128
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" -0.84375
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 10.7545
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n150#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n122#" -327.173
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 76.539
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_n63_n172#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n122#" 0.181579
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n150#" 87.6941
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" -13.3296
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n150#" 40.0977
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_63_n150#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 40.4355
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n122#" 13.0498
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n150#" 193.876
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 2.46429
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 47.3142
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 2.88991
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" -27.8754
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 11.449
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" -27.5
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 2.62644
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 6.73469
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" 2.55855
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 2.88991
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" -22
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 4.71429
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" -26.9925
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_159_n100#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n150#" -224.081 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -952 -260 -7202 -554 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n150#" "m1_n128_236#"
+merge "m1_n128_236#" "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n33_n100#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n33_n100#" "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#" "li_n484_188#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_63_n100#" -616.933 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -168244 -328 0 0 0 0 -2816 -456 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_63_n100#" "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n129_n100#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n129_n100#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_33_n172#"
+merge "sky130_fd_pr__nfet_01v8_RURP52_1/a_33_n172#" "a_414_798#"
+merge "a_414_798#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n63_n172#"
+merge "sky130_fd_pr__nfet_01v8_RURP52_1/a_n63_n172#" "a_318_800#"
+merge "a_318_800#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "a_n656_268#"
+merge "sky130_fd_pr__nfet_01v8_8FHE5N_0/VSUBS" "sky130_fd_pr__nfet_01v8_F5U58G_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/VSUBS" "sky130_fd_pr__nfet_01v8_F5U58G_1/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/VSUBS" "sky130_fd_pr__nfet_01v8_G6PLX8_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/VSUBS" "sky130_fd_pr__nfet_01v8_G6PLX8_1/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/VSUBS" "sky130_fd_pr__nfet_01v8_RURP52_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_RURP52_0/VSUBS" "sky130_fd_pr__nfet_01v8_RURP52_1/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_RURP52_1/VSUBS" "sky130_fd_pr__pfet_01v8_RFM3CD_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/VSUBS" "sky130_fd_pr__pfet_01v8_RFM3CD_1/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/VSUBS" "VSUBS"
+merge "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_33_n76#" "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n63_n76#" -43.072 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -480 -152 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n63_n76#" "a_80_n258#"
+merge "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_63_n50#" "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n125_n39#" -67.604 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 716 -340 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n125_n39#" "sky130_fd_pr__nfet_01v8_F5U58G_0/a_15_n100#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/a_15_n100#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "li_n720_n74#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_63_n100#" -138.901 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1644 -352 0 0 0 0 -440 -352 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_63_n100#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n129_n100#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n129_n100#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_33_n172#"
+merge "sky130_fd_pr__nfet_01v8_RURP52_0/a_33_n172#" "a_n72_436#"
+merge "a_n72_436#" "a_n168_434#"
+merge "a_n168_434#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_n63_n172#"
+merge "sky130_fd_pr__nfet_01v8_RURP52_0/a_n63_n172#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "a_n170_802#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n73_n100#" "m1_n692_190#" -99.667 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -5100 -368 0 -88 0 0 0 0 0 0 0 0 0 0
+merge "m1_n692_190#" "li_n718_44#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_159_n100#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n33_n100#" 72.9738 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2748 -248 8040 -202 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n33_n100#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n74#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n74#" "li_338_192#"
+merge "li_338_192#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n150#"
+merge "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n150#" "m1_338_180#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n122#" "a_388_n260#" -70.7932 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1512 -272 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "a_n482_1452#" 8.427 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3180 -100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "a_688_1452#" -0.106 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -40 -80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n33_n50#" "li_122_87#" -556.672 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 790 -2604 -2254 -190 0 0 0 0 0 0 0 0 0 0
+merge "li_122_87#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_63_n150#"
+merge "sky130_fd_pr__nfet_01v8_RURP52_0/a_63_n150#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_n125_n150#"
+merge "sky130_fd_pr__nfet_01v8_RURP52_0/a_n125_n150#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_63_n150#"
+merge "sky130_fd_pr__nfet_01v8_RURP52_1/a_63_n150#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n125_n150#"
+merge "sky130_fd_pr__nfet_01v8_RURP52_1/a_n125_n150#" "li_n218_392#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n159_n122#" "a_n434_n260#" -81.108 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -720 -288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" -423.792 0 0 0 0 -141264 -2168 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "w_n720_994#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" -2.4017 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -136 -252 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" "li_n720_1336#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "li_954_42#" -65.9972 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7648 -320 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/preamp/preamp_part1.mag b/mag/preamp/preamp_part1.mag
new file mode 100755
index 0000000..94be798
--- /dev/null
+++ b/mag/preamp/preamp_part1.mag
@@ -0,0 +1,256 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1651643300
+<< nwell >>
+rect -720 994 1018 1328
+<< poly >>
+rect -482 1512 -414 1528
+rect -482 1470 -466 1512
+rect -430 1470 -414 1512
+rect -482 1452 -414 1470
+rect 688 1512 756 1528
+rect 688 1470 704 1512
+rect 744 1470 756 1512
+rect 688 1452 756 1470
+rect -462 1266 -432 1452
+rect 706 1276 738 1452
+rect -170 888 -42 908
+rect -170 842 -148 888
+rect -72 842 -42 888
+rect -170 802 -42 842
+rect 318 800 348 812
+rect 414 798 444 810
+rect -168 434 -138 464
+rect -72 436 -42 466
+rect 220 384 446 462
+rect -656 326 -594 342
+rect 220 340 298 384
+rect -656 284 -640 326
+rect -606 284 -594 326
+rect -656 268 -594 284
+rect 218 336 300 340
+rect 218 294 236 336
+rect 284 294 300 336
+rect -640 242 -610 268
+rect 218 266 300 294
+rect 864 328 926 344
+rect 864 286 880 328
+rect 914 286 926 328
+rect 864 270 926 286
+rect 882 234 912 270
+rect -434 4 -404 6
+rect -338 4 -308 6
+rect -242 4 -212 6
+rect -146 4 -116 6
+rect -434 -168 -116 4
+rect -434 -234 -406 -168
+rect -144 -234 -116 -168
+rect -434 -260 -116 -234
+rect 80 -170 206 58
+rect 80 -238 104 -170
+rect 180 -238 206 -170
+rect 80 -258 206 -238
+rect 388 -2 418 4
+rect 484 -2 514 4
+rect 580 -2 610 4
+rect 676 -2 706 4
+rect 388 -164 706 -2
+rect 388 -234 414 -164
+rect 680 -234 706 -164
+rect 388 -260 706 -234
+<< polycont >>
+rect -466 1470 -430 1512
+rect 704 1470 744 1512
+rect -148 842 -72 888
+rect -640 284 -606 326
+rect 236 294 284 336
+rect 880 286 914 328
+rect -406 -234 -144 -168
+rect 104 -238 180 -170
+rect 414 -234 680 -164
+<< locali >>
+rect -482 1512 -414 1528
+rect -482 1470 -466 1512
+rect -430 1470 -414 1512
+rect -482 1452 -414 1470
+rect 688 1512 756 1528
+rect 688 1470 704 1512
+rect 744 1470 756 1512
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+rect -720 1336 1020 1386
+rect -508 1208 -474 1336
+rect 748 1210 782 1336
+rect -164 896 -56 904
+rect -164 832 -158 896
+rect -60 832 -56 896
+rect -164 826 -56 832
+rect -218 434 -184 748
+rect -26 434 8 746
+rect 268 434 302 742
+rect 460 434 494 739
+rect -218 392 100 434
+rect 180 392 494 434
+rect -656 326 -594 342
+rect -656 284 -642 326
+rect -606 284 -594 326
+rect -418 312 -412 350
+rect -352 340 298 352
+rect -352 336 300 340
+rect -352 312 236 336
+rect -418 308 236 312
+rect -418 306 -352 308
+rect -656 268 -594 284
+rect 218 294 236 308
+rect 284 294 300 336
+rect -484 238 -66 272
+rect 218 266 300 294
+rect 864 328 926 344
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+rect 914 286 926 328
+rect -718 44 -652 200
+rect -484 188 -450 238
+rect -292 194 -258 238
+rect -100 190 -66 238
+rect 338 238 756 272
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+rect 530 194 564 238
+rect 722 192 756 238
+rect -598 -22 -564 52
+rect 30 48 66 88
+rect 122 87 166 148
+rect 222 48 256 86
+rect 30 -22 256 48
+rect 836 -22 870 54
+rect 954 42 1020 198
+rect -720 -74 1020 -22
+rect -422 -166 -128 -150
+rect -422 -234 -406 -166
+rect -144 -234 -128 -166
+rect -422 -252 -128 -234
+rect 78 -170 206 -152
+rect 78 -238 104 -170
+rect 180 -238 206 -170
+rect 78 -260 206 -238
+rect 398 -164 696 -148
+rect 398 -234 414 -164
+rect 680 -234 696 -164
+rect 398 -250 696 -234
+<< viali >>
+rect -466 1470 -430 1512
+rect 704 1470 744 1512
+rect -158 888 -60 896
+rect -158 842 -148 888
+rect -148 842 -72 888
+rect -72 842 -60 888
+rect -158 832 -60 842
+rect 100 386 180 434
+rect -642 284 -640 326
+rect -640 284 -606 326
+rect -412 312 -352 350
+rect 878 286 880 328
+rect 880 286 914 328
+rect -406 -168 -144 -166
+rect -406 -234 -144 -168
+rect 106 -238 180 -170
+rect 414 -234 680 -164
+<< metal1 >>
+rect -482 1512 -414 1528
+rect -482 1470 -466 1512
+rect -430 1470 -414 1512
+rect -482 1452 -414 1470
+rect 688 1512 756 1528
+rect 688 1470 704 1512
+rect 744 1470 756 1512
+rect 688 1452 756 1470
+rect -428 362 -380 1104
+rect -170 896 -46 910
+rect -170 832 -158 896
+rect -60 886 -46 896
+rect 654 886 702 1132
+rect -60 838 702 886
+rect -60 832 -46 838
+rect -170 818 -46 832
+rect -428 350 -346 362
+rect -656 326 -594 342
+rect -428 326 -412 350
+rect -718 284 -642 326
+rect -606 312 -412 326
+rect -352 330 -346 350
+rect -352 312 -160 330
+rect -606 284 -160 312
+rect -656 268 -594 284
+rect -692 190 -648 212
+rect -390 154 -352 284
+rect -198 150 -160 284
+rect -122 272 -88 668
+rect 88 434 194 450
+rect 88 386 100 434
+rect 180 386 194 434
+rect 88 372 194 386
+rect -128 236 -66 272
+rect -104 138 -66 236
+rect 120 116 166 372
+rect 364 272 398 536
+rect 654 326 702 838
+rect 864 328 926 344
+rect 864 326 878 328
+rect 434 286 878 326
+rect 914 326 926 328
+rect 914 286 1020 326
+rect 434 284 1020 286
+rect 338 238 406 272
+rect 338 180 374 238
+rect 434 188 470 284
+rect 624 192 660 284
+rect 864 270 926 284
+rect -422 -166 -128 -150
+rect -422 -234 -406 -166
+rect -144 -234 -128 -166
+rect -422 -254 -128 -234
+rect 78 -170 206 -152
+rect 78 -238 106 -170
+rect 180 -238 206 -170
+rect 78 -258 206 -238
+rect 398 -164 696 -148
+rect 398 -234 414 -164
+rect 680 -234 696 -164
+rect 398 -250 696 -234
+use sky130_fd_pr__nfet_01v8_8FHE5N sky130_fd_pr__nfet_01v8_8FHE5N_0
+timestamp 1646423143
+transform 1 0 143 0 1 126
+box -125 -76 125 76
+use sky130_fd_pr__nfet_01v8_F5U58G#1 sky130_fd_pr__nfet_01v8_F5U58G_0
+timestamp 1646431323
+transform 1 0 -625 0 1 116
+box -73 -126 73 126
+use sky130_fd_pr__nfet_01v8_F5U58G#1 sky130_fd_pr__nfet_01v8_F5U58G_1
+timestamp 1646431323
+transform 1 0 897 0 1 120
+box -73 -126 73 126
+use sky130_fd_pr__nfet_01v8_G6PLX8 sky130_fd_pr__nfet_01v8_G6PLX8_0
+timestamp 1646422066
+transform 1 0 -275 0 1 122
+box -221 -126 221 150
+use sky130_fd_pr__nfet_01v8_G6PLX8 sky130_fd_pr__nfet_01v8_G6PLX8_1
+timestamp 1646422066
+transform 1 0 547 0 1 122
+box -221 -126 221 150
+use sky130_fd_pr__nfet_01v8_RURP52 sky130_fd_pr__nfet_01v8_RURP52_0
+timestamp 1651643300
+transform 1 0 -105 0 1 630
+box -125 -176 125 176
+use sky130_fd_pr__nfet_01v8_RURP52 sky130_fd_pr__nfet_01v8_RURP52_1
+timestamp 1651643300
+transform 1 0 381 0 1 630
+box -125 -176 125 176
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_0
+timestamp 1646431323
+transform 1 0 -447 0 1 1160
+box -109 -162 109 162
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_1
+timestamp 1646431323
+transform 1 0 721 0 1 1160
+box -109 -162 109 162
+<< end >>
diff --git a/mag/preamp/preamp_part12.ext b/mag/preamp/preamp_part12.ext
new file mode 100644
index 0000000..acaa79c
--- /dev/null
+++ b/mag/preamp/preamp_part12.ext
@@ -0,0 +1,202 @@
+timestamp 1652163895
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_1 1 0 721 0 1 1160
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_0 1 0 -447 0 1 1160
+use sky130_fd_pr__nfet_01v8_RURP52 sky130_fd_pr__nfet_01v8_RURP52_1 1 0 381 0 1 630
+use sky130_fd_pr__nfet_01v8_RURP52 sky130_fd_pr__nfet_01v8_RURP52_0 1 0 -105 0 1 630
+use sky130_fd_pr__nfet_01v8_G6PLX8 sky130_fd_pr__nfet_01v8_G6PLX8_1 1 0 547 0 1 122
+use sky130_fd_pr__nfet_01v8_G6PLX8 sky130_fd_pr__nfet_01v8_G6PLX8_0 1 0 -275 0 1 122
+use sky130_fd_pr__nfet_01v8_F5U58G#1 sky130_fd_pr__nfet_01v8_F5U58G_1 1 0 897 0 1 120
+use sky130_fd_pr__nfet_01v8_F5U58G#1 sky130_fd_pr__nfet_01v8_F5U58G_0 1 0 -625 0 1 116
+use sky130_fd_pr__nfet_01v8_8FHE5N sky130_fd_pr__nfet_01v8_8FHE5N_0 1 0 143 0 1 126
+node "m1_338_n220#" 2 247.366 338 -220 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20652 1276 0 0 0 0 0 0 0 0 0 0
+node "m1_n128_n164#" 3 314.214 -128 -164 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26220 1584 0 0 0 0 0 0 0 0 0 0
+node "m1_n692_n210#" 0 17.1792 -692 -210 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 968 132 0 0 0 0 0 0 0 0 0 0
+node "li_954_n358#" 29 100.544 954 -358 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10296 444 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_122_n313#" 17 45.5327 122 -313 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2684 210 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n720_n474#" 442 605.241 -720 -474 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 114132 4180 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_338_n208#" 199 258.503 338 -208 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18836 1176 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n718_n356#" 29 100.544 -718 -356 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10296 444 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n484_n212#" 201 261.152 -484 -212 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19040 1188 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n218_192#" 466 914.73 -218 192 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 56660 3016 29244 1280 0 0 0 0 0 0 0 0 0 0
+node "li_n720_1336#" 508 807.498 -720 1336 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95636 4088 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_388_n660#" 122 549.325 388 -660 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82764 1200 0 0 30396 800 30396 800 0 0 0 0 0 0 0 0 0 0
+node "a_80_n658#" 135 463.845 80 -658 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39816 884 0 0 13824 472 13568 468 0 0 0 0 0 0 0 0 0 0
+node "a_n434_n660#" 105 547.609 -434 -660 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 84192 1180 0 0 29988 792 30576 796 0 0 0 0 0 0 0 0 0 0
+node "a_414_256#" 181 21.536 414 256 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 240 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_318_256#" 181 21.536 318 256 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 240 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n72_236#" 48 35.385 -72 236 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 900 120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n168_234#" 48 35.385 -168 234 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 900 120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n656_n132#" 422 1613.54 -656 -132 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19508 860 0 0 30248 932 135892 5820 0 0 0 0 0 0 0 0 0 0
+node "a_n168_604#" 382 1353.32 -168 604 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20284 828 0 0 13012 644 136076 5840 0 0 0 0 0 0 0 0 0 0
+node "a_706_862#" 293 124.937 706 862 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7712 504 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n506_870#" 309 119.062 -506 870 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6948 488 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n720_994#" 8846 1741.48 -720 994 nw 0 0 0 0 580492 4144 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_n718_n356#" "li_n720_n474#" 37.8889
+cap "a_318_256#" "a_n72_236#" 0.511111
+cap "a_n168_604#" "a_n656_n132#" 593.064
+cap "a_388_n660#" "li_n720_n474#" 350.111
+cap "a_388_n660#" "a_80_n658#" 73.7878
+cap "li_n218_192#" "a_n168_234#" 11.55
+cap "a_n168_604#" "li_n720_n474#" 7.24543
+cap "a_n168_234#" "a_n72_236#" 9.75758
+cap "a_n656_n132#" "a_318_256#" 2.04142
+cap "li_338_n208#" "li_954_n358#" 1.33846
+cap "a_n168_604#" "m1_n128_n164#" 9.44444
+cap "m1_338_n220#" "li_n218_192#" 153.648
+cap "li_n720_1336#" "w_n720_994#" 119.005
+cap "li_338_n208#" "li_n218_192#" 16.0875
+cap "li_n218_192#" "li_n484_n212#" 15.675
+cap "li_n484_n212#" "a_n434_n660#" 25.375
+cap "a_318_256#" "a_414_256#" 2.78788
+cap "li_122_n313#" "li_n218_192#" 30.2928
+cap "a_388_n660#" "a_n168_604#" 9.58613
+cap "m1_n692_n210#" "a_n656_n132#" 32.7658
+cap "li_954_n358#" "li_n720_n474#" 38.7455
+cap "li_338_n208#" "m1_338_n220#" 41.3766
+cap "a_n656_n132#" "w_n720_994#" 58.372
+cap "li_n218_192#" "a_n656_n132#" 28.9286
+cap "a_n656_n132#" "a_n434_n660#" 11.325
+cap "a_n434_n660#" "li_n720_n474#" 344.877
+cap "li_n218_192#" "a_80_n658#" 7.72388
+cap "a_n434_n660#" "a_80_n658#" 69.5567
+cap "a_n656_n132#" "li_n484_n212#" 75.2844
+cap "li_338_n208#" "li_n720_n474#" 55.7881
+cap "li_n484_n212#" "li_n720_n474#" 55.9374
+cap "li_122_n313#" "li_n720_n474#" 37.8201
+cap "li_122_n313#" "a_80_n658#" 6.07531
+cap "li_n718_n356#" "m1_n692_n210#" 24.64
+cap "a_n168_604#" "a_n168_234#" 2.02941
+cap "li_n218_192#" "m1_n128_n164#" 158.016
+cap "a_n656_n132#" "li_n720_n474#" 7.21111
+cap "a_706_862#" "w_n720_994#" 34.1
+cap "a_n168_604#" "w_n720_994#" 70.7256
+cap "m1_n128_n164#" "li_n484_n212#" 45.889
+cap "a_n506_870#" "w_n720_994#" 33.55
+cap "li_n218_192#" "a_n168_604#" 23.1716
+cap "a_n656_n132#" "a_414_256#" 2.12963
+cap "m1_338_n220#" "a_388_n660#" 0.932642
+cap "li_n720_n474#" "a_80_n658#" 186.298
+cap "li_n718_n356#" "li_n484_n212#" 2.90714
+cap "li_338_n208#" "a_388_n660#" 25.8506
+cap "m1_338_n220#" "a_n168_604#" 256.962
+cap "a_n168_604#" "a_n72_236#" 2.04142
+cap "a_n656_n132#" "m1_n128_n164#" 311.585
+cap "li_338_n208#" "a_n168_604#" 72.9079
+cap "li_n718_n356#" "a_n656_n132#" 1.94118
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n522#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n348#" 97.2439
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_63_n348#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 185.003
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n348#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n500#" 16.3288
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n159_n522#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n348#" 118.85
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n500#" 237.661
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n500#" 170.488
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n522#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 1.79688
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n522#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 71.0899
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n500#" 22.6607
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n348#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 27.8947
+cap "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n348#" "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n73_n500#" 103.84
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n348#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 124.24
+cap "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n348#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_63_n348#" 131.421
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n159_n522#" "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n63_n476#" 4.08628
+cap "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n348#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n500#" 372.168
+cap "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n73_n500#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n500#" -3.18889
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 2.55556
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_63_n348#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n500#" 8.50776
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n159_n522#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 76.9611
+cap "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n348#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n348#" 16.9898
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_63_n348#" "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n63_n476#" 1.01711
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n159_n522#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 1.90608
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_63_n348#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n348#" 145.73
+cap "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n348#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 77.009
+cap "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n73_n500#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 46.0275
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n348#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n500#" 202.444
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_63_n348#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 132.419
+cap "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n348#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 35.3909
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n522#" "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n63_n476#" 4.87089
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n500#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n500#" 10.7545
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n348#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n522#" -201.753
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n522#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 13.0498
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n348#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 39.1402
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n348#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n500#" 193.876
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n500#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 76.539
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n348#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n500#" 87.6941
+cap "sky130_fd_pr__nfet_01v8_RURP52_1/a_63_n348#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 40.4355
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n500#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 47.3142
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n348#" 1.8583
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" -27.8754
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" -21.7168
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" -27.6128
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 6.73469
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_63_n348#" 4.29461
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 12.4133
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n125_n348#" 4.29461
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" -19.8
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_n125_n348#" 4.29461
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n348#" 4.51965
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 7.17857
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" -13.3296
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" -19.8
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" -26.9925
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n526#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_63_n500#" -124.691 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1764 -344 0 0 0 0 17548 -352 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_63_n500#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n129_n500#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n129_n500#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_33_n370#"
+merge "sky130_fd_pr__nfet_01v8_RURP52_0/a_33_n370#" "a_n72_236#"
+merge "a_n72_236#" "a_n168_234#"
+merge "a_n168_234#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_n63_n370#"
+merge "sky130_fd_pr__nfet_01v8_RURP52_0/a_n63_n370#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "a_n168_604#"
+merge "sky130_fd_pr__nfet_01v8_8FHE5N_0/VSUBS" "sky130_fd_pr__nfet_01v8_F5U58G_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/VSUBS" "sky130_fd_pr__nfet_01v8_F5U58G_1/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/VSUBS" "sky130_fd_pr__nfet_01v8_G6PLX8_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/VSUBS" "sky130_fd_pr__nfet_01v8_G6PLX8_1/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/VSUBS" "sky130_fd_pr__nfet_01v8_RURP52_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_RURP52_0/VSUBS" "sky130_fd_pr__nfet_01v8_RURP52_1/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_RURP52_1/VSUBS" "sky130_fd_pr__pfet_01v8_RFM3CD_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/VSUBS" "sky130_fd_pr__pfet_01v8_RFM3CD_1/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/VSUBS" "VSUBS"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n526#" "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_63_n500#" -337.471 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -63156 -352 0 0 0 0 8844 -456 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_63_n500#" "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n129_n500#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n129_n500#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_33_n370#"
+merge "sky130_fd_pr__nfet_01v8_RURP52_1/a_33_n370#" "a_414_256#"
+merge "a_414_256#" "a_318_256#"
+merge "a_318_256#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n63_n370#"
+merge "sky130_fd_pr__nfet_01v8_RURP52_1/a_n63_n370#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "a_n656_n132#"
+merge "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n33_n450#" "li_122_n313#" -350.605 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3818 -1578 -2254 -190 0 0 0 0 0 0 0 0 0 0
+merge "li_122_n313#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_63_n348#"
+merge "sky130_fd_pr__nfet_01v8_RURP52_0/a_63_n348#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_n125_n348#"
+merge "sky130_fd_pr__nfet_01v8_RURP52_0/a_n125_n348#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n125_n348#"
+merge "sky130_fd_pr__nfet_01v8_RURP52_1/a_n125_n348#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_63_n348#"
+merge "sky130_fd_pr__nfet_01v8_RURP52_1/a_63_n348#" "li_n218_192#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n500#" "li_954_n358#" -65.9972 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7648 -320 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_159_n500#" "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n348#" -217.206 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -952 -260 2114 -550 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_RURP52_0/a_n33_n348#" "m1_n128_n164#"
+merge "m1_n128_n164#" "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n33_n500#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n33_n500#" "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n474#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n474#" "li_n484_n212#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_159_n500#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n33_n500#" -62.9898 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2748 -248 -85704 -226 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n33_n500#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n474#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n474#" "li_338_n208#"
+merge "li_338_n208#" "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n348#"
+merge "sky130_fd_pr__nfet_01v8_RURP52_1/a_n33_n348#" "m1_338_n220#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "a_706_862#" -0.1272 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -48 -72 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_63_n450#" "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n125_n439#" -67.604 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 716 -340 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n125_n439#" "sky130_fd_pr__nfet_01v8_F5U58G_0/a_15_n500#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/a_15_n500#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n500#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n500#" "li_n720_n474#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" -86.328 0 0 0 0 -28776 -2168 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "w_n720_994#"
+merge "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_33_n476#" "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n63_n476#" -43.072 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -480 -152 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n63_n476#" "a_80_n658#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n73_n500#" "m1_n692_n210#" -99.667 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -5100 -368 0 -88 0 0 0 0 0 0 0 0 0 0
+merge "m1_n692_n210#" "li_n718_n356#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n522#" "a_388_n660#" -70.7932 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1512 -272 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "a_n506_870#" 22.896 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8640 -72 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n159_n522#" "a_n434_n660#" -81.108 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -720 -288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" -2.3388 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -68 -252 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" "li_n720_1336#"
diff --git a/mag/preamp/preamp_part12.mag b/mag/preamp/preamp_part12.mag
new file mode 100644
index 0000000..c313c25
--- /dev/null
+++ b/mag/preamp/preamp_part12.mag
@@ -0,0 +1,238 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1652163895
+<< nwell >>
+rect -720 994 1018 1328
+<< poly >>
+rect -462 912 -432 1040
+rect -506 870 -432 912
+rect 706 910 738 1040
+rect 706 862 780 910
+rect -168 700 -42 720
+rect -168 654 -148 700
+rect -72 654 -42 700
+rect -168 604 -42 654
+rect 316 688 446 714
+rect 316 650 338 688
+rect 418 650 446 688
+rect 316 614 446 650
+rect 318 602 348 614
+rect 414 588 444 614
+rect -168 234 -138 264
+rect -72 236 -42 266
+rect 318 256 348 264
+rect 414 256 444 264
+rect -656 -74 -594 -58
+rect -656 -116 -640 -74
+rect -606 -116 -594 -74
+rect -656 -132 -594 -116
+rect 864 -72 926 -56
+rect 864 -114 880 -72
+rect 914 -114 926 -72
+rect 864 -130 926 -114
+rect -640 -158 -610 -132
+rect 882 -166 912 -130
+rect -434 -396 -404 -394
+rect -338 -396 -308 -394
+rect -242 -396 -212 -394
+rect -146 -396 -116 -394
+rect -434 -568 -116 -396
+rect -434 -634 -406 -568
+rect -144 -634 -116 -568
+rect -434 -660 -116 -634
+rect 80 -570 206 -342
+rect 80 -638 104 -570
+rect 180 -638 206 -570
+rect 80 -658 206 -638
+rect 388 -402 418 -396
+rect 484 -402 514 -396
+rect 580 -402 610 -396
+rect 676 -402 706 -396
+rect 388 -564 706 -402
+rect 388 -634 414 -564
+rect 680 -634 706 -564
+rect 388 -660 706 -634
+<< polycont >>
+rect -148 654 -72 700
+rect 338 650 418 688
+rect -640 -116 -606 -74
+rect 880 -114 914 -72
+rect -406 -634 -144 -568
+rect 104 -638 180 -570
+rect 414 -634 680 -564
+<< locali >>
+rect -720 1336 1020 1386
+rect -508 1208 -474 1336
+rect 748 1210 782 1336
+rect 314 820 442 832
+rect 314 782 330 820
+rect 426 782 442 820
+rect -164 708 -56 716
+rect -164 644 -158 708
+rect -60 644 -56 708
+rect -164 638 -56 644
+rect 314 714 442 782
+rect 314 688 446 714
+rect 314 650 338 688
+rect 418 650 446 688
+rect 314 636 446 650
+rect 316 634 446 636
+rect -218 234 -184 548
+rect -26 234 8 546
+rect 92 234 182 242
+rect 268 234 302 280
+rect 460 234 494 296
+rect -218 230 494 234
+rect -218 192 104 230
+rect 92 190 104 192
+rect 172 192 494 230
+rect 172 190 182 192
+rect 92 180 182 190
+rect -656 -74 -594 -58
+rect -656 -116 -642 -74
+rect -606 -116 -594 -74
+rect -656 -132 -594 -116
+rect 864 -72 926 -56
+rect 864 -114 878 -72
+rect 914 -114 926 -72
+rect -484 -162 -66 -128
+rect -718 -356 -652 -200
+rect -484 -212 -450 -162
+rect -292 -206 -258 -162
+rect -100 -210 -66 -162
+rect 338 -162 756 -128
+rect 864 -130 926 -114
+rect 338 -208 372 -162
+rect 530 -206 564 -162
+rect 722 -208 756 -162
+rect -598 -422 -564 -348
+rect 30 -352 66 -312
+rect 122 -313 166 -252
+rect 222 -352 256 -314
+rect 30 -422 256 -352
+rect 836 -422 870 -346
+rect 954 -358 1020 -202
+rect -720 -474 1020 -422
+rect -422 -566 -128 -550
+rect -422 -634 -406 -566
+rect -144 -634 -128 -566
+rect -422 -652 -128 -634
+rect 78 -570 206 -552
+rect 78 -638 104 -570
+rect 180 -638 206 -570
+rect 78 -660 206 -638
+rect 398 -564 696 -548
+rect 398 -634 414 -564
+rect 680 -634 696 -564
+rect 398 -650 696 -634
+<< viali >>
+rect 330 782 426 820
+rect -158 700 -60 708
+rect -158 654 -148 700
+rect -148 654 -72 700
+rect -72 654 -60 700
+rect -158 644 -60 654
+rect 104 190 172 230
+rect -642 -116 -640 -74
+rect -640 -116 -606 -74
+rect 878 -114 880 -72
+rect 880 -114 914 -72
+rect -406 -568 -144 -566
+rect -406 -634 -144 -568
+rect 106 -638 180 -570
+rect 414 -634 680 -564
+<< metal1 >>
+rect -428 830 -380 1104
+rect 314 830 442 832
+rect -428 820 442 830
+rect -428 810 330 820
+rect -430 782 330 810
+rect 426 782 442 820
+rect -656 -74 -594 -58
+rect -430 -70 -380 782
+rect 314 770 442 782
+rect -168 708 -46 722
+rect -168 644 -158 708
+rect -60 698 -46 708
+rect 654 698 702 1132
+rect -60 650 702 698
+rect -60 644 -46 650
+rect -168 630 -46 644
+rect -430 -74 -160 -70
+rect -718 -116 -642 -74
+rect -606 -116 -160 -74
+rect -656 -132 -594 -116
+rect -692 -210 -648 -188
+rect -390 -246 -352 -116
+rect -198 -250 -160 -116
+rect -122 -128 -88 468
+rect 88 230 194 250
+rect 88 190 104 230
+rect 172 190 194 230
+rect 88 172 194 190
+rect -128 -164 -66 -128
+rect -104 -262 -66 -164
+rect 120 -284 166 172
+rect 364 -128 398 350
+rect 654 -74 702 650
+rect 864 -72 926 -56
+rect 864 -74 878 -72
+rect 434 -114 878 -74
+rect 914 -74 926 -72
+rect 914 -114 1020 -74
+rect 434 -116 1020 -114
+rect 338 -162 406 -128
+rect 338 -220 374 -162
+rect 434 -212 470 -116
+rect 624 -208 660 -116
+rect 864 -130 926 -116
+rect -422 -566 -128 -550
+rect -422 -634 -406 -566
+rect -144 -634 -128 -566
+rect -422 -654 -128 -634
+rect 78 -570 206 -552
+rect 78 -638 106 -570
+rect 180 -638 206 -570
+rect 78 -658 206 -638
+rect 398 -564 696 -548
+rect 398 -634 414 -564
+rect 680 -634 696 -564
+rect 398 -650 696 -634
+use sky130_fd_pr__nfet_01v8_8FHE5N sky130_fd_pr__nfet_01v8_8FHE5N_0
+timestamp 1651835070
+transform 1 0 143 0 1 126
+box -125 -476 125 -324
+use sky130_fd_pr__nfet_01v8_F5U58G#1 sky130_fd_pr__nfet_01v8_F5U58G_0
+timestamp 1651835070
+transform 1 0 -625 0 1 116
+box -73 -526 73 -274
+use sky130_fd_pr__nfet_01v8_F5U58G#1 sky130_fd_pr__nfet_01v8_F5U58G_1
+timestamp 1651835070
+transform 1 0 897 0 1 120
+box -73 -526 73 -274
+use sky130_fd_pr__nfet_01v8_G6PLX8 sky130_fd_pr__nfet_01v8_G6PLX8_0
+timestamp 1651835070
+transform 1 0 -275 0 1 122
+box -221 -526 221 -250
+use sky130_fd_pr__nfet_01v8_G6PLX8 sky130_fd_pr__nfet_01v8_G6PLX8_1
+timestamp 1651835070
+transform 1 0 547 0 1 122
+box -221 -526 221 -250
+use sky130_fd_pr__nfet_01v8_RURP52 sky130_fd_pr__nfet_01v8_RURP52_0
+timestamp 1651837652
+transform 1 0 -105 0 1 630
+box -125 -374 125 -22
+use sky130_fd_pr__nfet_01v8_RURP52 sky130_fd_pr__nfet_01v8_RURP52_1
+timestamp 1651837652
+transform 1 0 381 0 1 630
+box -125 -374 125 -22
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_0
+timestamp 1646431323
+transform 1 0 -447 0 1 1160
+box -109 -162 109 162
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_1
+timestamp 1646431323
+transform 1 0 721 0 1 1160
+box -109 -162 109 162
+<< end >>
diff --git a/mag/preamp/preamp_part2.ext b/mag/preamp/preamp_part2.ext
new file mode 100644
index 0000000..71f2b25
--- /dev/null
+++ b/mag/preamp/preamp_part2.ext
@@ -0,0 +1,67 @@
+timestamp 1651654292
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__nfet_01v8_XJTKXQ#0#0 sky130_fd_pr__nfet_01v8_XJTKXQ_0 1 0 443 0 1 346
+use sky130_fd_pr__nfet_01v8_XJTKXQ#0#0 sky130_fd_pr__nfet_01v8_XJTKXQ_1 1 0 975 0 1 346
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_0 1 0 407 0 1 864
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD#0_1 1 0 989 0 1 464
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD#0_0 1 0 407 0 1 464
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_1 1 0 989 0 1 864
+node "li_1016_536#" 91 0 1016 536 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8636 576 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_346_530#" 95 0 346 530 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9044 600 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_116_1034#" 327 549.799 116 1034 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 69696 2836 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_810_594#" 554 24.275 810 594 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12100 688 0 0 20316 1184 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_392_716#" 495 -0.4206 392 716 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8196 504 0 0 25164 1440 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_296_302#" 1878 1746.76 296 302 nw 0 0 0 0 582252 3056 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_392_716#" "li_1016_536#" 130.778
+cap "a_810_594#" "a_392_716#" 284.512
+cap "a_392_716#" "li_116_1034#" 54.9607
+cap "a_392_716#" "li_346_530#" 16.5
+cap "a_810_594#" "li_1016_536#" 17.9143
+cap "li_1016_536#" "li_116_1034#" 4.59836
+cap "a_810_594#" "li_116_1034#" 38.9136
+cap "a_810_594#" "li_346_530#" 66
+cap "li_346_530#" "li_116_1034#" 4.71429
+cap "a_392_716#" "w_296_302#" 451.712
+cap "li_1016_536#" "w_296_302#" 126.068
+cap "a_810_594#" "w_296_302#" 446.072
+cap "w_296_302#" "li_116_1034#" 96.0497
+cap "w_296_302#" "li_346_530#" 131.366
+cap "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" -36.1977
+cap "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 7.59729
+cap "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126#" 16.4286
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 33.2161
+cap "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" -2.44444
+cap "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 12.3861
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" -35.4441
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" -38.9757
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#" 5.47619
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_15_n100#" -3.66667
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 7.48137
+cap "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" -33.6783
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_15_n100#" 1.16162
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" -50.0678
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" -4.485 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -300 -80 0 0 -1020 -128 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "a_392_716#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/VSUBS" "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/VSUBS" "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/VSUBS" "sky130_fd_pr__pfet_01v8_RFM3CD_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/VSUBS" "sky130_fd_pr__nfet_01v8_XJTKXQ_1/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_1/VSUBS" "sky130_fd_pr__nfet_01v8_XJTKXQ_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/VSUBS" "VSUBS"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" -4.1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -748 -180 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" "li_346_530#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" -4.1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -476 -164 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "li_116_1034#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/w_n109_n162#" -847.584 0 0 0 0 -282528 -4336 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/w_n109_n162#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "w_296_302#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_15_n100#" -4.1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -340 -156 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_15_n100#" "li_1016_536#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_15_n100#" -2.527 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -180 -72 0 0 -136 -76 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_15_n100#" "a_810_594#"
diff --git a/mag/preamp/preamp_part2.mag b/mag/preamp/preamp_part2.mag
new file mode 100755
index 0000000..1bb26c9
--- /dev/null
+++ b/mag/preamp/preamp_part2.mag
@@ -0,0 +1,63 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1651654292
+<< nwell >>
+rect 296 302 1098 1028
+<< poly >>
+rect 512 750 578 766
+rect 512 748 528 750
+rect 392 716 528 748
+rect 562 716 578 750
+rect 512 700 578 716
+rect 974 670 1004 744
+rect 810 650 1004 670
+rect 810 612 824 650
+rect 860 632 1004 650
+rect 860 612 876 632
+rect 810 594 876 612
+<< polycont >>
+rect 528 716 562 750
+rect 824 612 860 650
+<< locali >>
+rect 116 1034 1282 1088
+rect 434 938 468 1034
+rect 928 932 962 1034
+rect 346 530 380 796
+rect 512 750 578 766
+rect 512 716 528 750
+rect 562 716 962 750
+rect 512 700 578 716
+rect 810 650 876 670
+rect 810 646 824 650
+rect 434 612 824 646
+rect 860 612 876 650
+rect 434 538 468 612
+rect 810 594 876 612
+rect 924 512 962 716
+rect 1016 536 1050 790
+use sky130_fd_pr__nfet_01v8_XJTKXQ#0#0 sky130_fd_pr__nfet_01v8_XJTKXQ_0
+timestamp 0
+transform 1 0 443 0 1 346
+box 0 0 1 1
+use sky130_fd_pr__nfet_01v8_XJTKXQ#0#0 sky130_fd_pr__nfet_01v8_XJTKXQ_1
+timestamp 0
+transform 1 0 975 0 1 346
+box 0 0 1 1
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD#0_0
+timestamp 1646431323
+transform 1 0 407 0 1 464
+box -109 -162 109 162
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD#0_1
+timestamp 1646431323
+transform 1 0 989 0 1 464
+box -109 -162 109 162
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_0
+timestamp 1646431323
+transform 1 0 407 0 1 864
+box -109 -162 109 162
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_1
+timestamp 1646431323
+transform 1 0 989 0 1 864
+box -109 -162 109 162
+<< end >>
diff --git a/mag/preamp/preamp_part22.ext b/mag/preamp/preamp_part22.ext
new file mode 100644
index 0000000..8bbc869
--- /dev/null
+++ b/mag/preamp/preamp_part22.ext
@@ -0,0 +1,86 @@
+timestamp 1652012215
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_1 1 0 989 0 1 864
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_0 1 0 407 0 1 864
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD#0_3 1 0 1207 0 1 464
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD#0_2 1 0 187 0 1 466
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD#0_1 1 0 989 0 1 464
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD#0_0 1 0 407 0 1 464
+use sky130_fd_pr__nfet_01v8_XJTKXQ#0#0 sky130_fd_pr__nfet_01v8_XJTKXQ_1 1 0 975 0 1 346
+use sky130_fd_pr__nfet_01v8_XJTKXQ#0#0 sky130_fd_pr__nfet_01v8_XJTKXQ_0 1 0 443 0 1 346
+node "li_1016_402#" 16 68.4454 1016 402 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20336 576 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1016_536#" 91 0 1016 536 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8636 576 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_214_402#" 100 0 214 402 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30292 1120 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_116_1034#" 327 506.749 116 1034 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 69696 2836 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_810_594#" 604 24.42 810 594 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12000 720 0 0 20316 1184 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_392_716#" 495 -11.9006 392 716 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8196 504 0 0 25164 1440 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_78_306#" 3805 2485.01 78 306 nw 0 0 0 0 828336 3940 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_214_402#" "w_78_306#" 257.62
+cap "li_1016_402#" "w_78_306#" 68.4454
+cap "a_810_594#" "li_116_1034#" 38.9136
+cap "w_78_306#" "li_116_1034#" 139.1
+cap "a_810_594#" "li_1016_536#" 17.9143
+cap "w_78_306#" "li_1016_536#" 126.068
+cap "li_214_402#" "li_116_1034#" 4.71429
+cap "li_1016_402#" "li_1016_536#" 112.2
+cap "li_116_1034#" "li_1016_536#" 4.59836
+cap "a_392_716#" "a_810_594#" 322.495
+cap "a_392_716#" "w_78_306#" 449.403
+cap "a_392_716#" "li_214_402#" 16.5
+cap "li_1016_402#" "a_392_716#" 8.55556
+cap "a_392_716#" "li_116_1034#" 54.9607
+cap "a_392_716#" "li_1016_536#" 130.778
+cap "a_810_594#" "w_78_306#" 454.872
+cap "li_214_402#" "a_810_594#" 66
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" 40.2819
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" -35.4441
+cap "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" 5.56452
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 32.2378
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_15_n100#" 44.5419
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" -50.0678
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" -36.1977
+cap "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_n15_n126#" 6.3617
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 33.2161
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 12.3861
+cap "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" 5.47619
+cap "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n15_n126#" 5.81053
+cap "sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" 43.8647
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" -168.768
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" 1.16162
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 7.48137
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" -105.345
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_15_n100#" 44.4601
+cap "sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" 42.7264
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 7.59729
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" -4.485 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -300 -80 0 0 -1020 -128 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "a_392_716#"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/VSUBS" "sky130_fd_pr__nfet_01v8_XJTKXQ_1/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_1/VSUBS" "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/VSUBS" "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/VSUBS" "sky130_fd_pr__pfet_01v8_RFM3CD#0_2/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_2/VSUBS" "sky130_fd_pr__pfet_01v8_RFM3CD#0_3/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_3/VSUBS" "sky130_fd_pr__pfet_01v8_RFM3CD_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/VSUBS" "sky130_fd_pr__pfet_01v8_RFM3CD_1/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/VSUBS" "VSUBS"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_15_n100#" -13.94 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -9452 -760 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" "li_214_402#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" -4.1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -476 -164 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "li_116_1034#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/w_n109_n162#" -1058.17 0 0 0 0 -352724 -6504 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD#0_2/w_n109_n162#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_2/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD#0_3/w_n109_n162#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_3/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "w_78_306#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" -82.3854 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -8772 -788 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" "li_1016_536#"
+merge "li_1016_536#" "sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_n73_n100#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_n73_n100#" "li_1016_402#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" -2.527 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -180 -72 0 0 -136 -76 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "a_810_594#"
diff --git a/mag/preamp/preamp_part22.mag b/mag/preamp/preamp_part22.mag
new file mode 100644
index 0000000..c59496d
--- /dev/null
+++ b/mag/preamp/preamp_part22.mag
@@ -0,0 +1,77 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1652012215
+<< nwell >>
+rect 78 1028 326 1034
+rect 78 1026 1098 1028
+rect 78 626 1316 1026
+rect 78 306 1098 626
+rect 296 302 1098 306
+<< poly >>
+rect 512 750 578 766
+rect 512 748 528 750
+rect 392 716 528 748
+rect 562 716 578 750
+rect 512 700 578 716
+rect 824 714 1004 744
+rect 824 670 860 714
+rect 810 650 876 670
+rect 810 612 824 650
+rect 860 612 876 650
+rect 810 594 876 612
+<< polycont >>
+rect 528 716 562 750
+rect 824 612 860 650
+<< locali >>
+rect 116 1034 1282 1088
+rect 434 938 468 1034
+rect 928 932 962 1034
+rect 346 530 380 796
+rect 512 750 578 766
+rect 512 716 528 750
+rect 562 716 962 750
+rect 512 700 578 716
+rect 810 650 876 670
+rect 810 646 824 650
+rect 434 612 824 646
+rect 860 612 876 650
+rect 434 538 468 612
+rect 810 594 876 612
+rect 214 402 380 530
+rect 924 512 962 716
+rect 1016 536 1050 790
+rect 1016 402 1180 526
+use sky130_fd_pr__nfet_01v8_XJTKXQ#0#0 sky130_fd_pr__nfet_01v8_XJTKXQ_0
+timestamp 1651654828
+transform 1 0 443 0 1 346
+box 0 0 1 1
+use sky130_fd_pr__nfet_01v8_XJTKXQ#0#0 sky130_fd_pr__nfet_01v8_XJTKXQ_1
+timestamp 1651654828
+transform 1 0 975 0 1 346
+box 0 0 1 1
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD#0_0
+timestamp 1646431323
+transform 1 0 407 0 1 464
+box -109 -162 109 162
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD#0_1
+timestamp 1646431323
+transform 1 0 989 0 1 464
+box -109 -162 109 162
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD#0_2
+timestamp 1646431323
+transform 1 0 187 0 1 466
+box -109 -162 109 162
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD#0_3
+timestamp 1646431323
+transform 1 0 1207 0 1 464
+box -109 -162 109 162
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_0
+timestamp 1646431323
+transform 1 0 407 0 1 864
+box -109 -162 109 162
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_1
+timestamp 1646431323
+transform 1 0 989 0 1 864
+box -109 -162 109 162
+<< end >>
diff --git a/mag/preamp/sky130_fd_pr__nfet_01v8_8FHE5N.ext b/mag/preamp/sky130_fd_pr__nfet_01v8_8FHE5N.ext
new file mode 100644
index 0000000..1a630b7
--- /dev/null
+++ b/mag/preamp/sky130_fd_pr__nfet_01v8_8FHE5N.ext
@@ -0,0 +1,19 @@
+timestamp 1651835070
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n450#" 236 -13.94 63 -450 ndif 0 0 0 0 0 0 0 0 6112 324 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2924 240 3588 248 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n450#" 213 -13.94 -33 -450 ndif 0 0 0 0 0 0 0 0 6600 332 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2924 240 3588 248 0 0 0 0 0 0 0 0 0 0
+node "a_n125_n439#" 236 -13.94 -125 -439 ndif 0 0 0 0 0 0 0 0 6112 324 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2924 240 3588 248 0 0 0 0 0 0 0 0 0 0
+node "a_33_n476#" 244 49.234 33 -476 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4560 364 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n63_n476#" 244 49.234 -63 -476 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4560 364 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n450#" "a_63_n450#" 115.974
+cap "a_n125_n439#" "a_n33_n450#" 115.974
+cap "a_33_n476#" "a_n63_n476#" 18.1212
+cap "a_n125_n439#" "a_63_n450#" 42.0031
+device msubckt sky130_fd_pr__nfet_01v8 33 -450 34 -449 l=30 w=100 "VSUBS" "a_33_n476#" 60 0 "a_n33_n450#" 100 0 "a_63_n450#" 100 0
+device msubckt sky130_fd_pr__nfet_01v8 -63 -450 -62 -449 l=30 w=100 "VSUBS" "a_n63_n476#" 60 0 "a_n125_n439#" 100 0 "a_n33_n450#" 100 0
diff --git a/mag/preamp/sky130_fd_pr__nfet_01v8_8FHE5N.mag b/mag/preamp/sky130_fd_pr__nfet_01v8_8FHE5N.mag
new file mode 100755
index 0000000..d10b9df
--- /dev/null
+++ b/mag/preamp/sky130_fd_pr__nfet_01v8_8FHE5N.mag
@@ -0,0 +1,62 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1651835070
+<< nmos >>
+rect -63 -450 -33 -350
+rect 33 -450 63 -350
+<< ndiff >>
+rect -121 -361 -63 -350
+rect -125 -373 -63 -361
+rect -125 -427 -113 -373
+rect -79 -427 -63 -373
+rect -125 -439 -63 -427
+rect -121 -450 -63 -439
+rect -33 -373 33 -350
+rect -33 -427 -17 -373
+rect 17 -427 33 -373
+rect -33 -450 33 -427
+rect 63 -361 121 -350
+rect 63 -373 125 -361
+rect 63 -427 79 -373
+rect 113 -427 125 -373
+rect 63 -439 125 -427
+rect 63 -450 121 -439
+<< ndiffc >>
+rect -113 -427 -79 -373
+rect -17 -427 17 -373
+rect 79 -427 113 -373
+<< poly >>
+rect -63 -350 -33 -324
+rect 33 -350 63 -324
+rect -63 -476 -33 -450
+rect 33 -476 63 -450
+<< locali >>
+rect -113 -373 -79 -357
+rect -113 -443 -79 -427
+rect -17 -373 17 -357
+rect -17 -443 17 -427
+rect 79 -373 113 -357
+rect 79 -443 113 -427
+<< viali >>
+rect -113 -427 -79 -373
+rect -17 -427 17 -373
+rect 79 -427 113 -373
+<< metal1 >>
+rect -119 -373 -73 -361
+rect -119 -427 -113 -373
+rect -79 -427 -73 -373
+rect -119 -439 -73 -427
+rect -23 -373 23 -361
+rect -23 -427 -17 -373
+rect 17 -427 23 -373
+rect -23 -439 23 -427
+rect 73 -373 119 -361
+rect 73 -427 79 -373
+rect 113 -427 119 -373
+rect 73 -439 119 -427
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 0.5 l 0.150 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git "a/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0430.ext" "b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0430.ext"
new file mode 100644
index 0000000..470e5e2
--- /dev/null
+++ "b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0430.ext"
@@ -0,0 +1,13 @@
+timestamp 1646431323
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n100#" 470 -13.94 15 -100 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n100#" 470 -13.94 -73 -100 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n126#" 405 49.234 -15 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7560 564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n100#" "a_15_n100#" 253.905
+device msubckt sky130_fd_pr__nfet_01v8 -15 -100 -14 -99 l=30 w=200 "VSUBS" "a_n15_n126#" 60 0 "a_n73_n100#" 200 0 "a_15_n100#" 200 0
diff --git "a/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0430.mag" "b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0430.mag"
new file mode 100755
index 0000000..8dc9818
--- /dev/null
+++ "b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0430.mag"
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646431323
+<< nmos >>
+rect -15 -100 15 100
+<< ndiff >>
+rect -73 62 -15 100
+rect -73 -62 -61 62
+rect -27 -62 -15 62
+rect -73 -100 -15 -62
+rect 15 62 73 100
+rect 15 -62 27 62
+rect 61 -62 73 62
+rect 15 -100 73 -62
+<< ndiffc >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< poly >>
+rect -15 100 15 126
+rect -15 -126 15 -100
+<< locali >>
+rect -61 62 -27 78
+rect -61 -78 -27 -62
+rect 27 62 61 78
+rect 27 -78 61 -62
+<< viali >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< metal1 >>
+rect -67 62 -21 74
+rect -67 -62 -61 62
+rect -27 -62 -21 62
+rect -67 -74 -21 -62
+rect 21 62 67 74
+rect 21 -62 27 62
+rect 61 -62 67 62
+rect 21 -74 67 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 1 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git "a/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0431.ext" "b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0431.ext"
new file mode 100644
index 0000000..c88c7a2
--- /dev/null
+++ "b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0431.ext"
@@ -0,0 +1,13 @@
+timestamp 1651835070
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n500#" 470 -13.94 15 -500 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n500#" 470 -13.94 -73 -500 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n526#" 405 49.234 -15 -526 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7560 564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n500#" "a_15_n500#" 253.905
+device msubckt sky130_fd_pr__nfet_01v8 -15 -500 -14 -499 l=30 w=200 "VSUBS" "a_n15_n526#" 60 0 "a_n73_n500#" 200 0 "a_15_n500#" 200 0
diff --git "a/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0431.mag" "b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0431.mag"
new file mode 100755
index 0000000..4e8b516
--- /dev/null
+++ "b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0431.mag"
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1651835070
+<< nmos >>
+rect -15 -500 15 -300
+<< ndiff >>
+rect -73 -338 -15 -300
+rect -73 -462 -61 -338
+rect -27 -462 -15 -338
+rect -73 -500 -15 -462
+rect 15 -338 73 -300
+rect 15 -462 27 -338
+rect 61 -462 73 -338
+rect 15 -500 73 -462
+<< ndiffc >>
+rect -61 -462 -27 -338
+rect 27 -462 61 -338
+<< poly >>
+rect -15 -300 15 -274
+rect -15 -526 15 -500
+<< locali >>
+rect -61 -338 -27 -322
+rect -61 -478 -27 -462
+rect 27 -338 61 -322
+rect 27 -478 61 -462
+<< viali >>
+rect -61 -462 -27 -338
+rect 27 -462 61 -338
+<< metal1 >>
+rect -67 -338 -21 -326
+rect -67 -462 -61 -338
+rect -27 -462 -21 -338
+rect -67 -474 -21 -462
+rect 21 -338 67 -326
+rect 21 -462 27 -338
+rect 61 -462 67 -338
+rect 21 -474 67 -462
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 1 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G.mag b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G.mag
new file mode 100755
index 0000000..8dc9818
--- /dev/null
+++ b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646431323
+<< nmos >>
+rect -15 -100 15 100
+<< ndiff >>
+rect -73 62 -15 100
+rect -73 -62 -61 62
+rect -27 -62 -15 62
+rect -73 -100 -15 -62
+rect 15 62 73 100
+rect 15 -62 27 62
+rect 61 -62 73 62
+rect 15 -100 73 -62
+<< ndiffc >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< poly >>
+rect -15 100 15 126
+rect -15 -126 15 -100
+<< locali >>
+rect -61 62 -27 78
+rect -61 -78 -27 -62
+rect 27 62 61 78
+rect 27 -78 61 -62
+<< viali >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< metal1 >>
+rect -67 62 -21 74
+rect -67 -62 -61 62
+rect -27 -62 -21 62
+rect -67 -74 -21 -62
+rect 21 62 67 74
+rect 21 -62 27 62
+rect 61 -62 67 62
+rect 21 -74 67 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 1 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.ext b/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.ext
new file mode 100644
index 0000000..c8c9b2a
--- /dev/null
+++ b/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.ext
@@ -0,0 +1,28 @@
+timestamp 1651835070
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_159_n500#" 456 -13.94 159 -500 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_63_n500#" 420 -13.94 63 -500 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n500#" 420 -13.94 -33 -500 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n129_n500#" 420 -13.94 -129 -500 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n221_n474#" 456 -13.94 -221 -474 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n159_n522#" 2066 322.437 -159 -522 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38580 2632 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n500#" "a_63_n500#" 216.232
+cap "a_n221_n474#" "a_63_n500#" 47.7884
+cap "a_63_n500#" "a_159_n500#" 216.232
+cap "a_n129_n500#" "a_n33_n500#" 216.232
+cap "a_n221_n474#" "a_n129_n500#" 216.232
+cap "a_n221_n474#" "a_n33_n500#" 78.1987
+cap "a_n129_n500#" "a_159_n500#" 47.7884
+cap "a_n33_n500#" "a_159_n500#" 78.1987
+cap "a_n221_n474#" "a_159_n500#" 34.4127
+cap "a_n129_n500#" "a_63_n500#" 78.1987
+device msubckt sky130_fd_pr__nfet_01v8 129 -500 130 -499 l=30 w=200 "VSUBS" "a_n159_n522#" 60 0 "a_63_n500#" 200 0 "a_159_n500#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 33 -500 34 -499 l=30 w=200 "VSUBS" "a_n159_n522#" 60 0 "a_n33_n500#" 200 0 "a_63_n500#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -63 -500 -62 -499 l=30 w=200 "VSUBS" "a_n159_n522#" 60 0 "a_n129_n500#" 200 0 "a_n33_n500#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -159 -500 -158 -499 l=30 w=200 "VSUBS" "a_n159_n522#" 60 0 "a_n221_n474#" 200 0 "a_n129_n500#" 200 0
diff --git a/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.mag b/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.mag
new file mode 100755
index 0000000..be4de9f
--- /dev/null
+++ b/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.mag
@@ -0,0 +1,98 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1651835070
+<< error_p >>
+rect -159 -526 -129 -522
+rect -63 -526 -33 -522
+rect 33 -526 63 -522
+rect 129 -526 159 -522
+<< nmos >>
+rect -159 -500 -129 -300
+rect -63 -500 -33 -300
+rect 33 -500 63 -300
+rect 129 -500 159 -300
+<< ndiff >>
+rect -217 -326 -159 -300
+rect -221 -338 -159 -326
+rect -221 -462 -209 -338
+rect -175 -462 -159 -338
+rect -221 -474 -159 -462
+rect -217 -500 -159 -474
+rect -129 -338 -63 -300
+rect -129 -462 -113 -338
+rect -79 -462 -63 -338
+rect -129 -500 -63 -462
+rect -33 -338 33 -300
+rect -33 -462 -17 -338
+rect 17 -462 33 -338
+rect -33 -500 33 -462
+rect 63 -338 129 -300
+rect 63 -462 79 -338
+rect 113 -462 129 -338
+rect 63 -500 129 -462
+rect 159 -326 217 -300
+rect 159 -338 221 -326
+rect 159 -462 175 -338
+rect 209 -462 221 -338
+rect 159 -474 221 -462
+rect 159 -500 217 -474
+<< ndiffc >>
+rect -209 -462 -175 -338
+rect -113 -462 -79 -338
+rect -17 -462 17 -338
+rect 79 -462 113 -338
+rect 175 -462 209 -338
+<< poly >>
+rect -159 -280 159 -250
+rect -159 -300 -129 -280
+rect -63 -300 -33 -280
+rect 33 -300 63 -280
+rect 129 -300 159 -280
+rect -159 -522 -129 -500
+rect -63 -522 -33 -500
+rect 33 -522 63 -500
+rect 129 -522 159 -500
+<< locali >>
+rect -209 -338 -175 -322
+rect -209 -478 -175 -462
+rect -113 -338 -79 -322
+rect -113 -478 -79 -462
+rect -17 -338 17 -322
+rect -17 -478 17 -462
+rect 79 -338 113 -322
+rect 79 -478 113 -462
+rect 175 -338 209 -322
+rect 175 -478 209 -462
+<< viali >>
+rect -209 -462 -175 -338
+rect -113 -462 -79 -338
+rect -17 -462 17 -338
+rect 79 -462 113 -338
+rect 175 -462 209 -338
+<< metal1 >>
+rect -215 -338 -169 -326
+rect -215 -462 -209 -338
+rect -175 -462 -169 -338
+rect -215 -474 -169 -462
+rect -119 -338 -73 -326
+rect -119 -462 -113 -338
+rect -79 -462 -73 -338
+rect -119 -474 -73 -462
+rect -23 -338 23 -326
+rect -23 -462 -17 -338
+rect 17 -462 23 -338
+rect -23 -474 23 -462
+rect 73 -338 119 -326
+rect 73 -462 79 -338
+rect 113 -462 119 -338
+rect 73 -474 119 -462
+rect 169 -338 215 -326
+rect 169 -462 175 -338
+rect 209 -462 215 -338
+rect 169 -474 215 -462
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 4 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/preamp/sky130_fd_pr__nfet_01v8_RURP52.ext b/mag/preamp/sky130_fd_pr__nfet_01v8_RURP52.ext
new file mode 100644
index 0000000..216c6fb
--- /dev/null
+++ b/mag/preamp/sky130_fd_pr__nfet_01v8_RURP52.ext
@@ -0,0 +1,19 @@
+timestamp 1651837652
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n348#" 692 3.5316 63 -348 ndif 0 0 0 0 0 0 0 0 18600 724 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10472 684 10028 528 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n348#" 657 3.5316 -33 -348 ndif 0 0 0 0 0 0 0 0 19800 732 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10472 684 10028 528 0 0 0 0 0 0 0 0 0 0
+node "a_n125_n348#" 692 3.5316 -125 -348 ndif 0 0 0 0 0 0 0 0 18600 724 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10472 684 10028 528 0 0 0 0 0 0 0 0 0 0
+node "a_33_n370#" 553 44.198 33 -370 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10320 748 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n63_n370#" 553 44.198 -63 -370 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10320 748 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n348#" "a_63_n348#" 360.135
+cap "a_n125_n348#" "a_n33_n348#" 360.135
+cap "a_33_n370#" "a_n63_n370#" 15.3333
+cap "a_n125_n348#" "a_63_n348#" 131.521
+device msubckt sky130_fd_pr__nfet_01v8 33 -348 34 -347 l=30 w=300 "VSUBS" "a_33_n370#" 60 0 "a_n33_n348#" 300 0 "a_63_n348#" 300 0
+device msubckt sky130_fd_pr__nfet_01v8 -63 -348 -62 -347 l=30 w=300 "VSUBS" "a_n63_n370#" 60 0 "a_n125_n348#" 300 0 "a_n33_n348#" 300 0
diff --git a/mag/preamp/sky130_fd_pr__nfet_01v8_RURP52.mag b/mag/preamp/sky130_fd_pr__nfet_01v8_RURP52.mag
new file mode 100644
index 0000000..06c27a1
--- /dev/null
+++ b/mag/preamp/sky130_fd_pr__nfet_01v8_RURP52.mag
@@ -0,0 +1,63 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1651837652
+<< error_p >>
+rect -63 -26 -33 -22
+rect 33 -26 63 -22
+rect -63 -374 -33 -370
+rect 33 -374 63 -370
+<< nmos >>
+rect -63 -348 -33 -48
+rect 33 -348 63 -48
+<< ndiff >>
+rect -125 -60 -63 -48
+rect -125 -336 -113 -60
+rect -79 -336 -63 -60
+rect -125 -348 -63 -336
+rect -33 -60 33 -48
+rect -33 -336 -17 -60
+rect 17 -336 33 -60
+rect -33 -348 33 -336
+rect 63 -60 125 -48
+rect 63 -336 79 -60
+rect 113 -336 125 -60
+rect 63 -348 125 -336
+<< ndiffc >>
+rect -113 -336 -79 -60
+rect -17 -336 17 -60
+rect 79 -336 113 -60
+<< poly >>
+rect -63 -48 -33 -26
+rect 33 -48 63 -26
+rect -63 -370 -33 -348
+rect 33 -370 63 -348
+<< locali >>
+rect -113 -60 -79 -44
+rect -113 -352 -79 -336
+rect -17 -60 17 -44
+rect -17 -352 17 -336
+rect 79 -60 113 -44
+rect 79 -352 113 -336
+<< viali >>
+rect -113 -295 -79 -101
+rect -17 -295 17 -101
+rect 79 -295 113 -101
+<< metal1 >>
+rect -119 -101 -73 -89
+rect -119 -295 -113 -101
+rect -79 -295 -73 -101
+rect -119 -307 -73 -295
+rect -23 -101 23 -89
+rect -23 -295 -17 -101
+rect 17 -295 23 -101
+rect -23 -307 23 -295
+rect 73 -101 119 -89
+rect 73 -295 79 -101
+rect 113 -295 119 -101
+rect 73 -307 119 -295
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1.5 l 0.150 m 1 nf 2 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git "a/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ\0430\0430.ext" "b/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ\0430\0430.ext"
new file mode 100644
index 0000000..b21a189
--- /dev/null
+++ "b/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ\0430\0430.ext"
@@ -0,0 +1,7 @@
+timestamp 1651654828
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
diff --git "a/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ\0430\0430.mag" "b/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ\0430\0430.mag"
new file mode 100644
index 0000000..7921c68
--- /dev/null
+++ "b/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ\0430\0430.mag"
@@ -0,0 +1,4 @@
+magic
+tech sky130A
+timestamp 1651654828
+<< end >>
diff --git "a/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ\0430.ext" "b/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ\0430.ext"
new file mode 100644
index 0000000..9c0c33c
--- /dev/null
+++ "b/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ\0430.ext"
@@ -0,0 +1,17 @@
+timestamp 1646429429
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n100#" 456 -13.94 63 -100 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 420 -13.94 -33 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n125_n74#" 456 -13.94 -125 -74 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n63_n152#" 1057 214.297 -63 -152 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22716 1476 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n125_n74#" "a_n33_n100#" 216.232
+cap "a_n33_n100#" "a_63_n100#" 216.232
+cap "a_n125_n74#" "a_63_n100#" 78.1987
+device msubckt sky130_fd_pr__nfet_01v8 33 -100 34 -99 l=30 w=200 "VSUBS" "a_n63_n152#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -63 -100 -62 -99 l=30 w=200 "VSUBS" "a_n63_n152#" 60 0 "a_n125_n74#" 200 0 "a_n33_n100#" 200 0
diff --git "a/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ\0430.mag" "b/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ\0430.mag"
new file mode 100755
index 0000000..38cbd5d
--- /dev/null
+++ "b/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ\0430.mag"
@@ -0,0 +1,64 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646429429
+<< nmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< ndiff >>
+rect -121 74 -63 100
+rect -125 62 -63 74
+rect -125 -62 -113 62
+rect -79 -62 -63 62
+rect -125 -74 -63 -62
+rect -121 -100 -63 -74
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 74 121 100
+rect 63 62 125 74
+rect 63 -62 79 62
+rect 113 -62 125 62
+rect 63 -74 125 -62
+rect 63 -100 121 -74
+<< ndiffc >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< poly >>
+rect -63 122 63 154
+rect -63 100 -33 122
+rect 33 100 63 122
+rect -63 -118 -33 -100
+rect 33 -118 63 -100
+rect -63 -152 63 -118
+<< locali >>
+rect -113 62 -79 78
+rect -113 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+<< viali >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< metal1 >>
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ.mag b/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ.mag
new file mode 100755
index 0000000..38cbd5d
--- /dev/null
+++ b/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ.mag
@@ -0,0 +1,64 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646429429
+<< nmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< ndiff >>
+rect -121 74 -63 100
+rect -125 62 -63 74
+rect -125 -62 -113 62
+rect -79 -62 -63 62
+rect -125 -74 -63 -62
+rect -121 -100 -63 -74
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 74 121 100
+rect 63 62 125 74
+rect 63 -62 79 62
+rect 113 -62 125 62
+rect 63 -74 125 -62
+rect 63 -100 121 -74
+<< ndiffc >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< poly >>
+rect -63 122 63 154
+rect -63 100 -33 122
+rect 33 100 63 122
+rect -63 -118 -33 -100
+rect 33 -118 63 -100
+rect -63 -152 63 -118
+<< locali >>
+rect -113 62 -79 78
+rect -113 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+<< viali >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< metal1 >>
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git "a/mag/preamp/sky130_fd_pr__pfet_01v8_RFM3CD\0430.ext" "b/mag/preamp/sky130_fd_pr__pfet_01v8_RFM3CD\0430.ext"
new file mode 100644
index 0000000..ed68149
--- /dev/null
+++ "b/mag/preamp/sky130_fd_pr__pfet_01v8_RFM3CD\0430.ext"
@@ -0,0 +1,17 @@
+timestamp 1646431323
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n100#" 736 -171.38 15 -100 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n100#" 736 -171.38 -73 -100 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n126#" 405 4.134 -15 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7560 564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n162#" 2527 211.896 -109 -162 nw 0 0 0 0 70632 1084 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n100#" "a_15_n100#" 253.905
+cap "w_n109_n162#" "a_15_n100#" 157.44
+cap "a_n15_n126#" "w_n109_n162#" 45.1
+cap "a_n73_n100#" "w_n109_n162#" 157.44
+device msubckt sky130_fd_pr__pfet_01v8 -15 -100 -14 -99 l=30 w=200 "w_n109_n162#" "a_n15_n126#" 60 0 "a_n73_n100#" 200 0 "a_15_n100#" 200 0
diff --git "a/mag/preamp/sky130_fd_pr__pfet_01v8_RFM3CD\0430.mag" "b/mag/preamp/sky130_fd_pr__pfet_01v8_RFM3CD\0430.mag"
new file mode 100755
index 0000000..7091e97
--- /dev/null
+++ "b/mag/preamp/sky130_fd_pr__pfet_01v8_RFM3CD\0430.mag"
@@ -0,0 +1,45 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646431323
+<< nwell >>
+rect -109 -162 109 162
+<< pmos >>
+rect -15 -100 15 100
+<< pdiff >>
+rect -73 62 -15 100
+rect -73 -62 -61 62
+rect -27 -62 -15 62
+rect -73 -100 -15 -62
+rect 15 62 73 100
+rect 15 -62 27 62
+rect 61 -62 73 62
+rect 15 -100 73 -62
+<< pdiffc >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< poly >>
+rect -15 100 15 126
+rect -15 -126 15 -100
+<< locali >>
+rect -61 62 -27 78
+rect -61 -78 -27 -62
+rect 27 62 61 78
+rect 27 -78 61 -62
+<< viali >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< metal1 >>
+rect -67 62 -21 74
+rect -67 -62 -61 62
+rect -27 -62 -21 62
+rect -67 -74 -21 -62
+rect 21 62 67 74
+rect 21 -62 27 62
+rect 61 -62 67 62
+rect 21 -74 67 -62
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 1 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/sky130_fd_pr__diode_pd2nw_05v5_G4XDRY.ext b/mag/sky130_fd_pr__diode_pd2nw_05v5_G4XDRY.ext
new file mode 100644
index 0000000..da16471
--- /dev/null
+++ b/mag/sky130_fd_pr__diode_pd2nw_05v5_G4XDRY.ext
@@ -0,0 +1,15 @@
+timestamp 1647842470
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__diode_pd2nw_05v5 a=area p=pj
+node "li_n340_n340#" 903 2200.15 -340 -340 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 87856 5168 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n100_n100#" 15 -236.16 -100 -100 pdi 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36608 768 37600 776 0 0 0 0 0 0 0 0 0 0
+node "w_n238_n238#" 7187 679.728 -238 -238 nw 0 0 0 0 226576 1904 0 0 50320 2960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50320 2960 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "w_n376_n376#" 0 0 -376 -376 pw 338928 4912 0 0 0 0 0 0 0 0 87856 5168 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_n340_n340#" "a_n100_n100#" 120.477
+cap "w_n238_n238#" "li_n340_n340#" 512.769
+cap "w_n238_n238#" "a_n100_n100#" 670.922
+device pdiode sky130_fd_pr__diode_pd2nw_05v5 -100 -100 -99 -99 a=40000 p=800 "w_n238_n238#" "a_n100_n100#" 352 0 "w_n238_n238#" 200 0
diff --git a/mag/sky130_fd_pr__diode_pd2nw_05v5_G4XDRY.mag b/mag/sky130_fd_pr__diode_pd2nw_05v5_G4XDRY.mag
new file mode 100644
index 0000000..4d67c1b
--- /dev/null
+++ b/mag/sky130_fd_pr__diode_pd2nw_05v5_G4XDRY.mag
@@ -0,0 +1,58 @@
+magic
+tech sky130A
+timestamp 1647842470
+<< nwell >>
+rect -119 -119 119 119
+<< pwell >>
+rect -188 119 188 188
+rect -188 -119 -119 119
+rect 119 -119 188 119
+rect -188 -188 188 -119
+<< psubdiff >>
+rect -170 153 170 170
+rect -170 -153 -153 153
+rect 153 -153 170 153
+rect -170 -170 170 -153
+<< nsubdiff >>
+rect -101 84 101 101
+rect -101 53 -84 84
+rect 84 53 101 84
+rect -101 -84 -84 -53
+rect 84 -84 101 -53
+rect -101 -101 101 -84
+<< nsubdiffcont >>
+rect -101 -53 -84 53
+rect 84 -53 101 53
+<< pdiode >>
+rect -50 44 50 50
+rect -50 -44 -44 44
+rect 44 -44 50 44
+rect -50 -50 50 -44
+<< pdiodec >>
+rect -44 -44 44 44
+<< locali >>
+rect -170 153 170 170
+rect -170 -153 -153 153
+rect -101 84 101 101
+rect -101 53 -84 84
+rect 84 53 101 84
+rect -52 -44 -44 44
+rect 44 -44 52 44
+rect -101 -84 -84 -53
+rect 84 -84 101 -53
+rect -101 -101 101 -84
+rect 153 -153 170 153
+rect -170 -170 170 -153
+<< viali >>
+rect -44 -44 44 44
+<< metal1 >>
+rect -50 44 50 47
+rect -50 -44 -44 44
+rect 44 -44 50 44
+rect -50 -47 50 -44
+<< properties >>
+string FIXED_BBOX -92 -92 92 92
+string gencell sky130_fd_pr__diode_pd2nw_05v5
+string library sky130
+string parameters w 1 l 1 area 1.0 peri 4.0 nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 elc 1 erc 1 etc 0 ebc 0 glc 0 grc 0 gtc 0 gbc 0 doverlap 0 compatible {sky130_fd_pr__diode_pd2nw_05v5 sky130_fd_pr__diode_pd2nw_05v5_lvt sky130_fd_pr__diode_pd2nw_05v5_hvt sky130_fd_pr__diode_pd2nw_11v0} full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+<< end >>
diff --git a/mag/sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y.ext b/mag/sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y.ext
new file mode 100644
index 0000000..d0cdc52
--- /dev/null
+++ b/mag/sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y.ext
@@ -0,0 +1,10 @@
+timestamp 1647842470
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__diode_pw2nd_05v5 a=area p=pj
+node "a_n100_n100#" 15 515.122 -100 -100 ndi 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36608 768 37600 776 0 0 0 0 0 0 0 0 0 0
+substrate "w_n238_n238#" 0 0 -238 -238 pw 226576 1904 0 0 0 0 0 0 0 0 50320 2960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50320 2960 0 0 0 0 0 0 0 0 0 0 0 0
+device ndiode sky130_fd_pr__diode_pw2nd_05v5 -100 -100 -99 -99 a=40000 p=800 "w_n238_n238#" "a_n100_n100#" 352 0 "w_n238_n238#" 200 0
diff --git a/mag/sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y.mag b/mag/sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y.mag
new file mode 100644
index 0000000..8d04c51
--- /dev/null
+++ b/mag/sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y.mag
@@ -0,0 +1,44 @@
+magic
+tech sky130A
+timestamp 1647842470
+<< pwell >>
+rect -119 -119 119 119
+<< psubdiff >>
+rect -101 84 101 101
+rect -101 53 -84 84
+rect 84 53 101 84
+rect -101 -84 -84 -53
+rect 84 -84 101 -53
+rect -101 -101 101 -84
+<< psubdiffcont >>
+rect -101 -53 -84 53
+rect 84 -53 101 53
+<< ndiode >>
+rect -50 44 50 50
+rect -50 -44 -44 44
+rect 44 -44 50 44
+rect -50 -50 50 -44
+<< ndiodec >>
+rect -44 -44 44 44
+<< locali >>
+rect -101 84 101 101
+rect -101 53 -84 84
+rect 84 53 101 84
+rect -52 -44 -44 44
+rect 44 -44 52 44
+rect -101 -84 -84 -53
+rect 84 -84 101 -53
+rect -101 -101 101 -84
+<< viali >>
+rect -44 -44 44 44
+<< metal1 >>
+rect -50 44 50 47
+rect -50 -44 -44 44
+rect 44 -44 50 44
+rect -50 -47 50 -44
+<< properties >>
+string FIXED_BBOX -92 -92 92 92
+string gencell sky130_fd_pr__diode_pw2nd_05v5
+string library sky130
+string parameters w 1 l 1 area 1.0 peri 4.0 nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 elc 1 erc 1 etc 0 ebc 0 doverlap 0 compatible {sky130_fd_pr__diode_pw2nd_05v5 sky130_fd_pr__diode_pw2nd_05v5_lvt sky130_fd_pr__diode_pw2nd_05v5_nvt sky130_fd_pr__diode_pw2nd_11v0} full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+<< end >>
diff --git a/mag/sky130_fd_pr__diode_pw2nd_05v5_FT76RJ.mag b/mag/sky130_fd_pr__diode_pw2nd_05v5_FT76RJ.mag
new file mode 100644
index 0000000..4973603
--- /dev/null
+++ b/mag/sky130_fd_pr__diode_pw2nd_05v5_FT76RJ.mag
@@ -0,0 +1,51 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647842470
+<< pwell >>
+rect -183 -183 183 183
+<< psubdiff >>
+rect -147 113 -51 147
+rect 51 113 147 147
+rect -147 51 -113 113
+rect 113 51 147 113
+rect -147 -113 -113 -51
+rect 113 -113 147 -51
+rect -147 -147 -51 -113
+rect 51 -147 147 -113
+<< psubdiffcont >>
+rect -51 113 51 147
+rect -147 -51 -113 51
+rect 113 -51 147 51
+rect -51 -147 51 -113
+<< ndiode >>
+rect -45 33 45 45
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -45 45 -33
+<< ndiodec >>
+rect -33 -33 33 33
+<< locali >>
+rect -147 113 -51 147
+rect 51 113 147 147
+rect -147 51 -113 113
+rect 113 51 147 113
+rect -49 -33 -33 33
+rect 33 -33 49 33
+rect -147 -113 -113 -51
+rect 113 -113 147 -51
+rect -147 -147 -51 -113
+rect 51 -147 147 -113
+<< viali >>
+rect -33 -33 33 33
+<< metal1 >>
+rect -45 33 45 39
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -39 45 -33
+<< properties >>
+string FIXED_BBOX -130 -130 130 130
+string gencell sky130_fd_pr__diode_pw2nd_05v5
+string library sky130
+string parameters w 0.45 l 0.45 area 202.5m peri 1.8 nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 elc 1 erc 1 etc 1 ebc 1 doverlap 0 compatible {sky130_fd_pr__diode_pw2nd_05v5 sky130_fd_pr__diode_pw2nd_05v5_lvt sky130_fd_pr__diode_pw2nd_05v5_nvt sky130_fd_pr__diode_pw2nd_11v0} full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+<< end >>
diff --git a/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.ext b/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.ext
new file mode 100644
index 0000000..48f8b44
--- /dev/null
+++ b/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.ext
@@ -0,0 +1,10 @@
+timestamp 1646995406
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__diode_pw2nd_05v5 a=area p=pj
+node "a_n45_n45#" 18 219.921 -45 -45 ndi 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6468 328 7020 336 0 0 0 0 0 0 0 0 0 0
+substrate "w_n183_n183#" 0 0 -183 -183 pw 133956 1464 0 0 0 0 0 0 0 0 35360 2080 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35360 2080 0 0 0 0 0 0 0 0 0 0 0 0
+device ndiode sky130_fd_pr__diode_pw2nd_05v5 -45 -45 -44 -44 a=8100 p=360 "w_n183_n183#" "a_n45_n45#" 132 0 "w_n183_n183#" 0 0
diff --git a/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.mag b/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.mag
new file mode 100644
index 0000000..65f1b71
--- /dev/null
+++ b/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.mag
@@ -0,0 +1,42 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646995406
+<< pwell >>
+rect -183 -183 183 183
+<< psubdiff >>
+rect -147 113 147 147
+rect -147 51 -113 113
+rect -147 -113 -113 -51
+rect 113 -113 147 113
+rect -147 -147 147 -113
+<< psubdiffcont >>
+rect -147 -51 -113 51
+<< ndiode >>
+rect -45 33 45 45
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -45 45 -33
+<< ndiodec >>
+rect -33 -33 33 33
+<< locali >>
+rect -147 113 147 147
+rect -147 51 -113 113
+rect -49 -33 -33 33
+rect 33 -33 49 33
+rect -147 -113 -113 -51
+rect 113 -113 147 113
+rect -147 -147 147 -113
+<< viali >>
+rect -33 -33 33 33
+<< metal1 >>
+rect -45 33 45 39
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -39 45 -33
+<< properties >>
+string FIXED_BBOX -130 -130 130 130
+string gencell sky130_fd_pr__diode_pw2nd_05v5
+string library sky130
+string parameters w 0.45 l 0.45 area 202.5m peri 1.8 nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 elc 1 erc 0 etc 0 ebc 0 doverlap 0 compatible {sky130_fd_pr__diode_pw2nd_05v5 sky130_fd_pr__diode_pw2nd_05v5_lvt sky130_fd_pr__diode_pw2nd_05v5_nvt sky130_fd_pr__diode_pw2nd_11v0} full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+<< end >>
diff --git a/mag/sky130_fd_pr__diode_pw2nd_05v5_GT7G3L.mag b/mag/sky130_fd_pr__diode_pw2nd_05v5_GT7G3L.mag
new file mode 100644
index 0000000..bf4185d
--- /dev/null
+++ b/mag/sky130_fd_pr__diode_pw2nd_05v5_GT7G3L.mag
@@ -0,0 +1,45 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646995406
+<< pwell >>
+rect -183 -183 183 183
+<< psubdiff >>
+rect -147 113 147 147
+rect -147 51 -113 113
+rect 113 51 147 113
+rect -147 -113 -113 -51
+rect 113 -113 147 -51
+rect -147 -147 147 -113
+<< psubdiffcont >>
+rect -147 -51 -113 51
+rect 113 -51 147 51
+<< ndiode >>
+rect -45 33 45 45
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -45 45 -33
+<< ndiodec >>
+rect -33 -33 33 33
+<< locali >>
+rect -147 113 147 147
+rect -147 51 -113 113
+rect 113 51 147 113
+rect -49 -33 -33 33
+rect 33 -33 49 33
+rect -147 -113 -113 -51
+rect 113 -113 147 -51
+rect -147 -147 147 -113
+<< viali >>
+rect -33 -33 33 33
+<< metal1 >>
+rect -45 33 45 39
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -39 45 -33
+<< properties >>
+string FIXED_BBOX -130 -130 130 130
+string gencell sky130_fd_pr__diode_pw2nd_05v5
+string library sky130
+string parameters w 0.45 l 0.45 area 202.5m peri 1.8 nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 elc 1 erc 1 etc 0 ebc 0 doverlap 0 compatible {sky130_fd_pr__diode_pw2nd_05v5 sky130_fd_pr__diode_pw2nd_05v5_lvt sky130_fd_pr__diode_pw2nd_05v5_nvt sky130_fd_pr__diode_pw2nd_11v0} full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+<< end >>
diff --git a/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.ext b/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.ext
new file mode 100644
index 0000000..48f8b44
--- /dev/null
+++ b/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.ext
@@ -0,0 +1,10 @@
+timestamp 1646995406
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__diode_pw2nd_05v5 a=area p=pj
+node "a_n45_n45#" 18 219.921 -45 -45 ndi 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6468 328 7020 336 0 0 0 0 0 0 0 0 0 0
+substrate "w_n183_n183#" 0 0 -183 -183 pw 133956 1464 0 0 0 0 0 0 0 0 35360 2080 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35360 2080 0 0 0 0 0 0 0 0 0 0 0 0
+device ndiode sky130_fd_pr__diode_pw2nd_05v5 -45 -45 -44 -44 a=8100 p=360 "w_n183_n183#" "a_n45_n45#" 132 0 "w_n183_n183#" 0 0
diff --git a/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.mag b/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.mag
new file mode 100644
index 0000000..044caf4
--- /dev/null
+++ b/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.mag
@@ -0,0 +1,42 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646995406
+<< pwell >>
+rect -183 -183 183 183
+<< psubdiff >>
+rect -147 113 147 147
+rect -147 -113 -113 113
+rect 113 51 147 113
+rect 113 -113 147 -51
+rect -147 -147 147 -113
+<< psubdiffcont >>
+rect 113 -51 147 51
+<< ndiode >>
+rect -45 33 45 45
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -45 45 -33
+<< ndiodec >>
+rect -33 -33 33 33
+<< locali >>
+rect -147 113 147 147
+rect -147 -113 -113 113
+rect 113 51 147 113
+rect -49 -33 -33 33
+rect 33 -33 49 33
+rect 113 -113 147 -51
+rect -147 -147 147 -113
+<< viali >>
+rect -33 -33 33 33
+<< metal1 >>
+rect -45 33 45 39
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -39 45 -33
+<< properties >>
+string FIXED_BBOX -130 -130 130 130
+string gencell sky130_fd_pr__diode_pw2nd_05v5
+string library sky130
+string parameters w 0.45 l 0.45 area 202.5m peri 1.8 nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 elc 0 erc 1 etc 0 ebc 0 doverlap 0 compatible {sky130_fd_pr__diode_pw2nd_05v5 sky130_fd_pr__diode_pw2nd_05v5_lvt sky130_fd_pr__diode_pw2nd_05v5_nvt sky130_fd_pr__diode_pw2nd_11v0} full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+<< end >>
diff --git a/mag/sky130_fd_pr__diode_pw2nd_05v5_U68KKY.mag b/mag/sky130_fd_pr__diode_pw2nd_05v5_U68KKY.mag
new file mode 100644
index 0000000..2abe223
--- /dev/null
+++ b/mag/sky130_fd_pr__diode_pw2nd_05v5_U68KKY.mag
@@ -0,0 +1,38 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646995406
+<< pwell >>
+rect -183 -183 183 183
+<< psubdiff >>
+rect -147 113 147 147
+rect -147 -113 -113 113
+rect 113 -113 147 113
+rect -147 -147 147 -113
+<< ndiode >>
+rect -45 33 45 45
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -45 45 -33
+<< ndiodec >>
+rect -33 -33 33 33
+<< locali >>
+rect -147 113 147 147
+rect -147 -113 -113 113
+rect -49 -33 -33 33
+rect 33 -33 49 33
+rect 113 -113 147 113
+rect -147 -147 147 -113
+<< viali >>
+rect -33 -33 33 33
+<< metal1 >>
+rect -45 33 45 39
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -39 45 -33
+<< properties >>
+string FIXED_BBOX -130 -130 130 130
+string gencell sky130_fd_pr__diode_pw2nd_05v5
+string library sky130
+string parameters w 0.45 l 0.45 area 202.5m peri 1.8 nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 elc 0 erc 0 etc 0 ebc 0 doverlap 0 compatible {sky130_fd_pr__diode_pw2nd_05v5 sky130_fd_pr__diode_pw2nd_05v5_lvt sky130_fd_pr__diode_pw2nd_05v5_nvt sky130_fd_pr__diode_pw2nd_11v0} full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_RFPF4W.mag b/mag/sky130_fd_pr__nfet_01v8_RFPF4W.mag
new file mode 100644
index 0000000..dbb5e09
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_RFPF4W.mag
@@ -0,0 +1,100 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1652161614
+<< error_p >>
+rect -29 207 29 213
+rect -29 173 -17 207
+rect -29 167 29 173
+rect -29 -173 29 -167
+rect -29 -207 -17 -173
+rect -29 -213 29 -207
+<< pwell >>
+rect -211 -345 211 345
+<< nmos >>
+rect -15 -135 15 135
+<< ndiff >>
+rect -73 123 -15 135
+rect -73 -123 -61 123
+rect -27 -123 -15 123
+rect -73 -135 -15 -123
+rect 15 123 73 135
+rect 15 -123 27 123
+rect 61 -123 73 123
+rect 15 -135 73 -123
+<< ndiffc >>
+rect -61 -123 -27 123
+rect 27 -123 61 123
+<< psubdiff >>
+rect -175 275 -79 309
+rect 79 275 175 309
+rect -175 213 -141 275
+rect 141 213 175 275
+rect -175 -275 -141 -213
+rect 141 -275 175 -213
+rect -175 -309 -79 -275
+rect 79 -309 175 -275
+<< psubdiffcont >>
+rect -79 275 79 309
+rect -175 -213 -141 213
+rect 141 -213 175 213
+rect -79 -309 79 -275
+<< poly >>
+rect -33 207 33 223
+rect -33 173 -17 207
+rect 17 173 33 207
+rect -33 157 33 173
+rect -15 135 15 157
+rect -15 -157 15 -135
+rect -33 -173 33 -157
+rect -33 -207 -17 -173
+rect 17 -207 33 -173
+rect -33 -223 33 -207
+<< polycont >>
+rect -17 173 17 207
+rect -17 -207 17 -173
+<< locali >>
+rect -175 275 -79 309
+rect 79 275 175 309
+rect -175 213 -141 275
+rect 141 213 175 275
+rect -33 173 -17 207
+rect 17 173 33 207
+rect -61 123 -27 139
+rect -61 -139 -27 -123
+rect 27 123 61 139
+rect 27 -139 61 -123
+rect -33 -207 -17 -173
+rect 17 -207 33 -173
+rect -175 -275 -141 -213
+rect 141 -275 175 -213
+rect -175 -309 -79 -275
+rect 79 -309 175 -275
+<< viali >>
+rect -17 173 17 207
+rect -61 -123 -27 123
+rect 27 -123 61 123
+rect -17 -207 17 -173
+<< metal1 >>
+rect -29 207 29 213
+rect -29 173 -17 207
+rect 17 173 29 207
+rect -29 167 29 173
+rect -67 123 -21 135
+rect -67 -123 -61 123
+rect -27 -123 -21 123
+rect -67 -135 -21 -123
+rect 21 123 67 135
+rect 21 -123 27 123
+rect 61 -123 67 123
+rect 21 -135 67 -123
+rect -29 -173 29 -167
+rect -29 -207 -17 -173
+rect 17 -207 29 -173
+rect -29 -213 29 -207
+<< properties >>
+string FIXED_BBOX -158 -292 158 292
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1.347 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git "a/mag/sky130_fd_pr__nfet_01v8_XJTKXQ\0431.ext" "b/mag/sky130_fd_pr__nfet_01v8_XJTKXQ\0431.ext"
new file mode 100755
index 0000000..150e91a
--- /dev/null
+++ "b/mag/sky130_fd_pr__nfet_01v8_XJTKXQ\0431.ext"
@@ -0,0 +1,19 @@
+timestamp 1646324451
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n100#" 456 -13.94 63 -100 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 420 -13.94 -33 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n125_n74#" 456 -13.94 -125 -74 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_33_n122#" 392 44.198 33 -122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7320 548 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n63_n122#" 392 44.198 -63 -122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7320 548 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n100#" "a_63_n100#" 216.232
+cap "a_n125_n74#" "a_63_n100#" 78.1987
+cap "a_n125_n74#" "a_n33_n100#" 216.232
+cap "a_n63_n122#" "a_33_n122#" 15.3333
+device msubckt sky130_fd_pr__nfet_01v8 33 -100 34 -99 l=30 w=200 "VSUBS" "a_33_n122#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -63 -100 -62 -99 l=30 w=200 "VSUBS" "a_n63_n122#" 60 0 "a_n125_n74#" 200 0 "a_n33_n100#" 200 0
diff --git "a/mag/sky130_fd_pr__nfet_01v8_XJTKXQ\0431.mag" "b/mag/sky130_fd_pr__nfet_01v8_XJTKXQ\0431.mag"
new file mode 100755
index 0000000..9e1b853
--- /dev/null
+++ "b/mag/sky130_fd_pr__nfet_01v8_XJTKXQ\0431.mag"
@@ -0,0 +1,67 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646324451
+<< error_p >>
+rect -63 122 -33 126
+rect 33 122 63 126
+rect -63 -126 -33 -122
+rect 33 -126 63 -122
+<< nmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< ndiff >>
+rect -121 74 -63 100
+rect -125 62 -63 74
+rect -125 -62 -113 62
+rect -79 -62 -63 62
+rect -125 -74 -63 -62
+rect -121 -100 -63 -74
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 74 121 100
+rect 63 62 125 74
+rect 63 -62 79 62
+rect 113 -62 125 62
+rect 63 -74 125 -62
+rect 63 -100 121 -74
+<< ndiffc >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< poly >>
+rect -63 100 -33 122
+rect 33 100 63 122
+rect -63 -122 -33 -100
+rect 33 -122 63 -100
+<< locali >>
+rect -113 62 -79 78
+rect -113 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+<< viali >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< metal1 >>
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.ext b/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
new file mode 100755
index 0000000..e7e29c9
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
@@ -0,0 +1,19 @@
+timestamp 1646324451
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n100#" 456 -13.94 63 -100 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 420 -13.94 -33 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n125_n74#" 456 -13.94 -125 -74 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_33_n122#" 392 44.198 33 -122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7320 548 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n63_n122#" 392 44.198 -63 -122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7320 548 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_33_n122#" "a_n63_n122#" 15.3333
+cap "a_n125_n74#" "a_n33_n100#" 216.232
+cap "a_n125_n74#" "a_63_n100#" 78.1987
+cap "a_n33_n100#" "a_63_n100#" 216.232
+device msubckt sky130_fd_pr__nfet_01v8 33 -100 34 -99 l=30 w=200 "VSUBS" "a_33_n122#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -63 -100 -62 -99 l=30 w=200 "VSUBS" "a_n63_n122#" 60 0 "a_n125_n74#" 200 0 "a_n33_n100#" 200 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.mag b/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.mag
new file mode 100755
index 0000000..9e1b853
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.mag
@@ -0,0 +1,67 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646324451
+<< error_p >>
+rect -63 122 -33 126
+rect 33 122 63 126
+rect -63 -126 -33 -122
+rect 33 -126 63 -122
+<< nmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< ndiff >>
+rect -121 74 -63 100
+rect -125 62 -63 74
+rect -125 -62 -113 62
+rect -79 -62 -63 62
+rect -125 -74 -63 -62
+rect -121 -100 -63 -74
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 74 121 100
+rect 63 62 125 74
+rect 63 -62 79 62
+rect 113 -62 125 62
+rect 63 -74 125 -62
+rect 63 -100 121 -74
+<< ndiffc >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< poly >>
+rect -63 100 -33 122
+rect 33 100 63 122
+rect -63 -122 -33 -100
+rect 33 -122 63 -100
+<< locali >>
+rect -113 62 -79 78
+rect -113 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+<< viali >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< metal1 >>
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_5SM9EE.ext b/mag/sky130_fd_pr__pfet_01v8_5SM9EE.ext
new file mode 100644
index 0000000..3922e59
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_5SM9EE.ext
@@ -0,0 +1,17 @@
+timestamp 1651811172
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n100#" 754 -177.94 15 -100 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n100#" 754 -177.94 -73 -100 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n126#" 405 4.134 -15 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7560 564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n162#" 2527 211.896 -109 -162 nw 0 0 0 0 70632 1084 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_n109_n162#" "a_n15_n126#" 45.1
+cap "a_n73_n100#" "a_15_n100#" 341.397
+cap "w_n109_n162#" "a_15_n100#" 200.332
+cap "w_n109_n162#" "a_n73_n100#" 200.332
+device msubckt sky130_fd_pr__pfet_01v8 -15 -100 -14 -99 l=30 w=200 "w_n109_n162#" "a_n15_n126#" 60 0 "a_n73_n100#" 200 0 "a_15_n100#" 200 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_5SM9EE.mag b/mag/sky130_fd_pr__pfet_01v8_5SM9EE.mag
new file mode 100644
index 0000000..b19de14
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_5SM9EE.mag
@@ -0,0 +1,45 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1651811172
+<< nwell >>
+rect -109 -162 109 162
+<< pmos >>
+rect -15 -100 15 100
+<< pdiff >>
+rect -73 88 -15 100
+rect -73 -88 -61 88
+rect -27 -88 -15 88
+rect -73 -100 -15 -88
+rect 15 88 73 100
+rect 15 -88 27 88
+rect 61 -88 73 88
+rect 15 -100 73 -88
+<< pdiffc >>
+rect -61 -88 -27 88
+rect 27 -88 61 88
+<< poly >>
+rect -15 100 15 126
+rect -15 -126 15 -100
+<< locali >>
+rect -61 88 -27 104
+rect -61 -104 -27 -88
+rect 27 88 61 104
+rect 27 -104 61 -88
+<< viali >>
+rect -61 -88 -27 88
+rect 27 -88 61 88
+<< metal1 >>
+rect -67 88 -21 100
+rect -67 -88 -61 88
+rect -27 -88 -21 88
+rect -67 -100 -21 -88
+rect 21 88 67 100
+rect 21 -88 27 88
+rect 61 -88 67 88
+rect 21 -100 67 -88
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git "a/mag/sky130_fd_pr__pfet_01v8_AC5Z8B\0430.ext" "b/mag/sky130_fd_pr__pfet_01v8_AC5Z8B\0430.ext"
new file mode 100755
index 0000000..7d564af
--- /dev/null
+++ "b/mag/sky130_fd_pr__pfet_01v8_AC5Z8B\0430.ext"
@@ -0,0 +1,44 @@
+timestamp 1646324451
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "li_225_n726#" 17 38.7278 225 -726 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1976 180 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n261_n726#" 17 38.7278 -261 -726 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1976 180 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_217_n290#" 15 44.2028 217 -290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2576 204 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n261_n290#" 19 39.5848 -261 -290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2016 184 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_229_174#" 18 22.8948 229 174 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1700 168 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n261_174#" 25 20.6228 -261 174 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1200 148 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_159_n100#" 753 -173.43 159 -100 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9180 608 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 694 -173.43 -33 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9180 608 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n129_n100#" 1931 -368.685 -129 -100 pdif 0 0 0 0 0 0 0 0 0 0 26400 1064 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24300 1440 13616 776 0 0 0 0 0 0 0 0 0 0
+node "a_n221_n74#" 753 -173.43 -221 -74 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9180 608 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n159_n152#" 2233 50.032 -159 -152 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42880 2880 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n261_n210#" 2173 644.52 -261 -210 nw 0 0 0 0 214840 1868 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_229_174#" "a_n33_n100#" 2.80189
+cap "li_n261_n726#" "li_n261_n290#" 3.09375
+cap "a_159_n100#" "li_229_174#" 29.7
+cap "li_n261_174#" "a_n33_n100#" 2.7
+cap "a_n129_n100#" "a_n33_n100#" 462.239
+cap "a_n221_n74#" "a_n33_n100#" 102.009
+cap "a_159_n100#" "a_n129_n100#" 264.021
+cap "a_n221_n74#" "a_159_n100#" 45.1613
+cap "w_n261_n210#" "a_n33_n100#" 207.073
+cap "li_217_n290#" "li_225_n726#" 3.26562
+cap "w_n261_n210#" "a_159_n100#" 207.073
+cap "a_n221_n74#" "li_n261_174#" 21.2143
+cap "a_n221_n74#" "a_n129_n100#" 264.212
+cap "w_n261_n210#" "li_229_174#" 13.1177
+cap "w_n261_n210#" "li_n261_174#" 10.8272
+cap "w_n261_n210#" "a_n129_n100#" 447.025
+cap "w_n261_n210#" "a_n221_n74#" 207.073
+cap "a_n129_n100#" "a_n159_n152#" 106.141
+cap "w_n261_n210#" "a_n159_n152#" 352
+cap "a_159_n100#" "a_n33_n100#" 102.009
+device msubckt sky130_fd_pr__pfet_01v8 129 -100 130 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n129_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 33 -100 34 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n33_n100#" 200 0 "a_n129_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -63 -100 -62 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -159 -100 -158 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n221_n74#" 200 0 "a_n129_n100#" 200 0
diff --git "a/mag/sky130_fd_pr__pfet_01v8_AC5Z8B\0430.mag" "b/mag/sky130_fd_pr__pfet_01v8_AC5Z8B\0430.mag"
new file mode 100755
index 0000000..dced6c3
--- /dev/null
+++ "b/mag/sky130_fd_pr__pfet_01v8_AC5Z8B\0430.mag"
@@ -0,0 +1,114 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646324451
+<< error_p >>
+rect -261 174 -227 224
+rect -209 140 -203 192
+rect 195 140 209 192
+rect 229 174 263 224
+rect -261 -290 -225 -234
+rect -261 -726 -223 -674
+rect 225 -726 263 -674
+<< nwell >>
+rect -261 -210 263 200
+<< pmos >>
+rect -159 -100 -129 100
+rect -63 -100 -33 100
+rect 33 -100 63 100
+rect 129 -100 159 100
+<< pdiff >>
+rect -217 74 -159 100
+rect -221 62 -159 74
+rect -221 -62 -209 62
+rect -175 -62 -159 62
+rect -221 -74 -159 -62
+rect -217 -100 -159 -74
+rect -129 62 -63 100
+rect -129 -62 -113 62
+rect -79 -62 -63 62
+rect -129 -100 -63 -62
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 62 129 100
+rect 63 -62 79 62
+rect 113 -62 129 62
+rect 63 -100 129 -62
+rect 159 74 217 100
+rect 159 62 221 74
+rect 159 -62 175 62
+rect 209 -62 221 62
+rect 159 -74 221 -62
+rect 159 -100 217 -74
+<< pdiffc >>
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+<< poly >>
+rect -159 100 -129 138
+rect -63 100 -33 138
+rect 33 100 63 138
+rect 129 100 159 138
+rect -159 -120 -129 -100
+rect -63 -120 -33 -100
+rect 33 -120 63 -100
+rect 129 -120 159 -100
+rect -159 -152 161 -120
+rect 15 -208 45 -152
+<< locali >>
+rect -261 174 -237 224
+rect -209 62 -175 192
+rect -209 -78 -175 -62
+rect -113 62 -79 78
+rect -113 -68 -79 -62
+rect -115 -116 -79 -68
+rect -17 62 17 192
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -64 113 -62
+rect 77 -116 113 -64
+rect 175 62 209 192
+rect 229 174 263 224
+rect 175 -78 209 -62
+rect -115 -154 113 -116
+rect 61 -220 95 -154
+rect -261 -290 -225 -234
+rect 217 -290 263 -234
+rect -261 -726 -223 -674
+rect 225 -726 263 -674
+<< viali >>
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+<< metal1 >>
+rect -215 62 -169 74
+rect -215 -62 -209 62
+rect -175 -62 -169 62
+rect -215 -74 -169 -62
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+rect 169 62 215 74
+rect 169 -62 175 62
+rect 209 -62 215 62
+rect 169 -74 215 -62
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 4 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.ext b/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
new file mode 100755
index 0000000..0889867
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
@@ -0,0 +1,44 @@
+timestamp 1646324451
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "li_225_n726#" 17 38.7278 225 -726 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1976 180 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n261_n726#" 17 38.7278 -261 -726 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1976 180 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_217_n290#" 15 44.2028 217 -290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2576 204 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n261_n290#" 19 39.5848 -261 -290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2016 184 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_229_174#" 18 22.8948 229 174 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1700 168 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n261_174#" 25 20.6228 -261 174 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1200 148 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_159_n100#" 753 -173.43 159 -100 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9180 608 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 694 -173.43 -33 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9180 608 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n129_n100#" 1931 -368.685 -129 -100 pdif 0 0 0 0 0 0 0 0 0 0 26400 1064 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24300 1440 13616 776 0 0 0 0 0 0 0 0 0 0
+node "a_n221_n74#" 753 -173.43 -221 -74 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9180 608 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n159_n152#" 2233 50.032 -159 -152 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42880 2880 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n261_n210#" 2173 644.52 -261 -210 nw 0 0 0 0 214840 1868 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_n261_n210#" "li_n261_174#" 10.8272
+cap "a_n129_n100#" "a_n159_n152#" 106.141
+cap "li_229_174#" "a_n33_n100#" 2.80189
+cap "li_229_174#" "a_159_n100#" 29.7
+cap "a_n33_n100#" "li_n261_174#" 2.7
+cap "a_n159_n152#" "w_n261_n210#" 352
+cap "a_n221_n74#" "a_n129_n100#" 264.212
+cap "a_n221_n74#" "w_n261_n210#" 207.073
+cap "a_n221_n74#" "a_n33_n100#" 102.009
+cap "a_n221_n74#" "a_159_n100#" 45.1613
+cap "a_n129_n100#" "w_n261_n210#" 447.025
+cap "a_n129_n100#" "a_n33_n100#" 462.239
+cap "a_159_n100#" "a_n129_n100#" 264.021
+cap "a_n33_n100#" "w_n261_n210#" 207.073
+cap "a_159_n100#" "w_n261_n210#" 207.073
+cap "a_n221_n74#" "li_n261_174#" 21.2143
+cap "a_159_n100#" "a_n33_n100#" 102.009
+cap "li_n261_n290#" "li_n261_n726#" 3.09375
+cap "li_225_n726#" "li_217_n290#" 3.26562
+cap "li_229_174#" "w_n261_n210#" 13.1177
+device msubckt sky130_fd_pr__pfet_01v8 129 -100 130 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n129_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 33 -100 34 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n33_n100#" 200 0 "a_n129_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -63 -100 -62 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -159 -100 -158 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n221_n74#" 200 0 "a_n129_n100#" 200 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.mag b/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.mag
new file mode 100755
index 0000000..dced6c3
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.mag
@@ -0,0 +1,114 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646324451
+<< error_p >>
+rect -261 174 -227 224
+rect -209 140 -203 192
+rect 195 140 209 192
+rect 229 174 263 224
+rect -261 -290 -225 -234
+rect -261 -726 -223 -674
+rect 225 -726 263 -674
+<< nwell >>
+rect -261 -210 263 200
+<< pmos >>
+rect -159 -100 -129 100
+rect -63 -100 -33 100
+rect 33 -100 63 100
+rect 129 -100 159 100
+<< pdiff >>
+rect -217 74 -159 100
+rect -221 62 -159 74
+rect -221 -62 -209 62
+rect -175 -62 -159 62
+rect -221 -74 -159 -62
+rect -217 -100 -159 -74
+rect -129 62 -63 100
+rect -129 -62 -113 62
+rect -79 -62 -63 62
+rect -129 -100 -63 -62
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 62 129 100
+rect 63 -62 79 62
+rect 113 -62 129 62
+rect 63 -100 129 -62
+rect 159 74 217 100
+rect 159 62 221 74
+rect 159 -62 175 62
+rect 209 -62 221 62
+rect 159 -74 221 -62
+rect 159 -100 217 -74
+<< pdiffc >>
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+<< poly >>
+rect -159 100 -129 138
+rect -63 100 -33 138
+rect 33 100 63 138
+rect 129 100 159 138
+rect -159 -120 -129 -100
+rect -63 -120 -33 -100
+rect 33 -120 63 -100
+rect 129 -120 159 -100
+rect -159 -152 161 -120
+rect 15 -208 45 -152
+<< locali >>
+rect -261 174 -237 224
+rect -209 62 -175 192
+rect -209 -78 -175 -62
+rect -113 62 -79 78
+rect -113 -68 -79 -62
+rect -115 -116 -79 -68
+rect -17 62 17 192
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -64 113 -62
+rect 77 -116 113 -64
+rect 175 62 209 192
+rect 229 174 263 224
+rect 175 -78 209 -62
+rect -115 -154 113 -116
+rect 61 -220 95 -154
+rect -261 -290 -225 -234
+rect 217 -290 263 -234
+rect -261 -726 -223 -674
+rect 225 -726 263 -674
+<< viali >>
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+<< metal1 >>
+rect -215 62 -169 74
+rect -215 -62 -209 62
+rect -175 -62 -169 62
+rect -215 -74 -169 -62
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+rect 169 62 215 74
+rect 169 -62 175 62
+rect 209 -62 215 62
+rect 169 -74 215 -62
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 4 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/user_analog_project_wrapper.ext b/mag/user_analog_project_wrapper.ext
new file mode 100644
index 0000000..ae1756e
--- /dev/null
+++ b/mag/user_analog_project_wrapper.ext
@@ -0,0 +1,1919 @@
+timestamp 1653478184
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2 0 1 70516 -1 0 673768
+use sky130_fd_pr__diode_pd2nw_05v5_G4XDRY sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0 1 0 125433 0 1 695295
+use sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y_0 1 0 119582 0 1 695306
+use sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3 0 1 122500 -1 0 673516
+use sky130_fd_sc_hd__buf_16 sky130_fd_sc_hd__buf_16_0 0 -1 415748 1 0 686664
+use sky130_fd_sc_hd__buf_16 sky130_fd_sc_hd__buf_16_2 1 0 406656 0 1 587358
+use sky130_fd_sc_hd__buf_16 sky130_fd_sc_hd__buf_16_3 1 0 406646 0 1 585256
+use comparator_v6 comparator_v6_0 0 1 419250 1 0 584722
+use sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0 0 -1 440640 1 0 591294
+use sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1 0 -1 448994 1 0 591314
+use sky130_fd_sc_hd__buf_16 sky130_fd_sc_hd__buf_16_1 0 -1 467556 1 0 686698
+use sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4 0 1 569338 -1 0 689064
+use sky130_fd_sc_hd__buf_16 sky130_fd_sc_hd__buf_16_4 0 1 569338 -1 0 688388
+parameters sky130_fd_pr__diode_pd2nw_05v5 a=area p=pj
+parameters sky130_fd_pr__diode_pw2nd_05v5 a=area p=pj
+port "VGND" 2 448448 591294 448544 591662 m1
+port "io_analog[4]" 41 329294 702300 334294 704800 m5
+port "io_analog[4]" 47 318994 702300 323994 704800 m5
+port "io_analog[4]" 41 329294 702300 334294 704800 m4
+port "io_analog[4]" 47 318994 702300 323994 704800 m4
+port "io_analog[5]" 48 217294 702300 222294 704800 m4
+port "io_analog[5]" 42 227594 702300 232594 704800 m4
+port "io_in_3v3[0]" 83 583520 1544 584800 1656 m3
+port "io_oeb[26]" 128 -800 1544 480 1656 m3
+port "io_in[0]" 56 583520 2726 584800 2838 m3
+port "io_out[26]" 155 -800 2726 480 2838 m3
+port "io_out[0]" 137 583520 3908 584800 4020 m3
+port "io_in[26]" 74 -800 3908 480 4020 m3
+port "io_oeb[0]" 110 583520 5090 584800 5202 m3
+port "io_in_3v3[26]" 101 -800 5090 480 5202 m3
+port "io_in_3v3[1]" 94 583520 6272 584800 6384 m3
+port "io_oeb[25]" 127 -800 6272 480 6384 m3
+port "io_in[1]" 67 583520 7454 584800 7566 m3
+port "io_out[25]" 154 -800 7454 480 7566 m3
+port "io_out[1]" 148 583520 8636 584800 8748 m3
+port "io_in[25]" 73 -800 8636 480 8748 m3
+port "io_oeb[1]" 121 583520 9818 584800 9930 m3
+port "io_in_3v3[25]" 100 -800 9818 480 9930 m3
+port "io_in_3v3[2]" 102 583520 11000 584800 11112 m3
+port "io_oeb[24]" 126 -800 11000 480 11112 m3
+port "io_in[2]" 75 583520 12182 584800 12294 m3
+port "io_out[24]" 153 -800 12182 480 12294 m3
+port "io_out[2]" 156 583520 13364 584800 13476 m3
+port "io_in[24]" 72 -800 13364 480 13476 m3
+port "io_oeb[2]" 129 583520 14546 584800 14658 m3
+port "io_in_3v3[24]" 99 -800 14546 480 14658 m3
+port "io_in_3v3[3]" 103 583520 15728 584800 15840 m3
+port "gpio_noesd[17]" 26 -800 15728 480 15840 m3
+port "io_in[3]" 76 583520 16910 584800 17022 m3
+port "gpio_analog[17]" 8 -800 16910 480 17022 m3
+port "io_out[3]" 157 583520 18092 584800 18204 m3
+port "io_oeb[3]" 130 583520 19274 584800 19386 m3
+port "io_in_3v3[4]" 104 583520 20456 584800 20568 m3
+port "io_in[4]" 77 583520 21638 584800 21750 m3
+port "io_out[4]" 158 583520 22820 584800 22932 m3
+port "io_oeb[4]" 131 583520 24002 584800 24114 m3
+port "io_oeb[23]" 125 -800 32422 480 32534 m3
+port "io_out[23]" 152 -800 33604 480 33716 m3
+port "io_in[23]" 71 -800 34786 480 34898 m3
+port "io_in_3v3[23]" 98 -800 35968 480 36080 m3
+port "gpio_noesd[16]" 25 -800 37150 480 37262 m3
+port "gpio_analog[16]" 7 -800 38332 480 38444 m3
+port "io_in_3v3[5]" 105 583520 46914 584800 47026 m3
+port "io_in[5]" 78 583520 48096 584800 48208 m3
+port "io_out[5]" 159 583520 49278 584800 49390 m3
+port "io_oeb[5]" 132 583520 50460 584800 50572 m3
+port "io_oeb[22]" 124 -800 75644 480 75756 m3
+port "io_out[22]" 151 -800 76826 480 76938 m3
+port "io_in[22]" 70 -800 78008 480 78120 m3
+port "io_in_3v3[22]" 97 -800 79190 480 79302 m3
+port "gpio_noesd[15]" 24 -800 80372 480 80484 m3
+port "gpio_analog[15]" 6 -800 81554 480 81666 m3
+port "io_in_3v3[6]" 106 583520 91572 584800 91684 m3
+port "io_in[6]" 79 583520 92754 584800 92866 m3
+port "io_out[6]" 160 583520 93936 584800 94048 m3
+port "io_oeb[6]" 133 583520 95118 584800 95230 m3
+port "io_oeb[21]" 123 -800 118866 480 118978 m3
+port "io_out[21]" 150 -800 120048 480 120160 m3
+port "io_in[21]" 69 -800 121230 480 121342 m3
+port "io_in_3v3[21]" 96 -800 122412 480 122524 m3
+port "gpio_noesd[14]" 23 -800 123594 480 123706 m3
+port "gpio_analog[14]" 5 -800 124776 480 124888 m3
+port "vssa1" 565 582340 136830 584800 141630 m3
+port "vssa1" 564 582340 146830 584800 151630 m3
+port "vssd2" 571 0 162888 1660 167688 m3
+port "vssd2" 570 0 172888 1660 177688 m3
+port "vssd1" 569 582340 181430 584800 186230 m3
+port "vssd1" 568 582340 191430 584800 196230 m3
+port "vdda2" 560 0 204888 1660 209688 m3
+port "vdda2" 561 0 214888 1660 219688 m3
+port "vdda1" 559 582340 225230 584800 230030 m3
+port "vdda1" 558 582340 235230 584800 240030 m3
+port "io_oeb[20]" 122 -800 246488 480 246600 m3
+port "io_out[20]" 149 -800 247670 480 247782 m3
+port "io_in[20]" 68 -800 248852 480 248964 m3
+port "io_in_3v3[20]" 95 -800 250034 480 250146 m3
+port "gpio_noesd[13]" 22 -800 251216 480 251328 m3
+port "gpio_analog[13]" 4 -800 252398 480 252510 m3
+port "gpio_analog[0]" 0 583520 269230 584800 269342 m3
+port "gpio_noesd[0]" 18 583520 270412 584800 270524 m3
+port "io_in_3v3[7]" 107 583520 271594 584800 271706 m3
+port "io_in[7]" 80 583520 272776 584800 272888 m3
+port "io_out[7]" 161 583520 273958 584800 274070 m3
+port "io_oeb[7]" 134 583520 275140 584800 275252 m3
+port "io_oeb[19]" 120 -800 289510 480 289622 m3
+port "io_out[19]" 147 -800 290692 480 290804 m3
+port "io_in[19]" 66 -800 291874 480 291986 m3
+port "io_in_3v3[19]" 93 -800 293056 480 293168 m3
+port "gpio_noesd[12]" 21 -800 294238 480 294350 m3
+port "gpio_analog[12]" 3 -800 295420 480 295532 m3
+port "gpio_analog[1]" 9 583520 313652 584800 313764 m3
+port "gpio_noesd[1]" 27 583520 314834 584800 314946 m3
+port "io_in_3v3[8]" 108 583520 316016 584800 316128 m3
+port "io_in[8]" 81 583520 317198 584800 317310 m3
+port "io_out[8]" 162 583520 318380 584800 318492 m3
+port "io_oeb[8]" 135 583520 319562 584800 319674 m3
+port "io_oeb[18]" 119 -800 332732 480 332844 m3
+port "io_out[18]" 146 -800 333914 480 334026 m3
+port "io_in[18]" 65 -800 335096 480 335208 m3
+port "io_in_3v3[18]" 92 -800 336278 480 336390 m3
+port "gpio_noesd[11]" 20 -800 337460 480 337572 m3
+port "gpio_analog[11]" 2 -800 338642 480 338754 m3
+port "gpio_analog[2]" 10 583520 358874 584800 358986 m3
+port "gpio_noesd[2]" 28 583520 360056 584800 360168 m3
+port "io_in_3v3[9]" 109 583520 361238 584800 361350 m3
+port "io_in[9]" 82 583520 362420 584800 362532 m3
+port "io_out[9]" 163 583520 363602 584800 363714 m3
+port "io_oeb[9]" 136 583520 364784 584800 364896 m3
+port "io_oeb[17]" 118 -800 375954 480 376066 m3
+port "io_out[17]" 145 -800 377136 480 377248 m3
+port "io_in[17]" 64 -800 378318 480 378430 m3
+port "io_in_3v3[17]" 91 -800 379500 480 379612 m3
+port "gpio_noesd[10]" 19 -800 380682 480 380794 m3
+port "gpio_analog[10]" 1 -800 381864 480 381976 m3
+port "gpio_analog[3]" 11 583520 405296 584800 405408 m3
+port "gpio_noesd[3]" 29 583520 406478 584800 406590 m3
+port "io_in_3v3[10]" 84 583520 407660 584800 407772 m3
+port "io_in[10]" 57 583520 408842 584800 408954 m3
+port "io_out[10]" 138 583520 410024 584800 410136 m3
+port "io_oeb[10]" 111 583520 411206 584800 411318 m3
+port "io_oeb[16]" 117 -800 419176 480 419288 m3
+port "io_out[16]" 144 -800 420358 480 420470 m3
+port "io_in[16]" 63 -800 421540 480 421652 m3
+port "io_in_3v3[16]" 90 -800 422722 480 422834 m3
+port "gpio_noesd[9]" 35 -800 423904 480 424016 m3
+port "gpio_analog[9]" 17 -800 425086 480 425198 m3
+port "gpio_analog[4]" 12 583520 449718 584800 449830 m3
+port "gpio_noesd[4]" 30 583520 450900 584800 451012 m3
+port "io_in_3v3[11]" 85 583520 452082 584800 452194 m3
+port "io_in[11]" 58 583520 453264 584800 453376 m3
+port "io_out[11]" 139 583520 454446 584800 454558 m3
+port "io_oeb[11]" 112 583520 455628 584800 455740 m3
+port "io_oeb[15]" 116 -800 462398 480 462510 m3
+port "io_out[15]" 143 -800 463580 480 463692 m3
+port "io_in[15]" 62 -800 464762 480 464874 m3
+port "io_in_3v3[15]" 89 -800 465944 480 466056 m3
+port "gpio_noesd[8]" 34 -800 467126 480 467238 m3
+port "gpio_analog[8]" 16 -800 468308 480 468420 m3
+port "gpio_analog[5]" 13 583520 494140 584800 494252 m3
+port "gpio_noesd[5]" 31 583520 495322 584800 495434 m3
+port "io_in_3v3[12]" 86 583520 496504 584800 496616 m3
+port "io_in[12]" 59 583520 497686 584800 497798 m3
+port "io_out[12]" 140 583520 498868 584800 498980 m3
+port "io_oeb[12]" 113 583520 500050 584800 500162 m3
+port "io_oeb[14]" 115 -800 505620 480 505732 m3
+port "io_out[14]" 142 -800 506802 480 506914 m3
+port "io_in[14]" 61 -800 507984 480 508096 m3
+port "io_in_3v3[14]" 88 -800 509166 480 509278 m3
+port "gpio_noesd[7]" 33 -800 510348 480 510460 m3
+port "gpio_analog[7]" 15 -800 511530 480 511642 m3
+port "vdda1" 556 582340 540562 584800 545362 m3
+port "vdda1" 557 582340 550562 584800 555362 m3
+port "vssa2" 567 0 549442 1660 554242 m3
+port "vssa2" 566 0 559442 1660 564242 m3
+port "gpio_analog[6]" 14 583520 583562 584800 583674 m3
+port "gpio_noesd[6]" 32 583520 584744 584800 584856 m3
+port "io_in_3v3[13]" 87 583520 585926 584800 586038 m3
+port "io_in[13]" 60 583520 587108 584800 587220 m3
+port "io_out[13]" 141 583520 588290 584800 588402 m3
+port "io_oeb[13]" 114 583520 589472 584800 589584 m3
+port "vccd2" 555 0 633842 1660 638642 m3
+port "vccd2" 554 0 643842 1660 648642 m3
+port "io_analog[10]" 37 0 680242 1700 685242 m3
+port "io_analog[4]" 41 329294 702300 334294 704800 m3
+port "io_clamp_high[0]" 50 326794 702300 328994 704800 m3
+port "io_clamp_low[0]" 53 324294 702300 326494 704800 m3
+port "io_analog[4]" 47 318994 702300 323994 704800 m3
+port "io_analog[5]" 42 227594 702300 232594 704800 m3
+port "io_analog[5]" 48 217294 702300 222294 704800 m3
+port "io_analog[6]" 43 175896 702300 180896 704800 m3
+port "io_analog[6]" 49 165596 702300 170596 704800 m3
+port "io_analog[9]" 46 16194 702300 21194 704800 m3
+port "user_irq[2]" 551 583250 -800 583362 480 m2
+port "user_irq[1]" 550 582068 -800 582180 480 m2
+port "user_irq[0]" 549 580886 -800 580998 480 m2
+port "user_clock2" 548 579704 -800 579816 480 m2
+port "la_oenb[127]" 450 578522 -800 578634 480 m2
+port "la_data_out[127]" 322 577340 -800 577452 480 m2
+port "la_data_in[127]" 194 576158 -800 576270 480 m2
+port "la_oenb[126]" 449 574976 -800 575088 480 m2
+port "la_data_out[126]" 321 573794 -800 573906 480 m2
+port "la_data_in[126]" 193 572612 -800 572724 480 m2
+port "la_oenb[125]" 448 571430 -800 571542 480 m2
+port "la_data_out[125]" 320 570248 -800 570360 480 m2
+port "la_data_in[125]" 192 569066 -800 569178 480 m2
+port "la_oenb[124]" 447 567884 -800 567996 480 m2
+port "la_data_out[124]" 319 566702 -800 566814 480 m2
+port "la_data_in[124]" 191 565520 -800 565632 480 m2
+port "la_oenb[123]" 446 564338 -800 564450 480 m2
+port "la_data_out[123]" 318 563156 -800 563268 480 m2
+port "la_data_in[123]" 190 561974 -800 562086 480 m2
+port "la_oenb[122]" 445 560792 -800 560904 480 m2
+port "la_data_out[122]" 317 559610 -800 559722 480 m2
+port "la_data_in[122]" 189 558428 -800 558540 480 m2
+port "la_oenb[121]" 444 557246 -800 557358 480 m2
+port "la_data_out[121]" 316 556064 -800 556176 480 m2
+port "la_data_in[121]" 188 554882 -800 554994 480 m2
+port "la_oenb[120]" 443 553700 -800 553812 480 m2
+port "la_data_out[120]" 315 552518 -800 552630 480 m2
+port "la_data_in[120]" 187 551336 -800 551448 480 m2
+port "la_oenb[119]" 441 550154 -800 550266 480 m2
+port "la_data_out[119]" 313 548972 -800 549084 480 m2
+port "la_data_in[119]" 185 547790 -800 547902 480 m2
+port "la_oenb[118]" 440 546608 -800 546720 480 m2
+port "la_data_out[118]" 312 545426 -800 545538 480 m2
+port "la_data_in[118]" 184 544244 -800 544356 480 m2
+port "la_oenb[117]" 439 543062 -800 543174 480 m2
+port "la_data_out[117]" 311 541880 -800 541992 480 m2
+port "la_data_in[117]" 183 540698 -800 540810 480 m2
+port "la_oenb[116]" 438 539516 -800 539628 480 m2
+port "la_data_out[116]" 310 538334 -800 538446 480 m2
+port "la_data_in[116]" 182 537152 -800 537264 480 m2
+port "la_oenb[115]" 437 535970 -800 536082 480 m2
+port "la_data_out[115]" 309 534788 -800 534900 480 m2
+port "la_data_in[115]" 181 533606 -800 533718 480 m2
+port "la_oenb[114]" 436 532424 -800 532536 480 m2
+port "la_data_out[114]" 308 531242 -800 531354 480 m2
+port "la_data_in[114]" 180 530060 -800 530172 480 m2
+port "la_oenb[113]" 435 528878 -800 528990 480 m2
+port "la_data_out[113]" 307 527696 -800 527808 480 m2
+port "la_data_in[113]" 179 526514 -800 526626 480 m2
+port "la_oenb[112]" 434 525332 -800 525444 480 m2
+port "la_data_out[112]" 306 524150 -800 524262 480 m2
+port "la_data_in[112]" 178 522968 -800 523080 480 m2
+port "la_oenb[111]" 433 521786 -800 521898 480 m2
+port "la_data_out[111]" 305 520604 -800 520716 480 m2
+port "la_data_in[111]" 177 519422 -800 519534 480 m2
+port "la_oenb[110]" 432 518240 -800 518352 480 m2
+port "la_data_out[110]" 304 517058 -800 517170 480 m2
+port "la_data_in[110]" 176 515876 -800 515988 480 m2
+port "la_oenb[109]" 430 514694 -800 514806 480 m2
+port "la_data_out[109]" 302 513512 -800 513624 480 m2
+port "la_data_in[109]" 174 512330 -800 512442 480 m2
+port "la_oenb[108]" 429 511148 -800 511260 480 m2
+port "la_data_out[108]" 301 509966 -800 510078 480 m2
+port "la_data_in[108]" 173 508784 -800 508896 480 m2
+port "la_oenb[107]" 428 507602 -800 507714 480 m2
+port "la_data_out[107]" 300 506420 -800 506532 480 m2
+port "la_data_in[107]" 172 505238 -800 505350 480 m2
+port "la_oenb[106]" 427 504056 -800 504168 480 m2
+port "la_data_out[106]" 299 502874 -800 502986 480 m2
+port "la_data_in[106]" 171 501692 -800 501804 480 m2
+port "la_oenb[105]" 426 500510 -800 500622 480 m2
+port "la_data_out[105]" 298 499328 -800 499440 480 m2
+port "la_data_in[105]" 170 498146 -800 498258 480 m2
+port "la_oenb[104]" 425 496964 -800 497076 480 m2
+port "la_data_out[104]" 297 495782 -800 495894 480 m2
+port "la_data_in[104]" 169 494600 -800 494712 480 m2
+port "la_oenb[103]" 424 493418 -800 493530 480 m2
+port "la_data_out[103]" 296 492236 -800 492348 480 m2
+port "la_data_in[103]" 168 491054 -800 491166 480 m2
+port "la_oenb[102]" 423 489872 -800 489984 480 m2
+port "la_data_out[102]" 295 488690 -800 488802 480 m2
+port "la_data_in[102]" 167 487508 -800 487620 480 m2
+port "la_oenb[101]" 422 486326 -800 486438 480 m2
+port "la_data_out[101]" 294 485144 -800 485256 480 m2
+port "la_data_in[101]" 166 483962 -800 484074 480 m2
+port "la_oenb[100]" 421 482780 -800 482892 480 m2
+port "la_data_out[100]" 293 481598 -800 481710 480 m2
+port "la_data_in[100]" 165 480416 -800 480528 480 m2
+port "la_oenb[99]" 546 479234 -800 479346 480 m2
+port "la_data_out[99]" 418 478052 -800 478164 480 m2
+port "la_data_in[99]" 290 476870 -800 476982 480 m2
+port "la_oenb[98]" 545 475688 -800 475800 480 m2
+port "la_data_out[98]" 417 474506 -800 474618 480 m2
+port "la_data_in[98]" 289 473324 -800 473436 480 m2
+port "la_oenb[97]" 544 472142 -800 472254 480 m2
+port "la_data_out[97]" 416 470960 -800 471072 480 m2
+port "la_data_in[97]" 288 469778 -800 469890 480 m2
+port "la_oenb[96]" 543 468596 -800 468708 480 m2
+port "la_data_out[96]" 415 467414 -800 467526 480 m2
+port "la_data_in[96]" 287 466232 -800 466344 480 m2
+port "la_oenb[95]" 542 465050 -800 465162 480 m2
+port "la_data_out[95]" 414 463868 -800 463980 480 m2
+port "la_data_in[95]" 286 462686 -800 462798 480 m2
+port "la_oenb[94]" 541 461504 -800 461616 480 m2
+port "la_data_out[94]" 413 460322 -800 460434 480 m2
+port "la_data_in[94]" 285 459140 -800 459252 480 m2
+port "la_oenb[93]" 540 457958 -800 458070 480 m2
+port "la_data_out[93]" 412 456776 -800 456888 480 m2
+port "la_data_in[93]" 284 455594 -800 455706 480 m2
+port "la_oenb[92]" 539 454412 -800 454524 480 m2
+port "la_data_out[92]" 411 453230 -800 453342 480 m2
+port "la_data_in[92]" 283 452048 -800 452160 480 m2
+port "la_oenb[91]" 538 450866 -800 450978 480 m2
+port "la_data_out[91]" 410 449684 -800 449796 480 m2
+port "la_data_in[91]" 282 448502 -800 448614 480 m2
+port "la_oenb[90]" 537 447320 -800 447432 480 m2
+port "la_data_out[90]" 409 446138 -800 446250 480 m2
+port "la_data_in[90]" 281 444956 -800 445068 480 m2
+port "la_oenb[89]" 535 443774 -800 443886 480 m2
+port "la_data_out[89]" 407 442592 -800 442704 480 m2
+port "la_data_in[89]" 279 441410 -800 441522 480 m2
+port "la_oenb[88]" 534 440228 -800 440340 480 m2
+port "la_data_out[88]" 406 439046 -800 439158 480 m2
+port "la_data_in[88]" 278 437864 -800 437976 480 m2
+port "la_oenb[87]" 533 436682 -800 436794 480 m2
+port "la_data_out[87]" 405 435500 -800 435612 480 m2
+port "la_data_in[87]" 277 434318 -800 434430 480 m2
+port "la_oenb[86]" 532 433136 -800 433248 480 m2
+port "la_data_out[86]" 404 431954 -800 432066 480 m2
+port "la_data_in[86]" 276 430772 -800 430884 480 m2
+port "la_oenb[85]" 531 429590 -800 429702 480 m2
+port "la_data_out[85]" 403 428408 -800 428520 480 m2
+port "la_data_in[85]" 275 427226 -800 427338 480 m2
+port "la_oenb[84]" 530 426044 -800 426156 480 m2
+port "la_data_out[84]" 402 424862 -800 424974 480 m2
+port "la_data_in[84]" 274 423680 -800 423792 480 m2
+port "la_oenb[83]" 529 422498 -800 422610 480 m2
+port "la_data_out[83]" 401 421316 -800 421428 480 m2
+port "la_data_in[83]" 273 420134 -800 420246 480 m2
+port "la_oenb[82]" 528 418952 -800 419064 480 m2
+port "la_data_out[82]" 400 417770 -800 417882 480 m2
+port "la_data_in[82]" 272 416588 -800 416700 480 m2
+port "la_oenb[81]" 527 415406 -800 415518 480 m2
+port "la_data_out[81]" 399 414224 -800 414336 480 m2
+port "la_data_in[81]" 271 413042 -800 413154 480 m2
+port "la_oenb[80]" 526 411860 -800 411972 480 m2
+port "la_data_out[80]" 398 410678 -800 410790 480 m2
+port "la_data_in[80]" 270 409496 -800 409608 480 m2
+port "la_oenb[79]" 524 408314 -800 408426 480 m2
+port "la_data_out[79]" 396 407132 -800 407244 480 m2
+port "la_data_in[79]" 268 405950 -800 406062 480 m2
+port "la_oenb[78]" 523 404768 -800 404880 480 m2
+port "la_data_out[78]" 395 403586 -800 403698 480 m2
+port "la_data_in[78]" 267 402404 -800 402516 480 m2
+port "la_oenb[77]" 522 401222 -800 401334 480 m2
+port "la_data_out[77]" 394 400040 -800 400152 480 m2
+port "la_data_in[77]" 266 398858 -800 398970 480 m2
+port "la_oenb[76]" 521 397676 -800 397788 480 m2
+port "la_data_out[76]" 393 396494 -800 396606 480 m2
+port "la_data_in[76]" 265 395312 -800 395424 480 m2
+port "la_oenb[75]" 520 394130 -800 394242 480 m2
+port "la_data_out[75]" 392 392948 -800 393060 480 m2
+port "la_data_in[75]" 264 391766 -800 391878 480 m2
+port "la_oenb[74]" 519 390584 -800 390696 480 m2
+port "la_data_out[74]" 391 389402 -800 389514 480 m2
+port "la_data_in[74]" 263 388220 -800 388332 480 m2
+port "la_oenb[73]" 518 387038 -800 387150 480 m2
+port "la_data_out[73]" 390 385856 -800 385968 480 m2
+port "la_data_in[73]" 262 384674 -800 384786 480 m2
+port "la_oenb[72]" 517 383492 -800 383604 480 m2
+port "la_data_out[72]" 389 382310 -800 382422 480 m2
+port "la_data_in[72]" 261 381128 -800 381240 480 m2
+port "la_oenb[71]" 516 379946 -800 380058 480 m2
+port "la_data_out[71]" 388 378764 -800 378876 480 m2
+port "la_data_in[71]" 260 377582 -800 377694 480 m2
+port "la_oenb[70]" 515 376400 -800 376512 480 m2
+port "la_data_out[70]" 387 375218 -800 375330 480 m2
+port "la_data_in[70]" 259 374036 -800 374148 480 m2
+port "la_oenb[69]" 513 372854 -800 372966 480 m2
+port "la_data_out[69]" 385 371672 -800 371784 480 m2
+port "la_data_in[69]" 257 370490 -800 370602 480 m2
+port "la_oenb[68]" 512 369308 -800 369420 480 m2
+port "la_data_out[68]" 384 368126 -800 368238 480 m2
+port "la_data_in[68]" 256 366944 -800 367056 480 m2
+port "la_oenb[67]" 511 365762 -800 365874 480 m2
+port "la_data_out[67]" 383 364580 -800 364692 480 m2
+port "la_data_in[67]" 255 363398 -800 363510 480 m2
+port "la_oenb[66]" 510 362216 -800 362328 480 m2
+port "la_data_out[66]" 382 361034 -800 361146 480 m2
+port "la_data_in[66]" 254 359852 -800 359964 480 m2
+port "la_oenb[65]" 509 358670 -800 358782 480 m2
+port "la_data_out[65]" 381 357488 -800 357600 480 m2
+port "la_data_in[65]" 253 356306 -800 356418 480 m2
+port "la_oenb[64]" 508 355124 -800 355236 480 m2
+port "la_data_out[64]" 380 353942 -800 354054 480 m2
+port "la_data_in[64]" 252 352760 -800 352872 480 m2
+port "la_oenb[63]" 507 351578 -800 351690 480 m2
+port "la_data_out[63]" 379 350396 -800 350508 480 m2
+port "la_data_in[63]" 251 349214 -800 349326 480 m2
+port "la_oenb[62]" 506 348032 -800 348144 480 m2
+port "la_data_out[62]" 378 346850 -800 346962 480 m2
+port "la_data_in[62]" 250 345668 -800 345780 480 m2
+port "la_oenb[61]" 505 344486 -800 344598 480 m2
+port "la_data_out[61]" 377 343304 -800 343416 480 m2
+port "la_data_in[61]" 249 342122 -800 342234 480 m2
+port "la_oenb[60]" 504 340940 -800 341052 480 m2
+port "la_data_out[60]" 376 339758 -800 339870 480 m2
+port "la_data_in[60]" 248 338576 -800 338688 480 m2
+port "la_oenb[59]" 502 337394 -800 337506 480 m2
+port "la_data_out[59]" 374 336212 -800 336324 480 m2
+port "la_data_in[59]" 246 335030 -800 335142 480 m2
+port "la_oenb[58]" 501 333848 -800 333960 480 m2
+port "la_data_out[58]" 373 332666 -800 332778 480 m2
+port "la_data_in[58]" 245 331484 -800 331596 480 m2
+port "la_oenb[57]" 500 330302 -800 330414 480 m2
+port "la_data_out[57]" 372 329120 -800 329232 480 m2
+port "la_data_in[57]" 244 327938 -800 328050 480 m2
+port "la_oenb[56]" 499 326756 -800 326868 480 m2
+port "la_data_out[56]" 371 325574 -800 325686 480 m2
+port "la_data_in[56]" 243 324392 -800 324504 480 m2
+port "la_oenb[55]" 498 323210 -800 323322 480 m2
+port "la_data_out[55]" 370 322028 -800 322140 480 m2
+port "la_data_in[55]" 242 320846 -800 320958 480 m2
+port "la_oenb[54]" 497 319664 -800 319776 480 m2
+port "la_data_out[54]" 369 318482 -800 318594 480 m2
+port "la_data_in[54]" 241 317300 -800 317412 480 m2
+port "la_oenb[53]" 496 316118 -800 316230 480 m2
+port "la_data_out[53]" 368 314936 -800 315048 480 m2
+port "la_data_in[53]" 240 313754 -800 313866 480 m2
+port "la_oenb[52]" 495 312572 -800 312684 480 m2
+port "la_data_out[52]" 367 311390 -800 311502 480 m2
+port "la_data_in[52]" 239 310208 -800 310320 480 m2
+port "la_oenb[51]" 494 309026 -800 309138 480 m2
+port "la_data_out[51]" 366 307844 -800 307956 480 m2
+port "la_data_in[51]" 238 306662 -800 306774 480 m2
+port "la_oenb[50]" 493 305480 -800 305592 480 m2
+port "la_data_out[50]" 365 304298 -800 304410 480 m2
+port "la_data_in[50]" 237 303116 -800 303228 480 m2
+port "la_oenb[49]" 491 301934 -800 302046 480 m2
+port "la_data_out[49]" 363 300752 -800 300864 480 m2
+port "la_data_in[49]" 235 299570 -800 299682 480 m2
+port "la_oenb[48]" 490 298388 -800 298500 480 m2
+port "la_data_out[48]" 362 297206 -800 297318 480 m2
+port "la_data_in[48]" 234 296024 -800 296136 480 m2
+port "la_oenb[47]" 489 294842 -800 294954 480 m2
+port "la_data_out[47]" 361 293660 -800 293772 480 m2
+port "la_data_in[47]" 233 292478 -800 292590 480 m2
+port "la_oenb[46]" 488 291296 -800 291408 480 m2
+port "la_data_out[46]" 360 290114 -800 290226 480 m2
+port "la_data_in[46]" 232 288932 -800 289044 480 m2
+port "la_oenb[45]" 487 287750 -800 287862 480 m2
+port "la_data_out[45]" 359 286568 -800 286680 480 m2
+port "la_data_in[45]" 231 285386 -800 285498 480 m2
+port "la_oenb[44]" 486 284204 -800 284316 480 m2
+port "la_data_out[44]" 358 283022 -800 283134 480 m2
+port "la_data_in[44]" 230 281840 -800 281952 480 m2
+port "la_oenb[43]" 485 280658 -800 280770 480 m2
+port "la_data_out[43]" 357 279476 -800 279588 480 m2
+port "la_data_in[43]" 229 278294 -800 278406 480 m2
+port "la_oenb[42]" 484 277112 -800 277224 480 m2
+port "la_data_out[42]" 356 275930 -800 276042 480 m2
+port "la_data_in[42]" 228 274748 -800 274860 480 m2
+port "la_oenb[41]" 483 273566 -800 273678 480 m2
+port "la_data_out[41]" 355 272384 -800 272496 480 m2
+port "la_data_in[41]" 227 271202 -800 271314 480 m2
+port "la_oenb[40]" 482 270020 -800 270132 480 m2
+port "la_data_out[40]" 354 268838 -800 268950 480 m2
+port "la_data_in[40]" 226 267656 -800 267768 480 m2
+port "la_oenb[39]" 480 266474 -800 266586 480 m2
+port "la_data_out[39]" 352 265292 -800 265404 480 m2
+port "la_data_in[39]" 224 264110 -800 264222 480 m2
+port "la_oenb[38]" 479 262928 -800 263040 480 m2
+port "la_data_out[38]" 351 261746 -800 261858 480 m2
+port "la_data_in[38]" 223 260564 -800 260676 480 m2
+port "la_oenb[37]" 478 259382 -800 259494 480 m2
+port "la_data_out[37]" 350 258200 -800 258312 480 m2
+port "la_data_in[37]" 222 257018 -800 257130 480 m2
+port "la_oenb[36]" 477 255836 -800 255948 480 m2
+port "la_data_out[36]" 349 254654 -800 254766 480 m2
+port "la_data_in[36]" 221 253472 -800 253584 480 m2
+port "la_oenb[35]" 476 252290 -800 252402 480 m2
+port "la_data_out[35]" 348 251108 -800 251220 480 m2
+port "la_data_in[35]" 220 249926 -800 250038 480 m2
+port "la_oenb[34]" 475 248744 -800 248856 480 m2
+port "la_data_out[34]" 347 247562 -800 247674 480 m2
+port "la_data_in[34]" 219 246380 -800 246492 480 m2
+port "la_oenb[33]" 474 245198 -800 245310 480 m2
+port "la_data_out[33]" 346 244016 -800 244128 480 m2
+port "la_data_in[33]" 218 242834 -800 242946 480 m2
+port "la_oenb[32]" 473 241652 -800 241764 480 m2
+port "la_data_out[32]" 345 240470 -800 240582 480 m2
+port "la_data_in[32]" 217 239288 -800 239400 480 m2
+port "la_oenb[31]" 472 238106 -800 238218 480 m2
+port "la_data_out[31]" 344 236924 -800 237036 480 m2
+port "la_data_in[31]" 216 235742 -800 235854 480 m2
+port "la_oenb[30]" 471 234560 -800 234672 480 m2
+port "la_data_out[30]" 343 233378 -800 233490 480 m2
+port "la_data_in[30]" 215 232196 -800 232308 480 m2
+port "la_oenb[29]" 469 231014 -800 231126 480 m2
+port "la_data_out[29]" 341 229832 -800 229944 480 m2
+port "la_data_in[29]" 213 228650 -800 228762 480 m2
+port "la_oenb[28]" 468 227468 -800 227580 480 m2
+port "la_data_out[28]" 340 226286 -800 226398 480 m2
+port "la_data_in[28]" 212 225104 -800 225216 480 m2
+port "la_oenb[27]" 467 223922 -800 224034 480 m2
+port "la_data_out[27]" 339 222740 -800 222852 480 m2
+port "la_data_in[27]" 211 221558 -800 221670 480 m2
+port "la_oenb[26]" 466 220376 -800 220488 480 m2
+port "la_data_out[26]" 338 219194 -800 219306 480 m2
+port "la_data_in[26]" 210 218012 -800 218124 480 m2
+port "la_oenb[25]" 465 216830 -800 216942 480 m2
+port "la_data_out[25]" 337 215648 -800 215760 480 m2
+port "la_data_in[25]" 209 214466 -800 214578 480 m2
+port "la_oenb[24]" 464 213284 -800 213396 480 m2
+port "la_data_out[24]" 336 212102 -800 212214 480 m2
+port "la_data_in[24]" 208 210920 -800 211032 480 m2
+port "la_oenb[23]" 463 209738 -800 209850 480 m2
+port "la_data_out[23]" 335 208556 -800 208668 480 m2
+port "la_data_in[23]" 207 207374 -800 207486 480 m2
+port "la_oenb[22]" 462 206192 -800 206304 480 m2
+port "la_data_out[22]" 334 205010 -800 205122 480 m2
+port "la_data_in[22]" 206 203828 -800 203940 480 m2
+port "la_oenb[21]" 461 202646 -800 202758 480 m2
+port "la_data_out[21]" 333 201464 -800 201576 480 m2
+port "la_data_in[21]" 205 200282 -800 200394 480 m2
+port "la_oenb[20]" 460 199100 -800 199212 480 m2
+port "la_data_out[20]" 332 197918 -800 198030 480 m2
+port "la_data_in[20]" 204 196736 -800 196848 480 m2
+port "la_oenb[19]" 458 195554 -800 195666 480 m2
+port "la_data_out[19]" 330 194372 -800 194484 480 m2
+port "la_data_in[19]" 202 193190 -800 193302 480 m2
+port "la_oenb[18]" 457 192008 -800 192120 480 m2
+port "la_data_out[18]" 329 190826 -800 190938 480 m2
+port "la_data_in[18]" 201 189644 -800 189756 480 m2
+port "la_oenb[17]" 456 188462 -800 188574 480 m2
+port "la_data_out[17]" 328 187280 -800 187392 480 m2
+port "la_data_in[17]" 200 186098 -800 186210 480 m2
+port "la_oenb[16]" 455 184916 -800 185028 480 m2
+port "la_data_out[16]" 327 183734 -800 183846 480 m2
+port "la_data_in[16]" 199 182552 -800 182664 480 m2
+port "la_oenb[15]" 454 181370 -800 181482 480 m2
+port "la_data_out[15]" 326 180188 -800 180300 480 m2
+port "la_data_in[15]" 198 179006 -800 179118 480 m2
+port "la_oenb[14]" 453 177824 -800 177936 480 m2
+port "la_data_out[14]" 325 176642 -800 176754 480 m2
+port "la_data_in[14]" 197 175460 -800 175572 480 m2
+port "la_oenb[13]" 452 174278 -800 174390 480 m2
+port "la_data_out[13]" 324 173096 -800 173208 480 m2
+port "la_data_in[13]" 196 171914 -800 172026 480 m2
+port "la_oenb[12]" 451 170732 -800 170844 480 m2
+port "la_data_out[12]" 323 169550 -800 169662 480 m2
+port "la_data_in[12]" 195 168368 -800 168480 480 m2
+port "la_oenb[11]" 442 167186 -800 167298 480 m2
+port "la_data_out[11]" 314 166004 -800 166116 480 m2
+port "la_data_in[11]" 186 164822 -800 164934 480 m2
+port "la_oenb[10]" 431 163640 -800 163752 480 m2
+port "la_data_out[10]" 303 162458 -800 162570 480 m2
+port "la_data_in[10]" 175 161276 -800 161388 480 m2
+port "la_oenb[9]" 547 160094 -800 160206 480 m2
+port "la_data_out[9]" 419 158912 -800 159024 480 m2
+port "la_data_in[9]" 291 157730 -800 157842 480 m2
+port "la_oenb[8]" 536 156548 -800 156660 480 m2
+port "la_data_out[8]" 408 155366 -800 155478 480 m2
+port "la_data_in[8]" 280 154184 -800 154296 480 m2
+port "la_oenb[7]" 525 153002 -800 153114 480 m2
+port "la_data_out[7]" 397 151820 -800 151932 480 m2
+port "la_data_in[7]" 269 150638 -800 150750 480 m2
+port "la_oenb[6]" 514 149456 -800 149568 480 m2
+port "la_data_out[6]" 386 148274 -800 148386 480 m2
+port "la_data_in[6]" 258 147092 -800 147204 480 m2
+port "la_oenb[5]" 503 145910 -800 146022 480 m2
+port "la_data_out[5]" 375 144728 -800 144840 480 m2
+port "la_data_in[5]" 247 143546 -800 143658 480 m2
+port "la_oenb[4]" 492 142364 -800 142476 480 m2
+port "la_data_out[4]" 364 141182 -800 141294 480 m2
+port "la_data_in[4]" 236 140000 -800 140112 480 m2
+port "la_oenb[3]" 481 138818 -800 138930 480 m2
+port "la_data_out[3]" 353 137636 -800 137748 480 m2
+port "la_data_in[3]" 225 136454 -800 136566 480 m2
+port "la_oenb[2]" 470 135272 -800 135384 480 m2
+port "la_data_out[2]" 342 134090 -800 134202 480 m2
+port "la_data_in[2]" 214 132908 -800 133020 480 m2
+port "la_oenb[1]" 459 131726 -800 131838 480 m2
+port "la_data_out[1]" 331 130544 -800 130656 480 m2
+port "la_data_in[1]" 203 129362 -800 129474 480 m2
+port "la_oenb[0]" 420 128180 -800 128292 480 m2
+port "la_data_out[0]" 292 126998 -800 127110 480 m2
+port "la_data_in[0]" 164 125816 -800 125928 480 m2
+port "wbs_dat_o[31]" 664 124634 -800 124746 480 m2
+port "wbs_dat_i[31]" 632 123452 -800 123564 480 m2
+port "wbs_adr_i[31]" 599 122270 -800 122382 480 m2
+port "wbs_dat_o[30]" 663 121088 -800 121200 480 m2
+port "wbs_dat_i[30]" 631 119906 -800 120018 480 m2
+port "wbs_adr_i[30]" 598 118724 -800 118836 480 m2
+port "wbs_dat_o[29]" 661 117542 -800 117654 480 m2
+port "wbs_dat_i[29]" 629 116360 -800 116472 480 m2
+port "wbs_adr_i[29]" 596 115178 -800 115290 480 m2
+port "wbs_dat_o[28]" 660 113996 -800 114108 480 m2
+port "wbs_dat_i[28]" 628 112814 -800 112926 480 m2
+port "wbs_adr_i[28]" 595 111632 -800 111744 480 m2
+port "wbs_dat_o[27]" 659 110450 -800 110562 480 m2
+port "wbs_dat_i[27]" 627 109268 -800 109380 480 m2
+port "wbs_adr_i[27]" 594 108086 -800 108198 480 m2
+port "wbs_dat_o[26]" 658 106904 -800 107016 480 m2
+port "wbs_dat_i[26]" 626 105722 -800 105834 480 m2
+port "wbs_adr_i[26]" 593 104540 -800 104652 480 m2
+port "wbs_dat_o[25]" 657 103358 -800 103470 480 m2
+port "wbs_dat_i[25]" 625 102176 -800 102288 480 m2
+port "wbs_adr_i[25]" 592 100994 -800 101106 480 m2
+port "wbs_dat_o[24]" 656 99812 -800 99924 480 m2
+port "wbs_dat_i[24]" 624 98630 -800 98742 480 m2
+port "wbs_adr_i[24]" 591 97448 -800 97560 480 m2
+port "wbs_dat_o[23]" 655 96266 -800 96378 480 m2
+port "wbs_dat_i[23]" 623 95084 -800 95196 480 m2
+port "wbs_adr_i[23]" 590 93902 -800 94014 480 m2
+port "wbs_dat_o[22]" 654 92720 -800 92832 480 m2
+port "wbs_dat_i[22]" 622 91538 -800 91650 480 m2
+port "wbs_adr_i[22]" 589 90356 -800 90468 480 m2
+port "wbs_dat_o[21]" 653 89174 -800 89286 480 m2
+port "wbs_dat_i[21]" 621 87992 -800 88104 480 m2
+port "wbs_adr_i[21]" 588 86810 -800 86922 480 m2
+port "wbs_dat_o[20]" 652 85628 -800 85740 480 m2
+port "wbs_dat_i[20]" 620 84446 -800 84558 480 m2
+port "wbs_adr_i[20]" 587 83264 -800 83376 480 m2
+port "wbs_dat_o[19]" 650 82082 -800 82194 480 m2
+port "wbs_dat_i[19]" 618 80900 -800 81012 480 m2
+port "wbs_adr_i[19]" 585 79718 -800 79830 480 m2
+port "wbs_dat_o[18]" 649 78536 -800 78648 480 m2
+port "wbs_dat_i[18]" 617 77354 -800 77466 480 m2
+port "wbs_adr_i[18]" 584 76172 -800 76284 480 m2
+port "wbs_dat_o[17]" 648 74990 -800 75102 480 m2
+port "wbs_dat_i[17]" 616 73808 -800 73920 480 m2
+port "wbs_adr_i[17]" 583 72626 -800 72738 480 m2
+port "wbs_dat_o[16]" 647 71444 -800 71556 480 m2
+port "wbs_dat_i[16]" 615 70262 -800 70374 480 m2
+port "wbs_adr_i[16]" 582 69080 -800 69192 480 m2
+port "wbs_dat_o[15]" 646 67898 -800 68010 480 m2
+port "wbs_dat_i[15]" 614 66716 -800 66828 480 m2
+port "wbs_adr_i[15]" 581 65534 -800 65646 480 m2
+port "wbs_dat_o[14]" 645 64352 -800 64464 480 m2
+port "wbs_dat_i[14]" 613 63170 -800 63282 480 m2
+port "wbs_adr_i[14]" 580 61988 -800 62100 480 m2
+port "wbs_dat_o[13]" 644 60806 -800 60918 480 m2
+port "wbs_dat_i[13]" 612 59624 -800 59736 480 m2
+port "wbs_adr_i[13]" 579 58442 -800 58554 480 m2
+port "wbs_dat_o[12]" 643 57260 -800 57372 480 m2
+port "wbs_dat_i[12]" 611 56078 -800 56190 480 m2
+port "wbs_adr_i[12]" 578 54896 -800 55008 480 m2
+port "wbs_dat_o[11]" 642 53714 -800 53826 480 m2
+port "wbs_dat_i[11]" 610 52532 -800 52644 480 m2
+port "wbs_adr_i[11]" 577 51350 -800 51462 480 m2
+port "wbs_dat_o[10]" 641 50168 -800 50280 480 m2
+port "wbs_dat_i[10]" 609 48986 -800 49098 480 m2
+port "wbs_adr_i[10]" 576 47804 -800 47916 480 m2
+port "wbs_dat_o[9]" 671 46622 -800 46734 480 m2
+port "wbs_dat_i[9]" 639 45440 -800 45552 480 m2
+port "wbs_adr_i[9]" 606 44258 -800 44370 480 m2
+port "wbs_dat_o[8]" 670 43076 -800 43188 480 m2
+port "wbs_dat_i[8]" 638 41894 -800 42006 480 m2
+port "wbs_adr_i[8]" 605 40712 -800 40824 480 m2
+port "wbs_dat_o[7]" 669 39530 -800 39642 480 m2
+port "wbs_dat_i[7]" 637 38348 -800 38460 480 m2
+port "wbs_adr_i[7]" 604 37166 -800 37278 480 m2
+port "wbs_dat_o[6]" 668 35984 -800 36096 480 m2
+port "wbs_dat_i[6]" 636 34802 -800 34914 480 m2
+port "wbs_adr_i[6]" 603 33620 -800 33732 480 m2
+port "wbs_dat_o[5]" 667 32438 -800 32550 480 m2
+port "wbs_dat_i[5]" 635 31256 -800 31368 480 m2
+port "wbs_adr_i[5]" 602 30074 -800 30186 480 m2
+port "wbs_dat_o[4]" 666 28892 -800 29004 480 m2
+port "wbs_dat_i[4]" 634 27710 -800 27822 480 m2
+port "wbs_adr_i[4]" 601 26528 -800 26640 480 m2
+port "wbs_sel_i[3]" 675 25346 -800 25458 480 m2
+port "wbs_dat_o[3]" 665 24164 -800 24276 480 m2
+port "wbs_dat_i[3]" 633 22982 -800 23094 480 m2
+port "wbs_adr_i[3]" 600 21800 -800 21912 480 m2
+port "wbs_sel_i[2]" 674 20618 -800 20730 480 m2
+port "wbs_dat_o[2]" 662 19436 -800 19548 480 m2
+port "wbs_dat_i[2]" 630 18254 -800 18366 480 m2
+port "wbs_adr_i[2]" 597 17072 -800 17184 480 m2
+port "wbs_sel_i[1]" 673 15890 -800 16002 480 m2
+port "wbs_dat_o[1]" 651 14708 -800 14820 480 m2
+port "wbs_dat_i[1]" 619 13526 -800 13638 480 m2
+port "wbs_adr_i[1]" 586 12344 -800 12456 480 m2
+port "wbs_sel_i[0]" 672 11162 -800 11274 480 m2
+port "wbs_dat_o[0]" 640 9980 -800 10092 480 m2
+port "wbs_dat_i[0]" 608 8798 -800 8910 480 m2
+port "wbs_adr_i[0]" 575 7616 -800 7728 480 m2
+port "wbs_we_i" 677 6434 -800 6546 480 m2
+port "wbs_stb_i" 676 5252 -800 5364 480 m2
+port "wbs_cyc_i" 607 4070 -800 4182 480 m2
+port "wbs_ack_o" 574 2888 -800 3000 480 m2
+port "wb_rst_i" 573 1706 -800 1818 480 m2
+port "wb_clk_i" 572 524 -800 636 480 m2
+port "io_analog[6]" 49 165594 702300 170594 704800 m5
+port "io_analog[6]" 43 175894 702300 180894 704800 m5
+port "io_analog[5]" 48 217294 702300 222294 704800 m5
+port "io_analog[5]" 42 227594 702300 232594 704800 m5
+port "io_analog[7]" 44 120194 702300 125194 704800 m3
+port "io_analog[0]" 36 582300 677984 584800 682984 m3
+port "io_analog[1]" 38 566594 702300 571594 704800 m3
+port "io_analog[3]" 40 413394 702300 418394 704800 m3
+port "io_analog[2]" 39 465394 702300 470394 704800 m3
+port "io_analog[8]" 45 68194 702300 73194 704800 m3
+port "vccd1" 553 582340 629784 584800 634584 m3
+port "vccd1" 552 582340 639784 584800 644584 m3
+port "io_clamp_high[2]" 52 173394 702300 175594 704800 m3
+port "io_clamp_high[1]" 51 225094 702300 227294 704800 m3
+port "vssa1" 563 510594 702340 515394 704800 m3
+port "vssa1" 562 520594 702340 525394 704800 m3
+port "io_clamp_low[2]" 55 170894 702300 173094 704800 m3
+port "io_clamp_low[1]" 54 222594 702300 224794 704800 m3
+node "VGND" 0 0 448448 591294 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "io_analog[4]" 0 2925 329294 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[4]" 0 2925 318994 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "m4_141154_541976#" 0 136634 141154 541976 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64946256 32764 0 0 0 0
+node "io_analog[4]" 0 2775 329294 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
+node "io_analog[4]" 0 2775 318994 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
+node "io_analog[5]" 0 123171 227594 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 379159248 156980 0 0 0 0
+node "m4_165510_677212#" 0 110872 165510 677212 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 365806656 152224 0 0 0 0
+node "io_in_3v3[0]" 1 613.728 583520 1544 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_oeb[26]" 1 613.728 -800 1544 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[0]" 1 613.728 583520 2726 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_out[26]" 1 613.728 -800 2726 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_out[0]" 1 613.728 583520 3908 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[26]" 1 613.728 -800 3908 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_oeb[0]" 1 613.728 583520 5090 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in_3v3[26]" 1 613.728 -800 5090 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in_3v3[1]" 1 613.728 583520 6272 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_oeb[25]" 1 613.728 -800 6272 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[1]" 1 613.728 583520 7454 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_out[25]" 1 613.728 -800 7454 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_out[1]" 1 613.728 583520 8636 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[25]" 1 613.728 -800 8636 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_oeb[1]" 1 613.728 583520 9818 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in_3v3[25]" 1 613.728 -800 9818 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in_3v3[2]" 1 613.728 583520 11000 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_oeb[24]" 1 613.728 -800 11000 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[2]" 1 613.728 583520 12182 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
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+node "io_out[2]" 1 613.728 583520 13364 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[24]" 1 613.728 -800 13364 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_oeb[2]" 1 613.728 583520 14546 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in_3v3[24]" 1 613.728 -800 14546 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in_3v3[3]" 1 613.728 583520 15728 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "gpio_noesd[17]" 1 613.728 -800 15728 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[3]" 1 613.728 583520 16910 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "gpio_analog[17]" 1 613.728 -800 16910 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_out[3]" 1 613.728 583520 18092 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
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+node "io_in_3v3[4]" 1 613.728 583520 20456 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[4]" 1 613.728 583520 21638 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_out[4]" 1 613.728 583520 22820 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_oeb[4]" 1 613.728 583520 24002 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_oeb[23]" 1 613.728 -800 32422 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_out[23]" 1 613.728 -800 33604 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[23]" 1 613.728 -800 34786 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in_3v3[23]" 1 613.728 -800 35968 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "gpio_noesd[16]" 1 613.728 -800 37150 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "gpio_analog[16]" 1 613.728 -800 38332 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in_3v3[5]" 1 613.728 583520 46914 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[5]" 1 613.728 583520 48096 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_out[5]" 1 613.728 583520 49278 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
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+node "io_oeb[22]" 1 613.728 -800 75644 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_out[22]" 1 613.728 -800 76826 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[22]" 1 613.728 -800 78008 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
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+node "gpio_noesd[15]" 1 613.728 -800 80372 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "gpio_analog[15]" 1 613.728 -800 81554 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in_3v3[6]" 1 613.728 583520 91572 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[6]" 1 613.728 583520 92754 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_out[6]" 1 613.728 583520 93936 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
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+node "io_oeb[21]" 1 613.728 -800 118866 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_out[21]" 1 613.728 -800 120048 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[21]" 1 613.728 -800 121230 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
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+equiv "VDD" "vccd1"
+equiv "VDD" "io_clamp_high[2]"
+equiv "VDD" "io_clamp_high[1]"
+node "w_415106_686340#" 37235 1263.75 415106 686340 nw 0 0 0 0 429724 6380 0 0 11656 500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16784 808 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "GND" 0 0 67344 687068 pw 565504 6816 0 0 0 0 0 0 0 0 138176 8128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22244276 58620 46505336 81996 13104640 41468 492659612 334300 626217612 338864 10667706496 3141104 0 0
+equiv "GND" "vssa1"
+equiv "GND" "io_clamp_low[2]"
+equiv "GND" "io_clamp_low[1]"
+cap "CLK" "w_70778_673802#" 80.5226
+cap "m4_165510_677212#" "io_analog[6]" 27348.2
+cap "VDD" "io_analog[6]" 832.378
+cap "VDD" "io_analog[5]" 525
+cap "CLKBAR" "VDD" 209.423
+cap "Vn" "io_analog[6]" 715.12
+cap "li_122514_671986#" "Vp" 75646.4
+cap "io_analog[4]" "io_analog[4]" 26250
+cap "w_408706_587622#" "VDD" 97.5825
+cap "L1" "w_415106_686340#" 21.7895
+cap "io_analog[5]" "io_analog[5]" 27459.6
+cap "li_408616_585444#" "VDD" 11.5413
+cap "Outn" "w_415106_686340#" 81.9456
+cap "li_408624_587536#" "Vp" 3070.78
+cap "li_440216_589824#" "VDD" 8992.53
+cap "li_408616_585444#" "Vn" 534.831
+cap "w_408694_585520#" "li_408616_585444#" 119.086
+cap "li_569558_688285#" "Iin" 6.13115
+cap "w_122758_673528#" "CLKBAR" 89.216
+cap "m4_165510_677212#" "VDD" 30182.1
+cap "L2" "li_448544_589824#" 7.61538
+cap "io_analog[4]" "io_analog[4]" 26250
+cap "Outn" "li_415508_688595#" 11.6471
+cap "li_122514_671986#" "CLKBAR" 7.7
+cap "io_analog[5]" "io_analog[5]" 27466.5
+cap "m4_165510_677212#" "Vn" 623011
+cap "Vn" "VDD" 522669
+cap "VDD" "io_analog[5]" 27239.7
+cap "L2" "VDD" 66349.8
+cap "CLK" "VDD" 1215
+cap "w_408694_585520#" "VDD" 63.3697
+cap "li_408624_587536#" "w_408706_587622#" 148.376
+cap "io_analog[4]" "io_clamp_low[0]" 525
+cap "Vp" "io_analog[5]" 787.64
+cap "w_408706_587622#" "Vp" 161.518
+cap "li_440216_589824#" "L1" 7.61538
+cap "li_408616_585444#" "Vp" 221.824
+cap "io_analog[4]" "io_analog[4]" 21250
+cap "li_122514_671986#" "li_122782_673260#" 17.0116
+cap "li_122514_671986#" "VDD" 130902
+cap "io_analog[0]" "VDD" 115675
+cap "io_analog[4]" "io_clamp_high[0]" 525
+cap "io_analog[4]" "io_analog[4]" 21250
+cap "L2" "w_466974_686458#" 36.8428
+cap "li_440216_589824#" "w_440058_591014#" 119.695
+cap "li_122514_671986#" "Vn" 1462.39
+cap "li_408624_587536#" "VDD" 23.0057
+cap "w_415106_686340#" "VDD" 516.95
+cap "li_73093_686955#" "VDD" 646.398
+cap "L1" "VDD" 66349.8
+cap "io_analog[5]" "Vp" 792.12
+cap "Outn" "VDD" 35146.4
+cap "Vp" "VDD" 544023
+cap "m4_165510_677212#" "io_analog[6]" 115952
+cap "li_73093_686955#" "CLK" 419.101
+cap "VDD" "w_440058_591014#" 222.609
+cap "Vp" "io_analog[5]" 645879
+cap "io_analog[6]" "Vn" 1013.88
+cap "li_70526_671944#" "VDD" 4197.46
+cap "li_448544_589824#" "w_448410_591030#" 52.0925
+cap "io_clamp_low[0]" "io_clamp_high[0]" 525
+cap "li_70526_671944#" "Vn" 1462.39
+cap "li_569558_688285#" "w_569596_688404#" 149.685
+cap "VDD" "w_448410_591030#" 208.239
+cap "li_70526_671944#" "CLK" 8.3494
+cap "VDD" "w_569596_688404#" 7.26786
+device pdiode sky130_fd_pr__diode_pd2nw_05v5 73333 687195 73334 687196 a=40000 p=800 "VDD" "CLK" 352 0 "VDD" 128 0
+device ndiode sky130_fd_pr__diode_pw2nd_05v5 67482 687206 67483 687207 a=40000 p=800 "GND" "CLK" 352 0 "GND" 128 0
+cap "Vn" "comparator_v6_0/GND" 0.368431
+cap "comparator_v6_0/GND" "comparator_v6_0/GND" 18.88
+cap "comparator_v6_0/GND" "comparator_v6_0/GND" 56
+cap "Vn" "comparator_v6_0/GND" 6.79235
+cap "sky130_fd_sc_hd__buf_16_3/VPWR" "sky130_fd_sc_hd__buf_16_3/A" 2.07235
+cap "sky130_fd_sc_hd__buf_16_3/VPWR" "sky130_fd_sc_hd__buf_16_3/X" 41.0217
+cap "sky130_fd_sc_hd__buf_16_3/A" "sky130_fd_sc_hd__buf_16_3/VGND" 42.7374
+cap "sky130_fd_sc_hd__buf_16_3/X" "sky130_fd_sc_hd__buf_16_3/VGND" 89.7633
+cap "sky130_fd_sc_hd__buf_16_3/a_109_47#" "sky130_fd_sc_hd__buf_16_3/VPWR" 25.5145
+cap "sky130_fd_sc_hd__buf_16_3/a_109_47#" "sky130_fd_sc_hd__buf_16_3/VGND" 121.607
+cap "sky130_fd_sc_hd__buf_16_3/X" "sky130_fd_sc_hd__buf_16_3/VPWR" 80.0331
+cap "sky130_fd_sc_hd__buf_16_3/VPWR" "sky130_fd_sc_hd__buf_16_3/a_109_47#" -4.125
+cap "sky130_fd_sc_hd__buf_16_3/X" "sky130_fd_sc_hd__buf_16_3/VGND" 76.1998
+cap "sky130_fd_sc_hd__buf_16_3/a_109_47#" "sky130_fd_sc_hd__buf_16_3/VGND" 44.3359
+cap "comparator_v6_0/CLK" "comparator_v6_0/Vn" 1295.87
+cap "comparator_v6_0/preamp_part12_0/a_80_n658#" "comparator_v6_0/Vn" 334.65
+cap "comparator_v6_0/Dp" "comparator_v6_0/Outp" 416.18
+cap "comparator_v6_0/Outn" "comparator_v6_0/Dn" 32.552
+cap "comparator_v6_0/Outn" "comparator_v6_0/SR_latch_0/GND" 134.887
+cap "comparator_v6_0/Outp" "comparator_v6_0/SR_latch_0/VDD" 76.7922
+cap "comparator_v6_0/Outn" "comparator_v6_0/SR_latch_0/VDD" 8.67188
+cap "comparator_v6_0/SR_latch_0/GND" "comparator_v6_0/Outp" 4.29936
+cap "sky130_fd_sc_hd__buf_16_3/X" "sky130_fd_sc_hd__buf_16_3/VPWR" 41.0217
+cap "sky130_fd_sc_hd__buf_16_2/VGND" "sky130_fd_sc_hd__buf_16_2/X" 40.4144
+cap "sky130_fd_sc_hd__buf_16_3/VPWR" "sky130_fd_sc_hd__buf_16_3/VPB" 0.8876
+cap "sky130_fd_sc_hd__buf_16_3/a_109_47#" "sky130_fd_sc_hd__buf_16_3/VPWR" 25.5145
+cap "sky130_fd_sc_hd__buf_16_3/A" "sky130_fd_sc_hd__buf_16_3/VPWR" 0.97495
+cap "sky130_fd_sc_hd__buf_16_2/VGND" "sky130_fd_sc_hd__buf_16_2/a_109_47#" 25.548
+cap "sky130_fd_sc_hd__buf_16_2/VGND" "sky130_fd_sc_hd__buf_16_2/X" 33.6443
+cap "sky130_fd_sc_hd__buf_16_3/X" "sky130_fd_sc_hd__buf_16_3/VPWR" 19.9896
+cap "comparator_v6_0/CLK" "comparator_v6_0/Vp" 792.396
+cap "comparator_v6_0/CLK" "li_408624_587536#" 3.18987
+cap "comparator_v6_0/CLK" "comparator_v6_0/Vp" 522.139
+cap "li_408624_587536#" "comparator_v6_0/CLK" 61.2057
+cap "comparator_v6_0/CLK" "comparator_v6_0/CLKBAR" 4.78481
+cap "comparator_v6_0/Outn" "comparator_v6_0/SR_latch_0/GND" 10.9087
+cap "comparator_v6_0/SR_latch_0/VDD" "comparator_v6_0/Outn" 242.649
+cap "comparator_v6_0/Dn" "comparator_v6_0/Outn" 257.721
+cap "Vp" "sky130_fd_sc_hd__buf_16_2/A" 0.32
+cap "sky130_fd_sc_hd__buf_16_2/VPWR" "sky130_fd_sc_hd__buf_16_2/a_109_47#" 55.8092
+cap "sky130_fd_sc_hd__buf_16_2/VGND" "Vp" 785.081
+cap "sky130_fd_sc_hd__buf_16_2/X" "Vp" 137.559
+cap "sky130_fd_sc_hd__buf_16_2/VPWR" "Vp" 835.704
+cap "sky130_fd_sc_hd__buf_16_2/X" "Vp" 105.991
+cap "sky130_fd_sc_hd__buf_16_2/X" "sky130_fd_sc_hd__buf_16_2/VGND" 40.4144
+cap "sky130_fd_sc_hd__buf_16_2/VPB" "Vp" 275.516
+cap "sky130_fd_sc_hd__buf_16_2/X" "sky130_fd_sc_hd__buf_16_2/VPWR" 88.865
+cap "sky130_fd_sc_hd__buf_16_2/A" "Vp" 31.2338
+cap "sky130_fd_sc_hd__buf_16_2/VPB" "sky130_fd_sc_hd__buf_16_2/VPWR" 0.4516
+cap "sky130_fd_sc_hd__buf_16_2/VGND" "sky130_fd_sc_hd__buf_16_2/A" 2.8191
+cap "sky130_fd_sc_hd__buf_16_2/a_109_47#" "Vp" 360.782
+cap "sky130_fd_sc_hd__buf_16_2/VNB" "Vp" 9.9804
+cap "sky130_fd_sc_hd__buf_16_2/VGND" "sky130_fd_sc_hd__buf_16_2/a_109_47#" 25.548
+cap "sky130_fd_sc_hd__buf_16_2/VPWR" "sky130_fd_sc_hd__buf_16_2/A" 2.05495
+cap "sky130_fd_sc_hd__buf_16_2/VNB" "Vp" -154.743
+cap "sky130_fd_sc_hd__buf_16_2/X" "sky130_fd_sc_hd__buf_16_2/VPWR" 123.49
+cap "Vp" "sky130_fd_sc_hd__buf_16_2/X" -1084.42
+cap "Vp" "sky130_fd_sc_hd__buf_16_2/VPWR" 114.093
+cap "sky130_fd_sc_hd__buf_16_2/X" "sky130_fd_sc_hd__buf_16_2/a_109_47#" -104.885
+cap "sky130_fd_sc_hd__buf_16_2/VPWR" "sky130_fd_sc_hd__buf_16_2/a_109_47#" -1.375
+cap "Vp" "sky130_fd_sc_hd__buf_16_2/a_109_47#" -787.061
+cap "sky130_fd_sc_hd__buf_16_2/VGND" "sky130_fd_sc_hd__buf_16_2/X" 37.1288
+cap "sky130_fd_sc_hd__buf_16_2/VNB" "sky130_fd_sc_hd__buf_16_2/X" -164.41
+cap "sky130_fd_sc_hd__buf_16_2/VGND" "Vp" 116.101
+cap "li_408624_587536#" "comparator_v6_0/CLK" 274.582
+cap "comparator_v6_0/CLK" "li_408624_587536#" 795.539
+cap "comparator_v6_0/CLK" "li_408624_587536#" 801.818
+cap "comparator_v6_0/VDD" "li_408624_587536#" 208.476
+cap "comparator_v6_0/VDD" "comparator_v6_0/CLKBAR" 12.6
+cap "comparator_v6_0/CLKBAR" "comparator_v6_0/CLK" 27.4909
+cap "comparator_v6_0/VDD" "comparator_v6_0/VDD" 13.2
+cap "comparator_v6_0/VDD" "comparator_v6_0/VDD" 29.04
+cap "comparator_v6_0/VDD" "comparator_v6_0/VDD" 70.1
+cap "comparator_v6_0/VDD" "comparator_v6_0/VDD" 154.22
+cap "sky130_fd_sc_hd__buf_2_0/VPWR" "sky130_fd_sc_hd__buf_2_0/a_27_47#" 9.77095
+cap "sky130_fd_sc_hd__buf_2_0/VPWR" "sky130_fd_sc_hd__buf_2_0/X" 2.45646
+cap "sky130_fd_sc_hd__buf_2_0/VPWR" "sky130_fd_sc_hd__buf_2_0/A" -2.36455
+cap "sky130_fd_sc_hd__buf_2_0/VGND" "sky130_fd_sc_hd__buf_2_0/A" 3.09945
+cap "sky130_fd_sc_hd__buf_2_0/VPWR" "sky130_fd_sc_hd__buf_2_0/X" 4.17135
+cap "sky130_fd_sc_hd__buf_2_0/VPWR" "sky130_fd_sc_hd__buf_2_0/A" -2.08797
+cap "sky130_fd_sc_hd__buf_2_0/A" "sky130_fd_sc_hd__buf_2_0/X" -3.69695
+cap "sky130_fd_sc_hd__buf_2_0/VPWR" "sky130_fd_sc_hd__buf_2_0/a_27_47#" 16.5922
+cap "sky130_fd_sc_hd__buf_2_0/A" "sky130_fd_sc_hd__buf_2_0/a_27_47#" 1.43638
+cap "VGND" "sky130_fd_sc_hd__buf_2_1/a_27_47#" 17.8525
+cap "VGND" "sky130_fd_sc_hd__buf_2_1/A" -1.27009
+cap "VGND" "sky130_fd_sc_hd__buf_2_1/X" 4.5375
+cap "sky130_fd_sc_hd__buf_2_1/VGND" "sky130_fd_sc_hd__buf_2_1/A" 2.90674
+cap "VGND" "sky130_fd_sc_hd__buf_2_1/a_27_47#" 11.1803
+cap "VGND" "sky130_fd_sc_hd__buf_2_1/A" -1.27009
+cap "sky130_fd_sc_hd__buf_2_1/A" "sky130_fd_sc_hd__buf_2_1/X" -3.80769
+cap "VGND" "sky130_fd_sc_hd__buf_2_1/X" 2.84167
+cap "sky130_fd_sc_hd__buf_2_0/a_27_47#" "sky130_fd_sc_hd__buf_2_0/VPWR" -2.84217e-14
+cap "sky130_fd_sc_hd__buf_2_0/X" "sky130_fd_sc_hd__buf_2_0/VPWR" 7.29753
+cap "sky130_fd_sc_hd__buf_2_0/VPWR" "sky130_fd_sc_hd__buf_2_0/A" 1.77636e-15
+cap "sky130_fd_sc_hd__buf_2_0/A" "sky130_fd_sc_hd__buf_2_0/X" -3.69695
+cap "sky130_fd_sc_hd__buf_2_0/a_27_47#" "sky130_fd_sc_hd__buf_2_0/VPWR" 1.42109e-14
+cap "sky130_fd_sc_hd__buf_2_0/VGND" "sky130_fd_sc_hd__buf_2_0/X" 58.4558
+cap "sky130_fd_sc_hd__buf_2_0/A" "sky130_fd_sc_hd__buf_2_0/a_27_47#" 0.257812
+cap "sky130_fd_sc_hd__buf_2_0/VPWR" "sky130_fd_sc_hd__buf_2_0/X" 49.2519
+cap "sky130_fd_sc_hd__buf_2_0/a_27_47#" "sky130_fd_sc_hd__buf_2_0/X" 10.255
+cap "sky130_fd_sc_hd__buf_2_1/X" "VGND" 9.97225
+cap "sky130_fd_sc_hd__buf_2_1/a_27_47#" "VGND" -5.68434e-14
+cap "sky130_fd_sc_hd__buf_2_1/X" "sky130_fd_sc_hd__buf_2_1/a_27_47#" 10.1025
+cap "sky130_fd_sc_hd__buf_2_1/a_27_47#" "VGND" 1.42109e-14
+cap "sky130_fd_sc_hd__buf_2_1/X" "VGND" 50.0926
+cap "sky130_fd_sc_hd__buf_2_1/X" "sky130_fd_sc_hd__buf_2_1/A" -3.80769
+cap "sky130_fd_sc_hd__buf_2_1/X" "sky130_fd_sc_hd__buf_2_1/VGND" 57.7722
+cap "sky130_fd_sc_hd__buf_2_2/VGND" "sky130_fd_sc_hd__buf_2_2/X" 6.49171
+cap "sky130_fd_sc_hd__buf_2_2/VGND" "sky130_fd_sc_hd__buf_2_2/A" 1.51622
+cap "sky130_fd_sc_hd__buf_2_2/A" "sky130_fd_sc_hd__buf_2_2/X" -8.3494
+cap "sky130_fd_sc_hd__buf_2_2/a_27_47#" "sky130_fd_sc_hd__buf_2_2/VPWR" 50.7913
+cap "sky130_fd_sc_hd__buf_2_2/VGND" "sky130_fd_sc_hd__buf_2_2/X" 56.3969
+cap "sky130_fd_sc_hd__buf_2_2/A" "sky130_fd_sc_hd__buf_2_2/VPWR" 7.83918
+cap "sky130_fd_sc_hd__buf_2_2/X" "sky130_fd_sc_hd__buf_2_2/a_27_47#" 9.7975
+cap "sky130_fd_sc_hd__buf_2_2/A" "sky130_fd_sc_hd__buf_2_2/VGND" 1.51622
+cap "sky130_fd_sc_hd__buf_2_2/X" "sky130_fd_sc_hd__buf_2_2/VPWR" 104.851
+cap "sky130_fd_sc_hd__buf_2_3/VGND" "sky130_fd_sc_hd__buf_2_3/X" -91.02
+cap "sky130_fd_sc_hd__buf_2_3/VGND" "sky130_fd_sc_hd__buf_2_3/VNB" -606.8
+cap "sky130_fd_sc_hd__buf_2_3/VGND" "sky130_fd_sc_hd__buf_2_3/a_27_47#" -160.58
+cap "sky130_fd_sc_hd__buf_2_3/VGND" "sky130_fd_sc_hd__buf_2_3/A" -34.78
+cap "sky130_fd_sc_hd__buf_2_3/X" "sky130_fd_sc_hd__buf_2_3/VGND" 61.0651
+cap "sky130_fd_sc_hd__buf_2_3/VPWR" "sky130_fd_sc_hd__buf_2_3/X" 103.043
+cap "sky130_fd_sc_hd__buf_2_3/A" "sky130_fd_sc_hd__buf_2_3/a_27_47#" 0.803934
+cap "sky130_fd_sc_hd__buf_2_3/A" "sky130_fd_sc_hd__buf_2_3/VGND" 3.16993
+cap "sky130_fd_sc_hd__buf_2_3/A" "sky130_fd_sc_hd__buf_2_3/VPWR" 1.66384
+cap "sky130_fd_sc_hd__buf_2_3/A" "sky130_fd_sc_hd__buf_2_3/X" -7.51356
+cap "sky130_fd_sc_hd__buf_2_3/VPWR" "sky130_fd_sc_hd__buf_2_3/a_27_47#" 46.2
+cap "sky130_fd_sc_hd__buf_2_3/X" "sky130_fd_sc_hd__buf_2_3/a_27_47#" 17.3874
+cap "sky130_fd_sc_hd__buf_16_0/VGND" "sky130_fd_sc_hd__buf_16_0/A" 22.5281
+cap "sky130_fd_sc_hd__buf_16_0/a_109_47#" "sky130_fd_sc_hd__buf_16_0/VPB" 6.40588
+cap "sky130_fd_sc_hd__buf_16_0/a_109_47#" "sky130_fd_sc_hd__buf_16_0/A" 15.6479
+cap "sky130_fd_sc_hd__buf_16_1/a_109_47#" "sky130_fd_sc_hd__buf_16_1/VPB" 19.0207
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/X" -79.13
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/VGND" -79.13
+cap "GND" "sky130_fd_sc_hd__buf_16_4/VGND" 11.287
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/a_109_47#" -90.71
+cap "sky130_fd_sc_hd__buf_16_4/VNB" "sky130_fd_sc_hd__buf_16_4/VGND" -316.52
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "GND" 11.287
+cap "sky130_fd_sc_hd__buf_16_4/VPB" "sky130_fd_sc_hd__buf_16_4/VPWR" 0.578
+cap "sky130_fd_sc_hd__buf_16_4/X" "VDD" 10.4976
+cap "sky130_fd_sc_hd__buf_16_4/X" "sky130_fd_sc_hd__buf_16_4/VPWR" 2.14943
+cap "sky130_fd_sc_hd__buf_16_4/VPB" "sky130_fd_sc_hd__buf_16_4/X" 10.5044
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/X" 3.4
+cap "VDD" "sky130_fd_sc_hd__buf_16_4/VPWR" 27.1359
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/a_109_47#" -59.22
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/a_109_47#" -59.22
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/a_109_47#" -103.32
+cap "VDD" "sky130_fd_sc_hd__buf_16_0/a_109_47#" 3.42941
+cap "VDD" "sky130_fd_sc_hd__buf_16_0/X" 4.27059
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/X" -103.32
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/a_109_47#" -59.22
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/a_109_47#" -59.22
+cap "VDD" "sky130_fd_sc_hd__buf_16_0/X" 4.27059
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/X" -154.98
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/a_109_47#" -59.22
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/a_109_47#" -59.22
+cap "VDD" "sky130_fd_sc_hd__buf_16_0/a_109_47#" 4.27059
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/a_109_47#" -103.32
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/A" -59.22
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/a_109_47#" -59.22
+cap "VDD" "sky130_fd_sc_hd__buf_16_0/X" 4.27059
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/A" -59.22
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/X" -103.32
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/a_109_47#" -59.22
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "VDD" -180.876
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/A" -59.22
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/X" -154.98
+cap "VDD" "sky130_fd_sc_hd__buf_16_0/X" 4.27059
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/X" -103.32
+cap "VDD" "sky130_fd_sc_hd__buf_16_0/X" 3.68824
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/a_109_47#" 6.40588
+cap "sky130_fd_sc_hd__buf_16_0/A" "sky130_fd_sc_hd__buf_16_0/a_109_47#" 33.3896
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/A" 0.127938
+cap "GND" "sky130_fd_sc_hd__buf_16_0/VGND" 130.528
+cap "sky130_fd_sc_hd__buf_16_0/VGND" "sky130_fd_sc_hd__buf_16_0/a_109_47#" 0.4243
+cap "sky130_fd_sc_hd__buf_16_0/VGND" "sky130_fd_sc_hd__buf_16_0/A" 53.6071
+cap "GND" "sky130_fd_sc_hd__buf_16_0/X" 31.3744
+cap "GND" "sky130_fd_sc_hd__buf_16_0/a_109_47#" 12.7899
+cap "VDD" "sky130_fd_sc_hd__buf_16_0/X" 94.3613
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/X" 3.86535e-12
+cap "VDD" "sky130_fd_sc_hd__buf_16_0/a_109_47#" 36.7143
+cap "sky130_fd_sc_hd__buf_16_0/VGND" "sky130_fd_sc_hd__buf_16_0/VNB" 1.2625
+cap "VDD" "sky130_fd_sc_hd__buf_16_0/VPB" -2356.72
+cap "sky130_fd_sc_hd__buf_16_1/A" "sky130_fd_sc_hd__buf_16_1/VPB" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/A" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/a_109_47#" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/a_109_47#" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/X" -106.6
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/a_109_47#" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/a_109_47#" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/X" "sky130_fd_sc_hd__buf_16_1/VPB" -159.9
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/X" -159.9
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/A" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/a_109_47#" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/a_109_47#" -106.6
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/a_109_47#" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/A" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/a_109_47#" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/a_109_47#" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/a_109_47#" -106.6
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/X" -106.6
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/X" -106.6
+cap "sky130_fd_sc_hd__buf_16_1/VGND" "sky130_fd_sc_hd__buf_16_1/A" 2.85533
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/X" 3.18323e-12
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/A" 0.126957
+cap "sky130_fd_sc_hd__buf_16_1/a_109_47#" "sky130_fd_sc_hd__buf_16_1/VPB" 19.0207
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/VGND" -79.13
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/VGND" -79.13
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/a_109_47#" -90.71
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/a_109_47#" -79.13
+cap "sky130_fd_sc_hd__buf_16_4/A" "sky130_fd_sc_hd__buf_16_4/VGND" -90.71
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/X" -79.13
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/X" -79.13
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/a_109_47#" -90.71
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/A" -90.71
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/VGND" -79.13
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/a_109_47#" -90.71
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/VGND" -79.13
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/VGND" -79.13
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/VGND" -79.13
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/a_109_47#" -90.71
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/X" -79.13
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/a_109_47#" -90.71
+cap "GND" "sky130_fd_sc_hd__buf_16_4/VGND" -2.82
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/a_109_47#" -90.71
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/X" -79.13
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "GND" 41.2915
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/X" -158.26
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/VNB" -2532.16
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/X" -79.13
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/a_109_47#" -90.71
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/a_109_47#" -90.71
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/a_109_47#" -90.71
+cap "sky130_fd_sc_hd__buf_16_4/a_109_47#" "sky130_fd_sc_hd__buf_16_4/VGND" -90.71
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/X" -79.13
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/VGND" -79.13
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/VGND" -79.13
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/a_109_47#" -90.71
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/a_109_47#" -90.71
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/a_109_47#" -90.71
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/VGND" -158.26
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_4/a_109_47#" -90.71
+cap "VDD" "sky130_fd_sc_hd__buf_16_4/X" 43.4113
+cap "sky130_fd_sc_hd__buf_16_4/VGND" "GND" 66.9565
+cap "VDD" "sky130_fd_sc_hd__buf_16_4/VPWR" 160.976
+cap "VDD" "sky130_fd_sc_hd__buf_16_4/a_109_47#" 6.13521
+cap "VDD" "sky130_fd_sc_hd__buf_16_0/VPWR" -101.053
+cap "VDD" "sky130_fd_sc_hd__buf_16_0/X" 0.582353
+cap "sky130_fd_sc_hd__buf_16_0/a_109_47#" "sky130_fd_sc_hd__buf_16_0/VPWR" -59.22
+cap "sky130_fd_sc_hd__buf_16_0/a_109_47#" "sky130_fd_sc_hd__buf_16_0/VPWR" -59.22
+cap "sky130_fd_sc_hd__buf_16_0/X" "sky130_fd_sc_hd__buf_16_0/VPWR" -154.98
+cap "sky130_fd_sc_hd__buf_16_0/VPWR" "sky130_fd_sc_hd__buf_16_0/a_109_47#" -59.22
+cap "sky130_fd_sc_hd__buf_16_0/a_109_47#" "sky130_fd_sc_hd__buf_16_0/VPWR" -59.22
+cap "sky130_fd_sc_hd__buf_16_0/X" "sky130_fd_sc_hd__buf_16_0/VPWR" -103.32
+cap "sky130_fd_sc_hd__buf_16_0/a_109_47#" "sky130_fd_sc_hd__buf_16_0/VPWR" -59.22
+cap "sky130_fd_sc_hd__buf_16_0/X" "sky130_fd_sc_hd__buf_16_0/VPWR" -154.98
+cap "sky130_fd_sc_hd__buf_16_0/a_109_47#" "sky130_fd_sc_hd__buf_16_0/VPWR" -59.22
+cap "sky130_fd_sc_hd__buf_16_0/X" "VDD" 4.27059
+cap "VDD" "sky130_fd_sc_hd__buf_16_0/X" 4.27059
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/VPWR" -315.7
+cap "sky130_fd_sc_hd__buf_16_0/X" "VDD" 4.27059
+cap "sky130_fd_sc_hd__buf_16_0/a_109_47#" "sky130_fd_sc_hd__buf_16_0/VPWR" -59.22
+cap "VDD" "sky130_fd_sc_hd__buf_16_0/X" 73.5966
+cap "GND" "sky130_fd_sc_hd__buf_16_0/VGND" -5.68434e-14
+cap "GND" "sky130_fd_sc_hd__buf_16_0/VGND" 72.9734
+cap "GND" "sky130_fd_sc_hd__buf_16_0/X" 20.2101
+cap "VDD" "sky130_fd_sc_hd__buf_16_0/VPWR" -1328.34
+cap "GND" "sky130_fd_sc_hd__buf_16_0/VGND" -5.68434e-14
+cap "sky130_fd_sc_hd__buf_16_0/X" "sky130_fd_sc_hd__buf_16_0/VGND" 2.18288
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/X" 9.55145
+cap "sky130_fd_sc_hd__buf_16_0/VPWR" "sky130_fd_sc_hd__buf_16_0/X" 3
+cap "sky130_fd_sc_hd__buf_16_0/VPB" "sky130_fd_sc_hd__buf_16_0/VPWR" -146.165
+cap "sky130_fd_sc_hd__buf_16_1/X" "sky130_fd_sc_hd__buf_16_1/VPWR" -106.6
+cap "sky130_fd_sc_hd__buf_16_1/X" "sky130_fd_sc_hd__buf_16_1/VPWR" -159.9
+cap "sky130_fd_sc_hd__buf_16_1/a_109_47#" "sky130_fd_sc_hd__buf_16_1/VPWR" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/a_109_47#" "sky130_fd_sc_hd__buf_16_1/VPWR" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/VPWR" "sky130_fd_sc_hd__buf_16_1/X" -159.9
+cap "sky130_fd_sc_hd__buf_16_1/VPWR" "sky130_fd_sc_hd__buf_16_1/X" -53.3
+cap "sky130_fd_sc_hd__buf_16_1/VPWR" "sky130_fd_sc_hd__buf_16_1/a_109_47#" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/a_109_47#" "sky130_fd_sc_hd__buf_16_1/VPWR" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/VPWR" -426.4
+cap "sky130_fd_sc_hd__buf_16_1/a_109_47#" "sky130_fd_sc_hd__buf_16_1/VPWR" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/a_109_47#" "sky130_fd_sc_hd__buf_16_1/VPWR" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/VPWR" "sky130_fd_sc_hd__buf_16_1/a_109_47#" -61.1
+cap "sky130_fd_sc_hd__buf_16_1/X" "sky130_fd_sc_hd__buf_16_1/VPWR" 1.73684
+cap "sky130_fd_sc_hd__buf_16_1/X" "sky130_fd_sc_hd__buf_16_1/VGND" 5.4466
+cap "sky130_fd_sc_hd__buf_16_1/VPB" "sky130_fd_sc_hd__buf_16_1/VPWR" -1.13687e-13
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_16_4/a_109_47#" -158.26
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_2_4/a_27_47#" -158.26
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_16_4/a_109_47#" -79.13
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_16_4/A" -90.71
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_16_4/A" -90.71
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_2_4/X" -158.26
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_16_4/VGND" -79.13
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "GND" 36.1565
+cap "sky130_fd_sc_hd__buf_2_4/a_27_47#" "sky130_fd_sc_hd__buf_2_4/VGND" -90.71
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_16_4/VGND" -158.26
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_2_4/VNB" -1740.86
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_2_4/a_27_47#" -90.71
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_16_4/A" -90.71
+cap "sky130_fd_sc_hd__buf_2_4/A" "sky130_fd_sc_hd__buf_2_4/VGND" -90.71
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_16_4/VGND" -79.13
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_16_4/A" -90.71
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_2_4/VGND" -158.26
+cap "VDD" "sky130_fd_sc_hd__buf_2_4/a_27_47#" 3.16056
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_2_4/A" 6.40592
+cap "sky130_fd_sc_hd__buf_16_4/a_109_47#" "VDD" 12.2704
+cap "sky130_fd_sc_hd__buf_2_4/A" "sky130_fd_sc_hd__buf_2_4/VPWR" 13.3934
+cap "VDD" "sky130_fd_sc_hd__buf_2_4/X" 4.74085
+cap "sky130_fd_sc_hd__buf_2_4/a_27_47#" "sky130_fd_sc_hd__buf_2_4/VPWR" 3.42453
+cap "sky130_fd_sc_hd__buf_16_4/a_109_47#" "sky130_fd_sc_hd__buf_2_4/VPWR" 22.0027
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_2_4/X" 60.4079
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_2_4/VNB" 5.68434e-14
+cap "sky130_fd_sc_hd__buf_2_4/X" "sky130_fd_sc_hd__buf_2_4/VPWR" 49.363
+cap "sky130_fd_sc_hd__buf_2_4/A" "sky130_fd_sc_hd__buf_2_4/a_27_47#" 29.4706
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "GND" 36.1565
+cap "sky130_fd_sc_hd__buf_2_4/A" "sky130_fd_sc_hd__buf_2_4/X" -6.13115
+cap "VDD" "sky130_fd_sc_hd__buf_2_4/VPWR" 86.9268
+cap "sky130_fd_sc_hd__buf_2_4/X" "sky130_fd_sc_hd__buf_2_4/a_27_47#" 10.4075
+cap "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_2_4/VPWR" 5.14902
+cap "sky130_fd_sc_hd__buf_2_4/VNB" "sky130_fd_sc_hd__buf_2_4/X" -4.26326e-14
+cap "sky130_fd_sc_hd__buf_2_4/A" "sky130_fd_sc_hd__buf_2_4/a_27_47#" 4.66981
+cap "sky130_fd_sc_hd__buf_2_4/A" "sky130_fd_sc_hd__buf_2_4/a_27_47#" 3.51348
+cap "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/w_n376_n376#" "CLKBAR" 35.4249
+cap "CLKBAR" "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/li_n340_n340#" 27.1249
+cap "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/w_n238_n238#" "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/li_n340_n340#" 0.497487
+cap "sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y_0/a_n100_n100#" "sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y_0/w_n238_n238#" 209.017
+cap "sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y_0/w_n238_n238#" "sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y_0/a_n100_n100#" 48.9819
+cap "CLKBAR" "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/li_n340_n340#" 120.944
+cap "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/w_n238_n238#" "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/a_n100_n100#" -407.821
+cap "CLKBAR" "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/w_n238_n238#" 97.6352
+cap "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/a_n100_n100#" "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/w_n376_n376#" 132.899
+cap "CLKBAR" "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/w_n376_n376#" 91.4967
+cap "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/li_n340_n340#" "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/a_n100_n100#" 150.555
+cap "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/a_n100_n100#" "VDD" -10.2591
+cap "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/w_n238_n238#" "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/li_n340_n340#" 133.132
+cap "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/w_n238_n238#" "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/a_n100_n100#" -99.5117
+cap "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/w_n238_n238#" "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/w_n376_n376#" 129.519
+merge "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/w_n238_n238#" "sky130_fd_sc_hd__buf_2_4/VPWR" -21210.3 0 0 0 0 52356 -11136 0 0 -23092 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 702517 -13274 -5366114 -22492 1655230 -1060 -32960770 -48900 -4883910 -20318 0 0 0 0
+merge "sky130_fd_sc_hd__buf_2_4/VPWR" "sky130_fd_sc_hd__buf_2_4/VPB"
+merge "sky130_fd_sc_hd__buf_2_4/VPB" "sky130_fd_sc_hd__buf_16_4/VPWR"
+merge "sky130_fd_sc_hd__buf_16_4/VPWR" "sky130_fd_sc_hd__buf_16_4/VPB"
+merge "sky130_fd_sc_hd__buf_16_4/VPB" "w_569596_688404#"
+merge "w_569596_688404#" "sky130_fd_sc_hd__buf_16_1/VPWR"
+merge "sky130_fd_sc_hd__buf_16_1/VPWR" "sky130_fd_sc_hd__buf_16_1/VPB"
+merge "sky130_fd_sc_hd__buf_16_1/VPB" "w_466974_686458#"
+merge "w_466974_686458#" "sky130_fd_sc_hd__buf_16_0/VPWR"
+merge "sky130_fd_sc_hd__buf_16_0/VPWR" "w_415450_686636#"
+merge "w_415450_686636#" "sky130_fd_sc_hd__buf_16_0/VPB"
+merge "sky130_fd_sc_hd__buf_16_0/VPB" "w_415106_686340#"
+merge "w_415106_686340#" "sky130_fd_sc_hd__buf_2_3/VPWR"
+merge "sky130_fd_sc_hd__buf_2_3/VPWR" "sky130_fd_sc_hd__buf_2_3/VPB"
+merge "sky130_fd_sc_hd__buf_2_3/VPB" "w_122758_673528#"
+merge "w_122758_673528#" "sky130_fd_sc_hd__buf_2_2/VPWR"
+merge "sky130_fd_sc_hd__buf_2_2/VPWR" "sky130_fd_sc_hd__buf_2_2/VPB"
+merge "sky130_fd_sc_hd__buf_2_2/VPB" "w_70778_673802#"
+merge "w_70778_673802#" "sky130_fd_sc_hd__buf_2_1/VPWR"
+merge "sky130_fd_sc_hd__buf_2_1/VPWR" "sky130_fd_sc_hd__buf_2_1/VPB"
+merge "sky130_fd_sc_hd__buf_2_1/VPB" "w_448410_591030#"
+merge "w_448410_591030#" "sky130_fd_sc_hd__buf_2_0/VPWR"
+merge "sky130_fd_sc_hd__buf_2_0/VPWR" "sky130_fd_sc_hd__buf_2_0/VPB"
+merge "sky130_fd_sc_hd__buf_2_0/VPB" "w_440058_591014#"
+merge "w_440058_591014#" "comparator_v6_0/VDD"
+merge "comparator_v6_0/VDD" "sky130_fd_sc_hd__buf_16_2/VPWR"
+merge "sky130_fd_sc_hd__buf_16_2/VPWR" "sky130_fd_sc_hd__buf_16_2/VPB"
+merge "sky130_fd_sc_hd__buf_16_2/VPB" "w_408706_587622#"
+merge "w_408706_587622#" "sky130_fd_sc_hd__buf_16_3/VPWR"
+merge "sky130_fd_sc_hd__buf_16_3/VPWR" "VDD"
+merge "VDD" "sky130_fd_sc_hd__buf_16_3/VPB"
+merge "sky130_fd_sc_hd__buf_16_3/VPB" "w_408694_585520#"
+merge "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/w_n376_n376#" "sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y_0/w_n238_n238#" -25688.6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15119 -11472 -8362095 -24460 178160 -3442 -34500632 -51550 144588 -3470 -8918894 -28524 0 0
+merge "sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y_0/w_n238_n238#" "sky130_fd_sc_hd__buf_2_4/VNB"
+merge "sky130_fd_sc_hd__buf_2_4/VNB" "sky130_fd_sc_hd__buf_2_4/VGND"
+merge "sky130_fd_sc_hd__buf_2_4/VGND" "sky130_fd_sc_hd__buf_16_4/VNB"
+merge "sky130_fd_sc_hd__buf_16_4/VNB" "sky130_fd_sc_hd__buf_16_4/VGND"
+merge "sky130_fd_sc_hd__buf_16_4/VGND" "sky130_fd_sc_hd__buf_16_1/VGND"
+merge "sky130_fd_sc_hd__buf_16_1/VGND" "sky130_fd_sc_hd__buf_16_1/VNB"
+merge "sky130_fd_sc_hd__buf_16_1/VNB" "sky130_fd_sc_hd__buf_16_0/VGND"
+merge "sky130_fd_sc_hd__buf_16_0/VGND" "sky130_fd_sc_hd__buf_16_0/VNB"
+merge "sky130_fd_sc_hd__buf_16_0/VNB" "sky130_fd_sc_hd__buf_2_3/VNB"
+merge "sky130_fd_sc_hd__buf_2_3/VNB" "sky130_fd_sc_hd__buf_2_3/VGND"
+merge "sky130_fd_sc_hd__buf_2_3/VGND" "sky130_fd_sc_hd__buf_2_2/VNB"
+merge "sky130_fd_sc_hd__buf_2_2/VNB" "sky130_fd_sc_hd__buf_2_2/VGND"
+merge "sky130_fd_sc_hd__buf_2_2/VGND" "sky130_fd_sc_hd__buf_2_1/VNB"
+merge "sky130_fd_sc_hd__buf_2_1/VNB" "sky130_fd_sc_hd__buf_2_1/VGND"
+merge "sky130_fd_sc_hd__buf_2_1/VGND" "sky130_fd_sc_hd__buf_2_0/VGND"
+merge "sky130_fd_sc_hd__buf_2_0/VGND" "sky130_fd_sc_hd__buf_2_0/VNB"
+merge "sky130_fd_sc_hd__buf_2_0/VNB" "sky130_fd_sc_hd__buf_16_2/VNB"
+merge "sky130_fd_sc_hd__buf_16_2/VNB" "sky130_fd_sc_hd__buf_16_2/VGND"
+merge "sky130_fd_sc_hd__buf_16_2/VGND" "sky130_fd_sc_hd__buf_16_3/VNB"
+merge "sky130_fd_sc_hd__buf_16_3/VNB" "sky130_fd_sc_hd__buf_16_3/VGND"
+merge "sky130_fd_sc_hd__buf_16_3/VGND" "comparator_v6_0/a_86_n1150#"
+merge "comparator_v6_0/a_86_n1150#" "comparator_v6_0/GND"
+merge "comparator_v6_0/GND" "GND"
+merge "sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/a_n100_n100#" "sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y_0/a_n100_n100#" -8908.82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -36254 -216 -775439 -1552 -132408 -3324 -13281102 -21938 0 0 0 0 0 0
+merge "sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y_0/a_n100_n100#" "sky130_fd_sc_hd__buf_2_3/A"
+merge "sky130_fd_sc_hd__buf_2_3/A" "CLKBAR"
+merge "sky130_fd_sc_hd__buf_2_4/X" "sky130_fd_sc_hd__buf_16_4/A" -87.6249 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -7004 -376 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__buf_16_4/A" "li_569558_688285#"
+merge "sky130_fd_sc_hd__buf_2_1/A" "comparator_v6_0/Outp" -371.169 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6524 -226 -123728 -1298 0 0 0 0 0 0 0 0 0 0
+merge "comparator_v6_0/Outp" "li_448544_589824#"
+merge "sky130_fd_sc_hd__buf_16_1/X" "Outp" -6860.87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16632 -250 0 0 0 0 -12500000 -15000 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__buf_16_0/A" "sky130_fd_sc_hd__buf_2_0/X" -44.3971 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7422 -232 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__buf_2_0/X" "L1"
+merge "comparator_v6_0/CLK" "sky130_fd_sc_hd__buf_16_3/X" -662.445 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -77592 -354 0 0 0 0 -139600 -400 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__buf_16_3/X" "li_408616_585444#"
+merge "sky130_fd_sc_hd__buf_2_2/X" "sky130_fd_sc_hd__buf_16_3/A" -477.479 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -435685 -208 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__buf_16_3/A" "li_70526_671944#"
+merge "comparator_v6_0/CLKBAR" "sky130_fd_sc_hd__buf_16_2/X" -2312.81 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -433496 -286 0 0 0 0 350736 -10730 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__buf_16_2/X" "li_408624_587536#"
+merge "sky130_fd_sc_hd__buf_16_1/A" "sky130_fd_sc_hd__buf_2_1/X" -203.39 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -8391 -938 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__buf_2_1/X" "L2"
+merge "sky130_fd_sc_hd__buf_2_4/A" "Iin" -6835.76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38842 -178 0 0 0 0 -12500000 -15000 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__buf_2_0/A" "comparator_v6_0/Outn" -386.897 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14180 -272 -1796 -1456 0 0 0 0 0 0 0 0 0 0
+merge "comparator_v6_0/Outn" "li_440216_589824#"
+merge "sky130_fd_sc_hd__buf_2_3/X" "li_122782_673260#" -130.151 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -32714 -332 0 0 0 0 0 0 0 0 0 0 0 0
+merge "li_122782_673260#" "sky130_fd_sc_hd__buf_16_2/A"
+merge "sky130_fd_sc_hd__buf_16_2/A" "li_122514_671986#"
+merge "sky130_fd_sc_hd__buf_2_2/A" "CLK" -6884.21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3276 -258 0 0 0 0 -12500000 -15000 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__buf_16_4/X" "io_analog[0]" -55.687 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3192 -206 0 0 0 0 0 0 0 0 0 0 0 0
+merge "comparator_v6_0/Vn" "Vn" -8097.78 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37044 -752 0 0 0 0 0 0 -25000748 -30008 0 0
+merge "sky130_fd_sc_hd__buf_16_0/X" "li_415508_688595#" -6889.39 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17844 -348 0 0 0 0 -12500000 -15000 0 0 0 0 0 0
+merge "li_415508_688595#" "Outn"
+merge "comparator_v6_0/Vp" "Vp" -10565 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -750736 -672 0 0 0 0 0 0 -25990578 -38399 0 0
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
new file mode 100644
index 0000000..9cabaa4
--- /dev/null
+++ b/mag/user_analog_project_wrapper.mag
@@ -0,0 +1,5932 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1653478184
+<< nwell >>
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+<< psubdiffcont >>
+rect 67380 687200 67414 687412
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+<< nsubdiffcont >>
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+<< pdiode >>
+rect 73333 687383 73533 687395
+rect 73333 687207 73345 687383
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+<< ndiode >>
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+rect 67482 687218 67494 687394
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+rect 67482 687206 67682 687218
+<< pdiodec >>
+rect 73345 687207 73521 687383
+<< ndiodec >>
+rect 67494 687218 67670 687394
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+rect 408022 580628 408800 581174
+rect 409222 580628 410000 581174
+<< metal5 >>
+rect 165596 702540 170596 704800
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+rect 44908 541976 54564 542110
+<< comment >>
+rect -100 704000 584100 704100
+rect -100 0 0 704000
+rect 584000 0 584100 704000
+rect -100 -100 584100 0
+use comparator_v6 comparator_v6_0
+timestamp 1653472115
+transform 0 1 419250 1 0 584722
+box -2598 -1934 4390 5556
+use sky130_fd_pr__diode_pd2nw_05v5_G4XDRY sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0
+timestamp 1647842470
+transform 1 0 125433 0 1 695295
+box -376 -376 376 376
+use sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y_0
+timestamp 1647842470
+transform 1 0 119582 0 1 695306
+box -238 -238 238 238
+use sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1643856600
+transform 0 -1 440640 1 0 591294
+box -38 -48 406 592
+use sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1
+timestamp 1643856600
+transform 0 -1 448994 1 0 591314
+box -38 -48 406 592
+use sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2
+timestamp 1643856600
+transform 0 1 70516 -1 0 673768
+box -38 -48 406 592
+use sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3
+timestamp 1643856600
+transform 0 1 122500 -1 0 673516
+box -38 -48 406 592
+use sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4
+timestamp 1643856600
+transform 0 1 569338 -1 0 689064
+box -38 -48 406 592
+use sky130_fd_sc_hd__buf_16 sky130_fd_sc_hd__buf_16_0 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1643856600
+transform 0 -1 415748 1 0 686664
+box -38 -48 2062 592
+use sky130_fd_sc_hd__buf_16 sky130_fd_sc_hd__buf_16_1
+timestamp 1643856600
+transform 0 -1 467556 1 0 686698
+box -38 -48 2062 592
+use sky130_fd_sc_hd__buf_16 sky130_fd_sc_hd__buf_16_2
+timestamp 1643856600
+transform 1 0 406656 0 1 587358
+box -38 -48 2062 592
+use sky130_fd_sc_hd__buf_16 sky130_fd_sc_hd__buf_16_3
+timestamp 1643856600
+transform 1 0 406646 0 1 585256
+box -38 -48 2062 592
+use sky130_fd_sc_hd__buf_16 sky130_fd_sc_hd__buf_16_4
+timestamp 1643856600
+transform 0 1 569338 -1 0 688388
+box -38 -48 2062 592
+<< labels >>
+flabel metal3 s 583520 269230 584800 269342 0 FreeSans 1120 0 0 0 gpio_analog[0]
+port 0 nsew signal bidirectional
+flabel metal3 s -800 381864 480 381976 0 FreeSans 1120 0 0 0 gpio_analog[10]
+port 1 nsew signal bidirectional
+flabel metal3 s -800 338642 480 338754 0 FreeSans 1120 0 0 0 gpio_analog[11]
+port 2 nsew signal bidirectional
+flabel metal3 s -800 295420 480 295532 0 FreeSans 1120 0 0 0 gpio_analog[12]
+port 3 nsew signal bidirectional
+flabel metal3 s -800 252398 480 252510 0 FreeSans 1120 0 0 0 gpio_analog[13]
+port 4 nsew signal bidirectional
+flabel metal3 s -800 124776 480 124888 0 FreeSans 1120 0 0 0 gpio_analog[14]
+port 5 nsew signal bidirectional
+flabel metal3 s -800 81554 480 81666 0 FreeSans 1120 0 0 0 gpio_analog[15]
+port 6 nsew signal bidirectional
+flabel metal3 s -800 38332 480 38444 0 FreeSans 1120 0 0 0 gpio_analog[16]
+port 7 nsew signal bidirectional
+flabel metal3 s -800 16910 480 17022 0 FreeSans 1120 0 0 0 gpio_analog[17]
+port 8 nsew signal bidirectional
+flabel metal3 s 583520 313652 584800 313764 0 FreeSans 1120 0 0 0 gpio_analog[1]
+port 9 nsew signal bidirectional
+flabel metal3 s 583520 358874 584800 358986 0 FreeSans 1120 0 0 0 gpio_analog[2]
+port 10 nsew signal bidirectional
+flabel metal3 s 583520 405296 584800 405408 0 FreeSans 1120 0 0 0 gpio_analog[3]
+port 11 nsew signal bidirectional
+flabel metal3 s 583520 449718 584800 449830 0 FreeSans 1120 0 0 0 gpio_analog[4]
+port 12 nsew signal bidirectional
+flabel metal3 s 583520 494140 584800 494252 0 FreeSans 1120 0 0 0 gpio_analog[5]
+port 13 nsew signal bidirectional
+flabel metal3 s 583520 583562 584800 583674 0 FreeSans 1120 0 0 0 gpio_analog[6]
+port 14 nsew signal bidirectional
+flabel metal3 s -800 511530 480 511642 0 FreeSans 1120 0 0 0 gpio_analog[7]
+port 15 nsew signal bidirectional
+flabel metal3 s -800 468308 480 468420 0 FreeSans 1120 0 0 0 gpio_analog[8]
+port 16 nsew signal bidirectional
+flabel metal3 s -800 425086 480 425198 0 FreeSans 1120 0 0 0 gpio_analog[9]
+port 17 nsew signal bidirectional
+flabel metal3 s 583520 270412 584800 270524 0 FreeSans 1120 0 0 0 gpio_noesd[0]
+port 18 nsew signal bidirectional
+flabel metal3 s -800 380682 480 380794 0 FreeSans 1120 0 0 0 gpio_noesd[10]
+port 19 nsew signal bidirectional
+flabel metal3 s -800 337460 480 337572 0 FreeSans 1120 0 0 0 gpio_noesd[11]
+port 20 nsew signal bidirectional
+flabel metal3 s -800 294238 480 294350 0 FreeSans 1120 0 0 0 gpio_noesd[12]
+port 21 nsew signal bidirectional
+flabel metal3 s -800 251216 480 251328 0 FreeSans 1120 0 0 0 gpio_noesd[13]
+port 22 nsew signal bidirectional
+flabel metal3 s -800 123594 480 123706 0 FreeSans 1120 0 0 0 gpio_noesd[14]
+port 23 nsew signal bidirectional
+flabel metal3 s -800 80372 480 80484 0 FreeSans 1120 0 0 0 gpio_noesd[15]
+port 24 nsew signal bidirectional
+flabel metal3 s -800 37150 480 37262 0 FreeSans 1120 0 0 0 gpio_noesd[16]
+port 25 nsew signal bidirectional
+flabel metal3 s -800 15728 480 15840 0 FreeSans 1120 0 0 0 gpio_noesd[17]
+port 26 nsew signal bidirectional
+flabel metal3 s 583520 314834 584800 314946 0 FreeSans 1120 0 0 0 gpio_noesd[1]
+port 27 nsew signal bidirectional
+flabel metal3 s 583520 360056 584800 360168 0 FreeSans 1120 0 0 0 gpio_noesd[2]
+port 28 nsew signal bidirectional
+flabel metal3 s 583520 406478 584800 406590 0 FreeSans 1120 0 0 0 gpio_noesd[3]
+port 29 nsew signal bidirectional
+flabel metal3 s 583520 450900 584800 451012 0 FreeSans 1120 0 0 0 gpio_noesd[4]
+port 30 nsew signal bidirectional
+flabel metal3 s 583520 495322 584800 495434 0 FreeSans 1120 0 0 0 gpio_noesd[5]
+port 31 nsew signal bidirectional
+flabel metal3 s 583520 584744 584800 584856 0 FreeSans 1120 0 0 0 gpio_noesd[6]
+port 32 nsew signal bidirectional
+flabel metal3 s -800 510348 480 510460 0 FreeSans 1120 0 0 0 gpio_noesd[7]
+port 33 nsew signal bidirectional
+flabel metal3 s -800 467126 480 467238 0 FreeSans 1120 0 0 0 gpio_noesd[8]
+port 34 nsew signal bidirectional
+flabel metal3 s -800 423904 480 424016 0 FreeSans 1120 0 0 0 gpio_noesd[9]
+port 35 nsew signal bidirectional
+flabel metal3 s 582300 677984 584800 682984 0 FreeSans 1120 0 0 0 io_analog[0]
+port 36 nsew signal bidirectional
+flabel metal3 s 0 680242 1700 685242 0 FreeSans 1120 0 0 0 io_analog[10]
+port 37 nsew signal bidirectional
+flabel metal3 s 566594 702300 571594 704800 0 FreeSans 1920 180 0 0 io_analog[1]
+port 38 nsew signal bidirectional
+flabel metal3 s 465394 702300 470394 704800 0 FreeSans 1920 180 0 0 io_analog[2]
+port 39 nsew signal bidirectional
+flabel metal3 s 413394 702300 418394 704800 0 FreeSans 1920 180 0 0 io_analog[3]
+port 40 nsew signal bidirectional
+flabel metal3 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal4 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal5 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal3 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal4 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal5 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal5 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal3 s 120194 702300 125194 704800 0 FreeSans 1920 180 0 0 io_analog[7]
+port 44 nsew signal bidirectional
+flabel metal3 s 68194 702300 73194 704800 0 FreeSans 1920 180 0 0 io_analog[8]
+port 45 nsew signal bidirectional
+flabel metal3 s 16194 702300 21194 704800 0 FreeSans 1920 180 0 0 io_analog[9]
+port 46 nsew signal bidirectional
+flabel metal3 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal4 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal5 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal3 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal4 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal5 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal5 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal3 s 326794 702300 328994 704800 0 FreeSans 1920 180 0 0 io_clamp_high[0]
+port 50 nsew signal bidirectional
+flabel metal3 s 225094 702300 227294 704800 0 FreeSans 1920 180 0 0 io_clamp_high[1]
+port 51 nsew signal bidirectional
+flabel metal3 s 173394 702300 175594 704800 0 FreeSans 1920 180 0 0 io_clamp_high[2]
+port 52 nsew signal bidirectional
+flabel metal3 s 324294 702300 326494 704800 0 FreeSans 1920 180 0 0 io_clamp_low[0]
+port 53 nsew signal bidirectional
+flabel metal3 s 222594 702300 224794 704800 0 FreeSans 1920 180 0 0 io_clamp_low[1]
+port 54 nsew signal bidirectional
+flabel metal3 s 170894 702300 173094 704800 0 FreeSans 1920 180 0 0 io_clamp_low[2]
+port 55 nsew signal bidirectional
+flabel metal3 s 583520 2726 584800 2838 0 FreeSans 1120 0 0 0 io_in[0]
+port 56 nsew signal input
+flabel metal3 s 583520 408842 584800 408954 0 FreeSans 1120 0 0 0 io_in[10]
+port 57 nsew signal input
+flabel metal3 s 583520 453264 584800 453376 0 FreeSans 1120 0 0 0 io_in[11]
+port 58 nsew signal input
+flabel metal3 s 583520 497686 584800 497798 0 FreeSans 1120 0 0 0 io_in[12]
+port 59 nsew signal input
+flabel metal3 s 583520 587108 584800 587220 0 FreeSans 1120 0 0 0 io_in[13]
+port 60 nsew signal input
+flabel metal3 s -800 507984 480 508096 0 FreeSans 1120 0 0 0 io_in[14]
+port 61 nsew signal input
+flabel metal3 s -800 464762 480 464874 0 FreeSans 1120 0 0 0 io_in[15]
+port 62 nsew signal input
+flabel metal3 s -800 421540 480 421652 0 FreeSans 1120 0 0 0 io_in[16]
+port 63 nsew signal input
+flabel metal3 s -800 378318 480 378430 0 FreeSans 1120 0 0 0 io_in[17]
+port 64 nsew signal input
+flabel metal3 s -800 335096 480 335208 0 FreeSans 1120 0 0 0 io_in[18]
+port 65 nsew signal input
+flabel metal3 s -800 291874 480 291986 0 FreeSans 1120 0 0 0 io_in[19]
+port 66 nsew signal input
+flabel metal3 s 583520 7454 584800 7566 0 FreeSans 1120 0 0 0 io_in[1]
+port 67 nsew signal input
+flabel metal3 s -800 248852 480 248964 0 FreeSans 1120 0 0 0 io_in[20]
+port 68 nsew signal input
+flabel metal3 s -800 121230 480 121342 0 FreeSans 1120 0 0 0 io_in[21]
+port 69 nsew signal input
+flabel metal3 s -800 78008 480 78120 0 FreeSans 1120 0 0 0 io_in[22]
+port 70 nsew signal input
+flabel metal3 s -800 34786 480 34898 0 FreeSans 1120 0 0 0 io_in[23]
+port 71 nsew signal input
+flabel metal3 s -800 13364 480 13476 0 FreeSans 1120 0 0 0 io_in[24]
+port 72 nsew signal input
+flabel metal3 s -800 8636 480 8748 0 FreeSans 1120 0 0 0 io_in[25]
+port 73 nsew signal input
+flabel metal3 s -800 3908 480 4020 0 FreeSans 1120 0 0 0 io_in[26]
+port 74 nsew signal input
+flabel metal3 s 583520 12182 584800 12294 0 FreeSans 1120 0 0 0 io_in[2]
+port 75 nsew signal input
+flabel metal3 s 583520 16910 584800 17022 0 FreeSans 1120 0 0 0 io_in[3]
+port 76 nsew signal input
+flabel metal3 s 583520 21638 584800 21750 0 FreeSans 1120 0 0 0 io_in[4]
+port 77 nsew signal input
+flabel metal3 s 583520 48096 584800 48208 0 FreeSans 1120 0 0 0 io_in[5]
+port 78 nsew signal input
+flabel metal3 s 583520 92754 584800 92866 0 FreeSans 1120 0 0 0 io_in[6]
+port 79 nsew signal input
+flabel metal3 s 583520 272776 584800 272888 0 FreeSans 1120 0 0 0 io_in[7]
+port 80 nsew signal input
+flabel metal3 s 583520 317198 584800 317310 0 FreeSans 1120 0 0 0 io_in[8]
+port 81 nsew signal input
+flabel metal3 s 583520 362420 584800 362532 0 FreeSans 1120 0 0 0 io_in[9]
+port 82 nsew signal input
+flabel metal3 s 583520 1544 584800 1656 0 FreeSans 1120 0 0 0 io_in_3v3[0]
+port 83 nsew signal input
+flabel metal3 s 583520 407660 584800 407772 0 FreeSans 1120 0 0 0 io_in_3v3[10]
+port 84 nsew signal input
+flabel metal3 s 583520 452082 584800 452194 0 FreeSans 1120 0 0 0 io_in_3v3[11]
+port 85 nsew signal input
+flabel metal3 s 583520 496504 584800 496616 0 FreeSans 1120 0 0 0 io_in_3v3[12]
+port 86 nsew signal input
+flabel metal3 s 583520 585926 584800 586038 0 FreeSans 1120 0 0 0 io_in_3v3[13]
+port 87 nsew signal input
+flabel metal3 s -800 509166 480 509278 0 FreeSans 1120 0 0 0 io_in_3v3[14]
+port 88 nsew signal input
+flabel metal3 s -800 465944 480 466056 0 FreeSans 1120 0 0 0 io_in_3v3[15]
+port 89 nsew signal input
+flabel metal3 s -800 422722 480 422834 0 FreeSans 1120 0 0 0 io_in_3v3[16]
+port 90 nsew signal input
+flabel metal3 s -800 379500 480 379612 0 FreeSans 1120 0 0 0 io_in_3v3[17]
+port 91 nsew signal input
+flabel metal3 s -800 336278 480 336390 0 FreeSans 1120 0 0 0 io_in_3v3[18]
+port 92 nsew signal input
+flabel metal3 s -800 293056 480 293168 0 FreeSans 1120 0 0 0 io_in_3v3[19]
+port 93 nsew signal input
+flabel metal3 s 583520 6272 584800 6384 0 FreeSans 1120 0 0 0 io_in_3v3[1]
+port 94 nsew signal input
+flabel metal3 s -800 250034 480 250146 0 FreeSans 1120 0 0 0 io_in_3v3[20]
+port 95 nsew signal input
+flabel metal3 s -800 122412 480 122524 0 FreeSans 1120 0 0 0 io_in_3v3[21]
+port 96 nsew signal input
+flabel metal3 s -800 79190 480 79302 0 FreeSans 1120 0 0 0 io_in_3v3[22]
+port 97 nsew signal input
+flabel metal3 s -800 35968 480 36080 0 FreeSans 1120 0 0 0 io_in_3v3[23]
+port 98 nsew signal input
+flabel metal3 s -800 14546 480 14658 0 FreeSans 1120 0 0 0 io_in_3v3[24]
+port 99 nsew signal input
+flabel metal3 s -800 9818 480 9930 0 FreeSans 1120 0 0 0 io_in_3v3[25]
+port 100 nsew signal input
+flabel metal3 s -800 5090 480 5202 0 FreeSans 1120 0 0 0 io_in_3v3[26]
+port 101 nsew signal input
+flabel metal3 s 583520 11000 584800 11112 0 FreeSans 1120 0 0 0 io_in_3v3[2]
+port 102 nsew signal input
+flabel metal3 s 583520 15728 584800 15840 0 FreeSans 1120 0 0 0 io_in_3v3[3]
+port 103 nsew signal input
+flabel metal3 s 583520 20456 584800 20568 0 FreeSans 1120 0 0 0 io_in_3v3[4]
+port 104 nsew signal input
+flabel metal3 s 583520 46914 584800 47026 0 FreeSans 1120 0 0 0 io_in_3v3[5]
+port 105 nsew signal input
+flabel metal3 s 583520 91572 584800 91684 0 FreeSans 1120 0 0 0 io_in_3v3[6]
+port 106 nsew signal input
+flabel metal3 s 583520 271594 584800 271706 0 FreeSans 1120 0 0 0 io_in_3v3[7]
+port 107 nsew signal input
+flabel metal3 s 583520 316016 584800 316128 0 FreeSans 1120 0 0 0 io_in_3v3[8]
+port 108 nsew signal input
+flabel metal3 s 583520 361238 584800 361350 0 FreeSans 1120 0 0 0 io_in_3v3[9]
+port 109 nsew signal input
+flabel metal3 s 583520 5090 584800 5202 0 FreeSans 1120 0 0 0 io_oeb[0]
+port 110 nsew signal tristate
+flabel metal3 s 583520 411206 584800 411318 0 FreeSans 1120 0 0 0 io_oeb[10]
+port 111 nsew signal tristate
+flabel metal3 s 583520 455628 584800 455740 0 FreeSans 1120 0 0 0 io_oeb[11]
+port 112 nsew signal tristate
+flabel metal3 s 583520 500050 584800 500162 0 FreeSans 1120 0 0 0 io_oeb[12]
+port 113 nsew signal tristate
+flabel metal3 s 583520 589472 584800 589584 0 FreeSans 1120 0 0 0 io_oeb[13]
+port 114 nsew signal tristate
+flabel metal3 s -800 505620 480 505732 0 FreeSans 1120 0 0 0 io_oeb[14]
+port 115 nsew signal tristate
+flabel metal3 s -800 462398 480 462510 0 FreeSans 1120 0 0 0 io_oeb[15]
+port 116 nsew signal tristate
+flabel metal3 s -800 419176 480 419288 0 FreeSans 1120 0 0 0 io_oeb[16]
+port 117 nsew signal tristate
+flabel metal3 s -800 375954 480 376066 0 FreeSans 1120 0 0 0 io_oeb[17]
+port 118 nsew signal tristate
+flabel metal3 s -800 332732 480 332844 0 FreeSans 1120 0 0 0 io_oeb[18]
+port 119 nsew signal tristate
+flabel metal3 s -800 289510 480 289622 0 FreeSans 1120 0 0 0 io_oeb[19]
+port 120 nsew signal tristate
+flabel metal3 s 583520 9818 584800 9930 0 FreeSans 1120 0 0 0 io_oeb[1]
+port 121 nsew signal tristate
+flabel metal3 s -800 246488 480 246600 0 FreeSans 1120 0 0 0 io_oeb[20]
+port 122 nsew signal tristate
+flabel metal3 s -800 118866 480 118978 0 FreeSans 1120 0 0 0 io_oeb[21]
+port 123 nsew signal tristate
+flabel metal3 s -800 75644 480 75756 0 FreeSans 1120 0 0 0 io_oeb[22]
+port 124 nsew signal tristate
+flabel metal3 s -800 32422 480 32534 0 FreeSans 1120 0 0 0 io_oeb[23]
+port 125 nsew signal tristate
+flabel metal3 s -800 11000 480 11112 0 FreeSans 1120 0 0 0 io_oeb[24]
+port 126 nsew signal tristate
+flabel metal3 s -800 6272 480 6384 0 FreeSans 1120 0 0 0 io_oeb[25]
+port 127 nsew signal tristate
+flabel metal3 s -800 1544 480 1656 0 FreeSans 1120 0 0 0 io_oeb[26]
+port 128 nsew signal tristate
+flabel metal3 s 583520 14546 584800 14658 0 FreeSans 1120 0 0 0 io_oeb[2]
+port 129 nsew signal tristate
+flabel metal3 s 583520 19274 584800 19386 0 FreeSans 1120 0 0 0 io_oeb[3]
+port 130 nsew signal tristate
+flabel metal3 s 583520 24002 584800 24114 0 FreeSans 1120 0 0 0 io_oeb[4]
+port 131 nsew signal tristate
+flabel metal3 s 583520 50460 584800 50572 0 FreeSans 1120 0 0 0 io_oeb[5]
+port 132 nsew signal tristate
+flabel metal3 s 583520 95118 584800 95230 0 FreeSans 1120 0 0 0 io_oeb[6]
+port 133 nsew signal tristate
+flabel metal3 s 583520 275140 584800 275252 0 FreeSans 1120 0 0 0 io_oeb[7]
+port 134 nsew signal tristate
+flabel metal3 s 583520 319562 584800 319674 0 FreeSans 1120 0 0 0 io_oeb[8]
+port 135 nsew signal tristate
+flabel metal3 s 583520 364784 584800 364896 0 FreeSans 1120 0 0 0 io_oeb[9]
+port 136 nsew signal tristate
+flabel metal3 s 583520 3908 584800 4020 0 FreeSans 1120 0 0 0 io_out[0]
+port 137 nsew signal tristate
+flabel metal3 s 583520 410024 584800 410136 0 FreeSans 1120 0 0 0 io_out[10]
+port 138 nsew signal tristate
+flabel metal3 s 583520 454446 584800 454558 0 FreeSans 1120 0 0 0 io_out[11]
+port 139 nsew signal tristate
+flabel metal3 s 583520 498868 584800 498980 0 FreeSans 1120 0 0 0 io_out[12]
+port 140 nsew signal tristate
+flabel metal3 s 583520 588290 584800 588402 0 FreeSans 1120 0 0 0 io_out[13]
+port 141 nsew signal tristate
+flabel metal3 s -800 506802 480 506914 0 FreeSans 1120 0 0 0 io_out[14]
+port 142 nsew signal tristate
+flabel metal3 s -800 463580 480 463692 0 FreeSans 1120 0 0 0 io_out[15]
+port 143 nsew signal tristate
+flabel metal3 s -800 420358 480 420470 0 FreeSans 1120 0 0 0 io_out[16]
+port 144 nsew signal tristate
+flabel metal3 s -800 377136 480 377248 0 FreeSans 1120 0 0 0 io_out[17]
+port 145 nsew signal tristate
+flabel metal3 s -800 333914 480 334026 0 FreeSans 1120 0 0 0 io_out[18]
+port 146 nsew signal tristate
+flabel metal3 s -800 290692 480 290804 0 FreeSans 1120 0 0 0 io_out[19]
+port 147 nsew signal tristate
+flabel metal3 s 583520 8636 584800 8748 0 FreeSans 1120 0 0 0 io_out[1]
+port 148 nsew signal tristate
+flabel metal3 s -800 247670 480 247782 0 FreeSans 1120 0 0 0 io_out[20]
+port 149 nsew signal tristate
+flabel metal3 s -800 120048 480 120160 0 FreeSans 1120 0 0 0 io_out[21]
+port 150 nsew signal tristate
+flabel metal3 s -800 76826 480 76938 0 FreeSans 1120 0 0 0 io_out[22]
+port 151 nsew signal tristate
+flabel metal3 s -800 33604 480 33716 0 FreeSans 1120 0 0 0 io_out[23]
+port 152 nsew signal tristate
+flabel metal3 s -800 12182 480 12294 0 FreeSans 1120 0 0 0 io_out[24]
+port 153 nsew signal tristate
+flabel metal3 s -800 7454 480 7566 0 FreeSans 1120 0 0 0 io_out[25]
+port 154 nsew signal tristate
+flabel metal3 s -800 2726 480 2838 0 FreeSans 1120 0 0 0 io_out[26]
+port 155 nsew signal tristate
+flabel metal3 s 583520 13364 584800 13476 0 FreeSans 1120 0 0 0 io_out[2]
+port 156 nsew signal tristate
+flabel metal3 s 583520 18092 584800 18204 0 FreeSans 1120 0 0 0 io_out[3]
+port 157 nsew signal tristate
+flabel metal3 s 583520 22820 584800 22932 0 FreeSans 1120 0 0 0 io_out[4]
+port 158 nsew signal tristate
+flabel metal3 s 583520 49278 584800 49390 0 FreeSans 1120 0 0 0 io_out[5]
+port 159 nsew signal tristate
+flabel metal3 s 583520 93936 584800 94048 0 FreeSans 1120 0 0 0 io_out[6]
+port 160 nsew signal tristate
+flabel metal3 s 583520 273958 584800 274070 0 FreeSans 1120 0 0 0 io_out[7]
+port 161 nsew signal tristate
+flabel metal3 s 583520 318380 584800 318492 0 FreeSans 1120 0 0 0 io_out[8]
+port 162 nsew signal tristate
+flabel metal3 s 583520 363602 584800 363714 0 FreeSans 1120 0 0 0 io_out[9]
+port 163 nsew signal tristate
+flabel metal2 s 125816 -800 125928 480 0 FreeSans 1120 90 0 0 la_data_in[0]
+port 164 nsew signal input
+flabel metal2 s 480416 -800 480528 480 0 FreeSans 1120 90 0 0 la_data_in[100]
+port 165 nsew signal input
+flabel metal2 s 483962 -800 484074 480 0 FreeSans 1120 90 0 0 la_data_in[101]
+port 166 nsew signal input
+flabel metal2 s 487508 -800 487620 480 0 FreeSans 1120 90 0 0 la_data_in[102]
+port 167 nsew signal input
+flabel metal2 s 491054 -800 491166 480 0 FreeSans 1120 90 0 0 la_data_in[103]
+port 168 nsew signal input
+flabel metal2 s 494600 -800 494712 480 0 FreeSans 1120 90 0 0 la_data_in[104]
+port 169 nsew signal input
+flabel metal2 s 498146 -800 498258 480 0 FreeSans 1120 90 0 0 la_data_in[105]
+port 170 nsew signal input
+flabel metal2 s 501692 -800 501804 480 0 FreeSans 1120 90 0 0 la_data_in[106]
+port 171 nsew signal input
+flabel metal2 s 505238 -800 505350 480 0 FreeSans 1120 90 0 0 la_data_in[107]
+port 172 nsew signal input
+flabel metal2 s 508784 -800 508896 480 0 FreeSans 1120 90 0 0 la_data_in[108]
+port 173 nsew signal input
+flabel metal2 s 512330 -800 512442 480 0 FreeSans 1120 90 0 0 la_data_in[109]
+port 174 nsew signal input
+flabel metal2 s 161276 -800 161388 480 0 FreeSans 1120 90 0 0 la_data_in[10]
+port 175 nsew signal input
+flabel metal2 s 515876 -800 515988 480 0 FreeSans 1120 90 0 0 la_data_in[110]
+port 176 nsew signal input
+flabel metal2 s 519422 -800 519534 480 0 FreeSans 1120 90 0 0 la_data_in[111]
+port 177 nsew signal input
+flabel metal2 s 522968 -800 523080 480 0 FreeSans 1120 90 0 0 la_data_in[112]
+port 178 nsew signal input
+flabel metal2 s 526514 -800 526626 480 0 FreeSans 1120 90 0 0 la_data_in[113]
+port 179 nsew signal input
+flabel metal2 s 530060 -800 530172 480 0 FreeSans 1120 90 0 0 la_data_in[114]
+port 180 nsew signal input
+flabel metal2 s 533606 -800 533718 480 0 FreeSans 1120 90 0 0 la_data_in[115]
+port 181 nsew signal input
+flabel metal2 s 537152 -800 537264 480 0 FreeSans 1120 90 0 0 la_data_in[116]
+port 182 nsew signal input
+flabel metal2 s 540698 -800 540810 480 0 FreeSans 1120 90 0 0 la_data_in[117]
+port 183 nsew signal input
+flabel metal2 s 544244 -800 544356 480 0 FreeSans 1120 90 0 0 la_data_in[118]
+port 184 nsew signal input
+flabel metal2 s 547790 -800 547902 480 0 FreeSans 1120 90 0 0 la_data_in[119]
+port 185 nsew signal input
+flabel metal2 s 164822 -800 164934 480 0 FreeSans 1120 90 0 0 la_data_in[11]
+port 186 nsew signal input
+flabel metal2 s 551336 -800 551448 480 0 FreeSans 1120 90 0 0 la_data_in[120]
+port 187 nsew signal input
+flabel metal2 s 554882 -800 554994 480 0 FreeSans 1120 90 0 0 la_data_in[121]
+port 188 nsew signal input
+flabel metal2 s 558428 -800 558540 480 0 FreeSans 1120 90 0 0 la_data_in[122]
+port 189 nsew signal input
+flabel metal2 s 561974 -800 562086 480 0 FreeSans 1120 90 0 0 la_data_in[123]
+port 190 nsew signal input
+flabel metal2 s 565520 -800 565632 480 0 FreeSans 1120 90 0 0 la_data_in[124]
+port 191 nsew signal input
+flabel metal2 s 569066 -800 569178 480 0 FreeSans 1120 90 0 0 la_data_in[125]
+port 192 nsew signal input
+flabel metal2 s 572612 -800 572724 480 0 FreeSans 1120 90 0 0 la_data_in[126]
+port 193 nsew signal input
+flabel metal2 s 576158 -800 576270 480 0 FreeSans 1120 90 0 0 la_data_in[127]
+port 194 nsew signal input
+flabel metal2 s 168368 -800 168480 480 0 FreeSans 1120 90 0 0 la_data_in[12]
+port 195 nsew signal input
+flabel metal2 s 171914 -800 172026 480 0 FreeSans 1120 90 0 0 la_data_in[13]
+port 196 nsew signal input
+flabel metal2 s 175460 -800 175572 480 0 FreeSans 1120 90 0 0 la_data_in[14]
+port 197 nsew signal input
+flabel metal2 s 179006 -800 179118 480 0 FreeSans 1120 90 0 0 la_data_in[15]
+port 198 nsew signal input
+flabel metal2 s 182552 -800 182664 480 0 FreeSans 1120 90 0 0 la_data_in[16]
+port 199 nsew signal input
+flabel metal2 s 186098 -800 186210 480 0 FreeSans 1120 90 0 0 la_data_in[17]
+port 200 nsew signal input
+flabel metal2 s 189644 -800 189756 480 0 FreeSans 1120 90 0 0 la_data_in[18]
+port 201 nsew signal input
+flabel metal2 s 193190 -800 193302 480 0 FreeSans 1120 90 0 0 la_data_in[19]
+port 202 nsew signal input
+flabel metal2 s 129362 -800 129474 480 0 FreeSans 1120 90 0 0 la_data_in[1]
+port 203 nsew signal input
+flabel metal2 s 196736 -800 196848 480 0 FreeSans 1120 90 0 0 la_data_in[20]
+port 204 nsew signal input
+flabel metal2 s 200282 -800 200394 480 0 FreeSans 1120 90 0 0 la_data_in[21]
+port 205 nsew signal input
+flabel metal2 s 203828 -800 203940 480 0 FreeSans 1120 90 0 0 la_data_in[22]
+port 206 nsew signal input
+flabel metal2 s 207374 -800 207486 480 0 FreeSans 1120 90 0 0 la_data_in[23]
+port 207 nsew signal input
+flabel metal2 s 210920 -800 211032 480 0 FreeSans 1120 90 0 0 la_data_in[24]
+port 208 nsew signal input
+flabel metal2 s 214466 -800 214578 480 0 FreeSans 1120 90 0 0 la_data_in[25]
+port 209 nsew signal input
+flabel metal2 s 218012 -800 218124 480 0 FreeSans 1120 90 0 0 la_data_in[26]
+port 210 nsew signal input
+flabel metal2 s 221558 -800 221670 480 0 FreeSans 1120 90 0 0 la_data_in[27]
+port 211 nsew signal input
+flabel metal2 s 225104 -800 225216 480 0 FreeSans 1120 90 0 0 la_data_in[28]
+port 212 nsew signal input
+flabel metal2 s 228650 -800 228762 480 0 FreeSans 1120 90 0 0 la_data_in[29]
+port 213 nsew signal input
+flabel metal2 s 132908 -800 133020 480 0 FreeSans 1120 90 0 0 la_data_in[2]
+port 214 nsew signal input
+flabel metal2 s 232196 -800 232308 480 0 FreeSans 1120 90 0 0 la_data_in[30]
+port 215 nsew signal input
+flabel metal2 s 235742 -800 235854 480 0 FreeSans 1120 90 0 0 la_data_in[31]
+port 216 nsew signal input
+flabel metal2 s 239288 -800 239400 480 0 FreeSans 1120 90 0 0 la_data_in[32]
+port 217 nsew signal input
+flabel metal2 s 242834 -800 242946 480 0 FreeSans 1120 90 0 0 la_data_in[33]
+port 218 nsew signal input
+flabel metal2 s 246380 -800 246492 480 0 FreeSans 1120 90 0 0 la_data_in[34]
+port 219 nsew signal input
+flabel metal2 s 249926 -800 250038 480 0 FreeSans 1120 90 0 0 la_data_in[35]
+port 220 nsew signal input
+flabel metal2 s 253472 -800 253584 480 0 FreeSans 1120 90 0 0 la_data_in[36]
+port 221 nsew signal input
+flabel metal2 s 257018 -800 257130 480 0 FreeSans 1120 90 0 0 la_data_in[37]
+port 222 nsew signal input
+flabel metal2 s 260564 -800 260676 480 0 FreeSans 1120 90 0 0 la_data_in[38]
+port 223 nsew signal input
+flabel metal2 s 264110 -800 264222 480 0 FreeSans 1120 90 0 0 la_data_in[39]
+port 224 nsew signal input
+flabel metal2 s 136454 -800 136566 480 0 FreeSans 1120 90 0 0 la_data_in[3]
+port 225 nsew signal input
+flabel metal2 s 267656 -800 267768 480 0 FreeSans 1120 90 0 0 la_data_in[40]
+port 226 nsew signal input
+flabel metal2 s 271202 -800 271314 480 0 FreeSans 1120 90 0 0 la_data_in[41]
+port 227 nsew signal input
+flabel metal2 s 274748 -800 274860 480 0 FreeSans 1120 90 0 0 la_data_in[42]
+port 228 nsew signal input
+flabel metal2 s 278294 -800 278406 480 0 FreeSans 1120 90 0 0 la_data_in[43]
+port 229 nsew signal input
+flabel metal2 s 281840 -800 281952 480 0 FreeSans 1120 90 0 0 la_data_in[44]
+port 230 nsew signal input
+flabel metal2 s 285386 -800 285498 480 0 FreeSans 1120 90 0 0 la_data_in[45]
+port 231 nsew signal input
+flabel metal2 s 288932 -800 289044 480 0 FreeSans 1120 90 0 0 la_data_in[46]
+port 232 nsew signal input
+flabel metal2 s 292478 -800 292590 480 0 FreeSans 1120 90 0 0 la_data_in[47]
+port 233 nsew signal input
+flabel metal2 s 296024 -800 296136 480 0 FreeSans 1120 90 0 0 la_data_in[48]
+port 234 nsew signal input
+flabel metal2 s 299570 -800 299682 480 0 FreeSans 1120 90 0 0 la_data_in[49]
+port 235 nsew signal input
+flabel metal2 s 140000 -800 140112 480 0 FreeSans 1120 90 0 0 la_data_in[4]
+port 236 nsew signal input
+flabel metal2 s 303116 -800 303228 480 0 FreeSans 1120 90 0 0 la_data_in[50]
+port 237 nsew signal input
+flabel metal2 s 306662 -800 306774 480 0 FreeSans 1120 90 0 0 la_data_in[51]
+port 238 nsew signal input
+flabel metal2 s 310208 -800 310320 480 0 FreeSans 1120 90 0 0 la_data_in[52]
+port 239 nsew signal input
+flabel metal2 s 313754 -800 313866 480 0 FreeSans 1120 90 0 0 la_data_in[53]
+port 240 nsew signal input
+flabel metal2 s 317300 -800 317412 480 0 FreeSans 1120 90 0 0 la_data_in[54]
+port 241 nsew signal input
+flabel metal2 s 320846 -800 320958 480 0 FreeSans 1120 90 0 0 la_data_in[55]
+port 242 nsew signal input
+flabel metal2 s 324392 -800 324504 480 0 FreeSans 1120 90 0 0 la_data_in[56]
+port 243 nsew signal input
+flabel metal2 s 327938 -800 328050 480 0 FreeSans 1120 90 0 0 la_data_in[57]
+port 244 nsew signal input
+flabel metal2 s 331484 -800 331596 480 0 FreeSans 1120 90 0 0 la_data_in[58]
+port 245 nsew signal input
+flabel metal2 s 335030 -800 335142 480 0 FreeSans 1120 90 0 0 la_data_in[59]
+port 246 nsew signal input
+flabel metal2 s 143546 -800 143658 480 0 FreeSans 1120 90 0 0 la_data_in[5]
+port 247 nsew signal input
+flabel metal2 s 338576 -800 338688 480 0 FreeSans 1120 90 0 0 la_data_in[60]
+port 248 nsew signal input
+flabel metal2 s 342122 -800 342234 480 0 FreeSans 1120 90 0 0 la_data_in[61]
+port 249 nsew signal input
+flabel metal2 s 345668 -800 345780 480 0 FreeSans 1120 90 0 0 la_data_in[62]
+port 250 nsew signal input
+flabel metal2 s 349214 -800 349326 480 0 FreeSans 1120 90 0 0 la_data_in[63]
+port 251 nsew signal input
+flabel metal2 s 352760 -800 352872 480 0 FreeSans 1120 90 0 0 la_data_in[64]
+port 252 nsew signal input
+flabel metal2 s 356306 -800 356418 480 0 FreeSans 1120 90 0 0 la_data_in[65]
+port 253 nsew signal input
+flabel metal2 s 359852 -800 359964 480 0 FreeSans 1120 90 0 0 la_data_in[66]
+port 254 nsew signal input
+flabel metal2 s 363398 -800 363510 480 0 FreeSans 1120 90 0 0 la_data_in[67]
+port 255 nsew signal input
+flabel metal2 s 366944 -800 367056 480 0 FreeSans 1120 90 0 0 la_data_in[68]
+port 256 nsew signal input
+flabel metal2 s 370490 -800 370602 480 0 FreeSans 1120 90 0 0 la_data_in[69]
+port 257 nsew signal input
+flabel metal2 s 147092 -800 147204 480 0 FreeSans 1120 90 0 0 la_data_in[6]
+port 258 nsew signal input
+flabel metal2 s 374036 -800 374148 480 0 FreeSans 1120 90 0 0 la_data_in[70]
+port 259 nsew signal input
+flabel metal2 s 377582 -800 377694 480 0 FreeSans 1120 90 0 0 la_data_in[71]
+port 260 nsew signal input
+flabel metal2 s 381128 -800 381240 480 0 FreeSans 1120 90 0 0 la_data_in[72]
+port 261 nsew signal input
+flabel metal2 s 384674 -800 384786 480 0 FreeSans 1120 90 0 0 la_data_in[73]
+port 262 nsew signal input
+flabel metal2 s 388220 -800 388332 480 0 FreeSans 1120 90 0 0 la_data_in[74]
+port 263 nsew signal input
+flabel metal2 s 391766 -800 391878 480 0 FreeSans 1120 90 0 0 la_data_in[75]
+port 264 nsew signal input
+flabel metal2 s 395312 -800 395424 480 0 FreeSans 1120 90 0 0 la_data_in[76]
+port 265 nsew signal input
+flabel metal2 s 398858 -800 398970 480 0 FreeSans 1120 90 0 0 la_data_in[77]
+port 266 nsew signal input
+flabel metal2 s 402404 -800 402516 480 0 FreeSans 1120 90 0 0 la_data_in[78]
+port 267 nsew signal input
+flabel metal2 s 405950 -800 406062 480 0 FreeSans 1120 90 0 0 la_data_in[79]
+port 268 nsew signal input
+flabel metal2 s 150638 -800 150750 480 0 FreeSans 1120 90 0 0 la_data_in[7]
+port 269 nsew signal input
+flabel metal2 s 409496 -800 409608 480 0 FreeSans 1120 90 0 0 la_data_in[80]
+port 270 nsew signal input
+flabel metal2 s 413042 -800 413154 480 0 FreeSans 1120 90 0 0 la_data_in[81]
+port 271 nsew signal input
+flabel metal2 s 416588 -800 416700 480 0 FreeSans 1120 90 0 0 la_data_in[82]
+port 272 nsew signal input
+flabel metal2 s 420134 -800 420246 480 0 FreeSans 1120 90 0 0 la_data_in[83]
+port 273 nsew signal input
+flabel metal2 s 423680 -800 423792 480 0 FreeSans 1120 90 0 0 la_data_in[84]
+port 274 nsew signal input
+flabel metal2 s 427226 -800 427338 480 0 FreeSans 1120 90 0 0 la_data_in[85]
+port 275 nsew signal input
+flabel metal2 s 430772 -800 430884 480 0 FreeSans 1120 90 0 0 la_data_in[86]
+port 276 nsew signal input
+flabel metal2 s 434318 -800 434430 480 0 FreeSans 1120 90 0 0 la_data_in[87]
+port 277 nsew signal input
+flabel metal2 s 437864 -800 437976 480 0 FreeSans 1120 90 0 0 la_data_in[88]
+port 278 nsew signal input
+flabel metal2 s 441410 -800 441522 480 0 FreeSans 1120 90 0 0 la_data_in[89]
+port 279 nsew signal input
+flabel metal2 s 154184 -800 154296 480 0 FreeSans 1120 90 0 0 la_data_in[8]
+port 280 nsew signal input
+flabel metal2 s 444956 -800 445068 480 0 FreeSans 1120 90 0 0 la_data_in[90]
+port 281 nsew signal input
+flabel metal2 s 448502 -800 448614 480 0 FreeSans 1120 90 0 0 la_data_in[91]
+port 282 nsew signal input
+flabel metal2 s 452048 -800 452160 480 0 FreeSans 1120 90 0 0 la_data_in[92]
+port 283 nsew signal input
+flabel metal2 s 455594 -800 455706 480 0 FreeSans 1120 90 0 0 la_data_in[93]
+port 284 nsew signal input
+flabel metal2 s 459140 -800 459252 480 0 FreeSans 1120 90 0 0 la_data_in[94]
+port 285 nsew signal input
+flabel metal2 s 462686 -800 462798 480 0 FreeSans 1120 90 0 0 la_data_in[95]
+port 286 nsew signal input
+flabel metal2 s 466232 -800 466344 480 0 FreeSans 1120 90 0 0 la_data_in[96]
+port 287 nsew signal input
+flabel metal2 s 469778 -800 469890 480 0 FreeSans 1120 90 0 0 la_data_in[97]
+port 288 nsew signal input
+flabel metal2 s 473324 -800 473436 480 0 FreeSans 1120 90 0 0 la_data_in[98]
+port 289 nsew signal input
+flabel metal2 s 476870 -800 476982 480 0 FreeSans 1120 90 0 0 la_data_in[99]
+port 290 nsew signal input
+flabel metal2 s 157730 -800 157842 480 0 FreeSans 1120 90 0 0 la_data_in[9]
+port 291 nsew signal input
+flabel metal2 s 126998 -800 127110 480 0 FreeSans 1120 90 0 0 la_data_out[0]
+port 292 nsew signal tristate
+flabel metal2 s 481598 -800 481710 480 0 FreeSans 1120 90 0 0 la_data_out[100]
+port 293 nsew signal tristate
+flabel metal2 s 485144 -800 485256 480 0 FreeSans 1120 90 0 0 la_data_out[101]
+port 294 nsew signal tristate
+flabel metal2 s 488690 -800 488802 480 0 FreeSans 1120 90 0 0 la_data_out[102]
+port 295 nsew signal tristate
+flabel metal2 s 492236 -800 492348 480 0 FreeSans 1120 90 0 0 la_data_out[103]
+port 296 nsew signal tristate
+flabel metal2 s 495782 -800 495894 480 0 FreeSans 1120 90 0 0 la_data_out[104]
+port 297 nsew signal tristate
+flabel metal2 s 499328 -800 499440 480 0 FreeSans 1120 90 0 0 la_data_out[105]
+port 298 nsew signal tristate
+flabel metal2 s 502874 -800 502986 480 0 FreeSans 1120 90 0 0 la_data_out[106]
+port 299 nsew signal tristate
+flabel metal2 s 506420 -800 506532 480 0 FreeSans 1120 90 0 0 la_data_out[107]
+port 300 nsew signal tristate
+flabel metal2 s 509966 -800 510078 480 0 FreeSans 1120 90 0 0 la_data_out[108]
+port 301 nsew signal tristate
+flabel metal2 s 513512 -800 513624 480 0 FreeSans 1120 90 0 0 la_data_out[109]
+port 302 nsew signal tristate
+flabel metal2 s 162458 -800 162570 480 0 FreeSans 1120 90 0 0 la_data_out[10]
+port 303 nsew signal tristate
+flabel metal2 s 517058 -800 517170 480 0 FreeSans 1120 90 0 0 la_data_out[110]
+port 304 nsew signal tristate
+flabel metal2 s 520604 -800 520716 480 0 FreeSans 1120 90 0 0 la_data_out[111]
+port 305 nsew signal tristate
+flabel metal2 s 524150 -800 524262 480 0 FreeSans 1120 90 0 0 la_data_out[112]
+port 306 nsew signal tristate
+flabel metal2 s 527696 -800 527808 480 0 FreeSans 1120 90 0 0 la_data_out[113]
+port 307 nsew signal tristate
+flabel metal2 s 531242 -800 531354 480 0 FreeSans 1120 90 0 0 la_data_out[114]
+port 308 nsew signal tristate
+flabel metal2 s 534788 -800 534900 480 0 FreeSans 1120 90 0 0 la_data_out[115]
+port 309 nsew signal tristate
+flabel metal2 s 538334 -800 538446 480 0 FreeSans 1120 90 0 0 la_data_out[116]
+port 310 nsew signal tristate
+flabel metal2 s 541880 -800 541992 480 0 FreeSans 1120 90 0 0 la_data_out[117]
+port 311 nsew signal tristate
+flabel metal2 s 545426 -800 545538 480 0 FreeSans 1120 90 0 0 la_data_out[118]
+port 312 nsew signal tristate
+flabel metal2 s 548972 -800 549084 480 0 FreeSans 1120 90 0 0 la_data_out[119]
+port 313 nsew signal tristate
+flabel metal2 s 166004 -800 166116 480 0 FreeSans 1120 90 0 0 la_data_out[11]
+port 314 nsew signal tristate
+flabel metal2 s 552518 -800 552630 480 0 FreeSans 1120 90 0 0 la_data_out[120]
+port 315 nsew signal tristate
+flabel metal2 s 556064 -800 556176 480 0 FreeSans 1120 90 0 0 la_data_out[121]
+port 316 nsew signal tristate
+flabel metal2 s 559610 -800 559722 480 0 FreeSans 1120 90 0 0 la_data_out[122]
+port 317 nsew signal tristate
+flabel metal2 s 563156 -800 563268 480 0 FreeSans 1120 90 0 0 la_data_out[123]
+port 318 nsew signal tristate
+flabel metal2 s 566702 -800 566814 480 0 FreeSans 1120 90 0 0 la_data_out[124]
+port 319 nsew signal tristate
+flabel metal2 s 570248 -800 570360 480 0 FreeSans 1120 90 0 0 la_data_out[125]
+port 320 nsew signal tristate
+flabel metal2 s 573794 -800 573906 480 0 FreeSans 1120 90 0 0 la_data_out[126]
+port 321 nsew signal tristate
+flabel metal2 s 577340 -800 577452 480 0 FreeSans 1120 90 0 0 la_data_out[127]
+port 322 nsew signal tristate
+flabel metal2 s 169550 -800 169662 480 0 FreeSans 1120 90 0 0 la_data_out[12]
+port 323 nsew signal tristate
+flabel metal2 s 173096 -800 173208 480 0 FreeSans 1120 90 0 0 la_data_out[13]
+port 324 nsew signal tristate
+flabel metal2 s 176642 -800 176754 480 0 FreeSans 1120 90 0 0 la_data_out[14]
+port 325 nsew signal tristate
+flabel metal2 s 180188 -800 180300 480 0 FreeSans 1120 90 0 0 la_data_out[15]
+port 326 nsew signal tristate
+flabel metal2 s 183734 -800 183846 480 0 FreeSans 1120 90 0 0 la_data_out[16]
+port 327 nsew signal tristate
+flabel metal2 s 187280 -800 187392 480 0 FreeSans 1120 90 0 0 la_data_out[17]
+port 328 nsew signal tristate
+flabel metal2 s 190826 -800 190938 480 0 FreeSans 1120 90 0 0 la_data_out[18]
+port 329 nsew signal tristate
+flabel metal2 s 194372 -800 194484 480 0 FreeSans 1120 90 0 0 la_data_out[19]
+port 330 nsew signal tristate
+flabel metal2 s 130544 -800 130656 480 0 FreeSans 1120 90 0 0 la_data_out[1]
+port 331 nsew signal tristate
+flabel metal2 s 197918 -800 198030 480 0 FreeSans 1120 90 0 0 la_data_out[20]
+port 332 nsew signal tristate
+flabel metal2 s 201464 -800 201576 480 0 FreeSans 1120 90 0 0 la_data_out[21]
+port 333 nsew signal tristate
+flabel metal2 s 205010 -800 205122 480 0 FreeSans 1120 90 0 0 la_data_out[22]
+port 334 nsew signal tristate
+flabel metal2 s 208556 -800 208668 480 0 FreeSans 1120 90 0 0 la_data_out[23]
+port 335 nsew signal tristate
+flabel metal2 s 212102 -800 212214 480 0 FreeSans 1120 90 0 0 la_data_out[24]
+port 336 nsew signal tristate
+flabel metal2 s 215648 -800 215760 480 0 FreeSans 1120 90 0 0 la_data_out[25]
+port 337 nsew signal tristate
+flabel metal2 s 219194 -800 219306 480 0 FreeSans 1120 90 0 0 la_data_out[26]
+port 338 nsew signal tristate
+flabel metal2 s 222740 -800 222852 480 0 FreeSans 1120 90 0 0 la_data_out[27]
+port 339 nsew signal tristate
+flabel metal2 s 226286 -800 226398 480 0 FreeSans 1120 90 0 0 la_data_out[28]
+port 340 nsew signal tristate
+flabel metal2 s 229832 -800 229944 480 0 FreeSans 1120 90 0 0 la_data_out[29]
+port 341 nsew signal tristate
+flabel metal2 s 134090 -800 134202 480 0 FreeSans 1120 90 0 0 la_data_out[2]
+port 342 nsew signal tristate
+flabel metal2 s 233378 -800 233490 480 0 FreeSans 1120 90 0 0 la_data_out[30]
+port 343 nsew signal tristate
+flabel metal2 s 236924 -800 237036 480 0 FreeSans 1120 90 0 0 la_data_out[31]
+port 344 nsew signal tristate
+flabel metal2 s 240470 -800 240582 480 0 FreeSans 1120 90 0 0 la_data_out[32]
+port 345 nsew signal tristate
+flabel metal2 s 244016 -800 244128 480 0 FreeSans 1120 90 0 0 la_data_out[33]
+port 346 nsew signal tristate
+flabel metal2 s 247562 -800 247674 480 0 FreeSans 1120 90 0 0 la_data_out[34]
+port 347 nsew signal tristate
+flabel metal2 s 251108 -800 251220 480 0 FreeSans 1120 90 0 0 la_data_out[35]
+port 348 nsew signal tristate
+flabel metal2 s 254654 -800 254766 480 0 FreeSans 1120 90 0 0 la_data_out[36]
+port 349 nsew signal tristate
+flabel metal2 s 258200 -800 258312 480 0 FreeSans 1120 90 0 0 la_data_out[37]
+port 350 nsew signal tristate
+flabel metal2 s 261746 -800 261858 480 0 FreeSans 1120 90 0 0 la_data_out[38]
+port 351 nsew signal tristate
+flabel metal2 s 265292 -800 265404 480 0 FreeSans 1120 90 0 0 la_data_out[39]
+port 352 nsew signal tristate
+flabel metal2 s 137636 -800 137748 480 0 FreeSans 1120 90 0 0 la_data_out[3]
+port 353 nsew signal tristate
+flabel metal2 s 268838 -800 268950 480 0 FreeSans 1120 90 0 0 la_data_out[40]
+port 354 nsew signal tristate
+flabel metal2 s 272384 -800 272496 480 0 FreeSans 1120 90 0 0 la_data_out[41]
+port 355 nsew signal tristate
+flabel metal2 s 275930 -800 276042 480 0 FreeSans 1120 90 0 0 la_data_out[42]
+port 356 nsew signal tristate
+flabel metal2 s 279476 -800 279588 480 0 FreeSans 1120 90 0 0 la_data_out[43]
+port 357 nsew signal tristate
+flabel metal2 s 283022 -800 283134 480 0 FreeSans 1120 90 0 0 la_data_out[44]
+port 358 nsew signal tristate
+flabel metal2 s 286568 -800 286680 480 0 FreeSans 1120 90 0 0 la_data_out[45]
+port 359 nsew signal tristate
+flabel metal2 s 290114 -800 290226 480 0 FreeSans 1120 90 0 0 la_data_out[46]
+port 360 nsew signal tristate
+flabel metal2 s 293660 -800 293772 480 0 FreeSans 1120 90 0 0 la_data_out[47]
+port 361 nsew signal tristate
+flabel metal2 s 297206 -800 297318 480 0 FreeSans 1120 90 0 0 la_data_out[48]
+port 362 nsew signal tristate
+flabel metal2 s 300752 -800 300864 480 0 FreeSans 1120 90 0 0 la_data_out[49]
+port 363 nsew signal tristate
+flabel metal2 s 141182 -800 141294 480 0 FreeSans 1120 90 0 0 la_data_out[4]
+port 364 nsew signal tristate
+flabel metal2 s 304298 -800 304410 480 0 FreeSans 1120 90 0 0 la_data_out[50]
+port 365 nsew signal tristate
+flabel metal2 s 307844 -800 307956 480 0 FreeSans 1120 90 0 0 la_data_out[51]
+port 366 nsew signal tristate
+flabel metal2 s 311390 -800 311502 480 0 FreeSans 1120 90 0 0 la_data_out[52]
+port 367 nsew signal tristate
+flabel metal2 s 314936 -800 315048 480 0 FreeSans 1120 90 0 0 la_data_out[53]
+port 368 nsew signal tristate
+flabel metal2 s 318482 -800 318594 480 0 FreeSans 1120 90 0 0 la_data_out[54]
+port 369 nsew signal tristate
+flabel metal2 s 322028 -800 322140 480 0 FreeSans 1120 90 0 0 la_data_out[55]
+port 370 nsew signal tristate
+flabel metal2 s 325574 -800 325686 480 0 FreeSans 1120 90 0 0 la_data_out[56]
+port 371 nsew signal tristate
+flabel metal2 s 329120 -800 329232 480 0 FreeSans 1120 90 0 0 la_data_out[57]
+port 372 nsew signal tristate
+flabel metal2 s 332666 -800 332778 480 0 FreeSans 1120 90 0 0 la_data_out[58]
+port 373 nsew signal tristate
+flabel metal2 s 336212 -800 336324 480 0 FreeSans 1120 90 0 0 la_data_out[59]
+port 374 nsew signal tristate
+flabel metal2 s 144728 -800 144840 480 0 FreeSans 1120 90 0 0 la_data_out[5]
+port 375 nsew signal tristate
+flabel metal2 s 339758 -800 339870 480 0 FreeSans 1120 90 0 0 la_data_out[60]
+port 376 nsew signal tristate
+flabel metal2 s 343304 -800 343416 480 0 FreeSans 1120 90 0 0 la_data_out[61]
+port 377 nsew signal tristate
+flabel metal2 s 346850 -800 346962 480 0 FreeSans 1120 90 0 0 la_data_out[62]
+port 378 nsew signal tristate
+flabel metal2 s 350396 -800 350508 480 0 FreeSans 1120 90 0 0 la_data_out[63]
+port 379 nsew signal tristate
+flabel metal2 s 353942 -800 354054 480 0 FreeSans 1120 90 0 0 la_data_out[64]
+port 380 nsew signal tristate
+flabel metal2 s 357488 -800 357600 480 0 FreeSans 1120 90 0 0 la_data_out[65]
+port 381 nsew signal tristate
+flabel metal2 s 361034 -800 361146 480 0 FreeSans 1120 90 0 0 la_data_out[66]
+port 382 nsew signal tristate
+flabel metal2 s 364580 -800 364692 480 0 FreeSans 1120 90 0 0 la_data_out[67]
+port 383 nsew signal tristate
+flabel metal2 s 368126 -800 368238 480 0 FreeSans 1120 90 0 0 la_data_out[68]
+port 384 nsew signal tristate
+flabel metal2 s 371672 -800 371784 480 0 FreeSans 1120 90 0 0 la_data_out[69]
+port 385 nsew signal tristate
+flabel metal2 s 148274 -800 148386 480 0 FreeSans 1120 90 0 0 la_data_out[6]
+port 386 nsew signal tristate
+flabel metal2 s 375218 -800 375330 480 0 FreeSans 1120 90 0 0 la_data_out[70]
+port 387 nsew signal tristate
+flabel metal2 s 378764 -800 378876 480 0 FreeSans 1120 90 0 0 la_data_out[71]
+port 388 nsew signal tristate
+flabel metal2 s 382310 -800 382422 480 0 FreeSans 1120 90 0 0 la_data_out[72]
+port 389 nsew signal tristate
+flabel metal2 s 385856 -800 385968 480 0 FreeSans 1120 90 0 0 la_data_out[73]
+port 390 nsew signal tristate
+flabel metal2 s 389402 -800 389514 480 0 FreeSans 1120 90 0 0 la_data_out[74]
+port 391 nsew signal tristate
+flabel metal2 s 392948 -800 393060 480 0 FreeSans 1120 90 0 0 la_data_out[75]
+port 392 nsew signal tristate
+flabel metal2 s 396494 -800 396606 480 0 FreeSans 1120 90 0 0 la_data_out[76]
+port 393 nsew signal tristate
+flabel metal2 s 400040 -800 400152 480 0 FreeSans 1120 90 0 0 la_data_out[77]
+port 394 nsew signal tristate
+flabel metal2 s 403586 -800 403698 480 0 FreeSans 1120 90 0 0 la_data_out[78]
+port 395 nsew signal tristate
+flabel metal2 s 407132 -800 407244 480 0 FreeSans 1120 90 0 0 la_data_out[79]
+port 396 nsew signal tristate
+flabel metal2 s 151820 -800 151932 480 0 FreeSans 1120 90 0 0 la_data_out[7]
+port 397 nsew signal tristate
+flabel metal2 s 410678 -800 410790 480 0 FreeSans 1120 90 0 0 la_data_out[80]
+port 398 nsew signal tristate
+flabel metal2 s 414224 -800 414336 480 0 FreeSans 1120 90 0 0 la_data_out[81]
+port 399 nsew signal tristate
+flabel metal2 s 417770 -800 417882 480 0 FreeSans 1120 90 0 0 la_data_out[82]
+port 400 nsew signal tristate
+flabel metal2 s 421316 -800 421428 480 0 FreeSans 1120 90 0 0 la_data_out[83]
+port 401 nsew signal tristate
+flabel metal2 s 424862 -800 424974 480 0 FreeSans 1120 90 0 0 la_data_out[84]
+port 402 nsew signal tristate
+flabel metal2 s 428408 -800 428520 480 0 FreeSans 1120 90 0 0 la_data_out[85]
+port 403 nsew signal tristate
+flabel metal2 s 431954 -800 432066 480 0 FreeSans 1120 90 0 0 la_data_out[86]
+port 404 nsew signal tristate
+flabel metal2 s 435500 -800 435612 480 0 FreeSans 1120 90 0 0 la_data_out[87]
+port 405 nsew signal tristate
+flabel metal2 s 439046 -800 439158 480 0 FreeSans 1120 90 0 0 la_data_out[88]
+port 406 nsew signal tristate
+flabel metal2 s 442592 -800 442704 480 0 FreeSans 1120 90 0 0 la_data_out[89]
+port 407 nsew signal tristate
+flabel metal2 s 155366 -800 155478 480 0 FreeSans 1120 90 0 0 la_data_out[8]
+port 408 nsew signal tristate
+flabel metal2 s 446138 -800 446250 480 0 FreeSans 1120 90 0 0 la_data_out[90]
+port 409 nsew signal tristate
+flabel metal2 s 449684 -800 449796 480 0 FreeSans 1120 90 0 0 la_data_out[91]
+port 410 nsew signal tristate
+flabel metal2 s 453230 -800 453342 480 0 FreeSans 1120 90 0 0 la_data_out[92]
+port 411 nsew signal tristate
+flabel metal2 s 456776 -800 456888 480 0 FreeSans 1120 90 0 0 la_data_out[93]
+port 412 nsew signal tristate
+flabel metal2 s 460322 -800 460434 480 0 FreeSans 1120 90 0 0 la_data_out[94]
+port 413 nsew signal tristate
+flabel metal2 s 463868 -800 463980 480 0 FreeSans 1120 90 0 0 la_data_out[95]
+port 414 nsew signal tristate
+flabel metal2 s 467414 -800 467526 480 0 FreeSans 1120 90 0 0 la_data_out[96]
+port 415 nsew signal tristate
+flabel metal2 s 470960 -800 471072 480 0 FreeSans 1120 90 0 0 la_data_out[97]
+port 416 nsew signal tristate
+flabel metal2 s 474506 -800 474618 480 0 FreeSans 1120 90 0 0 la_data_out[98]
+port 417 nsew signal tristate
+flabel metal2 s 478052 -800 478164 480 0 FreeSans 1120 90 0 0 la_data_out[99]
+port 418 nsew signal tristate
+flabel metal2 s 158912 -800 159024 480 0 FreeSans 1120 90 0 0 la_data_out[9]
+port 419 nsew signal tristate
+flabel metal2 s 128180 -800 128292 480 0 FreeSans 1120 90 0 0 la_oenb[0]
+port 420 nsew signal input
+flabel metal2 s 482780 -800 482892 480 0 FreeSans 1120 90 0 0 la_oenb[100]
+port 421 nsew signal input
+flabel metal2 s 486326 -800 486438 480 0 FreeSans 1120 90 0 0 la_oenb[101]
+port 422 nsew signal input
+flabel metal2 s 489872 -800 489984 480 0 FreeSans 1120 90 0 0 la_oenb[102]
+port 423 nsew signal input
+flabel metal2 s 493418 -800 493530 480 0 FreeSans 1120 90 0 0 la_oenb[103]
+port 424 nsew signal input
+flabel metal2 s 496964 -800 497076 480 0 FreeSans 1120 90 0 0 la_oenb[104]
+port 425 nsew signal input
+flabel metal2 s 500510 -800 500622 480 0 FreeSans 1120 90 0 0 la_oenb[105]
+port 426 nsew signal input
+flabel metal2 s 504056 -800 504168 480 0 FreeSans 1120 90 0 0 la_oenb[106]
+port 427 nsew signal input
+flabel metal2 s 507602 -800 507714 480 0 FreeSans 1120 90 0 0 la_oenb[107]
+port 428 nsew signal input
+flabel metal2 s 511148 -800 511260 480 0 FreeSans 1120 90 0 0 la_oenb[108]
+port 429 nsew signal input
+flabel metal2 s 514694 -800 514806 480 0 FreeSans 1120 90 0 0 la_oenb[109]
+port 430 nsew signal input
+flabel metal2 s 163640 -800 163752 480 0 FreeSans 1120 90 0 0 la_oenb[10]
+port 431 nsew signal input
+flabel metal2 s 518240 -800 518352 480 0 FreeSans 1120 90 0 0 la_oenb[110]
+port 432 nsew signal input
+flabel metal2 s 521786 -800 521898 480 0 FreeSans 1120 90 0 0 la_oenb[111]
+port 433 nsew signal input
+flabel metal2 s 525332 -800 525444 480 0 FreeSans 1120 90 0 0 la_oenb[112]
+port 434 nsew signal input
+flabel metal2 s 528878 -800 528990 480 0 FreeSans 1120 90 0 0 la_oenb[113]
+port 435 nsew signal input
+flabel metal2 s 532424 -800 532536 480 0 FreeSans 1120 90 0 0 la_oenb[114]
+port 436 nsew signal input
+flabel metal2 s 535970 -800 536082 480 0 FreeSans 1120 90 0 0 la_oenb[115]
+port 437 nsew signal input
+flabel metal2 s 539516 -800 539628 480 0 FreeSans 1120 90 0 0 la_oenb[116]
+port 438 nsew signal input
+flabel metal2 s 543062 -800 543174 480 0 FreeSans 1120 90 0 0 la_oenb[117]
+port 439 nsew signal input
+flabel metal2 s 546608 -800 546720 480 0 FreeSans 1120 90 0 0 la_oenb[118]
+port 440 nsew signal input
+flabel metal2 s 550154 -800 550266 480 0 FreeSans 1120 90 0 0 la_oenb[119]
+port 441 nsew signal input
+flabel metal2 s 167186 -800 167298 480 0 FreeSans 1120 90 0 0 la_oenb[11]
+port 442 nsew signal input
+flabel metal2 s 553700 -800 553812 480 0 FreeSans 1120 90 0 0 la_oenb[120]
+port 443 nsew signal input
+flabel metal2 s 557246 -800 557358 480 0 FreeSans 1120 90 0 0 la_oenb[121]
+port 444 nsew signal input
+flabel metal2 s 560792 -800 560904 480 0 FreeSans 1120 90 0 0 la_oenb[122]
+port 445 nsew signal input
+flabel metal2 s 564338 -800 564450 480 0 FreeSans 1120 90 0 0 la_oenb[123]
+port 446 nsew signal input
+flabel metal2 s 567884 -800 567996 480 0 FreeSans 1120 90 0 0 la_oenb[124]
+port 447 nsew signal input
+flabel metal2 s 571430 -800 571542 480 0 FreeSans 1120 90 0 0 la_oenb[125]
+port 448 nsew signal input
+flabel metal2 s 574976 -800 575088 480 0 FreeSans 1120 90 0 0 la_oenb[126]
+port 449 nsew signal input
+flabel metal2 s 578522 -800 578634 480 0 FreeSans 1120 90 0 0 la_oenb[127]
+port 450 nsew signal input
+flabel metal2 s 170732 -800 170844 480 0 FreeSans 1120 90 0 0 la_oenb[12]
+port 451 nsew signal input
+flabel metal2 s 174278 -800 174390 480 0 FreeSans 1120 90 0 0 la_oenb[13]
+port 452 nsew signal input
+flabel metal2 s 177824 -800 177936 480 0 FreeSans 1120 90 0 0 la_oenb[14]
+port 453 nsew signal input
+flabel metal2 s 181370 -800 181482 480 0 FreeSans 1120 90 0 0 la_oenb[15]
+port 454 nsew signal input
+flabel metal2 s 184916 -800 185028 480 0 FreeSans 1120 90 0 0 la_oenb[16]
+port 455 nsew signal input
+flabel metal2 s 188462 -800 188574 480 0 FreeSans 1120 90 0 0 la_oenb[17]
+port 456 nsew signal input
+flabel metal2 s 192008 -800 192120 480 0 FreeSans 1120 90 0 0 la_oenb[18]
+port 457 nsew signal input
+flabel metal2 s 195554 -800 195666 480 0 FreeSans 1120 90 0 0 la_oenb[19]
+port 458 nsew signal input
+flabel metal2 s 131726 -800 131838 480 0 FreeSans 1120 90 0 0 la_oenb[1]
+port 459 nsew signal input
+flabel metal2 s 199100 -800 199212 480 0 FreeSans 1120 90 0 0 la_oenb[20]
+port 460 nsew signal input
+flabel metal2 s 202646 -800 202758 480 0 FreeSans 1120 90 0 0 la_oenb[21]
+port 461 nsew signal input
+flabel metal2 s 206192 -800 206304 480 0 FreeSans 1120 90 0 0 la_oenb[22]
+port 462 nsew signal input
+flabel metal2 s 209738 -800 209850 480 0 FreeSans 1120 90 0 0 la_oenb[23]
+port 463 nsew signal input
+flabel metal2 s 213284 -800 213396 480 0 FreeSans 1120 90 0 0 la_oenb[24]
+port 464 nsew signal input
+flabel metal2 s 216830 -800 216942 480 0 FreeSans 1120 90 0 0 la_oenb[25]
+port 465 nsew signal input
+flabel metal2 s 220376 -800 220488 480 0 FreeSans 1120 90 0 0 la_oenb[26]
+port 466 nsew signal input
+flabel metal2 s 223922 -800 224034 480 0 FreeSans 1120 90 0 0 la_oenb[27]
+port 467 nsew signal input
+flabel metal2 s 227468 -800 227580 480 0 FreeSans 1120 90 0 0 la_oenb[28]
+port 468 nsew signal input
+flabel metal2 s 231014 -800 231126 480 0 FreeSans 1120 90 0 0 la_oenb[29]
+port 469 nsew signal input
+flabel metal2 s 135272 -800 135384 480 0 FreeSans 1120 90 0 0 la_oenb[2]
+port 470 nsew signal input
+flabel metal2 s 234560 -800 234672 480 0 FreeSans 1120 90 0 0 la_oenb[30]
+port 471 nsew signal input
+flabel metal2 s 238106 -800 238218 480 0 FreeSans 1120 90 0 0 la_oenb[31]
+port 472 nsew signal input
+flabel metal2 s 241652 -800 241764 480 0 FreeSans 1120 90 0 0 la_oenb[32]
+port 473 nsew signal input
+flabel metal2 s 245198 -800 245310 480 0 FreeSans 1120 90 0 0 la_oenb[33]
+port 474 nsew signal input
+flabel metal2 s 248744 -800 248856 480 0 FreeSans 1120 90 0 0 la_oenb[34]
+port 475 nsew signal input
+flabel metal2 s 252290 -800 252402 480 0 FreeSans 1120 90 0 0 la_oenb[35]
+port 476 nsew signal input
+flabel metal2 s 255836 -800 255948 480 0 FreeSans 1120 90 0 0 la_oenb[36]
+port 477 nsew signal input
+flabel metal2 s 259382 -800 259494 480 0 FreeSans 1120 90 0 0 la_oenb[37]
+port 478 nsew signal input
+flabel metal2 s 262928 -800 263040 480 0 FreeSans 1120 90 0 0 la_oenb[38]
+port 479 nsew signal input
+flabel metal2 s 266474 -800 266586 480 0 FreeSans 1120 90 0 0 la_oenb[39]
+port 480 nsew signal input
+flabel metal2 s 138818 -800 138930 480 0 FreeSans 1120 90 0 0 la_oenb[3]
+port 481 nsew signal input
+flabel metal2 s 270020 -800 270132 480 0 FreeSans 1120 90 0 0 la_oenb[40]
+port 482 nsew signal input
+flabel metal2 s 273566 -800 273678 480 0 FreeSans 1120 90 0 0 la_oenb[41]
+port 483 nsew signal input
+flabel metal2 s 277112 -800 277224 480 0 FreeSans 1120 90 0 0 la_oenb[42]
+port 484 nsew signal input
+flabel metal2 s 280658 -800 280770 480 0 FreeSans 1120 90 0 0 la_oenb[43]
+port 485 nsew signal input
+flabel metal2 s 284204 -800 284316 480 0 FreeSans 1120 90 0 0 la_oenb[44]
+port 486 nsew signal input
+flabel metal2 s 287750 -800 287862 480 0 FreeSans 1120 90 0 0 la_oenb[45]
+port 487 nsew signal input
+flabel metal2 s 291296 -800 291408 480 0 FreeSans 1120 90 0 0 la_oenb[46]
+port 488 nsew signal input
+flabel metal2 s 294842 -800 294954 480 0 FreeSans 1120 90 0 0 la_oenb[47]
+port 489 nsew signal input
+flabel metal2 s 298388 -800 298500 480 0 FreeSans 1120 90 0 0 la_oenb[48]
+port 490 nsew signal input
+flabel metal2 s 301934 -800 302046 480 0 FreeSans 1120 90 0 0 la_oenb[49]
+port 491 nsew signal input
+flabel metal2 s 142364 -800 142476 480 0 FreeSans 1120 90 0 0 la_oenb[4]
+port 492 nsew signal input
+flabel metal2 s 305480 -800 305592 480 0 FreeSans 1120 90 0 0 la_oenb[50]
+port 493 nsew signal input
+flabel metal2 s 309026 -800 309138 480 0 FreeSans 1120 90 0 0 la_oenb[51]
+port 494 nsew signal input
+flabel metal2 s 312572 -800 312684 480 0 FreeSans 1120 90 0 0 la_oenb[52]
+port 495 nsew signal input
+flabel metal2 s 316118 -800 316230 480 0 FreeSans 1120 90 0 0 la_oenb[53]
+port 496 nsew signal input
+flabel metal2 s 319664 -800 319776 480 0 FreeSans 1120 90 0 0 la_oenb[54]
+port 497 nsew signal input
+flabel metal2 s 323210 -800 323322 480 0 FreeSans 1120 90 0 0 la_oenb[55]
+port 498 nsew signal input
+flabel metal2 s 326756 -800 326868 480 0 FreeSans 1120 90 0 0 la_oenb[56]
+port 499 nsew signal input
+flabel metal2 s 330302 -800 330414 480 0 FreeSans 1120 90 0 0 la_oenb[57]
+port 500 nsew signal input
+flabel metal2 s 333848 -800 333960 480 0 FreeSans 1120 90 0 0 la_oenb[58]
+port 501 nsew signal input
+flabel metal2 s 337394 -800 337506 480 0 FreeSans 1120 90 0 0 la_oenb[59]
+port 502 nsew signal input
+flabel metal2 s 145910 -800 146022 480 0 FreeSans 1120 90 0 0 la_oenb[5]
+port 503 nsew signal input
+flabel metal2 s 340940 -800 341052 480 0 FreeSans 1120 90 0 0 la_oenb[60]
+port 504 nsew signal input
+flabel metal2 s 344486 -800 344598 480 0 FreeSans 1120 90 0 0 la_oenb[61]
+port 505 nsew signal input
+flabel metal2 s 348032 -800 348144 480 0 FreeSans 1120 90 0 0 la_oenb[62]
+port 506 nsew signal input
+flabel metal2 s 351578 -800 351690 480 0 FreeSans 1120 90 0 0 la_oenb[63]
+port 507 nsew signal input
+flabel metal2 s 355124 -800 355236 480 0 FreeSans 1120 90 0 0 la_oenb[64]
+port 508 nsew signal input
+flabel metal2 s 358670 -800 358782 480 0 FreeSans 1120 90 0 0 la_oenb[65]
+port 509 nsew signal input
+flabel metal2 s 362216 -800 362328 480 0 FreeSans 1120 90 0 0 la_oenb[66]
+port 510 nsew signal input
+flabel metal2 s 365762 -800 365874 480 0 FreeSans 1120 90 0 0 la_oenb[67]
+port 511 nsew signal input
+flabel metal2 s 369308 -800 369420 480 0 FreeSans 1120 90 0 0 la_oenb[68]
+port 512 nsew signal input
+flabel metal2 s 372854 -800 372966 480 0 FreeSans 1120 90 0 0 la_oenb[69]
+port 513 nsew signal input
+flabel metal2 s 149456 -800 149568 480 0 FreeSans 1120 90 0 0 la_oenb[6]
+port 514 nsew signal input
+flabel metal2 s 376400 -800 376512 480 0 FreeSans 1120 90 0 0 la_oenb[70]
+port 515 nsew signal input
+flabel metal2 s 379946 -800 380058 480 0 FreeSans 1120 90 0 0 la_oenb[71]
+port 516 nsew signal input
+flabel metal2 s 383492 -800 383604 480 0 FreeSans 1120 90 0 0 la_oenb[72]
+port 517 nsew signal input
+flabel metal2 s 387038 -800 387150 480 0 FreeSans 1120 90 0 0 la_oenb[73]
+port 518 nsew signal input
+flabel metal2 s 390584 -800 390696 480 0 FreeSans 1120 90 0 0 la_oenb[74]
+port 519 nsew signal input
+flabel metal2 s 394130 -800 394242 480 0 FreeSans 1120 90 0 0 la_oenb[75]
+port 520 nsew signal input
+flabel metal2 s 397676 -800 397788 480 0 FreeSans 1120 90 0 0 la_oenb[76]
+port 521 nsew signal input
+flabel metal2 s 401222 -800 401334 480 0 FreeSans 1120 90 0 0 la_oenb[77]
+port 522 nsew signal input
+flabel metal2 s 404768 -800 404880 480 0 FreeSans 1120 90 0 0 la_oenb[78]
+port 523 nsew signal input
+flabel metal2 s 408314 -800 408426 480 0 FreeSans 1120 90 0 0 la_oenb[79]
+port 524 nsew signal input
+flabel metal2 s 153002 -800 153114 480 0 FreeSans 1120 90 0 0 la_oenb[7]
+port 525 nsew signal input
+flabel metal2 s 411860 -800 411972 480 0 FreeSans 1120 90 0 0 la_oenb[80]
+port 526 nsew signal input
+flabel metal2 s 415406 -800 415518 480 0 FreeSans 1120 90 0 0 la_oenb[81]
+port 527 nsew signal input
+flabel metal2 s 418952 -800 419064 480 0 FreeSans 1120 90 0 0 la_oenb[82]
+port 528 nsew signal input
+flabel metal2 s 422498 -800 422610 480 0 FreeSans 1120 90 0 0 la_oenb[83]
+port 529 nsew signal input
+flabel metal2 s 426044 -800 426156 480 0 FreeSans 1120 90 0 0 la_oenb[84]
+port 530 nsew signal input
+flabel metal2 s 429590 -800 429702 480 0 FreeSans 1120 90 0 0 la_oenb[85]
+port 531 nsew signal input
+flabel metal2 s 433136 -800 433248 480 0 FreeSans 1120 90 0 0 la_oenb[86]
+port 532 nsew signal input
+flabel metal2 s 436682 -800 436794 480 0 FreeSans 1120 90 0 0 la_oenb[87]
+port 533 nsew signal input
+flabel metal2 s 440228 -800 440340 480 0 FreeSans 1120 90 0 0 la_oenb[88]
+port 534 nsew signal input
+flabel metal2 s 443774 -800 443886 480 0 FreeSans 1120 90 0 0 la_oenb[89]
+port 535 nsew signal input
+flabel metal2 s 156548 -800 156660 480 0 FreeSans 1120 90 0 0 la_oenb[8]
+port 536 nsew signal input
+flabel metal2 s 447320 -800 447432 480 0 FreeSans 1120 90 0 0 la_oenb[90]
+port 537 nsew signal input
+flabel metal2 s 450866 -800 450978 480 0 FreeSans 1120 90 0 0 la_oenb[91]
+port 538 nsew signal input
+flabel metal2 s 454412 -800 454524 480 0 FreeSans 1120 90 0 0 la_oenb[92]
+port 539 nsew signal input
+flabel metal2 s 457958 -800 458070 480 0 FreeSans 1120 90 0 0 la_oenb[93]
+port 540 nsew signal input
+flabel metal2 s 461504 -800 461616 480 0 FreeSans 1120 90 0 0 la_oenb[94]
+port 541 nsew signal input
+flabel metal2 s 465050 -800 465162 480 0 FreeSans 1120 90 0 0 la_oenb[95]
+port 542 nsew signal input
+flabel metal2 s 468596 -800 468708 480 0 FreeSans 1120 90 0 0 la_oenb[96]
+port 543 nsew signal input
+flabel metal2 s 472142 -800 472254 480 0 FreeSans 1120 90 0 0 la_oenb[97]
+port 544 nsew signal input
+flabel metal2 s 475688 -800 475800 480 0 FreeSans 1120 90 0 0 la_oenb[98]
+port 545 nsew signal input
+flabel metal2 s 479234 -800 479346 480 0 FreeSans 1120 90 0 0 la_oenb[99]
+port 546 nsew signal input
+flabel metal2 s 160094 -800 160206 480 0 FreeSans 1120 90 0 0 la_oenb[9]
+port 547 nsew signal input
+flabel metal2 s 579704 -800 579816 480 0 FreeSans 1120 90 0 0 user_clock2
+port 548 nsew signal input
+flabel metal2 s 580886 -800 580998 480 0 FreeSans 1120 90 0 0 user_irq[0]
+port 549 nsew signal tristate
+flabel metal2 s 582068 -800 582180 480 0 FreeSans 1120 90 0 0 user_irq[1]
+port 550 nsew signal tristate
+flabel metal2 s 583250 -800 583362 480 0 FreeSans 1120 90 0 0 user_irq[2]
+port 551 nsew signal tristate
+flabel metal3 s 582340 639784 584800 644584 0 FreeSans 1120 0 0 0 vccd1
+port 552 nsew signal bidirectional
+flabel metal3 s 582340 629784 584800 634584 0 FreeSans 1120 0 0 0 vccd1
+port 553 nsew signal bidirectional
+flabel metal3 s 0 643842 1660 648642 0 FreeSans 1120 0 0 0 vccd2
+port 554 nsew signal bidirectional
+flabel metal3 s 0 633842 1660 638642 0 FreeSans 1120 0 0 0 vccd2
+port 555 nsew signal bidirectional
+flabel metal3 s 582340 540562 584800 545362 0 FreeSans 1120 0 0 0 vdda1
+port 556 nsew signal bidirectional
+flabel metal3 s 582340 550562 584800 555362 0 FreeSans 1120 0 0 0 vdda1
+port 557 nsew signal bidirectional
+flabel metal3 s 582340 235230 584800 240030 0 FreeSans 1120 0 0 0 vdda1
+port 558 nsew signal bidirectional
+flabel metal3 s 582340 225230 584800 230030 0 FreeSans 1120 0 0 0 vdda1
+port 559 nsew signal bidirectional
+flabel metal3 s 0 204888 1660 209688 0 FreeSans 1120 0 0 0 vdda2
+port 560 nsew signal bidirectional
+flabel metal3 s 0 214888 1660 219688 0 FreeSans 1120 0 0 0 vdda2
+port 561 nsew signal bidirectional
+flabel metal3 s 520594 702340 525394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 562 nsew signal bidirectional
+flabel metal3 s 510594 702340 515394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 563 nsew signal bidirectional
+flabel metal3 s 582340 146830 584800 151630 0 FreeSans 1120 0 0 0 vssa1
+port 564 nsew signal bidirectional
+flabel metal3 s 582340 136830 584800 141630 0 FreeSans 1120 0 0 0 vssa1
+port 565 nsew signal bidirectional
+flabel metal3 s 0 559442 1660 564242 0 FreeSans 1120 0 0 0 vssa2
+port 566 nsew signal bidirectional
+flabel metal3 s 0 549442 1660 554242 0 FreeSans 1120 0 0 0 vssa2
+port 567 nsew signal bidirectional
+flabel metal3 s 0 172888 1660 177688 0 FreeSans 1120 0 0 0 vssd2
+port 570 nsew signal bidirectional
+flabel metal3 s 0 162888 1660 167688 0 FreeSans 1120 0 0 0 vssd2
+port 571 nsew signal bidirectional
+flabel metal2 s 524 -800 636 480 0 FreeSans 1120 90 0 0 wb_clk_i
+port 572 nsew signal input
+flabel metal2 s 1706 -800 1818 480 0 FreeSans 1120 90 0 0 wb_rst_i
+port 573 nsew signal input
+flabel metal2 s 2888 -800 3000 480 0 FreeSans 1120 90 0 0 wbs_ack_o
+port 574 nsew signal tristate
+flabel metal2 s 7616 -800 7728 480 0 FreeSans 1120 90 0 0 wbs_adr_i[0]
+port 575 nsew signal input
+flabel metal2 s 47804 -800 47916 480 0 FreeSans 1120 90 0 0 wbs_adr_i[10]
+port 576 nsew signal input
+flabel metal2 s 51350 -800 51462 480 0 FreeSans 1120 90 0 0 wbs_adr_i[11]
+port 577 nsew signal input
+flabel metal2 s 54896 -800 55008 480 0 FreeSans 1120 90 0 0 wbs_adr_i[12]
+port 578 nsew signal input
+flabel metal2 s 58442 -800 58554 480 0 FreeSans 1120 90 0 0 wbs_adr_i[13]
+port 579 nsew signal input
+flabel metal2 s 61988 -800 62100 480 0 FreeSans 1120 90 0 0 wbs_adr_i[14]
+port 580 nsew signal input
+flabel metal2 s 65534 -800 65646 480 0 FreeSans 1120 90 0 0 wbs_adr_i[15]
+port 581 nsew signal input
+flabel metal2 s 69080 -800 69192 480 0 FreeSans 1120 90 0 0 wbs_adr_i[16]
+port 582 nsew signal input
+flabel metal2 s 72626 -800 72738 480 0 FreeSans 1120 90 0 0 wbs_adr_i[17]
+port 583 nsew signal input
+flabel metal2 s 76172 -800 76284 480 0 FreeSans 1120 90 0 0 wbs_adr_i[18]
+port 584 nsew signal input
+flabel metal2 s 79718 -800 79830 480 0 FreeSans 1120 90 0 0 wbs_adr_i[19]
+port 585 nsew signal input
+flabel metal2 s 12344 -800 12456 480 0 FreeSans 1120 90 0 0 wbs_adr_i[1]
+port 586 nsew signal input
+flabel metal2 s 83264 -800 83376 480 0 FreeSans 1120 90 0 0 wbs_adr_i[20]
+port 587 nsew signal input
+flabel metal2 s 86810 -800 86922 480 0 FreeSans 1120 90 0 0 wbs_adr_i[21]
+port 588 nsew signal input
+flabel metal2 s 90356 -800 90468 480 0 FreeSans 1120 90 0 0 wbs_adr_i[22]
+port 589 nsew signal input
+flabel metal2 s 93902 -800 94014 480 0 FreeSans 1120 90 0 0 wbs_adr_i[23]
+port 590 nsew signal input
+flabel metal2 s 97448 -800 97560 480 0 FreeSans 1120 90 0 0 wbs_adr_i[24]
+port 591 nsew signal input
+flabel metal2 s 100994 -800 101106 480 0 FreeSans 1120 90 0 0 wbs_adr_i[25]
+port 592 nsew signal input
+flabel metal2 s 104540 -800 104652 480 0 FreeSans 1120 90 0 0 wbs_adr_i[26]
+port 593 nsew signal input
+flabel metal2 s 108086 -800 108198 480 0 FreeSans 1120 90 0 0 wbs_adr_i[27]
+port 594 nsew signal input
+flabel metal2 s 111632 -800 111744 480 0 FreeSans 1120 90 0 0 wbs_adr_i[28]
+port 595 nsew signal input
+flabel metal2 s 115178 -800 115290 480 0 FreeSans 1120 90 0 0 wbs_adr_i[29]
+port 596 nsew signal input
+flabel metal2 s 17072 -800 17184 480 0 FreeSans 1120 90 0 0 wbs_adr_i[2]
+port 597 nsew signal input
+flabel metal2 s 118724 -800 118836 480 0 FreeSans 1120 90 0 0 wbs_adr_i[30]
+port 598 nsew signal input
+flabel metal2 s 122270 -800 122382 480 0 FreeSans 1120 90 0 0 wbs_adr_i[31]
+port 599 nsew signal input
+flabel metal2 s 21800 -800 21912 480 0 FreeSans 1120 90 0 0 wbs_adr_i[3]
+port 600 nsew signal input
+flabel metal2 s 26528 -800 26640 480 0 FreeSans 1120 90 0 0 wbs_adr_i[4]
+port 601 nsew signal input
+flabel metal2 s 30074 -800 30186 480 0 FreeSans 1120 90 0 0 wbs_adr_i[5]
+port 602 nsew signal input
+flabel metal2 s 33620 -800 33732 480 0 FreeSans 1120 90 0 0 wbs_adr_i[6]
+port 603 nsew signal input
+flabel metal2 s 37166 -800 37278 480 0 FreeSans 1120 90 0 0 wbs_adr_i[7]
+port 604 nsew signal input
+flabel metal2 s 40712 -800 40824 480 0 FreeSans 1120 90 0 0 wbs_adr_i[8]
+port 605 nsew signal input
+flabel metal2 s 44258 -800 44370 480 0 FreeSans 1120 90 0 0 wbs_adr_i[9]
+port 606 nsew signal input
+flabel metal2 s 4070 -800 4182 480 0 FreeSans 1120 90 0 0 wbs_cyc_i
+port 607 nsew signal input
+flabel metal2 s 8798 -800 8910 480 0 FreeSans 1120 90 0 0 wbs_dat_i[0]
+port 608 nsew signal input
+flabel metal2 s 48986 -800 49098 480 0 FreeSans 1120 90 0 0 wbs_dat_i[10]
+port 609 nsew signal input
+flabel metal2 s 52532 -800 52644 480 0 FreeSans 1120 90 0 0 wbs_dat_i[11]
+port 610 nsew signal input
+flabel metal2 s 56078 -800 56190 480 0 FreeSans 1120 90 0 0 wbs_dat_i[12]
+port 611 nsew signal input
+flabel metal2 s 59624 -800 59736 480 0 FreeSans 1120 90 0 0 wbs_dat_i[13]
+port 612 nsew signal input
+flabel metal2 s 63170 -800 63282 480 0 FreeSans 1120 90 0 0 wbs_dat_i[14]
+port 613 nsew signal input
+flabel metal2 s 66716 -800 66828 480 0 FreeSans 1120 90 0 0 wbs_dat_i[15]
+port 614 nsew signal input
+flabel metal2 s 70262 -800 70374 480 0 FreeSans 1120 90 0 0 wbs_dat_i[16]
+port 615 nsew signal input
+flabel metal2 s 73808 -800 73920 480 0 FreeSans 1120 90 0 0 wbs_dat_i[17]
+port 616 nsew signal input
+flabel metal2 s 77354 -800 77466 480 0 FreeSans 1120 90 0 0 wbs_dat_i[18]
+port 617 nsew signal input
+flabel metal2 s 80900 -800 81012 480 0 FreeSans 1120 90 0 0 wbs_dat_i[19]
+port 618 nsew signal input
+flabel metal2 s 13526 -800 13638 480 0 FreeSans 1120 90 0 0 wbs_dat_i[1]
+port 619 nsew signal input
+flabel metal2 s 84446 -800 84558 480 0 FreeSans 1120 90 0 0 wbs_dat_i[20]
+port 620 nsew signal input
+flabel metal2 s 87992 -800 88104 480 0 FreeSans 1120 90 0 0 wbs_dat_i[21]
+port 621 nsew signal input
+flabel metal2 s 91538 -800 91650 480 0 FreeSans 1120 90 0 0 wbs_dat_i[22]
+port 622 nsew signal input
+flabel metal2 s 95084 -800 95196 480 0 FreeSans 1120 90 0 0 wbs_dat_i[23]
+port 623 nsew signal input
+flabel metal2 s 98630 -800 98742 480 0 FreeSans 1120 90 0 0 wbs_dat_i[24]
+port 624 nsew signal input
+flabel metal2 s 102176 -800 102288 480 0 FreeSans 1120 90 0 0 wbs_dat_i[25]
+port 625 nsew signal input
+flabel metal2 s 105722 -800 105834 480 0 FreeSans 1120 90 0 0 wbs_dat_i[26]
+port 626 nsew signal input
+flabel metal2 s 109268 -800 109380 480 0 FreeSans 1120 90 0 0 wbs_dat_i[27]
+port 627 nsew signal input
+flabel metal2 s 112814 -800 112926 480 0 FreeSans 1120 90 0 0 wbs_dat_i[28]
+port 628 nsew signal input
+flabel metal2 s 116360 -800 116472 480 0 FreeSans 1120 90 0 0 wbs_dat_i[29]
+port 629 nsew signal input
+flabel metal2 s 18254 -800 18366 480 0 FreeSans 1120 90 0 0 wbs_dat_i[2]
+port 630 nsew signal input
+flabel metal2 s 119906 -800 120018 480 0 FreeSans 1120 90 0 0 wbs_dat_i[30]
+port 631 nsew signal input
+flabel metal2 s 123452 -800 123564 480 0 FreeSans 1120 90 0 0 wbs_dat_i[31]
+port 632 nsew signal input
+flabel metal2 s 22982 -800 23094 480 0 FreeSans 1120 90 0 0 wbs_dat_i[3]
+port 633 nsew signal input
+flabel metal2 s 27710 -800 27822 480 0 FreeSans 1120 90 0 0 wbs_dat_i[4]
+port 634 nsew signal input
+flabel metal2 s 31256 -800 31368 480 0 FreeSans 1120 90 0 0 wbs_dat_i[5]
+port 635 nsew signal input
+flabel metal2 s 34802 -800 34914 480 0 FreeSans 1120 90 0 0 wbs_dat_i[6]
+port 636 nsew signal input
+flabel metal2 s 38348 -800 38460 480 0 FreeSans 1120 90 0 0 wbs_dat_i[7]
+port 637 nsew signal input
+flabel metal2 s 41894 -800 42006 480 0 FreeSans 1120 90 0 0 wbs_dat_i[8]
+port 638 nsew signal input
+flabel metal2 s 45440 -800 45552 480 0 FreeSans 1120 90 0 0 wbs_dat_i[9]
+port 639 nsew signal input
+flabel metal2 s 9980 -800 10092 480 0 FreeSans 1120 90 0 0 wbs_dat_o[0]
+port 640 nsew signal tristate
+flabel metal2 s 50168 -800 50280 480 0 FreeSans 1120 90 0 0 wbs_dat_o[10]
+port 641 nsew signal tristate
+flabel metal2 s 53714 -800 53826 480 0 FreeSans 1120 90 0 0 wbs_dat_o[11]
+port 642 nsew signal tristate
+flabel metal2 s 57260 -800 57372 480 0 FreeSans 1120 90 0 0 wbs_dat_o[12]
+port 643 nsew signal tristate
+flabel metal2 s 60806 -800 60918 480 0 FreeSans 1120 90 0 0 wbs_dat_o[13]
+port 644 nsew signal tristate
+flabel metal2 s 64352 -800 64464 480 0 FreeSans 1120 90 0 0 wbs_dat_o[14]
+port 645 nsew signal tristate
+flabel metal2 s 67898 -800 68010 480 0 FreeSans 1120 90 0 0 wbs_dat_o[15]
+port 646 nsew signal tristate
+flabel metal2 s 71444 -800 71556 480 0 FreeSans 1120 90 0 0 wbs_dat_o[16]
+port 647 nsew signal tristate
+flabel metal2 s 74990 -800 75102 480 0 FreeSans 1120 90 0 0 wbs_dat_o[17]
+port 648 nsew signal tristate
+flabel metal2 s 78536 -800 78648 480 0 FreeSans 1120 90 0 0 wbs_dat_o[18]
+port 649 nsew signal tristate
+flabel metal2 s 82082 -800 82194 480 0 FreeSans 1120 90 0 0 wbs_dat_o[19]
+port 650 nsew signal tristate
+flabel metal2 s 14708 -800 14820 480 0 FreeSans 1120 90 0 0 wbs_dat_o[1]
+port 651 nsew signal tristate
+flabel metal2 s 85628 -800 85740 480 0 FreeSans 1120 90 0 0 wbs_dat_o[20]
+port 652 nsew signal tristate
+flabel metal2 s 89174 -800 89286 480 0 FreeSans 1120 90 0 0 wbs_dat_o[21]
+port 653 nsew signal tristate
+flabel metal2 s 92720 -800 92832 480 0 FreeSans 1120 90 0 0 wbs_dat_o[22]
+port 654 nsew signal tristate
+flabel metal2 s 96266 -800 96378 480 0 FreeSans 1120 90 0 0 wbs_dat_o[23]
+port 655 nsew signal tristate
+flabel metal2 s 99812 -800 99924 480 0 FreeSans 1120 90 0 0 wbs_dat_o[24]
+port 656 nsew signal tristate
+flabel metal2 s 103358 -800 103470 480 0 FreeSans 1120 90 0 0 wbs_dat_o[25]
+port 657 nsew signal tristate
+flabel metal2 s 106904 -800 107016 480 0 FreeSans 1120 90 0 0 wbs_dat_o[26]
+port 658 nsew signal tristate
+flabel metal2 s 110450 -800 110562 480 0 FreeSans 1120 90 0 0 wbs_dat_o[27]
+port 659 nsew signal tristate
+flabel metal2 s 113996 -800 114108 480 0 FreeSans 1120 90 0 0 wbs_dat_o[28]
+port 660 nsew signal tristate
+flabel metal2 s 117542 -800 117654 480 0 FreeSans 1120 90 0 0 wbs_dat_o[29]
+port 661 nsew signal tristate
+flabel metal2 s 19436 -800 19548 480 0 FreeSans 1120 90 0 0 wbs_dat_o[2]
+port 662 nsew signal tristate
+flabel metal2 s 121088 -800 121200 480 0 FreeSans 1120 90 0 0 wbs_dat_o[30]
+port 663 nsew signal tristate
+flabel metal2 s 124634 -800 124746 480 0 FreeSans 1120 90 0 0 wbs_dat_o[31]
+port 664 nsew signal tristate
+flabel metal2 s 24164 -800 24276 480 0 FreeSans 1120 90 0 0 wbs_dat_o[3]
+port 665 nsew signal tristate
+flabel metal2 s 28892 -800 29004 480 0 FreeSans 1120 90 0 0 wbs_dat_o[4]
+port 666 nsew signal tristate
+flabel metal2 s 32438 -800 32550 480 0 FreeSans 1120 90 0 0 wbs_dat_o[5]
+port 667 nsew signal tristate
+flabel metal2 s 35984 -800 36096 480 0 FreeSans 1120 90 0 0 wbs_dat_o[6]
+port 668 nsew signal tristate
+flabel metal2 s 39530 -800 39642 480 0 FreeSans 1120 90 0 0 wbs_dat_o[7]
+port 669 nsew signal tristate
+flabel metal2 s 43076 -800 43188 480 0 FreeSans 1120 90 0 0 wbs_dat_o[8]
+port 670 nsew signal tristate
+flabel metal2 s 46622 -800 46734 480 0 FreeSans 1120 90 0 0 wbs_dat_o[9]
+port 671 nsew signal tristate
+flabel metal2 s 11162 -800 11274 480 0 FreeSans 1120 90 0 0 wbs_sel_i[0]
+port 672 nsew signal input
+flabel metal2 s 15890 -800 16002 480 0 FreeSans 1120 90 0 0 wbs_sel_i[1]
+port 673 nsew signal input
+flabel metal2 s 20618 -800 20730 480 0 FreeSans 1120 90 0 0 wbs_sel_i[2]
+port 674 nsew signal input
+flabel metal2 s 25346 -800 25458 480 0 FreeSans 1120 90 0 0 wbs_sel_i[3]
+port 675 nsew signal input
+flabel metal2 s 5252 -800 5364 480 0 FreeSans 1120 90 0 0 wbs_stb_i
+port 676 nsew signal input
+flabel metal2 s 6434 -800 6546 480 0 FreeSans 1120 90 0 0 wbs_we_i
+port 677 nsew signal input
+flabel metal3 s 582340 181430 584800 186230 0 FreeSans 1120 0 0 0 vssd1
+port 569 nsew signal bidirectional
+flabel metal3 s 582340 191430 584800 196230 0 FreeSans 1120 0 0 0 vssd1
+port 568 nsew signal bidirectional
+rlabel metal4 559206 641470 559206 641470 1 VDD
+rlabel metal5 524812 682428 524812 682428 3 GND
+rlabel metal5 217310 693970 217310 693970 7 Vp
+rlabel metal3 68152 698908 68152 698908 7 CLK
+rlabel metal3 120128 689268 120128 689268 7 CLKBAR
+rlabel metal3 465398 698900 465398 698900 7 Outp
+rlabel metal3 413390 699678 413390 699678 7 Outn
+rlabel metal3 438920 662050 438920 662050 7 L1
+rlabel metal3 447318 662074 447318 662074 7 L2
+rlabel metal3 571616 691292 571616 691292 3 Iin
+rlabel metal1 s 448448 591294 448544 591662 3 VGND
+port 2 nsew ground bidirectional abutment
+rlabel metal5 165554 699664 165554 699664 7 Vn
+flabel metal3 s 165596 702300 170596 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal3 s 175896 702300 180896 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+<< properties >>
+string FIXED_BBOX 0 0 584000 704000
+<< end >>
diff --git a/mag/user_analog_project_wrapper.spice b/mag/user_analog_project_wrapper.spice
new file mode 100644
index 0000000..94268bf
--- /dev/null
+++ b/mag/user_analog_project_wrapper.spice
@@ -0,0 +1,407 @@
+* SPICE3 file created from user_analog_project_wrapper.ext - technology: sky130A
+
+.subckt sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y a_n100_n100# w_n238_n238#
+D0 w_n238_n238# a_n100_n100# sky130_fd_pr__diode_pw2nd_05v5 pj=4e+06u area=1e+12p
+.ends
+
+.subckt sky130_fd_pr__diode_pd2nw_05v5_G4XDRY w_n376_n376# a_n100_n100# w_n238_n238#
+D0 a_n100_n100# w_n238_n238# sky130_fd_pr__diode_pd2nw_05v5 pj=4e+06u area=1e+12p
+C0 li_n340_n340# w_n376_n376# 2.20fF **FLOATING
+.ends
+
+.subckt sky130_fd_sc_hd__buf_2 A VGND VPWR X VNB VPB
+X0 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=5.63e+11p pd=5.18e+06u as=2.7e+11p ps=2.54e+06u w=1e+06u l=150000u
+X1 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 VPWR A a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=1.664e+11p ps=1.8e+06u w=640000u l=150000u
+X3 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=1.755e+11p pd=1.84e+06u as=3.6625e+11p ps=3.78e+06u w=650000u l=150000u
+X4 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X5 VGND A a_27_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.092e+11p ps=1.36e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hd__buf_16 A VGND VPWR X VNB VPB
+X0 VGND A a_109_47# VNB sky130_fd_pr__nfet_01v8 ad=2.093e+12p pd=2.204e+07u as=5.265e+11p ps=5.52e+06u w=650000u l=150000u
+X1 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=2.16e+12p pd=2.032e+07u as=3.22e+12p ps=3.044e+07u w=1e+06u l=150000u
+X2 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.404e+12p ps=1.472e+07u w=650000u l=150000u
+X3 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X4 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X6 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_109_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=8.1e+11p pd=7.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 VPWR A a_109_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X11 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X12 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X13 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X14 a_109_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X17 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 VPWR A a_109_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 VGND A a_109_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X21 VGND A a_109_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X22 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X23 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X25 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X27 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X30 a_109_47# A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X31 a_109_47# A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X32 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X35 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X36 VPWR A a_109_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X39 a_109_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_109_47# A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X43 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+C0 VPWR X 3.72fF
+C1 X a_109_47# 4.49fF
+C2 X VGND 2.53fF
+C3 VPWR VPB 2.24fF
+C4 VPB VNB 2.02fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_GJYUB2 a_207_n100# a_81_n126# a_n207_n128# a_15_n100#
++ a_n177_n100# a_111_n100# a_n15_n128# a_n111_n126# w_n305_n200# a_n81_n100# a_177_n128#
++ a_n269_n100# VSUBS
+X0 a_207_n100# a_177_n128# a_111_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=3.1e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_15_n100# a_n15_n128# a_n81_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_111_n100# a_81_n126# a_15_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n81_n100# a_n111_n126# a_n177_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_n177_n100# a_n207_n128# a_n269_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n15_n89# a_15_n69# VSUBS
+X0 a_15_n69# a_n15_n89# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u#0 sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89# sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n73_n69# VSUBS
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n73_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# VSUBS sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2#0 a_n139_n100# a_63_n100# a_33_n130# a_n33_n100# w_n319_n202# a_n63_n130#
++ VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n319_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n139_n100# w_n319_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W12 Vout Vin VDD GND pmos_2uf2_0/w_n319_n202# nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ VSUBS
+Xnmos_1u_0 Vin nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# GND VSUBS nmos_1u#0
+Xpmos_2uf2_0 VDD VDD Vin Vout pmos_2uf2_0/w_n319_n202# Vin VSUBS pmos_2uf2#0
+.ends
+
+.subckt latch_3 a_646_808# inv_W12_1/GND m1_686_734# w_n16_492# inv_W12_1/Vin VSUBS
++ inv_W12_0/Vin
+Xsky130_fd_pr__pfet_01v8_GJYUB2_0 m1_686_734# a_646_808# a_646_808# m1_686_734# m1_686_734#
++ inv_W12_1/VDD a_646_808# a_646_808# w_n16_492# inv_W12_1/VDD a_646_808# inv_W12_1/VDD
++ VSUBS sky130_fd_pr__pfet_01v8_GJYUB2
+Xinv_W12_0 inv_W12_1/Vin inv_W12_0/Vin inv_W12_1/VDD inv_W12_1/GND w_n16_492# inv_W12_1/Vin
++ VSUBS inv_W12
+Xinv_W12_1 inv_W12_0/Vin inv_W12_1/Vin inv_W12_1/VDD inv_W12_1/GND w_n16_492# inv_W12_0/Vin
++ VSUBS inv_W12
+C0 w_n16_492# VSUBS 2.44fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_G6PLX8 a_n129_n500# a_63_n500# a_n221_n474# a_n33_n500#
++ a_n159_n522# a_159_n500# VSUBS
+X0 a_n33_n500# a_n159_n522# a_n129_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_159_n500# a_n159_n522# a_63_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_63_n500# a_n159_n522# a_n33_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n500# a_n159_n522# a_n221_n474# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_RFM3CD#0 a_n73_n100# w_n109_n162# a_15_n100# a_n15_n126#
++ VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# w_n109_n162# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#1 a_15_n500# a_n15_n526# a_n73_n500# VSUBS
+X0 a_15_n500# a_n15_n526# a_n73_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_RURP52 a_33_n370# a_63_n348# a_n63_n370# a_n33_n348#
++ a_n125_n348# VSUBS
+X0 a_n33_n348# a_n63_n370# a_n125_n348# VSUBS sky130_fd_pr__nfet_01v8 ad=4.95e+11p pd=3.66e+06u as=4.65e+11p ps=3.62e+06u w=1.5e+06u l=150000u
+X1 a_63_n348# a_33_n370# a_n33_n348# VSUBS sky130_fd_pr__nfet_01v8 ad=4.65e+11p pd=3.62e+06u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8FHE5N a_n125_n439# a_63_n450# a_n63_n476# a_n33_n450#
++ a_33_n476# VSUBS
+X0 a_63_n450# a_33_n476# a_n33_n450# VSUBS sky130_fd_pr__nfet_01v8 ad=1.528e+11p pd=1.62e+06u as=1.65e+11p ps=1.66e+06u w=500000u l=150000u
+X1 a_n33_n450# a_n63_n476# a_n125_n439# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.528e+11p ps=1.62e+06u w=500000u l=150000u
+.ends
+
+.subckt preamp_part12 li_n720_1336# a_n72_236# a_80_n658# a_n434_n660# m1_n692_n210#
++ a_n506_870# a_388_n660# w_n720_994# li_n720_n474# a_414_256# a_706_862# li_954_n358#
++ VSUBS
+Xsky130_fd_pr__nfet_01v8_G6PLX8_0 a_414_256# a_414_256# m1_n128_n164# m1_n128_n164#
++ a_n434_n660# m1_n128_n164# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__nfet_01v8_G6PLX8_1 a_n72_236# a_n72_236# m1_338_n220# m1_338_n220#
++ a_388_n660# m1_338_n220# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 li_n720_1336# w_n720_994# a_414_256# a_n506_870#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 a_n72_236# w_n720_994# li_n720_1336# a_706_862#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 li_n720_n474# a_414_256# m1_n692_n210# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 li_954_n358# a_n72_236# li_n720_n474# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_RURP52_0 a_n72_236# li_n218_192# a_n72_236# m1_n128_n164#
++ li_n218_192# VSUBS sky130_fd_pr__nfet_01v8_RURP52
+Xsky130_fd_pr__nfet_01v8_RURP52_1 a_414_256# li_n218_192# a_414_256# m1_338_n220#
++ li_n218_192# VSUBS sky130_fd_pr__nfet_01v8_RURP52
+Xsky130_fd_pr__nfet_01v8_8FHE5N_0 li_n720_n474# li_n720_n474# a_80_n658# li_n218_192#
++ a_80_n658# VSUBS sky130_fd_pr__nfet_01v8_8FHE5N
+C0 w_n720_994# VSUBS 2.08fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5E9B w_n161_n200# a_33_n126# a_63_n100# a_n125_n74#
++ a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n126# a_n33_n100# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n125_n74# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt SR_latch a_648_848# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ a_262_508# VDD w_0_524# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 a_648_848# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND a_262_508# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__pfet_01v8_AC5E9B_0 w_0_524# a_262_508# VDD VDD a_648_848# a_262_508#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+Xsky130_fd_pr__pfet_01v8_AC5E9B_1 w_0_524# a_648_848# VDD VDD a_262_508# a_648_848#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+.ends
+
+.subckt preamp_part22 w_78_306# a_392_716# sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#
++ sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126# sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n15_n126#
++ sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_n15_n126# a_810_594# li_116_1034# sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_15_n100#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n73_n100#
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_0 li_214_402# w_78_306# a_810_594# sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_1 a_392_716# w_78_306# li_1016_536# sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_2 sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n73_n100#
++ w_78_306# li_214_402# sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_3 li_1016_536# w_78_306# sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_15_n100#
++ sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 li_214_402# w_78_306# li_116_1034# a_392_716# VSUBS
++ sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 li_116_1034# w_78_306# li_1016_536# a_810_594# VSUBS
++ sky130_fd_pr__pfet_01v8_RFM3CD#0
+C0 w_78_306# VSUBS 2.70fF
+.ends
+
+.subckt comparator_v6 Outn Vp Vn CLK VDD GND Outp CLKBAR
+Xlatch_3_0 CLKBAR GND VDD VDD Dp GND Dn latch_3
+Xpreamp_part12_0 VDD fp CLK Vn Dp CLK Vp VDD GND fn CLK Dn GND preamp_part12
+XSR_latch_0 Outp Dn Dp Outn VDD VDD GND GND SR_latch
+Xpreamp_part22_0 VDD fp CLKBAR CLKBAR CLK CLK fn VDD VDD GND VDD preamp_part22
+C0 CLKBAR VDD 2.34fF
+C1 VDD GND 29.75fF
+C2 CLK GND 14.11fF
+C3 fp GND 2.32fF
+C4 fn GND 2.31fF
+C5 Dp GND 3.77fF
+C6 Dn GND 3.24fF
+C7 CLKBAR GND 3.04fF
+.ends
+
+.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[5] io_analog[6] io_analog[7] io_analog[8]
++ io_analog[9] io_analog[4] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
++ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
++ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
++ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
++ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
++ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
++ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
++ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
++ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
++ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
++ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
++ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
++ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
++ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
++ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
++ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
++ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
++ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
++ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
++ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
++ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
++ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
++ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
++ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
++ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
++ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
++ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
++ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
++ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
++ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
++ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
++ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
++ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
++ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
++ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
++ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
++ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
++ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
++ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
++ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
++ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
++ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
++ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
++ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
++ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
++ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
++ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
++ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
++ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
++ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
++ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
++ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
++ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
++ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
++ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
++ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
++ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
++ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
++ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
++ vccd2 vdda1 vdda2 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] wbs_adr_i[10]
++ wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15] wbs_adr_i[16]
++ wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20] wbs_adr_i[21]
++ wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26] wbs_adr_i[27]
++ wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31] wbs_adr_i[3]
++ wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9] wbs_cyc_i
++ wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i vccd1 vssa1
+Xsky130_fd_pr__diode_pw2nd_05v5_3P6M5Y_0 io_analog[7] vssa1 sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y
+Xsky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0 vssa1 io_analog[7] vccd1 sky130_fd_pr__diode_pd2nw_05v5_G4XDRY
+Xsky130_fd_sc_hd__buf_2_0 comparator_v6_0/Outn vssa1 vccd1 L1 vssa1 vccd1 sky130_fd_sc_hd__buf_2
+Xsky130_fd_sc_hd__buf_16_0 L1 vssa1 vccd1 io_analog[3] vssa1 vccd1 sky130_fd_sc_hd__buf_16
+Xsky130_fd_sc_hd__buf_16_1 L2 vssa1 vccd1 io_analog[2] vssa1 vccd1 sky130_fd_sc_hd__buf_16
+Xsky130_fd_sc_hd__buf_2_1 comparator_v6_0/Outp vssa1 vccd1 L2 vssa1 vccd1 sky130_fd_sc_hd__buf_2
+Xsky130_fd_sc_hd__buf_16_2 sky130_fd_sc_hd__buf_2_3/X vssa1 vccd1 comparator_v6_0/CLKBAR
++ vssa1 vccd1 sky130_fd_sc_hd__buf_16
+Xsky130_fd_sc_hd__buf_2_2 io_analog[8] vssa1 vccd1 sky130_fd_sc_hd__buf_2_2/X vssa1
++ vccd1 sky130_fd_sc_hd__buf_2
+Xsky130_fd_sc_hd__buf_16_3 sky130_fd_sc_hd__buf_2_2/X vssa1 vccd1 comparator_v6_0/CLK
++ vssa1 vccd1 sky130_fd_sc_hd__buf_16
+Xsky130_fd_sc_hd__buf_2_3 io_analog[7] vssa1 vccd1 sky130_fd_sc_hd__buf_2_3/X vssa1
++ vccd1 sky130_fd_sc_hd__buf_2
+Xsky130_fd_sc_hd__buf_16_4 sky130_fd_sc_hd__buf_2_4/X vssa1 vccd1 io_analog[0] vssa1
++ vccd1 sky130_fd_sc_hd__buf_16
+Xsky130_fd_sc_hd__buf_2_4 io_analog[1] vssa1 vccd1 sky130_fd_sc_hd__buf_2_4/X vssa1
++ vccd1 sky130_fd_sc_hd__buf_2
+Xcomparator_v6_0 comparator_v6_0/Outn io_analog[5] io_analog[6] comparator_v6_0/CLK
++ vccd1 vssa1 comparator_v6_0/Outp comparator_v6_0/CLKBAR comparator_v6
+R0 vccd1 io_clamp_high[1] 0.000000
+R1 vccd1 io_clamp_high[2] 0.000000
+R2 vssa1 io_clamp_low[2] 0.000000
+D0 vssa1 io_analog[8] sky130_fd_pr__diode_pw2nd_05v5 pj=4e+06u area=1e+12p
+D1 io_analog[8] vccd1 sky130_fd_pr__diode_pd2nw_05v5 pj=4e+06u area=1e+12p
+R3 vssa1 io_clamp_low[1] 0.000000
+C0 comparator_v6_0/CLK io_analog[6] 2.17fF
+C1 io_analog[5] vccd1 573.17fF
+C2 io_analog[5] comparator_v6_0/CLKBAR 2.23fF
+C3 vccd1 io_analog[3] 34.41fF
+C4 vccd1 io_analog[6] 523.50fF
+C5 L2 vccd1 66.14fF
+C6 vccd1 comparator_v6_0/Outn 9.36fF
+C7 vccd1 sky130_fd_sc_hd__buf_2_2/X 4.31fF
+C8 sky130_fd_sc_hd__buf_2_3/X io_analog[5] 75.68fF
+C9 io_analog[0] vccd1 115.74fF
+C10 sky130_fd_sc_hd__buf_2_3/X vccd1 131.01fF
+C11 vccd1 m4_165510_677212# 30.18fF
+C12 vccd1 L1 66.26fF
+C13 m4_165510_677212# io_analog[6] 766.31fF
+C14 io_analog[4] vssa1 25.05fF
+C15 vssd2 vssa1 13.04fF
+C16 vssd1 vssa1 13.62fF
+C17 vdda2 vssa1 13.04fF
+C18 vdda1 vssa1 26.08fF
+C19 vssa2 vssa1 13.04fF
+C20 vccd2 vssa1 13.04fF
+C21 io_analog[10] vssa1 6.83fF
+C22 io_clamp_high[0] vssa1 3.58fF
+C23 io_clamp_low[0] vssa1 3.58fF
+C24 io_analog[9] vssa1 6.83fF
+C25 m4_141154_541976# vssa1 136.63fF **FLOATING
+C26 m4_165510_677212# vssa1 110.87fF **FLOATING
+C27 li_73093_686955# vssa1 2.20fF **FLOATING
+C28 io_analog[3] vssa1 26.43fF
+C29 vccd1 vssa1 2918.34fF
+C30 comparator_v6_0/Outp vssa1 26.62fF
+C31 comparator_v6_0/Outn vssa1 19.87fF
+C32 comparator_v6_0/CLK vssa1 17.79fF
+C33 comparator_v6_0/fp vssa1 2.32fF
+C34 comparator_v6_0/fn vssa1 2.31fF
+C35 io_analog[5] vssa1 337.44fF
+C36 io_analog[6] vssa1 234.19fF
+C37 comparator_v6_0/Dp vssa1 3.53fF
+C38 comparator_v6_0/Dn vssa1 3.23fF
+C39 comparator_v6_0/CLKBAR vssa1 7.21fF
+C40 io_analog[1] vssa1 25.06fF
+C41 io_analog[0] vssa1 431.98fF
+C42 io_analog[7] vssa1 63.99fF
+C43 sky130_fd_sc_hd__buf_2_2/X vssa1 354.67fF
+C44 io_analog[8] vssa1 68.96fF
+C45 sky130_fd_sc_hd__buf_2_3/X vssa1 303.55fF
+C46 L2 vssa1 190.71fF
+C47 io_analog[2] vssa1 25.67fF
+C48 L1 vssa1 195.71fF
+C49 sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/li_n340_n340# vssa1 2.20fF **FLOATING
+.ends
+
diff --git a/mag/user_analog_project_wrapper_empty.mag b/mag/user_analog_project_wrapper_empty.mag
new file mode 100644
index 0000000..02dbe79
--- /dev/null
+++ b/mag/user_analog_project_wrapper_empty.mag
@@ -0,0 +1,2091 @@
+magic
+tech sky130A
+timestamp 1632839657
+<< checkpaint >>
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+<< metal3 >>
+rect 8097 351150 10597 352400
+rect 34097 351150 36597 352400
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+rect -400 166366 240 166422
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+rect -400 145937 240 145993
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+rect -400 144755 240 144811
+rect 291760 137570 292400 137626
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+rect -400 126199 240 126255
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+rect 291760 47559 292400 47615
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+rect -400 772 240 828
+rect 291760 772 292400 828
+<< metal4 >>
+rect 82797 351150 85297 352400
+rect 87947 351150 90447 352400
+rect 108647 351150 111147 352400
+rect 113797 351150 116297 352400
+rect 159497 351150 161997 352400
+rect 164647 351150 167147 352400
+<< metal5 >>
+rect 82797 351150 85297 352400
+rect 87947 351150 90447 352400
+rect 108647 351150 111147 352400
+rect 113797 351150 116297 352400
+rect 159497 351150 161997 352400
+rect 164647 351150 167147 352400
+<< comment >>
+rect -50 352000 292050 352050
+rect -50 0 0 352000
+rect 292000 0 292050 352000
+rect -50 -50 292050 0
+<< labels >>
+flabel metal3 s 291760 134615 292400 134671 0 FreeSans 560 0 0 0 gpio_analog[0]
+port 0 nsew signal bidirectional
+flabel metal3 s -400 190932 240 190988 0 FreeSans 560 0 0 0 gpio_analog[10]
+port 1 nsew signal bidirectional
+flabel metal3 s -400 169321 240 169377 0 FreeSans 560 0 0 0 gpio_analog[11]
+port 2 nsew signal bidirectional
+flabel metal3 s -400 147710 240 147766 0 FreeSans 560 0 0 0 gpio_analog[12]
+port 3 nsew signal bidirectional
+flabel metal3 s -400 126199 240 126255 0 FreeSans 560 0 0 0 gpio_analog[13]
+port 4 nsew signal bidirectional
+flabel metal3 s -400 62388 240 62444 0 FreeSans 560 0 0 0 gpio_analog[14]
+port 5 nsew signal bidirectional
+flabel metal3 s -400 40777 240 40833 0 FreeSans 560 0 0 0 gpio_analog[15]
+port 6 nsew signal bidirectional
+flabel metal3 s -400 19166 240 19222 0 FreeSans 560 0 0 0 gpio_analog[16]
+port 7 nsew signal bidirectional
+flabel metal3 s -400 8455 240 8511 0 FreeSans 560 0 0 0 gpio_analog[17]
+port 8 nsew signal bidirectional
+flabel metal3 s 291760 156826 292400 156882 0 FreeSans 560 0 0 0 gpio_analog[1]
+port 9 nsew signal bidirectional
+flabel metal3 s 291760 179437 292400 179493 0 FreeSans 560 0 0 0 gpio_analog[2]
+port 10 nsew signal bidirectional
+flabel metal3 s 291760 202648 292400 202704 0 FreeSans 560 0 0 0 gpio_analog[3]
+port 11 nsew signal bidirectional
+flabel metal3 s 291760 224859 292400 224915 0 FreeSans 560 0 0 0 gpio_analog[4]
+port 12 nsew signal bidirectional
+flabel metal3 s 291760 247070 292400 247126 0 FreeSans 560 0 0 0 gpio_analog[5]
+port 13 nsew signal bidirectional
+flabel metal3 s 291760 291781 292400 291837 0 FreeSans 560 0 0 0 gpio_analog[6]
+port 14 nsew signal bidirectional
+flabel metal3 s -400 255765 240 255821 0 FreeSans 560 0 0 0 gpio_analog[7]
+port 15 nsew signal bidirectional
+flabel metal3 s -400 234154 240 234210 0 FreeSans 560 0 0 0 gpio_analog[8]
+port 16 nsew signal bidirectional
+flabel metal3 s -400 212543 240 212599 0 FreeSans 560 0 0 0 gpio_analog[9]
+port 17 nsew signal bidirectional
+flabel metal3 s 291760 135206 292400 135262 0 FreeSans 560 0 0 0 gpio_noesd[0]
+port 18 nsew signal bidirectional
+flabel metal3 s -400 190341 240 190397 0 FreeSans 560 0 0 0 gpio_noesd[10]
+port 19 nsew signal bidirectional
+flabel metal3 s -400 168730 240 168786 0 FreeSans 560 0 0 0 gpio_noesd[11]
+port 20 nsew signal bidirectional
+flabel metal3 s -400 147119 240 147175 0 FreeSans 560 0 0 0 gpio_noesd[12]
+port 21 nsew signal bidirectional
+flabel metal3 s -400 125608 240 125664 0 FreeSans 560 0 0 0 gpio_noesd[13]
+port 22 nsew signal bidirectional
+flabel metal3 s -400 61797 240 61853 0 FreeSans 560 0 0 0 gpio_noesd[14]
+port 23 nsew signal bidirectional
+flabel metal3 s -400 40186 240 40242 0 FreeSans 560 0 0 0 gpio_noesd[15]
+port 24 nsew signal bidirectional
+flabel metal3 s -400 18575 240 18631 0 FreeSans 560 0 0 0 gpio_noesd[16]
+port 25 nsew signal bidirectional
+flabel metal3 s -400 7864 240 7920 0 FreeSans 560 0 0 0 gpio_noesd[17]
+port 26 nsew signal bidirectional
+flabel metal3 s 291760 157417 292400 157473 0 FreeSans 560 0 0 0 gpio_noesd[1]
+port 27 nsew signal bidirectional
+flabel metal3 s 291760 180028 292400 180084 0 FreeSans 560 0 0 0 gpio_noesd[2]
+port 28 nsew signal bidirectional
+flabel metal3 s 291760 203239 292400 203295 0 FreeSans 560 0 0 0 gpio_noesd[3]
+port 29 nsew signal bidirectional
+flabel metal3 s 291760 225450 292400 225506 0 FreeSans 560 0 0 0 gpio_noesd[4]
+port 30 nsew signal bidirectional
+flabel metal3 s 291760 247661 292400 247717 0 FreeSans 560 0 0 0 gpio_noesd[5]
+port 31 nsew signal bidirectional
+flabel metal3 s 291760 292372 292400 292428 0 FreeSans 560 0 0 0 gpio_noesd[6]
+port 32 nsew signal bidirectional
+flabel metal3 s -400 255174 240 255230 0 FreeSans 560 0 0 0 gpio_noesd[7]
+port 33 nsew signal bidirectional
+flabel metal3 s -400 233563 240 233619 0 FreeSans 560 0 0 0 gpio_noesd[8]
+port 34 nsew signal bidirectional
+flabel metal3 s -400 211952 240 212008 0 FreeSans 560 0 0 0 gpio_noesd[9]
+port 35 nsew signal bidirectional
+flabel metal3 s 291150 338992 292400 341492 0 FreeSans 560 0 0 0 io_analog[0]
+port 36 nsew signal bidirectional
+flabel metal3 s 0 340121 850 342621 0 FreeSans 560 0 0 0 io_analog[10]
+port 37 nsew signal bidirectional
+flabel metal3 s 283297 351150 285797 352400 0 FreeSans 960 180 0 0 io_analog[1]
+port 38 nsew signal bidirectional
+flabel metal3 s 232697 351150 235197 352400 0 FreeSans 960 180 0 0 io_analog[2]
+port 39 nsew signal bidirectional
+flabel metal3 s 206697 351150 209197 352400 0 FreeSans 960 180 0 0 io_analog[3]
+port 40 nsew signal bidirectional
+flabel metal3 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal4 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal5 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal3 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal4 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal5 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal3 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal4 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal5 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal3 s 60097 351150 62597 352400 0 FreeSans 960 180 0 0 io_analog[7]
+port 44 nsew signal bidirectional
+flabel metal3 s 34097 351150 36597 352400 0 FreeSans 960 180 0 0 io_analog[8]
+port 45 nsew signal bidirectional
+flabel metal3 s 8097 351150 10597 352400 0 FreeSans 960 180 0 0 io_analog[9]
+port 46 nsew signal bidirectional
+flabel metal3 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal4 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal5 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal3 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal4 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal5 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal3 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal4 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal5 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal3 s 163397 351150 164497 352400 0 FreeSans 960 180 0 0 io_clamp_high[0]
+port 50 nsew signal bidirectional
+flabel metal3 s 112547 351150 113647 352400 0 FreeSans 960 180 0 0 io_clamp_high[1]
+port 51 nsew signal bidirectional
+flabel metal3 s 86697 351150 87797 352400 0 FreeSans 960 180 0 0 io_clamp_high[2]
+port 52 nsew signal bidirectional
+flabel metal3 s 162147 351150 163247 352400 0 FreeSans 960 180 0 0 io_clamp_low[0]
+port 53 nsew signal bidirectional
+flabel metal3 s 111297 351150 112397 352400 0 FreeSans 960 180 0 0 io_clamp_low[1]
+port 54 nsew signal bidirectional
+flabel metal3 s 85447 351150 86547 352400 0 FreeSans 960 180 0 0 io_clamp_low[2]
+port 55 nsew signal bidirectional
+flabel metal3 s 291760 1363 292400 1419 0 FreeSans 560 0 0 0 io_in[0]
+port 56 nsew signal input
+flabel metal3 s 291760 204421 292400 204477 0 FreeSans 560 0 0 0 io_in[10]
+port 57 nsew signal input
+flabel metal3 s 291760 226632 292400 226688 0 FreeSans 560 0 0 0 io_in[11]
+port 58 nsew signal input
+flabel metal3 s 291760 248843 292400 248899 0 FreeSans 560 0 0 0 io_in[12]
+port 59 nsew signal input
+flabel metal3 s 291760 293554 292400 293610 0 FreeSans 560 0 0 0 io_in[13]
+port 60 nsew signal input
+flabel metal3 s -400 253992 240 254048 0 FreeSans 560 0 0 0 io_in[14]
+port 61 nsew signal input
+flabel metal3 s -400 232381 240 232437 0 FreeSans 560 0 0 0 io_in[15]
+port 62 nsew signal input
+flabel metal3 s -400 210770 240 210826 0 FreeSans 560 0 0 0 io_in[16]
+port 63 nsew signal input
+flabel metal3 s -400 189159 240 189215 0 FreeSans 560 0 0 0 io_in[17]
+port 64 nsew signal input
+flabel metal3 s -400 167548 240 167604 0 FreeSans 560 0 0 0 io_in[18]
+port 65 nsew signal input
+flabel metal3 s -400 145937 240 145993 0 FreeSans 560 0 0 0 io_in[19]
+port 66 nsew signal input
+flabel metal3 s 291760 3727 292400 3783 0 FreeSans 560 0 0 0 io_in[1]
+port 67 nsew signal input
+flabel metal3 s -400 124426 240 124482 0 FreeSans 560 0 0 0 io_in[20]
+port 68 nsew signal input
+flabel metal3 s -400 60615 240 60671 0 FreeSans 560 0 0 0 io_in[21]
+port 69 nsew signal input
+flabel metal3 s -400 39004 240 39060 0 FreeSans 560 0 0 0 io_in[22]
+port 70 nsew signal input
+flabel metal3 s -400 17393 240 17449 0 FreeSans 560 0 0 0 io_in[23]
+port 71 nsew signal input
+flabel metal3 s -400 6682 240 6738 0 FreeSans 560 0 0 0 io_in[24]
+port 72 nsew signal input
+flabel metal3 s -400 4318 240 4374 0 FreeSans 560 0 0 0 io_in[25]
+port 73 nsew signal input
+flabel metal3 s -400 1954 240 2010 0 FreeSans 560 0 0 0 io_in[26]
+port 74 nsew signal input
+flabel metal3 s 291760 6091 292400 6147 0 FreeSans 560 0 0 0 io_in[2]
+port 75 nsew signal input
+flabel metal3 s 291760 8455 292400 8511 0 FreeSans 560 0 0 0 io_in[3]
+port 76 nsew signal input
+flabel metal3 s 291760 10819 292400 10875 0 FreeSans 560 0 0 0 io_in[4]
+port 77 nsew signal input
+flabel metal3 s 291760 24048 292400 24104 0 FreeSans 560 0 0 0 io_in[5]
+port 78 nsew signal input
+flabel metal3 s 291760 46377 292400 46433 0 FreeSans 560 0 0 0 io_in[6]
+port 79 nsew signal input
+flabel metal3 s 291760 136388 292400 136444 0 FreeSans 560 0 0 0 io_in[7]
+port 80 nsew signal input
+flabel metal3 s 291760 158599 292400 158655 0 FreeSans 560 0 0 0 io_in[8]
+port 81 nsew signal input
+flabel metal3 s 291760 181210 292400 181266 0 FreeSans 560 0 0 0 io_in[9]
+port 82 nsew signal input
+flabel metal3 s 291760 772 292400 828 0 FreeSans 560 0 0 0 io_in_3v3[0]
+port 83 nsew signal input
+flabel metal3 s 291760 203830 292400 203886 0 FreeSans 560 0 0 0 io_in_3v3[10]
+port 84 nsew signal input
+flabel metal3 s 291760 226041 292400 226097 0 FreeSans 560 0 0 0 io_in_3v3[11]
+port 85 nsew signal input
+flabel metal3 s 291760 248252 292400 248308 0 FreeSans 560 0 0 0 io_in_3v3[12]
+port 86 nsew signal input
+flabel metal3 s 291760 292963 292400 293019 0 FreeSans 560 0 0 0 io_in_3v3[13]
+port 87 nsew signal input
+flabel metal3 s -400 254583 240 254639 0 FreeSans 560 0 0 0 io_in_3v3[14]
+port 88 nsew signal input
+flabel metal3 s -400 232972 240 233028 0 FreeSans 560 0 0 0 io_in_3v3[15]
+port 89 nsew signal input
+flabel metal3 s -400 211361 240 211417 0 FreeSans 560 0 0 0 io_in_3v3[16]
+port 90 nsew signal input
+flabel metal3 s -400 189750 240 189806 0 FreeSans 560 0 0 0 io_in_3v3[17]
+port 91 nsew signal input
+flabel metal3 s -400 168139 240 168195 0 FreeSans 560 0 0 0 io_in_3v3[18]
+port 92 nsew signal input
+flabel metal3 s -400 146528 240 146584 0 FreeSans 560 0 0 0 io_in_3v3[19]
+port 93 nsew signal input
+flabel metal3 s 291760 3136 292400 3192 0 FreeSans 560 0 0 0 io_in_3v3[1]
+port 94 nsew signal input
+flabel metal3 s -400 125017 240 125073 0 FreeSans 560 0 0 0 io_in_3v3[20]
+port 95 nsew signal input
+flabel metal3 s -400 61206 240 61262 0 FreeSans 560 0 0 0 io_in_3v3[21]
+port 96 nsew signal input
+flabel metal3 s -400 39595 240 39651 0 FreeSans 560 0 0 0 io_in_3v3[22]
+port 97 nsew signal input
+flabel metal3 s -400 17984 240 18040 0 FreeSans 560 0 0 0 io_in_3v3[23]
+port 98 nsew signal input
+flabel metal3 s -400 7273 240 7329 0 FreeSans 560 0 0 0 io_in_3v3[24]
+port 99 nsew signal input
+flabel metal3 s -400 4909 240 4965 0 FreeSans 560 0 0 0 io_in_3v3[25]
+port 100 nsew signal input
+flabel metal3 s -400 2545 240 2601 0 FreeSans 560 0 0 0 io_in_3v3[26]
+port 101 nsew signal input
+flabel metal3 s 291760 5500 292400 5556 0 FreeSans 560 0 0 0 io_in_3v3[2]
+port 102 nsew signal input
+flabel metal3 s 291760 7864 292400 7920 0 FreeSans 560 0 0 0 io_in_3v3[3]
+port 103 nsew signal input
+flabel metal3 s 291760 10228 292400 10284 0 FreeSans 560 0 0 0 io_in_3v3[4]
+port 104 nsew signal input
+flabel metal3 s 291760 23457 292400 23513 0 FreeSans 560 0 0 0 io_in_3v3[5]
+port 105 nsew signal input
+flabel metal3 s 291760 45786 292400 45842 0 FreeSans 560 0 0 0 io_in_3v3[6]
+port 106 nsew signal input
+flabel metal3 s 291760 135797 292400 135853 0 FreeSans 560 0 0 0 io_in_3v3[7]
+port 107 nsew signal input
+flabel metal3 s 291760 158008 292400 158064 0 FreeSans 560 0 0 0 io_in_3v3[8]
+port 108 nsew signal input
+flabel metal3 s 291760 180619 292400 180675 0 FreeSans 560 0 0 0 io_in_3v3[9]
+port 109 nsew signal input
+flabel metal3 s 291760 2545 292400 2601 0 FreeSans 560 0 0 0 io_oeb[0]
+port 110 nsew signal tristate
+flabel metal3 s 291760 205603 292400 205659 0 FreeSans 560 0 0 0 io_oeb[10]
+port 111 nsew signal tristate
+flabel metal3 s 291760 227814 292400 227870 0 FreeSans 560 0 0 0 io_oeb[11]
+port 112 nsew signal tristate
+flabel metal3 s 291760 250025 292400 250081 0 FreeSans 560 0 0 0 io_oeb[12]
+port 113 nsew signal tristate
+flabel metal3 s 291760 294736 292400 294792 0 FreeSans 560 0 0 0 io_oeb[13]
+port 114 nsew signal tristate
+flabel metal3 s -400 252810 240 252866 0 FreeSans 560 0 0 0 io_oeb[14]
+port 115 nsew signal tristate
+flabel metal3 s -400 231199 240 231255 0 FreeSans 560 0 0 0 io_oeb[15]
+port 116 nsew signal tristate
+flabel metal3 s -400 209588 240 209644 0 FreeSans 560 0 0 0 io_oeb[16]
+port 117 nsew signal tristate
+flabel metal3 s -400 187977 240 188033 0 FreeSans 560 0 0 0 io_oeb[17]
+port 118 nsew signal tristate
+flabel metal3 s -400 166366 240 166422 0 FreeSans 560 0 0 0 io_oeb[18]
+port 119 nsew signal tristate
+flabel metal3 s -400 144755 240 144811 0 FreeSans 560 0 0 0 io_oeb[19]
+port 120 nsew signal tristate
+flabel metal3 s 291760 4909 292400 4965 0 FreeSans 560 0 0 0 io_oeb[1]
+port 121 nsew signal tristate
+flabel metal3 s -400 123244 240 123300 0 FreeSans 560 0 0 0 io_oeb[20]
+port 122 nsew signal tristate
+flabel metal3 s -400 59433 240 59489 0 FreeSans 560 0 0 0 io_oeb[21]
+port 123 nsew signal tristate
+flabel metal3 s -400 37822 240 37878 0 FreeSans 560 0 0 0 io_oeb[22]
+port 124 nsew signal tristate
+flabel metal3 s -400 16211 240 16267 0 FreeSans 560 0 0 0 io_oeb[23]
+port 125 nsew signal tristate
+flabel metal3 s -400 5500 240 5556 0 FreeSans 560 0 0 0 io_oeb[24]
+port 126 nsew signal tristate
+flabel metal3 s -400 3136 240 3192 0 FreeSans 560 0 0 0 io_oeb[25]
+port 127 nsew signal tristate
+flabel metal3 s -400 772 240 828 0 FreeSans 560 0 0 0 io_oeb[26]
+port 128 nsew signal tristate
+flabel metal3 s 291760 7273 292400 7329 0 FreeSans 560 0 0 0 io_oeb[2]
+port 129 nsew signal tristate
+flabel metal3 s 291760 9637 292400 9693 0 FreeSans 560 0 0 0 io_oeb[3]
+port 130 nsew signal tristate
+flabel metal3 s 291760 12001 292400 12057 0 FreeSans 560 0 0 0 io_oeb[4]
+port 131 nsew signal tristate
+flabel metal3 s 291760 25230 292400 25286 0 FreeSans 560 0 0 0 io_oeb[5]
+port 132 nsew signal tristate
+flabel metal3 s 291760 47559 292400 47615 0 FreeSans 560 0 0 0 io_oeb[6]
+port 133 nsew signal tristate
+flabel metal3 s 291760 137570 292400 137626 0 FreeSans 560 0 0 0 io_oeb[7]
+port 134 nsew signal tristate
+flabel metal3 s 291760 159781 292400 159837 0 FreeSans 560 0 0 0 io_oeb[8]
+port 135 nsew signal tristate
+flabel metal3 s 291760 182392 292400 182448 0 FreeSans 560 0 0 0 io_oeb[9]
+port 136 nsew signal tristate
+flabel metal3 s 291760 1954 292400 2010 0 FreeSans 560 0 0 0 io_out[0]
+port 137 nsew signal tristate
+flabel metal3 s 291760 205012 292400 205068 0 FreeSans 560 0 0 0 io_out[10]
+port 138 nsew signal tristate
+flabel metal3 s 291760 227223 292400 227279 0 FreeSans 560 0 0 0 io_out[11]
+port 139 nsew signal tristate
+flabel metal3 s 291760 249434 292400 249490 0 FreeSans 560 0 0 0 io_out[12]
+port 140 nsew signal tristate
+flabel metal3 s 291760 294145 292400 294201 0 FreeSans 560 0 0 0 io_out[13]
+port 141 nsew signal tristate
+flabel metal3 s -400 253401 240 253457 0 FreeSans 560 0 0 0 io_out[14]
+port 142 nsew signal tristate
+flabel metal3 s -400 231790 240 231846 0 FreeSans 560 0 0 0 io_out[15]
+port 143 nsew signal tristate
+flabel metal3 s -400 210179 240 210235 0 FreeSans 560 0 0 0 io_out[16]
+port 144 nsew signal tristate
+flabel metal3 s -400 188568 240 188624 0 FreeSans 560 0 0 0 io_out[17]
+port 145 nsew signal tristate
+flabel metal3 s -400 166957 240 167013 0 FreeSans 560 0 0 0 io_out[18]
+port 146 nsew signal tristate
+flabel metal3 s -400 145346 240 145402 0 FreeSans 560 0 0 0 io_out[19]
+port 147 nsew signal tristate
+flabel metal3 s 291760 4318 292400 4374 0 FreeSans 560 0 0 0 io_out[1]
+port 148 nsew signal tristate
+flabel metal3 s -400 123835 240 123891 0 FreeSans 560 0 0 0 io_out[20]
+port 149 nsew signal tristate
+flabel metal3 s -400 60024 240 60080 0 FreeSans 560 0 0 0 io_out[21]
+port 150 nsew signal tristate
+flabel metal3 s -400 38413 240 38469 0 FreeSans 560 0 0 0 io_out[22]
+port 151 nsew signal tristate
+flabel metal3 s -400 16802 240 16858 0 FreeSans 560 0 0 0 io_out[23]
+port 152 nsew signal tristate
+flabel metal3 s -400 6091 240 6147 0 FreeSans 560 0 0 0 io_out[24]
+port 153 nsew signal tristate
+flabel metal3 s -400 3727 240 3783 0 FreeSans 560 0 0 0 io_out[25]
+port 154 nsew signal tristate
+flabel metal3 s -400 1363 240 1419 0 FreeSans 560 0 0 0 io_out[26]
+port 155 nsew signal tristate
+flabel metal3 s 291760 6682 292400 6738 0 FreeSans 560 0 0 0 io_out[2]
+port 156 nsew signal tristate
+flabel metal3 s 291760 9046 292400 9102 0 FreeSans 560 0 0 0 io_out[3]
+port 157 nsew signal tristate
+flabel metal3 s 291760 11410 292400 11466 0 FreeSans 560 0 0 0 io_out[4]
+port 158 nsew signal tristate
+flabel metal3 s 291760 24639 292400 24695 0 FreeSans 560 0 0 0 io_out[5]
+port 159 nsew signal tristate
+flabel metal3 s 291760 46968 292400 47024 0 FreeSans 560 0 0 0 io_out[6]
+port 160 nsew signal tristate
+flabel metal3 s 291760 136979 292400 137035 0 FreeSans 560 0 0 0 io_out[7]
+port 161 nsew signal tristate
+flabel metal3 s 291760 159190 292400 159246 0 FreeSans 560 0 0 0 io_out[8]
+port 162 nsew signal tristate
+flabel metal3 s 291760 181801 292400 181857 0 FreeSans 560 0 0 0 io_out[9]
+port 163 nsew signal tristate
+flabel metal2 s 62908 -400 62964 240 0 FreeSans 560 90 0 0 la_data_in[0]
+port 164 nsew signal input
+flabel metal2 s 240208 -400 240264 240 0 FreeSans 560 90 0 0 la_data_in[100]
+port 165 nsew signal input
+flabel metal2 s 241981 -400 242037 240 0 FreeSans 560 90 0 0 la_data_in[101]
+port 166 nsew signal input
+flabel metal2 s 243754 -400 243810 240 0 FreeSans 560 90 0 0 la_data_in[102]
+port 167 nsew signal input
+flabel metal2 s 245527 -400 245583 240 0 FreeSans 560 90 0 0 la_data_in[103]
+port 168 nsew signal input
+flabel metal2 s 247300 -400 247356 240 0 FreeSans 560 90 0 0 la_data_in[104]
+port 169 nsew signal input
+flabel metal2 s 249073 -400 249129 240 0 FreeSans 560 90 0 0 la_data_in[105]
+port 170 nsew signal input
+flabel metal2 s 250846 -400 250902 240 0 FreeSans 560 90 0 0 la_data_in[106]
+port 171 nsew signal input
+flabel metal2 s 252619 -400 252675 240 0 FreeSans 560 90 0 0 la_data_in[107]
+port 172 nsew signal input
+flabel metal2 s 254392 -400 254448 240 0 FreeSans 560 90 0 0 la_data_in[108]
+port 173 nsew signal input
+flabel metal2 s 256165 -400 256221 240 0 FreeSans 560 90 0 0 la_data_in[109]
+port 174 nsew signal input
+flabel metal2 s 80638 -400 80694 240 0 FreeSans 560 90 0 0 la_data_in[10]
+port 175 nsew signal input
+flabel metal2 s 257938 -400 257994 240 0 FreeSans 560 90 0 0 la_data_in[110]
+port 176 nsew signal input
+flabel metal2 s 259711 -400 259767 240 0 FreeSans 560 90 0 0 la_data_in[111]
+port 177 nsew signal input
+flabel metal2 s 261484 -400 261540 240 0 FreeSans 560 90 0 0 la_data_in[112]
+port 178 nsew signal input
+flabel metal2 s 263257 -400 263313 240 0 FreeSans 560 90 0 0 la_data_in[113]
+port 179 nsew signal input
+flabel metal2 s 265030 -400 265086 240 0 FreeSans 560 90 0 0 la_data_in[114]
+port 180 nsew signal input
+flabel metal2 s 266803 -400 266859 240 0 FreeSans 560 90 0 0 la_data_in[115]
+port 181 nsew signal input
+flabel metal2 s 268576 -400 268632 240 0 FreeSans 560 90 0 0 la_data_in[116]
+port 182 nsew signal input
+flabel metal2 s 270349 -400 270405 240 0 FreeSans 560 90 0 0 la_data_in[117]
+port 183 nsew signal input
+flabel metal2 s 272122 -400 272178 240 0 FreeSans 560 90 0 0 la_data_in[118]
+port 184 nsew signal input
+flabel metal2 s 273895 -400 273951 240 0 FreeSans 560 90 0 0 la_data_in[119]
+port 185 nsew signal input
+flabel metal2 s 82411 -400 82467 240 0 FreeSans 560 90 0 0 la_data_in[11]
+port 186 nsew signal input
+flabel metal2 s 275668 -400 275724 240 0 FreeSans 560 90 0 0 la_data_in[120]
+port 187 nsew signal input
+flabel metal2 s 277441 -400 277497 240 0 FreeSans 560 90 0 0 la_data_in[121]
+port 188 nsew signal input
+flabel metal2 s 279214 -400 279270 240 0 FreeSans 560 90 0 0 la_data_in[122]
+port 189 nsew signal input
+flabel metal2 s 280987 -400 281043 240 0 FreeSans 560 90 0 0 la_data_in[123]
+port 190 nsew signal input
+flabel metal2 s 282760 -400 282816 240 0 FreeSans 560 90 0 0 la_data_in[124]
+port 191 nsew signal input
+flabel metal2 s 284533 -400 284589 240 0 FreeSans 560 90 0 0 la_data_in[125]
+port 192 nsew signal input
+flabel metal2 s 286306 -400 286362 240 0 FreeSans 560 90 0 0 la_data_in[126]
+port 193 nsew signal input
+flabel metal2 s 288079 -400 288135 240 0 FreeSans 560 90 0 0 la_data_in[127]
+port 194 nsew signal input
+flabel metal2 s 84184 -400 84240 240 0 FreeSans 560 90 0 0 la_data_in[12]
+port 195 nsew signal input
+flabel metal2 s 85957 -400 86013 240 0 FreeSans 560 90 0 0 la_data_in[13]
+port 196 nsew signal input
+flabel metal2 s 87730 -400 87786 240 0 FreeSans 560 90 0 0 la_data_in[14]
+port 197 nsew signal input
+flabel metal2 s 89503 -400 89559 240 0 FreeSans 560 90 0 0 la_data_in[15]
+port 198 nsew signal input
+flabel metal2 s 91276 -400 91332 240 0 FreeSans 560 90 0 0 la_data_in[16]
+port 199 nsew signal input
+flabel metal2 s 93049 -400 93105 240 0 FreeSans 560 90 0 0 la_data_in[17]
+port 200 nsew signal input
+flabel metal2 s 94822 -400 94878 240 0 FreeSans 560 90 0 0 la_data_in[18]
+port 201 nsew signal input
+flabel metal2 s 96595 -400 96651 240 0 FreeSans 560 90 0 0 la_data_in[19]
+port 202 nsew signal input
+flabel metal2 s 64681 -400 64737 240 0 FreeSans 560 90 0 0 la_data_in[1]
+port 203 nsew signal input
+flabel metal2 s 98368 -400 98424 240 0 FreeSans 560 90 0 0 la_data_in[20]
+port 204 nsew signal input
+flabel metal2 s 100141 -400 100197 240 0 FreeSans 560 90 0 0 la_data_in[21]
+port 205 nsew signal input
+flabel metal2 s 101914 -400 101970 240 0 FreeSans 560 90 0 0 la_data_in[22]
+port 206 nsew signal input
+flabel metal2 s 103687 -400 103743 240 0 FreeSans 560 90 0 0 la_data_in[23]
+port 207 nsew signal input
+flabel metal2 s 105460 -400 105516 240 0 FreeSans 560 90 0 0 la_data_in[24]
+port 208 nsew signal input
+flabel metal2 s 107233 -400 107289 240 0 FreeSans 560 90 0 0 la_data_in[25]
+port 209 nsew signal input
+flabel metal2 s 109006 -400 109062 240 0 FreeSans 560 90 0 0 la_data_in[26]
+port 210 nsew signal input
+flabel metal2 s 110779 -400 110835 240 0 FreeSans 560 90 0 0 la_data_in[27]
+port 211 nsew signal input
+flabel metal2 s 112552 -400 112608 240 0 FreeSans 560 90 0 0 la_data_in[28]
+port 212 nsew signal input
+flabel metal2 s 114325 -400 114381 240 0 FreeSans 560 90 0 0 la_data_in[29]
+port 213 nsew signal input
+flabel metal2 s 66454 -400 66510 240 0 FreeSans 560 90 0 0 la_data_in[2]
+port 214 nsew signal input
+flabel metal2 s 116098 -400 116154 240 0 FreeSans 560 90 0 0 la_data_in[30]
+port 215 nsew signal input
+flabel metal2 s 117871 -400 117927 240 0 FreeSans 560 90 0 0 la_data_in[31]
+port 216 nsew signal input
+flabel metal2 s 119644 -400 119700 240 0 FreeSans 560 90 0 0 la_data_in[32]
+port 217 nsew signal input
+flabel metal2 s 121417 -400 121473 240 0 FreeSans 560 90 0 0 la_data_in[33]
+port 218 nsew signal input
+flabel metal2 s 123190 -400 123246 240 0 FreeSans 560 90 0 0 la_data_in[34]
+port 219 nsew signal input
+flabel metal2 s 124963 -400 125019 240 0 FreeSans 560 90 0 0 la_data_in[35]
+port 220 nsew signal input
+flabel metal2 s 126736 -400 126792 240 0 FreeSans 560 90 0 0 la_data_in[36]
+port 221 nsew signal input
+flabel metal2 s 128509 -400 128565 240 0 FreeSans 560 90 0 0 la_data_in[37]
+port 222 nsew signal input
+flabel metal2 s 130282 -400 130338 240 0 FreeSans 560 90 0 0 la_data_in[38]
+port 223 nsew signal input
+flabel metal2 s 132055 -400 132111 240 0 FreeSans 560 90 0 0 la_data_in[39]
+port 224 nsew signal input
+flabel metal2 s 68227 -400 68283 240 0 FreeSans 560 90 0 0 la_data_in[3]
+port 225 nsew signal input
+flabel metal2 s 133828 -400 133884 240 0 FreeSans 560 90 0 0 la_data_in[40]
+port 226 nsew signal input
+flabel metal2 s 135601 -400 135657 240 0 FreeSans 560 90 0 0 la_data_in[41]
+port 227 nsew signal input
+flabel metal2 s 137374 -400 137430 240 0 FreeSans 560 90 0 0 la_data_in[42]
+port 228 nsew signal input
+flabel metal2 s 139147 -400 139203 240 0 FreeSans 560 90 0 0 la_data_in[43]
+port 229 nsew signal input
+flabel metal2 s 140920 -400 140976 240 0 FreeSans 560 90 0 0 la_data_in[44]
+port 230 nsew signal input
+flabel metal2 s 142693 -400 142749 240 0 FreeSans 560 90 0 0 la_data_in[45]
+port 231 nsew signal input
+flabel metal2 s 144466 -400 144522 240 0 FreeSans 560 90 0 0 la_data_in[46]
+port 232 nsew signal input
+flabel metal2 s 146239 -400 146295 240 0 FreeSans 560 90 0 0 la_data_in[47]
+port 233 nsew signal input
+flabel metal2 s 148012 -400 148068 240 0 FreeSans 560 90 0 0 la_data_in[48]
+port 234 nsew signal input
+flabel metal2 s 149785 -400 149841 240 0 FreeSans 560 90 0 0 la_data_in[49]
+port 235 nsew signal input
+flabel metal2 s 70000 -400 70056 240 0 FreeSans 560 90 0 0 la_data_in[4]
+port 236 nsew signal input
+flabel metal2 s 151558 -400 151614 240 0 FreeSans 560 90 0 0 la_data_in[50]
+port 237 nsew signal input
+flabel metal2 s 153331 -400 153387 240 0 FreeSans 560 90 0 0 la_data_in[51]
+port 238 nsew signal input
+flabel metal2 s 155104 -400 155160 240 0 FreeSans 560 90 0 0 la_data_in[52]
+port 239 nsew signal input
+flabel metal2 s 156877 -400 156933 240 0 FreeSans 560 90 0 0 la_data_in[53]
+port 240 nsew signal input
+flabel metal2 s 158650 -400 158706 240 0 FreeSans 560 90 0 0 la_data_in[54]
+port 241 nsew signal input
+flabel metal2 s 160423 -400 160479 240 0 FreeSans 560 90 0 0 la_data_in[55]
+port 242 nsew signal input
+flabel metal2 s 162196 -400 162252 240 0 FreeSans 560 90 0 0 la_data_in[56]
+port 243 nsew signal input
+flabel metal2 s 163969 -400 164025 240 0 FreeSans 560 90 0 0 la_data_in[57]
+port 244 nsew signal input
+flabel metal2 s 165742 -400 165798 240 0 FreeSans 560 90 0 0 la_data_in[58]
+port 245 nsew signal input
+flabel metal2 s 167515 -400 167571 240 0 FreeSans 560 90 0 0 la_data_in[59]
+port 246 nsew signal input
+flabel metal2 s 71773 -400 71829 240 0 FreeSans 560 90 0 0 la_data_in[5]
+port 247 nsew signal input
+flabel metal2 s 169288 -400 169344 240 0 FreeSans 560 90 0 0 la_data_in[60]
+port 248 nsew signal input
+flabel metal2 s 171061 -400 171117 240 0 FreeSans 560 90 0 0 la_data_in[61]
+port 249 nsew signal input
+flabel metal2 s 172834 -400 172890 240 0 FreeSans 560 90 0 0 la_data_in[62]
+port 250 nsew signal input
+flabel metal2 s 174607 -400 174663 240 0 FreeSans 560 90 0 0 la_data_in[63]
+port 251 nsew signal input
+flabel metal2 s 176380 -400 176436 240 0 FreeSans 560 90 0 0 la_data_in[64]
+port 252 nsew signal input
+flabel metal2 s 178153 -400 178209 240 0 FreeSans 560 90 0 0 la_data_in[65]
+port 253 nsew signal input
+flabel metal2 s 179926 -400 179982 240 0 FreeSans 560 90 0 0 la_data_in[66]
+port 254 nsew signal input
+flabel metal2 s 181699 -400 181755 240 0 FreeSans 560 90 0 0 la_data_in[67]
+port 255 nsew signal input
+flabel metal2 s 183472 -400 183528 240 0 FreeSans 560 90 0 0 la_data_in[68]
+port 256 nsew signal input
+flabel metal2 s 185245 -400 185301 240 0 FreeSans 560 90 0 0 la_data_in[69]
+port 257 nsew signal input
+flabel metal2 s 73546 -400 73602 240 0 FreeSans 560 90 0 0 la_data_in[6]
+port 258 nsew signal input
+flabel metal2 s 187018 -400 187074 240 0 FreeSans 560 90 0 0 la_data_in[70]
+port 259 nsew signal input
+flabel metal2 s 188791 -400 188847 240 0 FreeSans 560 90 0 0 la_data_in[71]
+port 260 nsew signal input
+flabel metal2 s 190564 -400 190620 240 0 FreeSans 560 90 0 0 la_data_in[72]
+port 261 nsew signal input
+flabel metal2 s 192337 -400 192393 240 0 FreeSans 560 90 0 0 la_data_in[73]
+port 262 nsew signal input
+flabel metal2 s 194110 -400 194166 240 0 FreeSans 560 90 0 0 la_data_in[74]
+port 263 nsew signal input
+flabel metal2 s 195883 -400 195939 240 0 FreeSans 560 90 0 0 la_data_in[75]
+port 264 nsew signal input
+flabel metal2 s 197656 -400 197712 240 0 FreeSans 560 90 0 0 la_data_in[76]
+port 265 nsew signal input
+flabel metal2 s 199429 -400 199485 240 0 FreeSans 560 90 0 0 la_data_in[77]
+port 266 nsew signal input
+flabel metal2 s 201202 -400 201258 240 0 FreeSans 560 90 0 0 la_data_in[78]
+port 267 nsew signal input
+flabel metal2 s 202975 -400 203031 240 0 FreeSans 560 90 0 0 la_data_in[79]
+port 268 nsew signal input
+flabel metal2 s 75319 -400 75375 240 0 FreeSans 560 90 0 0 la_data_in[7]
+port 269 nsew signal input
+flabel metal2 s 204748 -400 204804 240 0 FreeSans 560 90 0 0 la_data_in[80]
+port 270 nsew signal input
+flabel metal2 s 206521 -400 206577 240 0 FreeSans 560 90 0 0 la_data_in[81]
+port 271 nsew signal input
+flabel metal2 s 208294 -400 208350 240 0 FreeSans 560 90 0 0 la_data_in[82]
+port 272 nsew signal input
+flabel metal2 s 210067 -400 210123 240 0 FreeSans 560 90 0 0 la_data_in[83]
+port 273 nsew signal input
+flabel metal2 s 211840 -400 211896 240 0 FreeSans 560 90 0 0 la_data_in[84]
+port 274 nsew signal input
+flabel metal2 s 213613 -400 213669 240 0 FreeSans 560 90 0 0 la_data_in[85]
+port 275 nsew signal input
+flabel metal2 s 215386 -400 215442 240 0 FreeSans 560 90 0 0 la_data_in[86]
+port 276 nsew signal input
+flabel metal2 s 217159 -400 217215 240 0 FreeSans 560 90 0 0 la_data_in[87]
+port 277 nsew signal input
+flabel metal2 s 218932 -400 218988 240 0 FreeSans 560 90 0 0 la_data_in[88]
+port 278 nsew signal input
+flabel metal2 s 220705 -400 220761 240 0 FreeSans 560 90 0 0 la_data_in[89]
+port 279 nsew signal input
+flabel metal2 s 77092 -400 77148 240 0 FreeSans 560 90 0 0 la_data_in[8]
+port 280 nsew signal input
+flabel metal2 s 222478 -400 222534 240 0 FreeSans 560 90 0 0 la_data_in[90]
+port 281 nsew signal input
+flabel metal2 s 224251 -400 224307 240 0 FreeSans 560 90 0 0 la_data_in[91]
+port 282 nsew signal input
+flabel metal2 s 226024 -400 226080 240 0 FreeSans 560 90 0 0 la_data_in[92]
+port 283 nsew signal input
+flabel metal2 s 227797 -400 227853 240 0 FreeSans 560 90 0 0 la_data_in[93]
+port 284 nsew signal input
+flabel metal2 s 229570 -400 229626 240 0 FreeSans 560 90 0 0 la_data_in[94]
+port 285 nsew signal input
+flabel metal2 s 231343 -400 231399 240 0 FreeSans 560 90 0 0 la_data_in[95]
+port 286 nsew signal input
+flabel metal2 s 233116 -400 233172 240 0 FreeSans 560 90 0 0 la_data_in[96]
+port 287 nsew signal input
+flabel metal2 s 234889 -400 234945 240 0 FreeSans 560 90 0 0 la_data_in[97]
+port 288 nsew signal input
+flabel metal2 s 236662 -400 236718 240 0 FreeSans 560 90 0 0 la_data_in[98]
+port 289 nsew signal input
+flabel metal2 s 238435 -400 238491 240 0 FreeSans 560 90 0 0 la_data_in[99]
+port 290 nsew signal input
+flabel metal2 s 78865 -400 78921 240 0 FreeSans 560 90 0 0 la_data_in[9]
+port 291 nsew signal input
+flabel metal2 s 63499 -400 63555 240 0 FreeSans 560 90 0 0 la_data_out[0]
+port 292 nsew signal tristate
+flabel metal2 s 240799 -400 240855 240 0 FreeSans 560 90 0 0 la_data_out[100]
+port 293 nsew signal tristate
+flabel metal2 s 242572 -400 242628 240 0 FreeSans 560 90 0 0 la_data_out[101]
+port 294 nsew signal tristate
+flabel metal2 s 244345 -400 244401 240 0 FreeSans 560 90 0 0 la_data_out[102]
+port 295 nsew signal tristate
+flabel metal2 s 246118 -400 246174 240 0 FreeSans 560 90 0 0 la_data_out[103]
+port 296 nsew signal tristate
+flabel metal2 s 247891 -400 247947 240 0 FreeSans 560 90 0 0 la_data_out[104]
+port 297 nsew signal tristate
+flabel metal2 s 249664 -400 249720 240 0 FreeSans 560 90 0 0 la_data_out[105]
+port 298 nsew signal tristate
+flabel metal2 s 251437 -400 251493 240 0 FreeSans 560 90 0 0 la_data_out[106]
+port 299 nsew signal tristate
+flabel metal2 s 253210 -400 253266 240 0 FreeSans 560 90 0 0 la_data_out[107]
+port 300 nsew signal tristate
+flabel metal2 s 254983 -400 255039 240 0 FreeSans 560 90 0 0 la_data_out[108]
+port 301 nsew signal tristate
+flabel metal2 s 256756 -400 256812 240 0 FreeSans 560 90 0 0 la_data_out[109]
+port 302 nsew signal tristate
+flabel metal2 s 81229 -400 81285 240 0 FreeSans 560 90 0 0 la_data_out[10]
+port 303 nsew signal tristate
+flabel metal2 s 258529 -400 258585 240 0 FreeSans 560 90 0 0 la_data_out[110]
+port 304 nsew signal tristate
+flabel metal2 s 260302 -400 260358 240 0 FreeSans 560 90 0 0 la_data_out[111]
+port 305 nsew signal tristate
+flabel metal2 s 262075 -400 262131 240 0 FreeSans 560 90 0 0 la_data_out[112]
+port 306 nsew signal tristate
+flabel metal2 s 263848 -400 263904 240 0 FreeSans 560 90 0 0 la_data_out[113]
+port 307 nsew signal tristate
+flabel metal2 s 265621 -400 265677 240 0 FreeSans 560 90 0 0 la_data_out[114]
+port 308 nsew signal tristate
+flabel metal2 s 267394 -400 267450 240 0 FreeSans 560 90 0 0 la_data_out[115]
+port 309 nsew signal tristate
+flabel metal2 s 269167 -400 269223 240 0 FreeSans 560 90 0 0 la_data_out[116]
+port 310 nsew signal tristate
+flabel metal2 s 270940 -400 270996 240 0 FreeSans 560 90 0 0 la_data_out[117]
+port 311 nsew signal tristate
+flabel metal2 s 272713 -400 272769 240 0 FreeSans 560 90 0 0 la_data_out[118]
+port 312 nsew signal tristate
+flabel metal2 s 274486 -400 274542 240 0 FreeSans 560 90 0 0 la_data_out[119]
+port 313 nsew signal tristate
+flabel metal2 s 83002 -400 83058 240 0 FreeSans 560 90 0 0 la_data_out[11]
+port 314 nsew signal tristate
+flabel metal2 s 276259 -400 276315 240 0 FreeSans 560 90 0 0 la_data_out[120]
+port 315 nsew signal tristate
+flabel metal2 s 278032 -400 278088 240 0 FreeSans 560 90 0 0 la_data_out[121]
+port 316 nsew signal tristate
+flabel metal2 s 279805 -400 279861 240 0 FreeSans 560 90 0 0 la_data_out[122]
+port 317 nsew signal tristate
+flabel metal2 s 281578 -400 281634 240 0 FreeSans 560 90 0 0 la_data_out[123]
+port 318 nsew signal tristate
+flabel metal2 s 283351 -400 283407 240 0 FreeSans 560 90 0 0 la_data_out[124]
+port 319 nsew signal tristate
+flabel metal2 s 285124 -400 285180 240 0 FreeSans 560 90 0 0 la_data_out[125]
+port 320 nsew signal tristate
+flabel metal2 s 286897 -400 286953 240 0 FreeSans 560 90 0 0 la_data_out[126]
+port 321 nsew signal tristate
+flabel metal2 s 288670 -400 288726 240 0 FreeSans 560 90 0 0 la_data_out[127]
+port 322 nsew signal tristate
+flabel metal2 s 84775 -400 84831 240 0 FreeSans 560 90 0 0 la_data_out[12]
+port 323 nsew signal tristate
+flabel metal2 s 86548 -400 86604 240 0 FreeSans 560 90 0 0 la_data_out[13]
+port 324 nsew signal tristate
+flabel metal2 s 88321 -400 88377 240 0 FreeSans 560 90 0 0 la_data_out[14]
+port 325 nsew signal tristate
+flabel metal2 s 90094 -400 90150 240 0 FreeSans 560 90 0 0 la_data_out[15]
+port 326 nsew signal tristate
+flabel metal2 s 91867 -400 91923 240 0 FreeSans 560 90 0 0 la_data_out[16]
+port 327 nsew signal tristate
+flabel metal2 s 93640 -400 93696 240 0 FreeSans 560 90 0 0 la_data_out[17]
+port 328 nsew signal tristate
+flabel metal2 s 95413 -400 95469 240 0 FreeSans 560 90 0 0 la_data_out[18]
+port 329 nsew signal tristate
+flabel metal2 s 97186 -400 97242 240 0 FreeSans 560 90 0 0 la_data_out[19]
+port 330 nsew signal tristate
+flabel metal2 s 65272 -400 65328 240 0 FreeSans 560 90 0 0 la_data_out[1]
+port 331 nsew signal tristate
+flabel metal2 s 98959 -400 99015 240 0 FreeSans 560 90 0 0 la_data_out[20]
+port 332 nsew signal tristate
+flabel metal2 s 100732 -400 100788 240 0 FreeSans 560 90 0 0 la_data_out[21]
+port 333 nsew signal tristate
+flabel metal2 s 102505 -400 102561 240 0 FreeSans 560 90 0 0 la_data_out[22]
+port 334 nsew signal tristate
+flabel metal2 s 104278 -400 104334 240 0 FreeSans 560 90 0 0 la_data_out[23]
+port 335 nsew signal tristate
+flabel metal2 s 106051 -400 106107 240 0 FreeSans 560 90 0 0 la_data_out[24]
+port 336 nsew signal tristate
+flabel metal2 s 107824 -400 107880 240 0 FreeSans 560 90 0 0 la_data_out[25]
+port 337 nsew signal tristate
+flabel metal2 s 109597 -400 109653 240 0 FreeSans 560 90 0 0 la_data_out[26]
+port 338 nsew signal tristate
+flabel metal2 s 111370 -400 111426 240 0 FreeSans 560 90 0 0 la_data_out[27]
+port 339 nsew signal tristate
+flabel metal2 s 113143 -400 113199 240 0 FreeSans 560 90 0 0 la_data_out[28]
+port 340 nsew signal tristate
+flabel metal2 s 114916 -400 114972 240 0 FreeSans 560 90 0 0 la_data_out[29]
+port 341 nsew signal tristate
+flabel metal2 s 67045 -400 67101 240 0 FreeSans 560 90 0 0 la_data_out[2]
+port 342 nsew signal tristate
+flabel metal2 s 116689 -400 116745 240 0 FreeSans 560 90 0 0 la_data_out[30]
+port 343 nsew signal tristate
+flabel metal2 s 118462 -400 118518 240 0 FreeSans 560 90 0 0 la_data_out[31]
+port 344 nsew signal tristate
+flabel metal2 s 120235 -400 120291 240 0 FreeSans 560 90 0 0 la_data_out[32]
+port 345 nsew signal tristate
+flabel metal2 s 122008 -400 122064 240 0 FreeSans 560 90 0 0 la_data_out[33]
+port 346 nsew signal tristate
+flabel metal2 s 123781 -400 123837 240 0 FreeSans 560 90 0 0 la_data_out[34]
+port 347 nsew signal tristate
+flabel metal2 s 125554 -400 125610 240 0 FreeSans 560 90 0 0 la_data_out[35]
+port 348 nsew signal tristate
+flabel metal2 s 127327 -400 127383 240 0 FreeSans 560 90 0 0 la_data_out[36]
+port 349 nsew signal tristate
+flabel metal2 s 129100 -400 129156 240 0 FreeSans 560 90 0 0 la_data_out[37]
+port 350 nsew signal tristate
+flabel metal2 s 130873 -400 130929 240 0 FreeSans 560 90 0 0 la_data_out[38]
+port 351 nsew signal tristate
+flabel metal2 s 132646 -400 132702 240 0 FreeSans 560 90 0 0 la_data_out[39]
+port 352 nsew signal tristate
+flabel metal2 s 68818 -400 68874 240 0 FreeSans 560 90 0 0 la_data_out[3]
+port 353 nsew signal tristate
+flabel metal2 s 134419 -400 134475 240 0 FreeSans 560 90 0 0 la_data_out[40]
+port 354 nsew signal tristate
+flabel metal2 s 136192 -400 136248 240 0 FreeSans 560 90 0 0 la_data_out[41]
+port 355 nsew signal tristate
+flabel metal2 s 137965 -400 138021 240 0 FreeSans 560 90 0 0 la_data_out[42]
+port 356 nsew signal tristate
+flabel metal2 s 139738 -400 139794 240 0 FreeSans 560 90 0 0 la_data_out[43]
+port 357 nsew signal tristate
+flabel metal2 s 141511 -400 141567 240 0 FreeSans 560 90 0 0 la_data_out[44]
+port 358 nsew signal tristate
+flabel metal2 s 143284 -400 143340 240 0 FreeSans 560 90 0 0 la_data_out[45]
+port 359 nsew signal tristate
+flabel metal2 s 145057 -400 145113 240 0 FreeSans 560 90 0 0 la_data_out[46]
+port 360 nsew signal tristate
+flabel metal2 s 146830 -400 146886 240 0 FreeSans 560 90 0 0 la_data_out[47]
+port 361 nsew signal tristate
+flabel metal2 s 148603 -400 148659 240 0 FreeSans 560 90 0 0 la_data_out[48]
+port 362 nsew signal tristate
+flabel metal2 s 150376 -400 150432 240 0 FreeSans 560 90 0 0 la_data_out[49]
+port 363 nsew signal tristate
+flabel metal2 s 70591 -400 70647 240 0 FreeSans 560 90 0 0 la_data_out[4]
+port 364 nsew signal tristate
+flabel metal2 s 152149 -400 152205 240 0 FreeSans 560 90 0 0 la_data_out[50]
+port 365 nsew signal tristate
+flabel metal2 s 153922 -400 153978 240 0 FreeSans 560 90 0 0 la_data_out[51]
+port 366 nsew signal tristate
+flabel metal2 s 155695 -400 155751 240 0 FreeSans 560 90 0 0 la_data_out[52]
+port 367 nsew signal tristate
+flabel metal2 s 157468 -400 157524 240 0 FreeSans 560 90 0 0 la_data_out[53]
+port 368 nsew signal tristate
+flabel metal2 s 159241 -400 159297 240 0 FreeSans 560 90 0 0 la_data_out[54]
+port 369 nsew signal tristate
+flabel metal2 s 161014 -400 161070 240 0 FreeSans 560 90 0 0 la_data_out[55]
+port 370 nsew signal tristate
+flabel metal2 s 162787 -400 162843 240 0 FreeSans 560 90 0 0 la_data_out[56]
+port 371 nsew signal tristate
+flabel metal2 s 164560 -400 164616 240 0 FreeSans 560 90 0 0 la_data_out[57]
+port 372 nsew signal tristate
+flabel metal2 s 166333 -400 166389 240 0 FreeSans 560 90 0 0 la_data_out[58]
+port 373 nsew signal tristate
+flabel metal2 s 168106 -400 168162 240 0 FreeSans 560 90 0 0 la_data_out[59]
+port 374 nsew signal tristate
+flabel metal2 s 72364 -400 72420 240 0 FreeSans 560 90 0 0 la_data_out[5]
+port 375 nsew signal tristate
+flabel metal2 s 169879 -400 169935 240 0 FreeSans 560 90 0 0 la_data_out[60]
+port 376 nsew signal tristate
+flabel metal2 s 171652 -400 171708 240 0 FreeSans 560 90 0 0 la_data_out[61]
+port 377 nsew signal tristate
+flabel metal2 s 173425 -400 173481 240 0 FreeSans 560 90 0 0 la_data_out[62]
+port 378 nsew signal tristate
+flabel metal2 s 175198 -400 175254 240 0 FreeSans 560 90 0 0 la_data_out[63]
+port 379 nsew signal tristate
+flabel metal2 s 176971 -400 177027 240 0 FreeSans 560 90 0 0 la_data_out[64]
+port 380 nsew signal tristate
+flabel metal2 s 178744 -400 178800 240 0 FreeSans 560 90 0 0 la_data_out[65]
+port 381 nsew signal tristate
+flabel metal2 s 180517 -400 180573 240 0 FreeSans 560 90 0 0 la_data_out[66]
+port 382 nsew signal tristate
+flabel metal2 s 182290 -400 182346 240 0 FreeSans 560 90 0 0 la_data_out[67]
+port 383 nsew signal tristate
+flabel metal2 s 184063 -400 184119 240 0 FreeSans 560 90 0 0 la_data_out[68]
+port 384 nsew signal tristate
+flabel metal2 s 185836 -400 185892 240 0 FreeSans 560 90 0 0 la_data_out[69]
+port 385 nsew signal tristate
+flabel metal2 s 74137 -400 74193 240 0 FreeSans 560 90 0 0 la_data_out[6]
+port 386 nsew signal tristate
+flabel metal2 s 187609 -400 187665 240 0 FreeSans 560 90 0 0 la_data_out[70]
+port 387 nsew signal tristate
+flabel metal2 s 189382 -400 189438 240 0 FreeSans 560 90 0 0 la_data_out[71]
+port 388 nsew signal tristate
+flabel metal2 s 191155 -400 191211 240 0 FreeSans 560 90 0 0 la_data_out[72]
+port 389 nsew signal tristate
+flabel metal2 s 192928 -400 192984 240 0 FreeSans 560 90 0 0 la_data_out[73]
+port 390 nsew signal tristate
+flabel metal2 s 194701 -400 194757 240 0 FreeSans 560 90 0 0 la_data_out[74]
+port 391 nsew signal tristate
+flabel metal2 s 196474 -400 196530 240 0 FreeSans 560 90 0 0 la_data_out[75]
+port 392 nsew signal tristate
+flabel metal2 s 198247 -400 198303 240 0 FreeSans 560 90 0 0 la_data_out[76]
+port 393 nsew signal tristate
+flabel metal2 s 200020 -400 200076 240 0 FreeSans 560 90 0 0 la_data_out[77]
+port 394 nsew signal tristate
+flabel metal2 s 201793 -400 201849 240 0 FreeSans 560 90 0 0 la_data_out[78]
+port 395 nsew signal tristate
+flabel metal2 s 203566 -400 203622 240 0 FreeSans 560 90 0 0 la_data_out[79]
+port 396 nsew signal tristate
+flabel metal2 s 75910 -400 75966 240 0 FreeSans 560 90 0 0 la_data_out[7]
+port 397 nsew signal tristate
+flabel metal2 s 205339 -400 205395 240 0 FreeSans 560 90 0 0 la_data_out[80]
+port 398 nsew signal tristate
+flabel metal2 s 207112 -400 207168 240 0 FreeSans 560 90 0 0 la_data_out[81]
+port 399 nsew signal tristate
+flabel metal2 s 208885 -400 208941 240 0 FreeSans 560 90 0 0 la_data_out[82]
+port 400 nsew signal tristate
+flabel metal2 s 210658 -400 210714 240 0 FreeSans 560 90 0 0 la_data_out[83]
+port 401 nsew signal tristate
+flabel metal2 s 212431 -400 212487 240 0 FreeSans 560 90 0 0 la_data_out[84]
+port 402 nsew signal tristate
+flabel metal2 s 214204 -400 214260 240 0 FreeSans 560 90 0 0 la_data_out[85]
+port 403 nsew signal tristate
+flabel metal2 s 215977 -400 216033 240 0 FreeSans 560 90 0 0 la_data_out[86]
+port 404 nsew signal tristate
+flabel metal2 s 217750 -400 217806 240 0 FreeSans 560 90 0 0 la_data_out[87]
+port 405 nsew signal tristate
+flabel metal2 s 219523 -400 219579 240 0 FreeSans 560 90 0 0 la_data_out[88]
+port 406 nsew signal tristate
+flabel metal2 s 221296 -400 221352 240 0 FreeSans 560 90 0 0 la_data_out[89]
+port 407 nsew signal tristate
+flabel metal2 s 77683 -400 77739 240 0 FreeSans 560 90 0 0 la_data_out[8]
+port 408 nsew signal tristate
+flabel metal2 s 223069 -400 223125 240 0 FreeSans 560 90 0 0 la_data_out[90]
+port 409 nsew signal tristate
+flabel metal2 s 224842 -400 224898 240 0 FreeSans 560 90 0 0 la_data_out[91]
+port 410 nsew signal tristate
+flabel metal2 s 226615 -400 226671 240 0 FreeSans 560 90 0 0 la_data_out[92]
+port 411 nsew signal tristate
+flabel metal2 s 228388 -400 228444 240 0 FreeSans 560 90 0 0 la_data_out[93]
+port 412 nsew signal tristate
+flabel metal2 s 230161 -400 230217 240 0 FreeSans 560 90 0 0 la_data_out[94]
+port 413 nsew signal tristate
+flabel metal2 s 231934 -400 231990 240 0 FreeSans 560 90 0 0 la_data_out[95]
+port 414 nsew signal tristate
+flabel metal2 s 233707 -400 233763 240 0 FreeSans 560 90 0 0 la_data_out[96]
+port 415 nsew signal tristate
+flabel metal2 s 235480 -400 235536 240 0 FreeSans 560 90 0 0 la_data_out[97]
+port 416 nsew signal tristate
+flabel metal2 s 237253 -400 237309 240 0 FreeSans 560 90 0 0 la_data_out[98]
+port 417 nsew signal tristate
+flabel metal2 s 239026 -400 239082 240 0 FreeSans 560 90 0 0 la_data_out[99]
+port 418 nsew signal tristate
+flabel metal2 s 79456 -400 79512 240 0 FreeSans 560 90 0 0 la_data_out[9]
+port 419 nsew signal tristate
+flabel metal2 s 64090 -400 64146 240 0 FreeSans 560 90 0 0 la_oenb[0]
+port 420 nsew signal input
+flabel metal2 s 241390 -400 241446 240 0 FreeSans 560 90 0 0 la_oenb[100]
+port 421 nsew signal input
+flabel metal2 s 243163 -400 243219 240 0 FreeSans 560 90 0 0 la_oenb[101]
+port 422 nsew signal input
+flabel metal2 s 244936 -400 244992 240 0 FreeSans 560 90 0 0 la_oenb[102]
+port 423 nsew signal input
+flabel metal2 s 246709 -400 246765 240 0 FreeSans 560 90 0 0 la_oenb[103]
+port 424 nsew signal input
+flabel metal2 s 248482 -400 248538 240 0 FreeSans 560 90 0 0 la_oenb[104]
+port 425 nsew signal input
+flabel metal2 s 250255 -400 250311 240 0 FreeSans 560 90 0 0 la_oenb[105]
+port 426 nsew signal input
+flabel metal2 s 252028 -400 252084 240 0 FreeSans 560 90 0 0 la_oenb[106]
+port 427 nsew signal input
+flabel metal2 s 253801 -400 253857 240 0 FreeSans 560 90 0 0 la_oenb[107]
+port 428 nsew signal input
+flabel metal2 s 255574 -400 255630 240 0 FreeSans 560 90 0 0 la_oenb[108]
+port 429 nsew signal input
+flabel metal2 s 257347 -400 257403 240 0 FreeSans 560 90 0 0 la_oenb[109]
+port 430 nsew signal input
+flabel metal2 s 81820 -400 81876 240 0 FreeSans 560 90 0 0 la_oenb[10]
+port 431 nsew signal input
+flabel metal2 s 259120 -400 259176 240 0 FreeSans 560 90 0 0 la_oenb[110]
+port 432 nsew signal input
+flabel metal2 s 260893 -400 260949 240 0 FreeSans 560 90 0 0 la_oenb[111]
+port 433 nsew signal input
+flabel metal2 s 262666 -400 262722 240 0 FreeSans 560 90 0 0 la_oenb[112]
+port 434 nsew signal input
+flabel metal2 s 264439 -400 264495 240 0 FreeSans 560 90 0 0 la_oenb[113]
+port 435 nsew signal input
+flabel metal2 s 266212 -400 266268 240 0 FreeSans 560 90 0 0 la_oenb[114]
+port 436 nsew signal input
+flabel metal2 s 267985 -400 268041 240 0 FreeSans 560 90 0 0 la_oenb[115]
+port 437 nsew signal input
+flabel metal2 s 269758 -400 269814 240 0 FreeSans 560 90 0 0 la_oenb[116]
+port 438 nsew signal input
+flabel metal2 s 271531 -400 271587 240 0 FreeSans 560 90 0 0 la_oenb[117]
+port 439 nsew signal input
+flabel metal2 s 273304 -400 273360 240 0 FreeSans 560 90 0 0 la_oenb[118]
+port 440 nsew signal input
+flabel metal2 s 275077 -400 275133 240 0 FreeSans 560 90 0 0 la_oenb[119]
+port 441 nsew signal input
+flabel metal2 s 83593 -400 83649 240 0 FreeSans 560 90 0 0 la_oenb[11]
+port 442 nsew signal input
+flabel metal2 s 276850 -400 276906 240 0 FreeSans 560 90 0 0 la_oenb[120]
+port 443 nsew signal input
+flabel metal2 s 278623 -400 278679 240 0 FreeSans 560 90 0 0 la_oenb[121]
+port 444 nsew signal input
+flabel metal2 s 280396 -400 280452 240 0 FreeSans 560 90 0 0 la_oenb[122]
+port 445 nsew signal input
+flabel metal2 s 282169 -400 282225 240 0 FreeSans 560 90 0 0 la_oenb[123]
+port 446 nsew signal input
+flabel metal2 s 283942 -400 283998 240 0 FreeSans 560 90 0 0 la_oenb[124]
+port 447 nsew signal input
+flabel metal2 s 285715 -400 285771 240 0 FreeSans 560 90 0 0 la_oenb[125]
+port 448 nsew signal input
+flabel metal2 s 287488 -400 287544 240 0 FreeSans 560 90 0 0 la_oenb[126]
+port 449 nsew signal input
+flabel metal2 s 289261 -400 289317 240 0 FreeSans 560 90 0 0 la_oenb[127]
+port 450 nsew signal input
+flabel metal2 s 85366 -400 85422 240 0 FreeSans 560 90 0 0 la_oenb[12]
+port 451 nsew signal input
+flabel metal2 s 87139 -400 87195 240 0 FreeSans 560 90 0 0 la_oenb[13]
+port 452 nsew signal input
+flabel metal2 s 88912 -400 88968 240 0 FreeSans 560 90 0 0 la_oenb[14]
+port 453 nsew signal input
+flabel metal2 s 90685 -400 90741 240 0 FreeSans 560 90 0 0 la_oenb[15]
+port 454 nsew signal input
+flabel metal2 s 92458 -400 92514 240 0 FreeSans 560 90 0 0 la_oenb[16]
+port 455 nsew signal input
+flabel metal2 s 94231 -400 94287 240 0 FreeSans 560 90 0 0 la_oenb[17]
+port 456 nsew signal input
+flabel metal2 s 96004 -400 96060 240 0 FreeSans 560 90 0 0 la_oenb[18]
+port 457 nsew signal input
+flabel metal2 s 97777 -400 97833 240 0 FreeSans 560 90 0 0 la_oenb[19]
+port 458 nsew signal input
+flabel metal2 s 65863 -400 65919 240 0 FreeSans 560 90 0 0 la_oenb[1]
+port 459 nsew signal input
+flabel metal2 s 99550 -400 99606 240 0 FreeSans 560 90 0 0 la_oenb[20]
+port 460 nsew signal input
+flabel metal2 s 101323 -400 101379 240 0 FreeSans 560 90 0 0 la_oenb[21]
+port 461 nsew signal input
+flabel metal2 s 103096 -400 103152 240 0 FreeSans 560 90 0 0 la_oenb[22]
+port 462 nsew signal input
+flabel metal2 s 104869 -400 104925 240 0 FreeSans 560 90 0 0 la_oenb[23]
+port 463 nsew signal input
+flabel metal2 s 106642 -400 106698 240 0 FreeSans 560 90 0 0 la_oenb[24]
+port 464 nsew signal input
+flabel metal2 s 108415 -400 108471 240 0 FreeSans 560 90 0 0 la_oenb[25]
+port 465 nsew signal input
+flabel metal2 s 110188 -400 110244 240 0 FreeSans 560 90 0 0 la_oenb[26]
+port 466 nsew signal input
+flabel metal2 s 111961 -400 112017 240 0 FreeSans 560 90 0 0 la_oenb[27]
+port 467 nsew signal input
+flabel metal2 s 113734 -400 113790 240 0 FreeSans 560 90 0 0 la_oenb[28]
+port 468 nsew signal input
+flabel metal2 s 115507 -400 115563 240 0 FreeSans 560 90 0 0 la_oenb[29]
+port 469 nsew signal input
+flabel metal2 s 67636 -400 67692 240 0 FreeSans 560 90 0 0 la_oenb[2]
+port 470 nsew signal input
+flabel metal2 s 117280 -400 117336 240 0 FreeSans 560 90 0 0 la_oenb[30]
+port 471 nsew signal input
+flabel metal2 s 119053 -400 119109 240 0 FreeSans 560 90 0 0 la_oenb[31]
+port 472 nsew signal input
+flabel metal2 s 120826 -400 120882 240 0 FreeSans 560 90 0 0 la_oenb[32]
+port 473 nsew signal input
+flabel metal2 s 122599 -400 122655 240 0 FreeSans 560 90 0 0 la_oenb[33]
+port 474 nsew signal input
+flabel metal2 s 124372 -400 124428 240 0 FreeSans 560 90 0 0 la_oenb[34]
+port 475 nsew signal input
+flabel metal2 s 126145 -400 126201 240 0 FreeSans 560 90 0 0 la_oenb[35]
+port 476 nsew signal input
+flabel metal2 s 127918 -400 127974 240 0 FreeSans 560 90 0 0 la_oenb[36]
+port 477 nsew signal input
+flabel metal2 s 129691 -400 129747 240 0 FreeSans 560 90 0 0 la_oenb[37]
+port 478 nsew signal input
+flabel metal2 s 131464 -400 131520 240 0 FreeSans 560 90 0 0 la_oenb[38]
+port 479 nsew signal input
+flabel metal2 s 133237 -400 133293 240 0 FreeSans 560 90 0 0 la_oenb[39]
+port 480 nsew signal input
+flabel metal2 s 69409 -400 69465 240 0 FreeSans 560 90 0 0 la_oenb[3]
+port 481 nsew signal input
+flabel metal2 s 135010 -400 135066 240 0 FreeSans 560 90 0 0 la_oenb[40]
+port 482 nsew signal input
+flabel metal2 s 136783 -400 136839 240 0 FreeSans 560 90 0 0 la_oenb[41]
+port 483 nsew signal input
+flabel metal2 s 138556 -400 138612 240 0 FreeSans 560 90 0 0 la_oenb[42]
+port 484 nsew signal input
+flabel metal2 s 140329 -400 140385 240 0 FreeSans 560 90 0 0 la_oenb[43]
+port 485 nsew signal input
+flabel metal2 s 142102 -400 142158 240 0 FreeSans 560 90 0 0 la_oenb[44]
+port 486 nsew signal input
+flabel metal2 s 143875 -400 143931 240 0 FreeSans 560 90 0 0 la_oenb[45]
+port 487 nsew signal input
+flabel metal2 s 145648 -400 145704 240 0 FreeSans 560 90 0 0 la_oenb[46]
+port 488 nsew signal input
+flabel metal2 s 147421 -400 147477 240 0 FreeSans 560 90 0 0 la_oenb[47]
+port 489 nsew signal input
+flabel metal2 s 149194 -400 149250 240 0 FreeSans 560 90 0 0 la_oenb[48]
+port 490 nsew signal input
+flabel metal2 s 150967 -400 151023 240 0 FreeSans 560 90 0 0 la_oenb[49]
+port 491 nsew signal input
+flabel metal2 s 71182 -400 71238 240 0 FreeSans 560 90 0 0 la_oenb[4]
+port 492 nsew signal input
+flabel metal2 s 152740 -400 152796 240 0 FreeSans 560 90 0 0 la_oenb[50]
+port 493 nsew signal input
+flabel metal2 s 154513 -400 154569 240 0 FreeSans 560 90 0 0 la_oenb[51]
+port 494 nsew signal input
+flabel metal2 s 156286 -400 156342 240 0 FreeSans 560 90 0 0 la_oenb[52]
+port 495 nsew signal input
+flabel metal2 s 158059 -400 158115 240 0 FreeSans 560 90 0 0 la_oenb[53]
+port 496 nsew signal input
+flabel metal2 s 159832 -400 159888 240 0 FreeSans 560 90 0 0 la_oenb[54]
+port 497 nsew signal input
+flabel metal2 s 161605 -400 161661 240 0 FreeSans 560 90 0 0 la_oenb[55]
+port 498 nsew signal input
+flabel metal2 s 163378 -400 163434 240 0 FreeSans 560 90 0 0 la_oenb[56]
+port 499 nsew signal input
+flabel metal2 s 165151 -400 165207 240 0 FreeSans 560 90 0 0 la_oenb[57]
+port 500 nsew signal input
+flabel metal2 s 166924 -400 166980 240 0 FreeSans 560 90 0 0 la_oenb[58]
+port 501 nsew signal input
+flabel metal2 s 168697 -400 168753 240 0 FreeSans 560 90 0 0 la_oenb[59]
+port 502 nsew signal input
+flabel metal2 s 72955 -400 73011 240 0 FreeSans 560 90 0 0 la_oenb[5]
+port 503 nsew signal input
+flabel metal2 s 170470 -400 170526 240 0 FreeSans 560 90 0 0 la_oenb[60]
+port 504 nsew signal input
+flabel metal2 s 172243 -400 172299 240 0 FreeSans 560 90 0 0 la_oenb[61]
+port 505 nsew signal input
+flabel metal2 s 174016 -400 174072 240 0 FreeSans 560 90 0 0 la_oenb[62]
+port 506 nsew signal input
+flabel metal2 s 175789 -400 175845 240 0 FreeSans 560 90 0 0 la_oenb[63]
+port 507 nsew signal input
+flabel metal2 s 177562 -400 177618 240 0 FreeSans 560 90 0 0 la_oenb[64]
+port 508 nsew signal input
+flabel metal2 s 179335 -400 179391 240 0 FreeSans 560 90 0 0 la_oenb[65]
+port 509 nsew signal input
+flabel metal2 s 181108 -400 181164 240 0 FreeSans 560 90 0 0 la_oenb[66]
+port 510 nsew signal input
+flabel metal2 s 182881 -400 182937 240 0 FreeSans 560 90 0 0 la_oenb[67]
+port 511 nsew signal input
+flabel metal2 s 184654 -400 184710 240 0 FreeSans 560 90 0 0 la_oenb[68]
+port 512 nsew signal input
+flabel metal2 s 186427 -400 186483 240 0 FreeSans 560 90 0 0 la_oenb[69]
+port 513 nsew signal input
+flabel metal2 s 74728 -400 74784 240 0 FreeSans 560 90 0 0 la_oenb[6]
+port 514 nsew signal input
+flabel metal2 s 188200 -400 188256 240 0 FreeSans 560 90 0 0 la_oenb[70]
+port 515 nsew signal input
+flabel metal2 s 189973 -400 190029 240 0 FreeSans 560 90 0 0 la_oenb[71]
+port 516 nsew signal input
+flabel metal2 s 191746 -400 191802 240 0 FreeSans 560 90 0 0 la_oenb[72]
+port 517 nsew signal input
+flabel metal2 s 193519 -400 193575 240 0 FreeSans 560 90 0 0 la_oenb[73]
+port 518 nsew signal input
+flabel metal2 s 195292 -400 195348 240 0 FreeSans 560 90 0 0 la_oenb[74]
+port 519 nsew signal input
+flabel metal2 s 197065 -400 197121 240 0 FreeSans 560 90 0 0 la_oenb[75]
+port 520 nsew signal input
+flabel metal2 s 198838 -400 198894 240 0 FreeSans 560 90 0 0 la_oenb[76]
+port 521 nsew signal input
+flabel metal2 s 200611 -400 200667 240 0 FreeSans 560 90 0 0 la_oenb[77]
+port 522 nsew signal input
+flabel metal2 s 202384 -400 202440 240 0 FreeSans 560 90 0 0 la_oenb[78]
+port 523 nsew signal input
+flabel metal2 s 204157 -400 204213 240 0 FreeSans 560 90 0 0 la_oenb[79]
+port 524 nsew signal input
+flabel metal2 s 76501 -400 76557 240 0 FreeSans 560 90 0 0 la_oenb[7]
+port 525 nsew signal input
+flabel metal2 s 205930 -400 205986 240 0 FreeSans 560 90 0 0 la_oenb[80]
+port 526 nsew signal input
+flabel metal2 s 207703 -400 207759 240 0 FreeSans 560 90 0 0 la_oenb[81]
+port 527 nsew signal input
+flabel metal2 s 209476 -400 209532 240 0 FreeSans 560 90 0 0 la_oenb[82]
+port 528 nsew signal input
+flabel metal2 s 211249 -400 211305 240 0 FreeSans 560 90 0 0 la_oenb[83]
+port 529 nsew signal input
+flabel metal2 s 213022 -400 213078 240 0 FreeSans 560 90 0 0 la_oenb[84]
+port 530 nsew signal input
+flabel metal2 s 214795 -400 214851 240 0 FreeSans 560 90 0 0 la_oenb[85]
+port 531 nsew signal input
+flabel metal2 s 216568 -400 216624 240 0 FreeSans 560 90 0 0 la_oenb[86]
+port 532 nsew signal input
+flabel metal2 s 218341 -400 218397 240 0 FreeSans 560 90 0 0 la_oenb[87]
+port 533 nsew signal input
+flabel metal2 s 220114 -400 220170 240 0 FreeSans 560 90 0 0 la_oenb[88]
+port 534 nsew signal input
+flabel metal2 s 221887 -400 221943 240 0 FreeSans 560 90 0 0 la_oenb[89]
+port 535 nsew signal input
+flabel metal2 s 78274 -400 78330 240 0 FreeSans 560 90 0 0 la_oenb[8]
+port 536 nsew signal input
+flabel metal2 s 223660 -400 223716 240 0 FreeSans 560 90 0 0 la_oenb[90]
+port 537 nsew signal input
+flabel metal2 s 225433 -400 225489 240 0 FreeSans 560 90 0 0 la_oenb[91]
+port 538 nsew signal input
+flabel metal2 s 227206 -400 227262 240 0 FreeSans 560 90 0 0 la_oenb[92]
+port 539 nsew signal input
+flabel metal2 s 228979 -400 229035 240 0 FreeSans 560 90 0 0 la_oenb[93]
+port 540 nsew signal input
+flabel metal2 s 230752 -400 230808 240 0 FreeSans 560 90 0 0 la_oenb[94]
+port 541 nsew signal input
+flabel metal2 s 232525 -400 232581 240 0 FreeSans 560 90 0 0 la_oenb[95]
+port 542 nsew signal input
+flabel metal2 s 234298 -400 234354 240 0 FreeSans 560 90 0 0 la_oenb[96]
+port 543 nsew signal input
+flabel metal2 s 236071 -400 236127 240 0 FreeSans 560 90 0 0 la_oenb[97]
+port 544 nsew signal input
+flabel metal2 s 237844 -400 237900 240 0 FreeSans 560 90 0 0 la_oenb[98]
+port 545 nsew signal input
+flabel metal2 s 239617 -400 239673 240 0 FreeSans 560 90 0 0 la_oenb[99]
+port 546 nsew signal input
+flabel metal2 s 80047 -400 80103 240 0 FreeSans 560 90 0 0 la_oenb[9]
+port 547 nsew signal input
+flabel metal2 s 289852 -400 289908 240 0 FreeSans 560 90 0 0 user_clock2
+port 548 nsew signal input
+flabel metal2 s 290443 -400 290499 240 0 FreeSans 560 90 0 0 user_irq[0]
+port 549 nsew signal tristate
+flabel metal2 s 291034 -400 291090 240 0 FreeSans 560 90 0 0 user_irq[1]
+port 550 nsew signal tristate
+flabel metal2 s 291625 -400 291681 240 0 FreeSans 560 90 0 0 user_irq[2]
+port 551 nsew signal tristate
+flabel metal3 s 291170 319892 292400 322292 0 FreeSans 560 0 0 0 vccd1
+port 552 nsew signal bidirectional
+flabel metal3 s 291170 314892 292400 317292 0 FreeSans 560 0 0 0 vccd1
+port 553 nsew signal bidirectional
+flabel metal3 s 0 321921 830 324321 0 FreeSans 560 0 0 0 vccd2
+port 554 nsew signal bidirectional
+flabel metal3 s 0 316921 830 319321 0 FreeSans 560 0 0 0 vccd2
+port 555 nsew signal bidirectional
+flabel metal3 s 291170 270281 292400 272681 0 FreeSans 560 0 0 0 vdda1
+port 556 nsew signal bidirectional
+flabel metal3 s 291170 275281 292400 277681 0 FreeSans 560 0 0 0 vdda1
+port 557 nsew signal bidirectional
+flabel metal3 s 291170 117615 292400 120015 0 FreeSans 560 0 0 0 vdda1
+port 558 nsew signal bidirectional
+flabel metal3 s 291170 112615 292400 115015 0 FreeSans 560 0 0 0 vdda1
+port 559 nsew signal bidirectional
+flabel metal3 s 0 102444 830 104844 0 FreeSans 560 0 0 0 vdda2
+port 560 nsew signal bidirectional
+flabel metal3 s 0 107444 830 109844 0 FreeSans 560 0 0 0 vdda2
+port 561 nsew signal bidirectional
+flabel metal3 s 260297 351170 262697 352400 0 FreeSans 960 180 0 0 vssa1
+port 562 nsew signal bidirectional
+flabel metal3 s 255297 351170 257697 352400 0 FreeSans 960 180 0 0 vssa1
+port 563 nsew signal bidirectional
+flabel metal3 s 291170 73415 292400 75815 0 FreeSans 560 0 0 0 vssa1
+port 564 nsew signal bidirectional
+flabel metal3 s 291170 68415 292400 70815 0 FreeSans 560 0 0 0 vssa1
+port 565 nsew signal bidirectional
+flabel metal3 s 0 279721 830 282121 0 FreeSans 560 0 0 0 vssa2
+port 566 nsew signal bidirectional
+flabel metal3 s 0 274721 830 277121 0 FreeSans 560 0 0 0 vssa2
+port 567 nsew signal bidirectional
+flabel metal3 s 291170 95715 292400 98115 0 FreeSans 560 0 0 0 vssd1
+port 568 nsew signal bidirectional
+flabel metal3 s 291170 90715 292400 93115 0 FreeSans 560 0 0 0 vssd1
+port 569 nsew signal bidirectional
+flabel metal3 s 0 86444 830 88844 0 FreeSans 560 0 0 0 vssd2
+port 570 nsew signal bidirectional
+flabel metal3 s 0 81444 830 83844 0 FreeSans 560 0 0 0 vssd2
+port 571 nsew signal bidirectional
+flabel metal2 s 262 -400 318 240 0 FreeSans 560 90 0 0 wb_clk_i
+port 572 nsew signal input
+flabel metal2 s 853 -400 909 240 0 FreeSans 560 90 0 0 wb_rst_i
+port 573 nsew signal input
+flabel metal2 s 1444 -400 1500 240 0 FreeSans 560 90 0 0 wbs_ack_o
+port 574 nsew signal tristate
+flabel metal2 s 3808 -400 3864 240 0 FreeSans 560 90 0 0 wbs_adr_i[0]
+port 575 nsew signal input
+flabel metal2 s 23902 -400 23958 240 0 FreeSans 560 90 0 0 wbs_adr_i[10]
+port 576 nsew signal input
+flabel metal2 s 25675 -400 25731 240 0 FreeSans 560 90 0 0 wbs_adr_i[11]
+port 577 nsew signal input
+flabel metal2 s 27448 -400 27504 240 0 FreeSans 560 90 0 0 wbs_adr_i[12]
+port 578 nsew signal input
+flabel metal2 s 29221 -400 29277 240 0 FreeSans 560 90 0 0 wbs_adr_i[13]
+port 579 nsew signal input
+flabel metal2 s 30994 -400 31050 240 0 FreeSans 560 90 0 0 wbs_adr_i[14]
+port 580 nsew signal input
+flabel metal2 s 32767 -400 32823 240 0 FreeSans 560 90 0 0 wbs_adr_i[15]
+port 581 nsew signal input
+flabel metal2 s 34540 -400 34596 240 0 FreeSans 560 90 0 0 wbs_adr_i[16]
+port 582 nsew signal input
+flabel metal2 s 36313 -400 36369 240 0 FreeSans 560 90 0 0 wbs_adr_i[17]
+port 583 nsew signal input
+flabel metal2 s 38086 -400 38142 240 0 FreeSans 560 90 0 0 wbs_adr_i[18]
+port 584 nsew signal input
+flabel metal2 s 39859 -400 39915 240 0 FreeSans 560 90 0 0 wbs_adr_i[19]
+port 585 nsew signal input
+flabel metal2 s 6172 -400 6228 240 0 FreeSans 560 90 0 0 wbs_adr_i[1]
+port 586 nsew signal input
+flabel metal2 s 41632 -400 41688 240 0 FreeSans 560 90 0 0 wbs_adr_i[20]
+port 587 nsew signal input
+flabel metal2 s 43405 -400 43461 240 0 FreeSans 560 90 0 0 wbs_adr_i[21]
+port 588 nsew signal input
+flabel metal2 s 45178 -400 45234 240 0 FreeSans 560 90 0 0 wbs_adr_i[22]
+port 589 nsew signal input
+flabel metal2 s 46951 -400 47007 240 0 FreeSans 560 90 0 0 wbs_adr_i[23]
+port 590 nsew signal input
+flabel metal2 s 48724 -400 48780 240 0 FreeSans 560 90 0 0 wbs_adr_i[24]
+port 591 nsew signal input
+flabel metal2 s 50497 -400 50553 240 0 FreeSans 560 90 0 0 wbs_adr_i[25]
+port 592 nsew signal input
+flabel metal2 s 52270 -400 52326 240 0 FreeSans 560 90 0 0 wbs_adr_i[26]
+port 593 nsew signal input
+flabel metal2 s 54043 -400 54099 240 0 FreeSans 560 90 0 0 wbs_adr_i[27]
+port 594 nsew signal input
+flabel metal2 s 55816 -400 55872 240 0 FreeSans 560 90 0 0 wbs_adr_i[28]
+port 595 nsew signal input
+flabel metal2 s 57589 -400 57645 240 0 FreeSans 560 90 0 0 wbs_adr_i[29]
+port 596 nsew signal input
+flabel metal2 s 8536 -400 8592 240 0 FreeSans 560 90 0 0 wbs_adr_i[2]
+port 597 nsew signal input
+flabel metal2 s 59362 -400 59418 240 0 FreeSans 560 90 0 0 wbs_adr_i[30]
+port 598 nsew signal input
+flabel metal2 s 61135 -400 61191 240 0 FreeSans 560 90 0 0 wbs_adr_i[31]
+port 599 nsew signal input
+flabel metal2 s 10900 -400 10956 240 0 FreeSans 560 90 0 0 wbs_adr_i[3]
+port 600 nsew signal input
+flabel metal2 s 13264 -400 13320 240 0 FreeSans 560 90 0 0 wbs_adr_i[4]
+port 601 nsew signal input
+flabel metal2 s 15037 -400 15093 240 0 FreeSans 560 90 0 0 wbs_adr_i[5]
+port 602 nsew signal input
+flabel metal2 s 16810 -400 16866 240 0 FreeSans 560 90 0 0 wbs_adr_i[6]
+port 603 nsew signal input
+flabel metal2 s 18583 -400 18639 240 0 FreeSans 560 90 0 0 wbs_adr_i[7]
+port 604 nsew signal input
+flabel metal2 s 20356 -400 20412 240 0 FreeSans 560 90 0 0 wbs_adr_i[8]
+port 605 nsew signal input
+flabel metal2 s 22129 -400 22185 240 0 FreeSans 560 90 0 0 wbs_adr_i[9]
+port 606 nsew signal input
+flabel metal2 s 2035 -400 2091 240 0 FreeSans 560 90 0 0 wbs_cyc_i
+port 607 nsew signal input
+flabel metal2 s 4399 -400 4455 240 0 FreeSans 560 90 0 0 wbs_dat_i[0]
+port 608 nsew signal input
+flabel metal2 s 24493 -400 24549 240 0 FreeSans 560 90 0 0 wbs_dat_i[10]
+port 609 nsew signal input
+flabel metal2 s 26266 -400 26322 240 0 FreeSans 560 90 0 0 wbs_dat_i[11]
+port 610 nsew signal input
+flabel metal2 s 28039 -400 28095 240 0 FreeSans 560 90 0 0 wbs_dat_i[12]
+port 611 nsew signal input
+flabel metal2 s 29812 -400 29868 240 0 FreeSans 560 90 0 0 wbs_dat_i[13]
+port 612 nsew signal input
+flabel metal2 s 31585 -400 31641 240 0 FreeSans 560 90 0 0 wbs_dat_i[14]
+port 613 nsew signal input
+flabel metal2 s 33358 -400 33414 240 0 FreeSans 560 90 0 0 wbs_dat_i[15]
+port 614 nsew signal input
+flabel metal2 s 35131 -400 35187 240 0 FreeSans 560 90 0 0 wbs_dat_i[16]
+port 615 nsew signal input
+flabel metal2 s 36904 -400 36960 240 0 FreeSans 560 90 0 0 wbs_dat_i[17]
+port 616 nsew signal input
+flabel metal2 s 38677 -400 38733 240 0 FreeSans 560 90 0 0 wbs_dat_i[18]
+port 617 nsew signal input
+flabel metal2 s 40450 -400 40506 240 0 FreeSans 560 90 0 0 wbs_dat_i[19]
+port 618 nsew signal input
+flabel metal2 s 6763 -400 6819 240 0 FreeSans 560 90 0 0 wbs_dat_i[1]
+port 619 nsew signal input
+flabel metal2 s 42223 -400 42279 240 0 FreeSans 560 90 0 0 wbs_dat_i[20]
+port 620 nsew signal input
+flabel metal2 s 43996 -400 44052 240 0 FreeSans 560 90 0 0 wbs_dat_i[21]
+port 621 nsew signal input
+flabel metal2 s 45769 -400 45825 240 0 FreeSans 560 90 0 0 wbs_dat_i[22]
+port 622 nsew signal input
+flabel metal2 s 47542 -400 47598 240 0 FreeSans 560 90 0 0 wbs_dat_i[23]
+port 623 nsew signal input
+flabel metal2 s 49315 -400 49371 240 0 FreeSans 560 90 0 0 wbs_dat_i[24]
+port 624 nsew signal input
+flabel metal2 s 51088 -400 51144 240 0 FreeSans 560 90 0 0 wbs_dat_i[25]
+port 625 nsew signal input
+flabel metal2 s 52861 -400 52917 240 0 FreeSans 560 90 0 0 wbs_dat_i[26]
+port 626 nsew signal input
+flabel metal2 s 54634 -400 54690 240 0 FreeSans 560 90 0 0 wbs_dat_i[27]
+port 627 nsew signal input
+flabel metal2 s 56407 -400 56463 240 0 FreeSans 560 90 0 0 wbs_dat_i[28]
+port 628 nsew signal input
+flabel metal2 s 58180 -400 58236 240 0 FreeSans 560 90 0 0 wbs_dat_i[29]
+port 629 nsew signal input
+flabel metal2 s 9127 -400 9183 240 0 FreeSans 560 90 0 0 wbs_dat_i[2]
+port 630 nsew signal input
+flabel metal2 s 59953 -400 60009 240 0 FreeSans 560 90 0 0 wbs_dat_i[30]
+port 631 nsew signal input
+flabel metal2 s 61726 -400 61782 240 0 FreeSans 560 90 0 0 wbs_dat_i[31]
+port 632 nsew signal input
+flabel metal2 s 11491 -400 11547 240 0 FreeSans 560 90 0 0 wbs_dat_i[3]
+port 633 nsew signal input
+flabel metal2 s 13855 -400 13911 240 0 FreeSans 560 90 0 0 wbs_dat_i[4]
+port 634 nsew signal input
+flabel metal2 s 15628 -400 15684 240 0 FreeSans 560 90 0 0 wbs_dat_i[5]
+port 635 nsew signal input
+flabel metal2 s 17401 -400 17457 240 0 FreeSans 560 90 0 0 wbs_dat_i[6]
+port 636 nsew signal input
+flabel metal2 s 19174 -400 19230 240 0 FreeSans 560 90 0 0 wbs_dat_i[7]
+port 637 nsew signal input
+flabel metal2 s 20947 -400 21003 240 0 FreeSans 560 90 0 0 wbs_dat_i[8]
+port 638 nsew signal input
+flabel metal2 s 22720 -400 22776 240 0 FreeSans 560 90 0 0 wbs_dat_i[9]
+port 639 nsew signal input
+flabel metal2 s 4990 -400 5046 240 0 FreeSans 560 90 0 0 wbs_dat_o[0]
+port 640 nsew signal tristate
+flabel metal2 s 25084 -400 25140 240 0 FreeSans 560 90 0 0 wbs_dat_o[10]
+port 641 nsew signal tristate
+flabel metal2 s 26857 -400 26913 240 0 FreeSans 560 90 0 0 wbs_dat_o[11]
+port 642 nsew signal tristate
+flabel metal2 s 28630 -400 28686 240 0 FreeSans 560 90 0 0 wbs_dat_o[12]
+port 643 nsew signal tristate
+flabel metal2 s 30403 -400 30459 240 0 FreeSans 560 90 0 0 wbs_dat_o[13]
+port 644 nsew signal tristate
+flabel metal2 s 32176 -400 32232 240 0 FreeSans 560 90 0 0 wbs_dat_o[14]
+port 645 nsew signal tristate
+flabel metal2 s 33949 -400 34005 240 0 FreeSans 560 90 0 0 wbs_dat_o[15]
+port 646 nsew signal tristate
+flabel metal2 s 35722 -400 35778 240 0 FreeSans 560 90 0 0 wbs_dat_o[16]
+port 647 nsew signal tristate
+flabel metal2 s 37495 -400 37551 240 0 FreeSans 560 90 0 0 wbs_dat_o[17]
+port 648 nsew signal tristate
+flabel metal2 s 39268 -400 39324 240 0 FreeSans 560 90 0 0 wbs_dat_o[18]
+port 649 nsew signal tristate
+flabel metal2 s 41041 -400 41097 240 0 FreeSans 560 90 0 0 wbs_dat_o[19]
+port 650 nsew signal tristate
+flabel metal2 s 7354 -400 7410 240 0 FreeSans 560 90 0 0 wbs_dat_o[1]
+port 651 nsew signal tristate
+flabel metal2 s 42814 -400 42870 240 0 FreeSans 560 90 0 0 wbs_dat_o[20]
+port 652 nsew signal tristate
+flabel metal2 s 44587 -400 44643 240 0 FreeSans 560 90 0 0 wbs_dat_o[21]
+port 653 nsew signal tristate
+flabel metal2 s 46360 -400 46416 240 0 FreeSans 560 90 0 0 wbs_dat_o[22]
+port 654 nsew signal tristate
+flabel metal2 s 48133 -400 48189 240 0 FreeSans 560 90 0 0 wbs_dat_o[23]
+port 655 nsew signal tristate
+flabel metal2 s 49906 -400 49962 240 0 FreeSans 560 90 0 0 wbs_dat_o[24]
+port 656 nsew signal tristate
+flabel metal2 s 51679 -400 51735 240 0 FreeSans 560 90 0 0 wbs_dat_o[25]
+port 657 nsew signal tristate
+flabel metal2 s 53452 -400 53508 240 0 FreeSans 560 90 0 0 wbs_dat_o[26]
+port 658 nsew signal tristate
+flabel metal2 s 55225 -400 55281 240 0 FreeSans 560 90 0 0 wbs_dat_o[27]
+port 659 nsew signal tristate
+flabel metal2 s 56998 -400 57054 240 0 FreeSans 560 90 0 0 wbs_dat_o[28]
+port 660 nsew signal tristate
+flabel metal2 s 58771 -400 58827 240 0 FreeSans 560 90 0 0 wbs_dat_o[29]
+port 661 nsew signal tristate
+flabel metal2 s 9718 -400 9774 240 0 FreeSans 560 90 0 0 wbs_dat_o[2]
+port 662 nsew signal tristate
+flabel metal2 s 60544 -400 60600 240 0 FreeSans 560 90 0 0 wbs_dat_o[30]
+port 663 nsew signal tristate
+flabel metal2 s 62317 -400 62373 240 0 FreeSans 560 90 0 0 wbs_dat_o[31]
+port 664 nsew signal tristate
+flabel metal2 s 12082 -400 12138 240 0 FreeSans 560 90 0 0 wbs_dat_o[3]
+port 665 nsew signal tristate
+flabel metal2 s 14446 -400 14502 240 0 FreeSans 560 90 0 0 wbs_dat_o[4]
+port 666 nsew signal tristate
+flabel metal2 s 16219 -400 16275 240 0 FreeSans 560 90 0 0 wbs_dat_o[5]
+port 667 nsew signal tristate
+flabel metal2 s 17992 -400 18048 240 0 FreeSans 560 90 0 0 wbs_dat_o[6]
+port 668 nsew signal tristate
+flabel metal2 s 19765 -400 19821 240 0 FreeSans 560 90 0 0 wbs_dat_o[7]
+port 669 nsew signal tristate
+flabel metal2 s 21538 -400 21594 240 0 FreeSans 560 90 0 0 wbs_dat_o[8]
+port 670 nsew signal tristate
+flabel metal2 s 23311 -400 23367 240 0 FreeSans 560 90 0 0 wbs_dat_o[9]
+port 671 nsew signal tristate
+flabel metal2 s 5581 -400 5637 240 0 FreeSans 560 90 0 0 wbs_sel_i[0]
+port 672 nsew signal input
+flabel metal2 s 7945 -400 8001 240 0 FreeSans 560 90 0 0 wbs_sel_i[1]
+port 673 nsew signal input
+flabel metal2 s 10309 -400 10365 240 0 FreeSans 560 90 0 0 wbs_sel_i[2]
+port 674 nsew signal input
+flabel metal2 s 12673 -400 12729 240 0 FreeSans 560 90 0 0 wbs_sel_i[3]
+port 675 nsew signal input
+flabel metal2 s 2626 -400 2682 240 0 FreeSans 560 90 0 0 wbs_stb_i
+port 676 nsew signal input
+flabel metal2 s 3217 -400 3273 240 0 FreeSans 560 90 0 0 wbs_we_i
+port 677 nsew signal input
+<< properties >>
+string FIXED_BBOX 0 0 292000 352000
+<< end >>
diff --git a/netgen/comp.out b/netgen/comp.out
new file mode 100644
index 0000000..93b0d63
--- /dev/null
+++ b/netgen/comp.out
@@ -0,0 +1,3521 @@
+Flattening unmatched subcell sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__diode_pd2nw_05v5_G4XDRY in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_sc_hd__buf_2 in circuit user_analog_project_wrapper (0)(5 instances)
+Flattening unmatched subcell sky130_fd_sc_hd__buf_16 in circuit user_analog_project_wrapper (0)(5 instances)
+Flattening unmatched subcell comparator_v6 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell latch_3 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_GJYUB2 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell inv_W12 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell nmos_1u#0 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_7RYEVP in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell pmos_2uf2#0 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell preamp_part12 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_G6PLX8 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_RFM3CD#0 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_F5U58G#1 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_RURP52 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_8FHE5N in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell SR_latch in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_F5U58G in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_AC5E9B in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell preamp_part22 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_RFM3CD#0 in circuit user_analog_project_wrapper (0)(6 instances)
+
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[10]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[11]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[12]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[13]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[14]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[15]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[16]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[17]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[1]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[2]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[3]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[4]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[5]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[6]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[7]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[8]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[9]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[10]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[11]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[12]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[13]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[14]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[15]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[16]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[17]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[1]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[2]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[3]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[4]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[5]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[6]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[7]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[8]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[9]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[0]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[100]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[101]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[102]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[103]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[104]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[105]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[106]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[107]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[108]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[109]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[10]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[110]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[111]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[112]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[113]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[114]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[115]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[116]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[117]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[118]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[119]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[11]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[120]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[121]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[122]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[123]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[124]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[125]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[126]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[127]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[12]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[13]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[14]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[15]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[16]
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+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[70]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[71]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[72]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[73]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[74]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[75]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[76]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[77]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[78]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[79]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[7]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[80]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[81]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[82]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[83]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[84]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[85]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[86]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[87]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[88]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[89]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[8]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[90]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[91]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[92]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[93]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[94]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[95]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[96]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[97]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[98]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[99]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[9]
+Cell user_analog_project_wrapper (0) disconnected node: user_clock2
+Cell user_analog_project_wrapper (0) disconnected node: user_irq[0]
+Cell user_analog_project_wrapper (0) disconnected node: user_irq[1]
+Cell user_analog_project_wrapper (0) disconnected node: user_irq[2]
+Cell user_analog_project_wrapper (0) disconnected node: vccd2
+Cell user_analog_project_wrapper (0) disconnected node: vdda1
+Cell user_analog_project_wrapper (0) disconnected node: vdda2
+Cell user_analog_project_wrapper (0) disconnected node: vssa2
+Cell user_analog_project_wrapper (0) disconnected node: vssd1
+Cell user_analog_project_wrapper (0) disconnected node: vssd2
+Cell user_analog_project_wrapper (0) disconnected node: wb_clk_i
+Cell user_analog_project_wrapper (0) disconnected node: wb_rst_i
+Cell user_analog_project_wrapper (0) disconnected node: wbs_ack_o
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[0]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[10]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[11]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[12]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[13]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[14]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[15]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[16]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[17]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[18]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[19]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[1]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[20]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[21]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[22]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[23]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[24]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[25]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[26]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[27]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[28]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[29]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[2]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[30]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[31]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[3]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[4]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[5]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[6]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[7]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[8]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[9]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_cyc_i
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[0]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[10]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[11]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[12]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[13]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[14]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[15]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[16]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[17]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[18]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[19]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[1]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[20]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[21]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[22]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[23]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[24]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[25]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[26]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[27]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[28]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[29]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[2]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[30]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[31]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[3]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[4]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[5]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[6]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[7]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[8]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[9]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[0]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[10]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[11]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[12]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[13]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[14]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[15]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[16]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[17]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[18]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[19]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[1]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[20]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[21]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[22]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[23]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[24]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[25]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[26]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[27]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[28]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[29]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[2]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[30]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[31]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[3]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[4]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[5]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[6]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[7]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[8]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[9]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[0]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[1]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[2]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[3]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_stb_i
+Cell user_analog_project_wrapper (0) disconnected node: wbs_we_i
+Cell user_analog_project_wrapper (1) disconnected node: `MPRJ_IO_PADS-`ANALOG_PADS
+Cell user_analog_project_wrapper (1) disconnected node: :
+Cell user_analog_project_wrapper (1) disconnected node: 0
+Cell user_analog_project_wrapper (1) disconnected node: ]
+Cell user_analog_project_wrapper (1) disconnected node: `MPRJ_IO_PADS-`ANALOG_PADS
+Cell user_analog_project_wrapper (1) disconnected node: :
+Cell user_analog_project_wrapper (1) disconnected node: 0
+Cell user_analog_project_wrapper (1) disconnected node: ]
+Cell user_analog_project_wrapper (1) disconnected node: `MPRJ_IO_PADS-`ANALOG_PADS
+Cell user_analog_project_wrapper (1) disconnected node: :
+Cell user_analog_project_wrapper (1) disconnected node: 0
+Cell user_analog_project_wrapper (1) disconnected node: ]
+Cell user_analog_project_wrapper (1) disconnected node: `MPRJ_IO_PADS-`ANALOG_PADS
+Cell user_analog_project_wrapper (1) disconnected node: :
+Cell user_analog_project_wrapper (1) disconnected node: 0
+Cell user_analog_project_wrapper (1) disconnected node: ]
+Cell user_analog_project_wrapper (1) disconnected node: `MPRJ_IO_PADS-`ANALOG_PADS
+Cell user_analog_project_wrapper (1) disconnected node: :
+Cell user_analog_project_wrapper (1) disconnected node: 0
+Cell user_analog_project_wrapper (1) disconnected node: ]
+Cell user_analog_project_wrapper (1) disconnected node: `MPRJ_IO_PADS-`ANALOG_PADS
+Cell user_analog_project_wrapper (1) disconnected node: :
+Cell user_analog_project_wrapper (1) disconnected node: 0
+Cell user_analog_project_wrapper (1) disconnected node: ]
+Cell user_analog_project_wrapper (1) disconnected node: `ANALOG_PADS
+Cell user_analog_project_wrapper (1) disconnected node: :
+Cell user_analog_project_wrapper (1) disconnected node: 0
+Cell user_analog_project_wrapper (1) disconnected node: ]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_high[2]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_high[1]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_high[0]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_low[2]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_low[1]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_low[0]
+Class user_analog_project_wrapper (0): Merged 227 parallel devices.
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[10]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[11]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[12]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[13]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[14]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[15]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[16]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[17]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[1]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[2]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[3]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[4]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[5]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[6]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[7]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[8]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[9]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[10]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[11]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[12]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[13]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[14]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[15]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[16]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[17]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[1]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[2]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[3]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[4]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[5]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[6]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[7]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[8]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[15]
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+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[20]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[21]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[22]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[23]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[24]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[25]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[26]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[27]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[28]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[29]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[2]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[30]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[31]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[32]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[33]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[34]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[35]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[36]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[37]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[38]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[39]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[3]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[40]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[41]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[42]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[43]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[44]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[45]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[46]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[47]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[48]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[49]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[4]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[50]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[51]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[52]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[53]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[54]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[55]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[56]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[57]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[58]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[59]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[5]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[60]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[61]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[62]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[63]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[64]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[65]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[66]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[67]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[68]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[69]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[6]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[70]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[71]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[72]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[73]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[74]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[75]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[76]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[77]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[78]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[79]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[7]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[80]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[81]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[82]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[83]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[84]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[85]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[86]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[87]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[88]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[89]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[8]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[90]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[91]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[92]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[93]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[94]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[95]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[96]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[97]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[98]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[99]
+Cell user_analog_project_wrapper (0) disconnected node: la_oenb[9]
+Cell user_analog_project_wrapper (0) disconnected node: user_clock2
+Cell user_analog_project_wrapper (0) disconnected node: user_irq[0]
+Cell user_analog_project_wrapper (0) disconnected node: user_irq[1]
+Cell user_analog_project_wrapper (0) disconnected node: user_irq[2]
+Cell user_analog_project_wrapper (0) disconnected node: vccd2
+Cell user_analog_project_wrapper (0) disconnected node: vdda1
+Cell user_analog_project_wrapper (0) disconnected node: vdda2
+Cell user_analog_project_wrapper (0) disconnected node: vssa2
+Cell user_analog_project_wrapper (0) disconnected node: vssd1
+Cell user_analog_project_wrapper (0) disconnected node: vssd2
+Cell user_analog_project_wrapper (0) disconnected node: wb_clk_i
+Cell user_analog_project_wrapper (0) disconnected node: wb_rst_i
+Cell user_analog_project_wrapper (0) disconnected node: wbs_ack_o
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[0]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[10]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[11]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[12]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[13]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[14]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[15]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[16]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[17]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[18]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[19]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[1]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[20]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[21]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[22]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[23]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[24]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[25]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[26]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[27]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[28]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[29]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[2]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[30]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[31]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[3]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[4]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[5]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[6]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[7]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[8]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[9]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_cyc_i
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[0]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[10]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[11]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[12]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[13]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[14]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[15]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[16]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[17]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[18]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[19]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[1]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[20]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[21]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[22]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[23]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[24]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[25]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[26]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[27]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[28]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[29]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[2]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[30]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[31]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[3]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[4]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[5]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[6]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[7]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[8]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[9]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[0]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[10]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[11]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[12]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[13]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[14]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[15]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[16]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[17]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[18]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[19]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[1]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[20]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[21]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[22]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[23]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[24]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[25]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[26]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[27]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[28]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[29]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[2]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[30]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[31]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[3]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[4]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[5]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[6]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[7]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[8]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[9]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[0]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[1]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[2]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[3]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_stb_i
+Cell user_analog_project_wrapper (0) disconnected node: wbs_we_i
+Cell user_analog_project_wrapper (1) disconnected node: `MPRJ_IO_PADS-`ANALOG_PADS
+Cell user_analog_project_wrapper (1) disconnected node: :
+Cell user_analog_project_wrapper (1) disconnected node: 0
+Cell user_analog_project_wrapper (1) disconnected node: ]
+Cell user_analog_project_wrapper (1) disconnected node: `MPRJ_IO_PADS-`ANALOG_PADS
+Cell user_analog_project_wrapper (1) disconnected node: :
+Cell user_analog_project_wrapper (1) disconnected node: 0
+Cell user_analog_project_wrapper (1) disconnected node: ]
+Cell user_analog_project_wrapper (1) disconnected node: `MPRJ_IO_PADS-`ANALOG_PADS
+Cell user_analog_project_wrapper (1) disconnected node: :
+Cell user_analog_project_wrapper (1) disconnected node: 0
+Cell user_analog_project_wrapper (1) disconnected node: ]
+Cell user_analog_project_wrapper (1) disconnected node: `MPRJ_IO_PADS-`ANALOG_PADS
+Cell user_analog_project_wrapper (1) disconnected node: :
+Cell user_analog_project_wrapper (1) disconnected node: 0
+Cell user_analog_project_wrapper (1) disconnected node: ]
+Cell user_analog_project_wrapper (1) disconnected node: `MPRJ_IO_PADS-`ANALOG_PADS
+Cell user_analog_project_wrapper (1) disconnected node: :
+Cell user_analog_project_wrapper (1) disconnected node: 0
+Cell user_analog_project_wrapper (1) disconnected node: ]
+Cell user_analog_project_wrapper (1) disconnected node: `MPRJ_IO_PADS-`ANALOG_PADS
+Cell user_analog_project_wrapper (1) disconnected node: :
+Cell user_analog_project_wrapper (1) disconnected node: 0
+Cell user_analog_project_wrapper (1) disconnected node: ]
+Cell user_analog_project_wrapper (1) disconnected node: `ANALOG_PADS
+Cell user_analog_project_wrapper (1) disconnected node: :
+Cell user_analog_project_wrapper (1) disconnected node: 0
+Cell user_analog_project_wrapper (1) disconnected node: ]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_high[2]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_high[1]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_high[0]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_low[2]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_low[1]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_low[0]
+Subcircuit summary:
+Circuit 1: user_analog_project_wrapper |Circuit 2: user_analog_project_wrapper
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__diode_pw2nd_05v5 (2) |(no matching element)
+sky130_fd_pr__diode_pd2nw_05v5 (2) |(no matching element)
+sky130_fd_pr__pfet_01v8_hvt (125->20) |(no matching element)
+sky130_fd_pr__nfet_01v8 (145->31) |(no matching element)
+sky130_fd_pr__pfet_01v8 (21->13) |(no matching element)
+vsrc (4) |(no matching element)
+(no matching element) |user_analog_proj_example (1)
+Number of devices: 72 **Mismatch** |Number of devices: 1 **Mismatch**
+Number of nets: 43 **Mismatch** |Number of nets: 503 **Mismatch**
+---------------------------------------------------------------------------------------
+NET mismatches: Class fragments follow (with fanout counts):
+Circuit 1: user_analog_project_wrapper |Circuit 2: user_analog_project_wrapper
+
+---------------------------------------------------------------------------------------
+Net: sky130_fd_sc_hd__buf_2_4/X |Net: wb_clk_i
+ sky130_fd_pr__nfet_01v8/2 = 1 | user_analog_proj_example/wb_clk_i = 1
+ sky130_fd_pr__pfet_01v8_hvt/2 = 1 |
+ sky130_fd_pr__pfet_01v8_hvt/(1|3) = 1 |
+ sky130_fd_pr__nfet_01v8/(1|3) = 1 |
+ |
+Net: /sky130_fd_sc_hd__buf_2_4/a_27_47# |Net: wb_rst_i
+ sky130_fd_pr__pfet_01v8_hvt/2 = 1 | user_analog_proj_example/wb_rst_i = 1
+ sky130_fd_pr__pfet_01v8_hvt/(1|3) = 1 |
+ sky130_fd_pr__nfet_01v8/2 = 1 |
+ sky130_fd_pr__nfet_01v8/(1|3) = 1 |
+ |
+Net: /sky130_fd_sc_hd__buf_16_4/a_109_47# |Net: wbs_cyc_i
+ sky130_fd_pr__nfet_01v8/(1|3) = 1 | user_analog_proj_example/wbs_cyc_i = 1
+ sky130_fd_pr__pfet_01v8_hvt/2 = 1 |
+ sky130_fd_pr__nfet_01v8/2 = 1 |
+ sky130_fd_pr__pfet_01v8_hvt/(1|3) = 1 |
+ |
+Net: vssa1 |Net: vssa1
+ sky130_fd_pr__diode_pw2nd_05v5/anode = 2 | user_analog_proj_example/io_clamp_low =
+ sky130_fd_pr__nfet_01v8/(1|3) = 27 |
+ sky130_fd_pr__nfet_01v8/4 = 31 |
+ vsrc/pos = 2 |
+ |
+Net: vccd1 |Net: vccd1
+ sky130_fd_pr__diode_pd2nw_05v5/cathode = | user_analog_proj_example/io_clamp_high =
+ sky130_fd_pr__pfet_01v8_hvt/(1|3) = 20 |
+ sky130_fd_pr__pfet_01v8_hvt/4 = 20 |
+ sky130_fd_pr__pfet_01v8/(1|3) = 9 |
+ sky130_fd_pr__pfet_01v8/4 = 13 |
+ vsrc/pos = 2 |
+ |
+Net: comparator_v6_0/CLKBAR |Net: wbs_sel_i[3]
+ sky130_fd_pr__pfet_01v8_hvt/(1|3) = 1 | user_analog_proj_example/wbs_sel_i[3] =
+ sky130_fd_pr__nfet_01v8/(1|3) = 1 |
+ sky130_fd_pr__pfet_01v8/2 = 3 |
+ |
+Net: io_analog[0] |Net: wbs_sel_i[2]
+ sky130_fd_pr__pfet_01v8_hvt/(1|3) = 1 | user_analog_proj_example/wbs_sel_i[2] =
+ sky130_fd_pr__nfet_01v8/(1|3) = 1 |
+ |
+Net: io_analog[1] |Net: wbs_sel_i[1]
+ sky130_fd_pr__pfet_01v8_hvt/2 = 1 | user_analog_proj_example/wbs_sel_i[1] =
+ sky130_fd_pr__nfet_01v8/2 = 1 |
+ |
+Net: comparator_v6_0/CLK |Net: wbs_sel_i[0]
+ sky130_fd_pr__pfet_01v8_hvt/(1|3) = 1 | user_analog_proj_example/wbs_sel_i[0] =
+ sky130_fd_pr__nfet_01v8/(1|3) = 1 |
+ sky130_fd_pr__pfet_01v8/2 = 4 |
+ sky130_fd_pr__nfet_01v8/2 = 1 |
+ |
+Net: io_clamp_high[1] |Net: wbs_adr_i[31]
+ vsrc/neg = 1 | user_analog_proj_example/wbs_adr_i[31] =
+ |
+Net: io_clamp_high[2] |Net: wbs_adr_i[30]
+ vsrc/neg = 1 | user_analog_proj_example/wbs_adr_i[30] =
+ |
+Net: io_clamp_low[2] |Net: wbs_adr_i[29]
+ vsrc/neg = 1 | user_analog_proj_example/wbs_adr_i[29] =
+ |
+Net: io_clamp_low[1] |Net: wbs_adr_i[28]
+ vsrc/neg = 1 | user_analog_proj_example/wbs_adr_i[28] =
+ |
+Net: /comparator_v6_0//latch_3_0/inv_W12_1 |Net: wbs_adr_i[27]
+ sky130_fd_pr__pfet_01v8/(1|3) = 3 | user_analog_proj_example/wbs_adr_i[27] =
+ |
+Net: /comparator_v6_0//preamp_part12_0/li_ |Net: wbs_adr_i[26]
+ sky130_fd_pr__nfet_01v8/(1|3) = 3 | user_analog_proj_example/wbs_adr_i[26] =
+ |
+(no matching net) |Net: wbs_adr_i[25]
+ | user_analog_proj_example/wbs_adr_i[25] =
+ |
+(no matching net) |Net: wbs_adr_i[24]
+ | user_analog_proj_example/wbs_adr_i[24] =
+ |
+(no matching net) |Net: wbs_adr_i[23]
+ | user_analog_proj_example/wbs_adr_i[23] =
+ |
+(no matching net) |Net: wbs_adr_i[22]
+ | user_analog_proj_example/wbs_adr_i[22] =
+ |
+(no matching net) |Net: wbs_adr_i[21]
+ | user_analog_proj_example/wbs_adr_i[21] =
+ |
+(no matching net) |Net: wbs_adr_i[20]
+ | user_analog_proj_example/wbs_adr_i[20] =
+ |
+(no matching net) |Net: wbs_adr_i[19]
+ | user_analog_proj_example/wbs_adr_i[19] =
+ |
+(no matching net) |Net: wbs_adr_i[18]
+ | user_analog_proj_example/wbs_adr_i[18] =
+ |
+(no matching net) |Net: wbs_adr_i[17]
+ | user_analog_proj_example/wbs_adr_i[17] =
+ |
+(no matching net) |Net: wbs_adr_i[16]
+ | user_analog_proj_example/wbs_adr_i[16] =
+ |
+(no matching net) |Net: wbs_adr_i[15]
+ | user_analog_proj_example/wbs_adr_i[15] =
+ |
+(no matching net) |Net: wbs_adr_i[14]
+ | user_analog_proj_example/wbs_adr_i[14] =
+ |
+(no matching net) |Net: wbs_adr_i[13]
+ | user_analog_proj_example/wbs_adr_i[13] =
+ |
+(no matching net) |Net: wbs_adr_i[12]
+ | user_analog_proj_example/wbs_adr_i[12] =
+ |
+(no matching net) |Net: wbs_adr_i[11]
+ | user_analog_proj_example/wbs_adr_i[11] =
+ |
+(no matching net) |Net: wbs_adr_i[10]
+ | user_analog_proj_example/wbs_adr_i[10] =
+ |
+(no matching net) |Net: wbs_adr_i[9]
+ | user_analog_proj_example/wbs_adr_i[9] =
+ |
+(no matching net) |Net: wbs_adr_i[8]
+ | user_analog_proj_example/wbs_adr_i[8] =
+ |
+(no matching net) |Net: wbs_adr_i[7]
+ | user_analog_proj_example/wbs_adr_i[7] =
+ |
+(no matching net) |Net: wbs_adr_i[6]
+ | user_analog_proj_example/wbs_adr_i[6] =
+ |
+(no matching net) |Net: wbs_adr_i[5]
+ | user_analog_proj_example/wbs_adr_i[5] =
+ |
+(no matching net) |Net: wbs_adr_i[4]
+ | user_analog_proj_example/wbs_adr_i[4] =
+ |
+(no matching net) |Net: wbs_adr_i[3]
+ | user_analog_proj_example/wbs_adr_i[3] =
+ |
+(no matching net) |Net: wbs_adr_i[2]
+ | user_analog_proj_example/wbs_adr_i[2] =
+ |
+(no matching net) |Net: wbs_adr_i[1]
+ | user_analog_proj_example/wbs_adr_i[1] =
+ |
+(no matching net) |Net: wbs_adr_i[0]
+ | user_analog_proj_example/wbs_adr_i[0] =
+ |
+(no matching net) |Net: wbs_dat_i[31]
+ | user_analog_proj_example/wbs_dat_i[31] =
+ |
+(no matching net) |Net: wbs_dat_i[30]
+ | user_analog_proj_example/wbs_dat_i[30] =
+ |
+(no matching net) |Net: wbs_dat_i[29]
+ | user_analog_proj_example/wbs_dat_i[29] =
+ |
+(no matching net) |Net: wbs_dat_i[28]
+ | user_analog_proj_example/wbs_dat_i[28] =
+ |
+(no matching net) |Net: wbs_dat_i[27]
+ | user_analog_proj_example/wbs_dat_i[27] =
+ |
+(no matching net) |Net: wbs_dat_i[26]
+ | user_analog_proj_example/wbs_dat_i[26] =
+ |
+(no matching net) |Net: wbs_dat_i[25]
+ | user_analog_proj_example/wbs_dat_i[25] =
+ |
+(no matching net) |Net: wbs_dat_i[24]
+ | user_analog_proj_example/wbs_dat_i[24] =
+ |
+(no matching net) |Net: wbs_dat_i[23]
+ | user_analog_proj_example/wbs_dat_i[23] =
+ |
+(no matching net) |Net: wbs_dat_i[22]
+ | user_analog_proj_example/wbs_dat_i[22] =
+ |
+(no matching net) |Net: wbs_dat_i[21]
+ | user_analog_proj_example/wbs_dat_i[21] =
+ |
+(no matching net) |Net: wbs_dat_i[20]
+ | user_analog_proj_example/wbs_dat_i[20] =
+ |
+(no matching net) |Net: wbs_dat_i[19]
+ | user_analog_proj_example/wbs_dat_i[19] =
+ |
+(no matching net) |Net: wbs_dat_i[18]
+ | user_analog_proj_example/wbs_dat_i[18] =
+ |
+(no matching net) |Net: wbs_dat_i[17]
+ | user_analog_proj_example/wbs_dat_i[17] =
+ |
+(no matching net) |Net: wbs_dat_i[16]
+ | user_analog_proj_example/wbs_dat_i[16] =
+ |
+(no matching net) |Net: wbs_dat_i[15]
+ | user_analog_proj_example/wbs_dat_i[15] =
+ |
+(no matching net) |Net: wbs_dat_i[14]
+ | user_analog_proj_example/wbs_dat_i[14] =
+ |
+(no matching net) |Net: wbs_dat_i[13]
+ | user_analog_proj_example/wbs_dat_i[13] =
+ |
+(no matching net) |Net: wbs_dat_i[12]
+ | user_analog_proj_example/wbs_dat_i[12] =
+ |
+(no matching net) |Net: wbs_dat_i[11]
+ | user_analog_proj_example/wbs_dat_i[11] =
+ |
+(no matching net) |Net: wbs_dat_i[10]
+ | user_analog_proj_example/wbs_dat_i[10] =
+ |
+(no matching net) |Net: wbs_dat_i[9]
+ | user_analog_proj_example/wbs_dat_i[9] =
+ |
+(no matching net) |Net: wbs_dat_i[8]
+ | user_analog_proj_example/wbs_dat_i[8] =
+ |
+(no matching net) |Net: wbs_dat_i[7]
+ | user_analog_proj_example/wbs_dat_i[7] =
+ |
+(no matching net) |Net: wbs_dat_i[6]
+ | user_analog_proj_example/wbs_dat_i[6] =
+ |
+(no matching net) |Net: wbs_dat_i[5]
+ | user_analog_proj_example/wbs_dat_i[5] =
+ |
+(no matching net) |Net: wbs_dat_i[4]
+ | user_analog_proj_example/wbs_dat_i[4] =
+ |
+(no matching net) |Net: wbs_dat_i[3]
+ | user_analog_proj_example/wbs_dat_i[3] =
+ |
+(no matching net) |Net: wbs_dat_i[2]
+ | user_analog_proj_example/wbs_dat_i[2] =
+ |
+(no matching net) |Net: wbs_dat_i[1]
+ | user_analog_proj_example/wbs_dat_i[1] =
+ |
+(no matching net) |Net: wbs_dat_i[0]
+ | user_analog_proj_example/wbs_dat_i[0] =
+ |
+(no matching net) |Net: wbs_ack_o
+ | user_analog_proj_example/wbs_ack_o = 1
+ |
+(no matching net) |Net: wbs_dat_o[31]
+ | user_analog_proj_example/wbs_dat_o[31] =
+ |
+(no matching net) |Net: wbs_dat_o[30]
+ | user_analog_proj_example/wbs_dat_o[30] =
+ |
+(no matching net) |Net: wbs_dat_o[29]
+ | user_analog_proj_example/wbs_dat_o[29] =
+ |
+(no matching net) |Net: wbs_dat_o[28]
+ | user_analog_proj_example/wbs_dat_o[28] =
+ |
+(no matching net) |Net: wbs_dat_o[27]
+ | user_analog_proj_example/wbs_dat_o[27] =
+ |
+(no matching net) |Net: wbs_dat_o[26]
+ | user_analog_proj_example/wbs_dat_o[26] =
+ |
+(no matching net) |Net: wbs_dat_o[25]
+ | user_analog_proj_example/wbs_dat_o[25] =
+ |
+(no matching net) |Net: wbs_dat_o[24]
+ | user_analog_proj_example/wbs_dat_o[24] =
+ |
+(no matching net) |Net: wbs_dat_o[23]
+ | user_analog_proj_example/wbs_dat_o[23] =
+ |
+(no matching net) |Net: wbs_dat_o[22]
+ | user_analog_proj_example/wbs_dat_o[22] =
+ |
+(no matching net) |Net: wbs_dat_o[21]
+ | user_analog_proj_example/wbs_dat_o[21] =
+ |
+(no matching net) |Net: wbs_dat_o[20]
+ | user_analog_proj_example/wbs_dat_o[20] =
+ |
+(no matching net) |Net: wbs_dat_o[19]
+ | user_analog_proj_example/wbs_dat_o[19] =
+ |
+(no matching net) |Net: wbs_dat_o[18]
+ | user_analog_proj_example/wbs_dat_o[18] =
+ |
+(no matching net) |Net: wbs_dat_o[17]
+ | user_analog_proj_example/wbs_dat_o[17] =
+ |
+(no matching net) |Net: wbs_dat_o[16]
+ | user_analog_proj_example/wbs_dat_o[16] =
+ |
+(no matching net) |Net: wbs_dat_o[15]
+ | user_analog_proj_example/wbs_dat_o[15] =
+ |
+(no matching net) |Net: wbs_dat_o[14]
+ | user_analog_proj_example/wbs_dat_o[14] =
+ |
+(no matching net) |Net: wbs_dat_o[13]
+ | user_analog_proj_example/wbs_dat_o[13] =
+ |
+(no matching net) |Net: wbs_dat_o[12]
+ | user_analog_proj_example/wbs_dat_o[12] =
+ |
+(no matching net) |Net: wbs_dat_o[11]
+ | user_analog_proj_example/wbs_dat_o[11] =
+ |
+(no matching net) |Net: wbs_dat_o[10]
+ | user_analog_proj_example/wbs_dat_o[10] =
+ |
+(no matching net) |Net: wbs_dat_o[9]
+ | user_analog_proj_example/wbs_dat_o[9] =
+ |
+(no matching net) |Net: wbs_dat_o[8]
+ | user_analog_proj_example/wbs_dat_o[8] =
+ |
+(no matching net) |Net: wbs_dat_o[7]
+ | user_analog_proj_example/wbs_dat_o[7] =
+ |
+(no matching net) |Net: wbs_dat_o[6]
+ | user_analog_proj_example/wbs_dat_o[6] =
+ |
+(no matching net) |Net: wbs_dat_o[5]
+ | user_analog_proj_example/wbs_dat_o[5] =
+ |
+(no matching net) |Net: wbs_dat_o[4]
+ | user_analog_proj_example/wbs_dat_o[4] =
+ |
+(no matching net) |Net: wbs_dat_o[3]
+ | user_analog_proj_example/wbs_dat_o[3] =
+ |
+(no matching net) |Net: wbs_dat_o[2]
+ | user_analog_proj_example/wbs_dat_o[2] =
+ |
+(no matching net) |Net: wbs_dat_o[1]
+ | user_analog_proj_example/wbs_dat_o[1] =
+ |
+(no matching net) |Net: wbs_dat_o[0]
+ | user_analog_proj_example/wbs_dat_o[0] =
+ |
+(no matching net) |Net: la_data_in[127]
+ | user_analog_proj_example/la_data_in[127]
+ |
+(no matching net) |Net: la_data_in[126]
+ | user_analog_proj_example/la_data_in[126]
+ |
+(no matching net) |Net: la_data_in[125]
+ | user_analog_proj_example/la_data_in[125]
+ |
+(no matching net) |Net: la_data_in[124]
+ | user_analog_proj_example/la_data_in[124]
+ |
+(no matching net) |Net: la_data_in[123]
+ | user_analog_proj_example/la_data_in[123]
+ |
+(no matching net) |Net: la_data_in[122]
+ | user_analog_proj_example/la_data_in[122]
+ |
+(no matching net) |Net: la_data_in[121]
+ | user_analog_proj_example/la_data_in[121]
+ |
+(no matching net) |Net: la_data_in[120]
+ | user_analog_proj_example/la_data_in[120]
+ |
+(no matching net) |Net: la_data_in[119]
+ | user_analog_proj_example/la_data_in[119]
+ |
+(no matching net) |Net: la_data_in[118]
+ | user_analog_proj_example/la_data_in[118]
+ |
+(no matching net) |Net: la_data_in[117]
+ | user_analog_proj_example/la_data_in[117]
+ |
+(no matching net) |Net: la_data_in[116]
+ | user_analog_proj_example/la_data_in[116]
+ |
+(no matching net) |Net: la_data_in[115]
+ | user_analog_proj_example/la_data_in[115]
+ |
+(no matching net) |Net: la_data_in[114]
+ | user_analog_proj_example/la_data_in[114]
+ |
+(no matching net) |Net: la_data_in[113]
+ | user_analog_proj_example/la_data_in[113]
+ |
+(no matching net) |Net: la_data_in[112]
+ | user_analog_proj_example/la_data_in[112]
+ |
+(no matching net) |Net: la_data_in[111]
+ | user_analog_proj_example/la_data_in[111]
+ |
+(no matching net) |Net: la_data_in[110]
+ | user_analog_proj_example/la_data_in[110]
+ |
+(no matching net) |Net: la_data_in[109]
+ | user_analog_proj_example/la_data_in[109]
+ |
+(no matching net) |Net: la_data_in[108]
+ | user_analog_proj_example/la_data_in[108]
+ |
+(no matching net) |Net: la_data_in[107]
+ | user_analog_proj_example/la_data_in[107]
+ |
+(no matching net) |Net: la_data_in[106]
+ | user_analog_proj_example/la_data_in[106]
+ |
+(no matching net) |Net: la_data_in[105]
+ | user_analog_proj_example/la_data_in[105]
+ |
+(no matching net) |Net: la_data_in[104]
+ | user_analog_proj_example/la_data_in[104]
+ |
+(no matching net) |Net: la_data_in[103]
+ | user_analog_proj_example/la_data_in[103]
+ |
+(no matching net) |Net: la_data_in[102]
+ | user_analog_proj_example/la_data_in[102]
+ |
+(no matching net) |Net: la_data_in[101]
+ | user_analog_proj_example/la_data_in[101]
+ |
+(no matching net) |Net: la_data_in[100]
+ | user_analog_proj_example/la_data_in[100]
+ |
+(no matching net) |Net: la_data_in[99]
+ | user_analog_proj_example/la_data_in[99]
+ |
+(no matching net) |Net: la_data_in[98]
+ | user_analog_proj_example/la_data_in[98]
+ |
+(no matching net) |Net: la_data_in[97]
+ | user_analog_proj_example/la_data_in[97]
+ |
+(no matching net) |Net: la_data_in[96]
+ | user_analog_proj_example/la_data_in[96]
+ |
+(no matching net) |Net: la_data_in[95]
+ | user_analog_proj_example/la_data_in[95]
+ |
+(no matching net) |Net: la_data_in[94]
+ | user_analog_proj_example/la_data_in[94]
+ |
+(no matching net) |Net: la_data_in[93]
+ | user_analog_proj_example/la_data_in[93]
+ |
+(no matching net) |Net: la_data_in[92]
+ | user_analog_proj_example/la_data_in[92]
+ |
+(no matching net) |Net: la_data_in[91]
+ | user_analog_proj_example/la_data_in[91]
+ |
+(no matching net) |Net: la_data_in[90]
+ | user_analog_proj_example/la_data_in[90]
+ |
+(no matching net) |Net: la_data_in[89]
+ | user_analog_proj_example/la_data_in[89]
+ |
+(no matching net) |Net: la_data_in[88]
+ | user_analog_proj_example/la_data_in[88]
+ |
+(no matching net) |Net: la_data_in[87]
+ | user_analog_proj_example/la_data_in[87]
+ |
+(no matching net) |Net: la_data_in[86]
+ | user_analog_proj_example/la_data_in[86]
+ |
+(no matching net) |Net: la_data_in[85]
+ | user_analog_proj_example/la_data_in[85]
+ |
+(no matching net) |Net: la_data_in[84]
+ | user_analog_proj_example/la_data_in[84]
+ |
+(no matching net) |Net: la_data_in[83]
+ | user_analog_proj_example/la_data_in[83]
+ |
+(no matching net) |Net: la_data_in[82]
+ | user_analog_proj_example/la_data_in[82]
+ |
+(no matching net) |Net: la_data_in[81]
+ | user_analog_proj_example/la_data_in[81]
+ |
+(no matching net) |Net: la_data_in[80]
+ | user_analog_proj_example/la_data_in[80]
+ |
+(no matching net) |Net: la_data_in[79]
+ | user_analog_proj_example/la_data_in[79]
+ |
+(no matching net) |Net: la_data_in[78]
+ | user_analog_proj_example/la_data_in[78]
+ |
+(no matching net) |Net: la_data_in[77]
+ | user_analog_proj_example/la_data_in[77]
+ |
+(no matching net) |Net: la_data_in[76]
+ | user_analog_proj_example/la_data_in[76]
+ |
+(no matching net) |Net: la_data_in[75]
+ | user_analog_proj_example/la_data_in[75]
+ |
+(no matching net) |Net: la_data_in[74]
+ | user_analog_proj_example/la_data_in[74]
+ |
+(no matching net) |Net: la_data_in[73]
+ | user_analog_proj_example/la_data_in[73]
+ |
+(no matching net) |Net: la_data_in[72]
+ | user_analog_proj_example/la_data_in[72]
+ |
+(no matching net) |Net: la_data_in[71]
+ | user_analog_proj_example/la_data_in[71]
+ |
+(no matching net) |Net: la_data_in[70]
+ | user_analog_proj_example/la_data_in[70]
+ |
+(no matching net) |Net: la_data_in[69]
+ | user_analog_proj_example/la_data_in[69]
+ |
+(no matching net) |Net: la_data_in[68]
+ | user_analog_proj_example/la_data_in[68]
+ |
+(no matching net) |Net: la_data_in[67]
+ | user_analog_proj_example/la_data_in[67]
+ |
+(no matching net) |Net: la_data_in[66]
+ | user_analog_proj_example/la_data_in[66]
+ |
+(no matching net) |Net: la_data_in[65]
+ | user_analog_proj_example/la_data_in[65]
+ |
+(no matching net) |Net: la_data_in[64]
+ | user_analog_proj_example/la_data_in[64]
+ |
+(no matching net) |Net: la_data_in[63]
+ | user_analog_proj_example/la_data_in[63]
+ |
+(no matching net) |Net: la_data_in[62]
+ | user_analog_proj_example/la_data_in[62]
+ |
+(no matching net) |Net: la_data_in[61]
+ | user_analog_proj_example/la_data_in[61]
+ |
+(no matching net) |Net: la_data_in[60]
+ | user_analog_proj_example/la_data_in[60]
+ |
+(no matching net) |Net: la_data_in[59]
+ | user_analog_proj_example/la_data_in[59]
+ |
+(no matching net) |Net: la_data_in[58]
+ | user_analog_proj_example/la_data_in[58]
+ |
+(no matching net) |Net: la_data_in[57]
+ | user_analog_proj_example/la_data_in[57]
+ |
+(no matching net) |Net: la_data_in[56]
+ | user_analog_proj_example/la_data_in[56]
+ |
+(no matching net) |Net: la_data_in[55]
+ | user_analog_proj_example/la_data_in[55]
+ |
+(no matching net) |Net: la_data_in[54]
+ | user_analog_proj_example/la_data_in[54]
+ |
+(no matching net) |Net: la_data_in[53]
+ | user_analog_proj_example/la_data_in[53]
+ |
+(no matching net) |Net: la_data_in[52]
+ | user_analog_proj_example/la_data_in[52]
+ |
+(no matching net) |Net: la_data_in[51]
+ | user_analog_proj_example/la_data_in[51]
+ |
+(no matching net) |Net: la_data_in[50]
+ | user_analog_proj_example/la_data_in[50]
+ |
+(no matching net) |Net: la_data_in[49]
+ | user_analog_proj_example/la_data_in[49]
+ |
+(no matching net) |Net: la_data_in[48]
+ | user_analog_proj_example/la_data_in[48]
+ |
+(no matching net) |Net: la_data_in[47]
+ | user_analog_proj_example/la_data_in[47]
+ |
+(no matching net) |Net: la_data_in[46]
+ | user_analog_proj_example/la_data_in[46]
+ |
+(no matching net) |Net: la_data_in[45]
+ | user_analog_proj_example/la_data_in[45]
+ |
+(no matching net) |Net: la_data_in[44]
+ | user_analog_proj_example/la_data_in[44]
+ |
+(no matching net) |Net: la_data_in[43]
+ | user_analog_proj_example/la_data_in[43]
+ |
+(no matching net) |Net: la_data_in[42]
+ | user_analog_proj_example/la_data_in[42]
+ |
+(no matching net) |Net: la_data_in[41]
+ | user_analog_proj_example/la_data_in[41]
+ |
+(no matching net) |Net: la_data_in[40]
+ | user_analog_proj_example/la_data_in[40]
+ |
+(no matching net) |Net: la_data_in[39]
+ | user_analog_proj_example/la_data_in[39]
+ |
+(no matching net) |Net: la_data_in[38]
+ | user_analog_proj_example/la_data_in[38]
+ |
+(no matching net) |Net: la_data_in[37]
+ | user_analog_proj_example/la_data_in[37]
+ |
+(no matching net) |Net: la_data_in[36]
+ | user_analog_proj_example/la_data_in[36]
+ |
+(no matching net) |Net: la_data_in[35]
+ | user_analog_proj_example/la_data_in[35]
+ |
+(no matching net) |Net: la_data_in[34]
+ | user_analog_proj_example/la_data_in[34]
+ |
+(no matching net) |Net: la_data_in[33]
+ | user_analog_proj_example/la_data_in[33]
+ |
+(no matching net) |Net: la_data_in[32]
+ | user_analog_proj_example/la_data_in[32]
+ |
+(no matching net) |Net: la_data_in[31]
+ | user_analog_proj_example/la_data_in[31]
+ |
+(no matching net) |Net: la_data_in[30]
+ | user_analog_proj_example/la_data_in[30]
+ |
+(no matching net) |Net: la_data_in[29]
+ | user_analog_proj_example/la_data_in[29]
+ |
+(no matching net) |Net: la_data_in[28]
+ | user_analog_proj_example/la_data_in[28]
+ |
+(no matching net) |Net: la_data_in[27]
+ | user_analog_proj_example/la_data_in[27]
+ |
+(no matching net) |Net: la_data_in[26]
+ | user_analog_proj_example/la_data_in[26]
+ |
+(no matching net) |Net: la_data_in[25]
+ | user_analog_proj_example/la_data_in[25]
+ |
+(no matching net) |Net: la_data_in[24]
+ | user_analog_proj_example/la_data_in[24]
+ |
+(no matching net) |Net: la_data_in[23]
+ | user_analog_proj_example/la_data_in[23]
+ |
+(no matching net) |Net: la_data_in[22]
+ | user_analog_proj_example/la_data_in[22]
+ |
+(no matching net) |Net: la_data_in[21]
+ | user_analog_proj_example/la_data_in[21]
+ |
+(no matching net) |Net: la_data_in[20]
+ | user_analog_proj_example/la_data_in[20]
+ |
+(no matching net) |Net: la_data_in[19]
+ | user_analog_proj_example/la_data_in[19]
+ |
+(no matching net) |Net: la_data_in[18]
+ | user_analog_proj_example/la_data_in[18]
+ |
+(no matching net) |Net: la_data_in[17]
+ | user_analog_proj_example/la_data_in[17]
+ |
+(no matching net) |Net: la_data_in[16]
+ | user_analog_proj_example/la_data_in[16]
+ |
+(no matching net) |Net: la_data_in[15]
+ | user_analog_proj_example/la_data_in[15]
+ |
+(no matching net) |Net: la_data_in[14]
+ | user_analog_proj_example/la_data_in[14]
+ |
+(no matching net) |Net: la_data_in[13]
+ | user_analog_proj_example/la_data_in[13]
+ |
+(no matching net) |Net: la_data_in[12]
+ | user_analog_proj_example/la_data_in[12]
+ |
+(no matching net) |Net: la_data_in[11]
+ | user_analog_proj_example/la_data_in[11]
+ |
+(no matching net) |Net: la_data_in[10]
+ | user_analog_proj_example/la_data_in[10]
+ |
+(no matching net) |Net: la_data_in[9]
+ | user_analog_proj_example/la_data_in[9] =
+ |
+(no matching net) |Net: la_data_in[8]
+ | user_analog_proj_example/la_data_in[8] =
+ |
+(no matching net) |Net: la_data_in[7]
+ | user_analog_proj_example/la_data_in[7] =
+ |
+(no matching net) |Net: la_data_in[6]
+ | user_analog_proj_example/la_data_in[6] =
+ |
+(no matching net) |Net: la_data_in[5]
+ | user_analog_proj_example/la_data_in[5] =
+ |
+(no matching net) |Net: la_data_in[4]
+ | user_analog_proj_example/la_data_in[4] =
+ |
+(no matching net) |Net: la_data_in[3]
+ | user_analog_proj_example/la_data_in[3] =
+ |
+(no matching net) |Net: la_data_in[2]
+ | user_analog_proj_example/la_data_in[2] =
+ |
+(no matching net) |Net: la_data_in[1]
+ | user_analog_proj_example/la_data_in[1] =
+ |
+(no matching net) |Net: la_data_in[0]
+ | user_analog_proj_example/la_data_in[0] =
+ |
+(no matching net) |Net: la_data_out[127]
+ | user_analog_proj_example/la_data_out[127
+ |
+(no matching net) |Net: la_data_out[126]
+ | user_analog_proj_example/la_data_out[126
+ |
+(no matching net) |Net: la_data_out[125]
+ | user_analog_proj_example/la_data_out[125
+ |
+(no matching net) |Net: la_data_out[124]
+ | user_analog_proj_example/la_data_out[124
+ |
+(no matching net) |Net: la_data_out[123]
+ | user_analog_proj_example/la_data_out[123
+ |
+(no matching net) |Net: la_data_out[122]
+ | user_analog_proj_example/la_data_out[122
+ |
+(no matching net) |Net: la_data_out[121]
+ | user_analog_proj_example/la_data_out[121
+ |
+(no matching net) |Net: la_data_out[120]
+ | user_analog_proj_example/la_data_out[120
+ |
+(no matching net) |Net: la_data_out[119]
+ | user_analog_proj_example/la_data_out[119
+ |
+(no matching net) |Net: la_data_out[118]
+ | user_analog_proj_example/la_data_out[118
+ |
+(no matching net) |Net: la_data_out[117]
+ | user_analog_proj_example/la_data_out[117
+ |
+(no matching net) |Net: la_data_out[116]
+ | user_analog_proj_example/la_data_out[116
+ |
+(no matching net) |Net: la_data_out[115]
+ | user_analog_proj_example/la_data_out[115
+ |
+(no matching net) |Net: la_data_out[114]
+ | user_analog_proj_example/la_data_out[114
+ |
+(no matching net) |Net: la_data_out[113]
+ | user_analog_proj_example/la_data_out[113
+ |
+(no matching net) |Net: la_data_out[112]
+ | user_analog_proj_example/la_data_out[112
+ |
+(no matching net) |Net: la_data_out[111]
+ | user_analog_proj_example/la_data_out[111
+ |
+(no matching net) |Net: la_data_out[110]
+ | user_analog_proj_example/la_data_out[110
+ |
+(no matching net) |Net: la_data_out[109]
+ | user_analog_proj_example/la_data_out[109
+ |
+(no matching net) |Net: la_data_out[108]
+ | user_analog_proj_example/la_data_out[108
+ |
+(no matching net) |Net: la_data_out[107]
+ | user_analog_proj_example/la_data_out[107
+ |
+(no matching net) |Net: la_data_out[106]
+ | user_analog_proj_example/la_data_out[106
+ |
+(no matching net) |Net: la_data_out[105]
+ | user_analog_proj_example/la_data_out[105
+ |
+(no matching net) |Net: la_data_out[104]
+ | user_analog_proj_example/la_data_out[104
+ |
+(no matching net) |Net: la_data_out[103]
+ | user_analog_proj_example/la_data_out[103
+ |
+(no matching net) |Net: la_data_out[102]
+ | user_analog_proj_example/la_data_out[102
+ |
+(no matching net) |Net: la_data_out[101]
+ | user_analog_proj_example/la_data_out[101
+ |
+(no matching net) |Net: la_data_out[100]
+ | user_analog_proj_example/la_data_out[100
+ |
+(no matching net) |Net: la_data_out[99]
+ | user_analog_proj_example/la_data_out[99]
+ |
+(no matching net) |Net: la_data_out[98]
+ | user_analog_proj_example/la_data_out[98]
+ |
+(no matching net) |Net: la_data_out[97]
+ | user_analog_proj_example/la_data_out[97]
+ |
+(no matching net) |Net: la_data_out[96]
+ | user_analog_proj_example/la_data_out[96]
+ |
+(no matching net) |Net: la_data_out[95]
+ | user_analog_proj_example/la_data_out[95]
+ |
+(no matching net) |Net: la_data_out[94]
+ | user_analog_proj_example/la_data_out[94]
+ |
+(no matching net) |Net: la_data_out[93]
+ | user_analog_proj_example/la_data_out[93]
+ |
+(no matching net) |Net: la_data_out[92]
+ | user_analog_proj_example/la_data_out[92]
+ |
+(no matching net) |Net: la_data_out[91]
+ | user_analog_proj_example/la_data_out[91]
+ |
+(no matching net) |Net: la_data_out[90]
+ | user_analog_proj_example/la_data_out[90]
+ |
+(no matching net) |Net: la_data_out[89]
+ | user_analog_proj_example/la_data_out[89]
+ |
+(no matching net) |Net: la_data_out[88]
+ | user_analog_proj_example/la_data_out[88]
+ |
+(no matching net) |Net: la_data_out[87]
+ | user_analog_proj_example/la_data_out[87]
+ |
+(no matching net) |Net: la_data_out[86]
+ | user_analog_proj_example/la_data_out[86]
+ |
+(no matching net) |Net: la_data_out[85]
+ | user_analog_proj_example/la_data_out[85]
+ |
+(no matching net) |Net: la_data_out[84]
+ | user_analog_proj_example/la_data_out[84]
+ |
+(no matching net) |Net: la_data_out[83]
+ | user_analog_proj_example/la_data_out[83]
+ |
+(no matching net) |Net: la_data_out[82]
+ | user_analog_proj_example/la_data_out[82]
+ |
+(no matching net) |Net: la_data_out[81]
+ | user_analog_proj_example/la_data_out[81]
+ |
+(no matching net) |Net: la_data_out[80]
+ | user_analog_proj_example/la_data_out[80]
+ |
+(no matching net) |Net: la_data_out[79]
+ | user_analog_proj_example/la_data_out[79]
+ |
+(no matching net) |Net: la_data_out[78]
+ | user_analog_proj_example/la_data_out[78]
+ |
+(no matching net) |Net: la_data_out[77]
+ | user_analog_proj_example/la_data_out[77]
+ |
+(no matching net) |Net: la_data_out[76]
+ | user_analog_proj_example/la_data_out[76]
+ |
+(no matching net) |Net: la_data_out[75]
+ | user_analog_proj_example/la_data_out[75]
+ |
+(no matching net) |Net: la_data_out[74]
+ | user_analog_proj_example/la_data_out[74]
+ |
+(no matching net) |Net: la_data_out[73]
+ | user_analog_proj_example/la_data_out[73]
+ |
+(no matching net) |Net: la_data_out[72]
+ | user_analog_proj_example/la_data_out[72]
+ |
+(no matching net) |Net: la_data_out[71]
+ | user_analog_proj_example/la_data_out[71]
+ |
+(no matching net) |Net: la_data_out[70]
+ | user_analog_proj_example/la_data_out[70]
+ |
+(no matching net) |Net: la_data_out[69]
+ | user_analog_proj_example/la_data_out[69]
+ |
+(no matching net) |Net: la_data_out[68]
+ | user_analog_proj_example/la_data_out[68]
+ |
+(no matching net) |Net: la_data_out[67]
+ | user_analog_proj_example/la_data_out[67]
+ |
+(no matching net) |Net: la_data_out[66]
+ | user_analog_proj_example/la_data_out[66]
+ |
+(no matching net) |Net: la_data_out[65]
+ | user_analog_proj_example/la_data_out[65]
+ |
+(no matching net) |Net: la_data_out[64]
+ | user_analog_proj_example/la_data_out[64]
+ |
+(no matching net) |Net: la_data_out[63]
+ | user_analog_proj_example/la_data_out[63]
+ |
+(no matching net) |Net: la_data_out[62]
+ | user_analog_proj_example/la_data_out[62]
+ |
+(no matching net) |Net: la_data_out[61]
+ | user_analog_proj_example/la_data_out[61]
+ |
+(no matching net) |Net: la_data_out[60]
+ | user_analog_proj_example/la_data_out[60]
+ |
+(no matching net) |Net: la_data_out[59]
+ | user_analog_proj_example/la_data_out[59]
+ |
+(no matching net) |Net: la_data_out[58]
+ | user_analog_proj_example/la_data_out[58]
+ |
+(no matching net) |Net: la_data_out[57]
+ | user_analog_proj_example/la_data_out[57]
+ |
+(no matching net) |Net: la_data_out[56]
+ | user_analog_proj_example/la_data_out[56]
+ |
+(no matching net) |Net: la_data_out[55]
+ | user_analog_proj_example/la_data_out[55]
+ |
+(no matching net) |Net: la_data_out[54]
+ | user_analog_proj_example/la_data_out[54]
+ |
+(no matching net) |Net: la_data_out[53]
+ | user_analog_proj_example/la_data_out[53]
+ |
+(no matching net) |Net: la_data_out[52]
+ | user_analog_proj_example/la_data_out[52]
+ |
+(no matching net) |Net: la_data_out[51]
+ | user_analog_proj_example/la_data_out[51]
+ |
+(no matching net) |Net: la_data_out[50]
+ | user_analog_proj_example/la_data_out[50]
+ |
+(no matching net) |Net: la_data_out[49]
+ | user_analog_proj_example/la_data_out[49]
+ |
+(no matching net) |Net: la_data_out[48]
+ | user_analog_proj_example/la_data_out[48]
+ |
+(no matching net) |Net: la_data_out[47]
+ | user_analog_proj_example/la_data_out[47]
+ |
+(no matching net) |Net: la_data_out[46]
+ | user_analog_proj_example/la_data_out[46]
+ |
+(no matching net) |Net: la_data_out[45]
+ | user_analog_proj_example/la_data_out[45]
+ |
+(no matching net) |Net: la_data_out[44]
+ | user_analog_proj_example/la_data_out[44]
+ |
+(no matching net) |Net: la_data_out[43]
+ | user_analog_proj_example/la_data_out[43]
+ |
+(no matching net) |Net: la_data_out[42]
+ | user_analog_proj_example/la_data_out[42]
+ |
+(no matching net) |Net: la_data_out[41]
+ | user_analog_proj_example/la_data_out[41]
+ |
+(no matching net) |Net: la_data_out[40]
+ | user_analog_proj_example/la_data_out[40]
+ |
+(no matching net) |Net: la_data_out[39]
+ | user_analog_proj_example/la_data_out[39]
+ |
+(no matching net) |Net: la_data_out[38]
+ | user_analog_proj_example/la_data_out[38]
+ |
+(no matching net) |Net: la_data_out[37]
+ | user_analog_proj_example/la_data_out[37]
+ |
+(no matching net) |Net: la_data_out[36]
+ | user_analog_proj_example/la_data_out[36]
+ |
+(no matching net) |Net: la_data_out[35]
+ | user_analog_proj_example/la_data_out[35]
+ |
+(no matching net) |Net: la_data_out[34]
+ | user_analog_proj_example/la_data_out[34]
+ |
+(no matching net) |Net: la_data_out[33]
+ | user_analog_proj_example/la_data_out[33]
+ |
+(no matching net) |Net: la_data_out[32]
+ | user_analog_proj_example/la_data_out[32]
+ |
+(no matching net) |Net: la_data_out[31]
+ | user_analog_proj_example/la_data_out[31]
+ |
+(no matching net) |Net: la_data_out[30]
+ | user_analog_proj_example/la_data_out[30]
+ |
+(no matching net) |Net: la_data_out[29]
+ | user_analog_proj_example/la_data_out[29]
+ |
+(no matching net) |Net: la_data_out[28]
+ | user_analog_proj_example/la_data_out[28]
+ |
+(no matching net) |Net: la_data_out[27]
+ | user_analog_proj_example/la_data_out[27]
+ |
+(no matching net) |Net: la_data_out[26]
+ | user_analog_proj_example/la_data_out[26]
+ |
+(no matching net) |Net: la_data_out[25]
+ | user_analog_proj_example/la_data_out[25]
+ |
+(no matching net) |Net: la_data_out[24]
+ | user_analog_proj_example/la_data_out[24]
+ |
+(no matching net) |Net: la_data_out[23]
+ | user_analog_proj_example/la_data_out[23]
+ |
+(no matching net) |Net: la_data_out[22]
+ | user_analog_proj_example/la_data_out[22]
+ |
+(no matching net) |Net: la_data_out[21]
+ | user_analog_proj_example/la_data_out[21]
+ |
+(no matching net) |Net: la_data_out[20]
+ | user_analog_proj_example/la_data_out[20]
+ |
+(no matching net) |Net: la_data_out[19]
+ | user_analog_proj_example/la_data_out[19]
+ |
+(no matching net) |Net: la_data_out[18]
+ | user_analog_proj_example/la_data_out[18]
+ |
+(no matching net) |Net: la_data_out[17]
+ | user_analog_proj_example/la_data_out[17]
+ |
+(no matching net) |Net: la_data_out[16]
+ | user_analog_proj_example/la_data_out[16]
+ |
+(no matching net) |Net: la_data_out[15]
+ | user_analog_proj_example/la_data_out[15]
+ |
+(no matching net) |Net: la_data_out[14]
+ | user_analog_proj_example/la_data_out[14]
+ |
+(no matching net) |Net: la_data_out[13]
+ | user_analog_proj_example/la_data_out[13]
+ |
+(no matching net) |Net: la_data_out[12]
+ | user_analog_proj_example/la_data_out[12]
+ |
+(no matching net) |Net: la_data_out[11]
+ | user_analog_proj_example/la_data_out[11]
+ |
+(no matching net) |Net: la_data_out[10]
+ | user_analog_proj_example/la_data_out[10]
+ |
+(no matching net) |Net: la_data_out[9]
+ | user_analog_proj_example/la_data_out[9]
+ |
+(no matching net) |Net: la_data_out[8]
+ | user_analog_proj_example/la_data_out[8]
+ |
+(no matching net) |Net: la_data_out[7]
+ | user_analog_proj_example/la_data_out[7]
+ |
+(no matching net) |Net: la_data_out[6]
+ | user_analog_proj_example/la_data_out[6]
+ |
+(no matching net) |Net: la_data_out[5]
+ | user_analog_proj_example/la_data_out[5]
+ |
+(no matching net) |Net: la_data_out[4]
+ | user_analog_proj_example/la_data_out[4]
+ |
+(no matching net) |Net: la_data_out[3]
+ | user_analog_proj_example/la_data_out[3]
+ |
+(no matching net) |Net: la_data_out[2]
+ | user_analog_proj_example/la_data_out[2]
+ |
+(no matching net) |Net: la_data_out[1]
+ | user_analog_proj_example/la_data_out[1]
+ |
+(no matching net) |Net: la_data_out[0]
+ | user_analog_proj_example/la_data_out[0]
+ |
+(no matching net) |Net: la_oenb[127]
+ | user_analog_proj_example/la_oenb[127] =
+ |
+(no matching net) |Net: la_oenb[126]
+ | user_analog_proj_example/la_oenb[126] =
+ |
+(no matching net) |Net: la_oenb[125]
+ | user_analog_proj_example/la_oenb[125] =
+ |
+(no matching net) |Net: la_oenb[124]
+ | user_analog_proj_example/la_oenb[124] =
+ |
+(no matching net) |Net: la_oenb[123]
+ | user_analog_proj_example/la_oenb[123] =
+ |
+(no matching net) |Net: la_oenb[122]
+ | user_analog_proj_example/la_oenb[122] =
+ |
+(no matching net) |Net: la_oenb[121]
+ | user_analog_proj_example/la_oenb[121] =
+ |
+(no matching net) |Net: la_oenb[120]
+ | user_analog_proj_example/la_oenb[120] =
+ |
+(no matching net) |Net: la_oenb[119]
+ | user_analog_proj_example/la_oenb[119] =
+ |
+(no matching net) |Net: la_oenb[118]
+ | user_analog_proj_example/la_oenb[118] =
+ |
+(no matching net) |Net: la_oenb[117]
+ | user_analog_proj_example/la_oenb[117] =
+ |
+(no matching net) |Net: la_oenb[116]
+ | user_analog_proj_example/la_oenb[116] =
+ |
+(no matching net) |Net: la_oenb[115]
+ | user_analog_proj_example/la_oenb[115] =
+ |
+(no matching net) |Net: la_oenb[114]
+ | user_analog_proj_example/la_oenb[114] =
+ |
+(no matching net) |Net: la_oenb[113]
+ | user_analog_proj_example/la_oenb[113] =
+ |
+(no matching net) |Net: la_oenb[112]
+ | user_analog_proj_example/la_oenb[112] =
+ |
+(no matching net) |Net: la_oenb[111]
+ | user_analog_proj_example/la_oenb[111] =
+ |
+(no matching net) |Net: la_oenb[110]
+ | user_analog_proj_example/la_oenb[110] =
+ |
+(no matching net) |Net: la_oenb[109]
+ | user_analog_proj_example/la_oenb[109] =
+ |
+(no matching net) |Net: la_oenb[108]
+ | user_analog_proj_example/la_oenb[108] =
+ |
+(no matching net) |Net: la_oenb[107]
+ | user_analog_proj_example/la_oenb[107] =
+ |
+(no matching net) |Net: la_oenb[106]
+ | user_analog_proj_example/la_oenb[106] =
+ |
+(no matching net) |Net: la_oenb[105]
+ | user_analog_proj_example/la_oenb[105] =
+ |
+(no matching net) |Net: la_oenb[104]
+ | user_analog_proj_example/la_oenb[104] =
+ |
+(no matching net) |Net: la_oenb[103]
+ | user_analog_proj_example/la_oenb[103] =
+ |
+(no matching net) |Net: la_oenb[102]
+ | user_analog_proj_example/la_oenb[102] =
+ |
+(no matching net) |Net: la_oenb[101]
+ | user_analog_proj_example/la_oenb[101] =
+ |
+(no matching net) |Net: la_oenb[100]
+ | user_analog_proj_example/la_oenb[100] =
+ |
+(no matching net) |Net: la_oenb[99]
+ | user_analog_proj_example/la_oenb[99] = 1
+ |
+(no matching net) |Net: la_oenb[98]
+ | user_analog_proj_example/la_oenb[98] = 1
+ |
+(no matching net) |Net: la_oenb[97]
+ | user_analog_proj_example/la_oenb[97] = 1
+ |
+(no matching net) |Net: la_oenb[96]
+ | user_analog_proj_example/la_oenb[96] = 1
+ |
+(no matching net) |Net: la_oenb[95]
+ | user_analog_proj_example/la_oenb[95] = 1
+ |
+(no matching net) |Net: la_oenb[94]
+ | user_analog_proj_example/la_oenb[94] = 1
+ |
+(no matching net) |Net: la_oenb[93]
+ | user_analog_proj_example/la_oenb[93] = 1
+ |
+(no matching net) |Net: la_oenb[92]
+ | user_analog_proj_example/la_oenb[92] = 1
+ |
+(no matching net) |Net: la_oenb[91]
+ | user_analog_proj_example/la_oenb[91] = 1
+ |
+(no matching net) |Net: la_oenb[90]
+ | user_analog_proj_example/la_oenb[90] = 1
+ |
+(no matching net) |Net: la_oenb[89]
+ | user_analog_proj_example/la_oenb[89] = 1
+ |
+(no matching net) |Net: la_oenb[88]
+ | user_analog_proj_example/la_oenb[88] = 1
+ |
+(no matching net) |Net: la_oenb[87]
+ | user_analog_proj_example/la_oenb[87] = 1
+ |
+(no matching net) |Net: la_oenb[86]
+ | user_analog_proj_example/la_oenb[86] = 1
+ |
+(no matching net) |Net: la_oenb[85]
+ | user_analog_proj_example/la_oenb[85] = 1
+ |
+(no matching net) |Net: la_oenb[84]
+ | user_analog_proj_example/la_oenb[84] = 1
+ |
+(no matching net) |Net: la_oenb[83]
+ | user_analog_proj_example/la_oenb[83] = 1
+ |
+(no matching net) |Net: la_oenb[82]
+ | user_analog_proj_example/la_oenb[82] = 1
+ |
+(no matching net) |Net: la_oenb[81]
+ | user_analog_proj_example/la_oenb[81] = 1
+ |
+(no matching net) |Net: la_oenb[80]
+ | user_analog_proj_example/la_oenb[80] = 1
+ |
+(no matching net) |Net: la_oenb[79]
+ | user_analog_proj_example/la_oenb[79] = 1
+ |
+(no matching net) |Net: la_oenb[78]
+ | user_analog_proj_example/la_oenb[78] = 1
+ |
+(no matching net) |Net: la_oenb[77]
+ | user_analog_proj_example/la_oenb[77] = 1
+ |
+(no matching net) |Net: la_oenb[76]
+ | user_analog_proj_example/la_oenb[76] = 1
+ |
+(no matching net) |Net: la_oenb[75]
+ | user_analog_proj_example/la_oenb[75] = 1
+ |
+(no matching net) |Net: la_oenb[74]
+ | user_analog_proj_example/la_oenb[74] = 1
+ |
+(no matching net) |Net: la_oenb[73]
+ | user_analog_proj_example/la_oenb[73] = 1
+ |
+(no matching net) |Net: la_oenb[72]
+ | user_analog_proj_example/la_oenb[72] = 1
+ |
+(no matching net) |Net: la_oenb[71]
+ | user_analog_proj_example/la_oenb[71] = 1
+ |
+(no matching net) |Net: la_oenb[70]
+ | user_analog_proj_example/la_oenb[70] = 1
+ |
+(no matching net) |Net: la_oenb[69]
+ | user_analog_proj_example/la_oenb[69] = 1
+ |
+(no matching net) |Net: la_oenb[68]
+ | user_analog_proj_example/la_oenb[68] = 1
+ |
+(no matching net) |Net: la_oenb[67]
+ | user_analog_proj_example/la_oenb[67] = 1
+ |
+(no matching net) |Net: la_oenb[66]
+ | user_analog_proj_example/la_oenb[66] = 1
+ |
+(no matching net) |Net: la_oenb[65]
+ | user_analog_proj_example/la_oenb[65] = 1
+ |
+(no matching net) |Net: la_oenb[64]
+ | user_analog_proj_example/la_oenb[64] = 1
+ |
+(no matching net) |Net: la_oenb[63]
+ | user_analog_proj_example/la_oenb[63] = 1
+ |
+(no matching net) |Net: la_oenb[62]
+ | user_analog_proj_example/la_oenb[62] = 1
+ |
+(no matching net) |Net: la_oenb[61]
+ | user_analog_proj_example/la_oenb[61] = 1
+ |
+(no matching net) |Net: la_oenb[60]
+ | user_analog_proj_example/la_oenb[60] = 1
+ |
+(no matching net) |Net: la_oenb[59]
+ | user_analog_proj_example/la_oenb[59] = 1
+ |
+(no matching net) |Net: la_oenb[58]
+ | user_analog_proj_example/la_oenb[58] = 1
+ |
+(no matching net) |Net: la_oenb[57]
+ | user_analog_proj_example/la_oenb[57] = 1
+ |
+(no matching net) |Net: la_oenb[56]
+ | user_analog_proj_example/la_oenb[56] = 1
+ |
+(no matching net) |Net: la_oenb[55]
+ | user_analog_proj_example/la_oenb[55] = 1
+ |
+(no matching net) |Net: la_oenb[54]
+ | user_analog_proj_example/la_oenb[54] = 1
+ |
+(no matching net) |Net: la_oenb[53]
+ | user_analog_proj_example/la_oenb[53] = 1
+ |
+(no matching net) |Net: la_oenb[52]
+ | user_analog_proj_example/la_oenb[52] = 1
+ |
+(no matching net) |Net: la_oenb[51]
+ | user_analog_proj_example/la_oenb[51] = 1
+ |
+(no matching net) |Net: la_oenb[50]
+ | user_analog_proj_example/la_oenb[50] = 1
+ |
+(no matching net) |Net: la_oenb[49]
+ | user_analog_proj_example/la_oenb[49] = 1
+ |
+(no matching net) |Net: la_oenb[48]
+ | user_analog_proj_example/la_oenb[48] = 1
+ |
+(no matching net) |Net: la_oenb[47]
+ | user_analog_proj_example/la_oenb[47] = 1
+ |
+(no matching net) |Net: la_oenb[46]
+ | user_analog_proj_example/la_oenb[46] = 1
+ |
+(no matching net) |Net: la_oenb[45]
+ | user_analog_proj_example/la_oenb[45] = 1
+ |
+(no matching net) |Net: la_oenb[44]
+ | user_analog_proj_example/la_oenb[44] = 1
+ |
+(no matching net) |Net: la_oenb[43]
+ | user_analog_proj_example/la_oenb[43] = 1
+ |
+(no matching net) |Net: la_oenb[42]
+ | user_analog_proj_example/la_oenb[42] = 1
+ |
+(no matching net) |Net: la_oenb[41]
+ | user_analog_proj_example/la_oenb[41] = 1
+ |
+(no matching net) |Net: la_oenb[40]
+ | user_analog_proj_example/la_oenb[40] = 1
+ |
+(no matching net) |Net: la_oenb[39]
+ | user_analog_proj_example/la_oenb[39] = 1
+ |
+(no matching net) |Net: la_oenb[38]
+ | user_analog_proj_example/la_oenb[38] = 1
+ |
+(no matching net) |Net: la_oenb[37]
+ | user_analog_proj_example/la_oenb[37] = 1
+ |
+(no matching net) |Net: la_oenb[36]
+ | user_analog_proj_example/la_oenb[36] = 1
+ |
+(no matching net) |Net: la_oenb[35]
+ | user_analog_proj_example/la_oenb[35] = 1
+ |
+(no matching net) |Net: la_oenb[34]
+ | user_analog_proj_example/la_oenb[34] = 1
+ |
+(no matching net) |Net: la_oenb[33]
+ | user_analog_proj_example/la_oenb[33] = 1
+ |
+(no matching net) |Net: la_oenb[32]
+ | user_analog_proj_example/la_oenb[32] = 1
+ |
+(no matching net) |Net: la_oenb[31]
+ | user_analog_proj_example/la_oenb[31] = 1
+ |
+(no matching net) |Net: la_oenb[30]
+ | user_analog_proj_example/la_oenb[30] = 1
+ |
+(no matching net) |Net: la_oenb[29]
+ | user_analog_proj_example/la_oenb[29] = 1
+ |
+(no matching net) |Net: la_oenb[28]
+ | user_analog_proj_example/la_oenb[28] = 1
+ |
+(no matching net) |Net: la_oenb[27]
+ | user_analog_proj_example/la_oenb[27] = 1
+ |
+(no matching net) |Net: la_oenb[26]
+ | user_analog_proj_example/la_oenb[26] = 1
+ |
+(no matching net) |Net: la_oenb[25]
+ | user_analog_proj_example/la_oenb[25] = 1
+ |
+(no matching net) |Net: la_oenb[24]
+ | user_analog_proj_example/la_oenb[24] = 1
+ |
+(no matching net) |Net: la_oenb[23]
+ | user_analog_proj_example/la_oenb[23] = 1
+ |
+(no matching net) |Net: la_oenb[22]
+ | user_analog_proj_example/la_oenb[22] = 1
+ |
+(no matching net) |Net: la_oenb[21]
+ | user_analog_proj_example/la_oenb[21] = 1
+ |
+(no matching net) |Net: la_oenb[20]
+ | user_analog_proj_example/la_oenb[20] = 1
+ |
+(no matching net) |Net: la_oenb[19]
+ | user_analog_proj_example/la_oenb[19] = 1
+ |
+(no matching net) |Net: la_oenb[18]
+ | user_analog_proj_example/la_oenb[18] = 1
+ |
+(no matching net) |Net: la_oenb[17]
+ | user_analog_proj_example/la_oenb[17] = 1
+ |
+(no matching net) |Net: la_oenb[16]
+ | user_analog_proj_example/la_oenb[16] = 1
+ |
+(no matching net) |Net: la_oenb[15]
+ | user_analog_proj_example/la_oenb[15] = 1
+ |
+(no matching net) |Net: la_oenb[14]
+ | user_analog_proj_example/la_oenb[14] = 1
+ |
+(no matching net) |Net: la_oenb[13]
+ | user_analog_proj_example/la_oenb[13] = 1
+ |
+(no matching net) |Net: la_oenb[12]
+ | user_analog_proj_example/la_oenb[12] = 1
+ |
+(no matching net) |Net: la_oenb[11]
+ | user_analog_proj_example/la_oenb[11] = 1
+ |
+(no matching net) |Net: la_oenb[10]
+ | user_analog_proj_example/la_oenb[10] = 1
+ |
+(no matching net) |Net: la_oenb[9]
+ | user_analog_proj_example/la_oenb[9] = 1
+ |
+(no matching net) |Net: la_oenb[8]
+ | user_analog_proj_example/la_oenb[8] = 1
+ |
+(no matching net) |Net: la_oenb[7]
+ | user_analog_proj_example/la_oenb[7] = 1
+ |
+(no matching net) |Net: la_oenb[6]
+ | user_analog_proj_example/la_oenb[6] = 1
+ |
+(no matching net) |Net: la_oenb[5]
+ | user_analog_proj_example/la_oenb[5] = 1
+ |
+(no matching net) |Net: la_oenb[4]
+ | user_analog_proj_example/la_oenb[4] = 1
+ |
+(no matching net) |Net: la_oenb[3]
+ | user_analog_proj_example/la_oenb[3] = 1
+ |
+(no matching net) |Net: la_oenb[2]
+ | user_analog_proj_example/la_oenb[2] = 1
+ |
+(no matching net) |Net: la_oenb[1]
+ | user_analog_proj_example/la_oenb[1] = 1
+ |
+(no matching net) |Net: la_oenb[0]
+ | user_analog_proj_example/la_oenb[0] = 1
+ |
+(no matching net) |Net: io_in
+ | user_analog_proj_example/io_in = 1
+ |
+(no matching net) |Net: io_in_3v3
+ | user_analog_proj_example/io_in_3v3 = 1
+ |
+(no matching net) |Net: io_out
+ | user_analog_proj_example/io_out = 1
+ |
+(no matching net) |Net: io_oeb
+ | user_analog_proj_example/io_oeb = 1
+ |
+(no matching net) |Net: gpio_analog
+ | user_analog_proj_example/gpio_analog = 1
+ |
+(no matching net) |Net: gpio_noesd
+ | user_analog_proj_example/gpio_noesd = 1
+ |
+(no matching net) |Net: io_analog
+ | user_analog_proj_example/io_analog = 1
+ |
+(no matching net) |Net: wbs_we_i
+ | user_analog_proj_example/wbs_we_i = 1
+ |
+(no matching net) |Net: wbs_stb_i
+ | user_analog_proj_example/wbs_stb_i = 1
+ |
+(no matching net) |Net: user_clock2
+ | user_analog_proj_example/user_clock2 = 1
+ |
+(no matching net) |Net: user_irq[2]
+ | user_analog_proj_example/irq[2] = 1
+ |
+(no matching net) |Net: user_irq[1]
+ | user_analog_proj_example/irq[1] = 1
+ |
+(no matching net) |Net: user_irq[0]
+ | user_analog_proj_example/irq[0] = 1
+---------------------------------------------------------------------------------------
+DEVICE mismatches: Class fragments follow (with node fanout counts):
+Circuit 1: user_analog_project_wrapper |Circuit 2: user_analog_project_wrapper
+
+---------------------------------------------------------------------------------------
+Instance: sky130_fd_sc_hd__buf_16_4/sky130 |Instance: mprj
+ (1,3) = (66,2) | wb_clk_i = 1
+ 2 = 4 | wb_rst_i = 1
+ 4 = 66 | wbs_cyc_i = 1
+ | wbs_stb_i = 1
+ | wbs_we_i = 1
+ | wbs_sel_i[3] = 1
+ | wbs_sel_i[2] = 1
+ | wbs_sel_i[1] = 1
+ | wbs_sel_i[0] = 1
+ | wbs_adr_i[31] = 1
+ | wbs_adr_i[30] = 1
+ | wbs_adr_i[29] = 1
+ | wbs_adr_i[28] = 1
+ | wbs_adr_i[27] = 1
+ | wbs_adr_i[26] = 1
+ | wbs_adr_i[25] = 1
+ | wbs_adr_i[24] = 1
+ | wbs_adr_i[23] = 1
+ | wbs_adr_i[22] = 1
+ | wbs_adr_i[21] = 1
+ | wbs_adr_i[20] = 1
+ | wbs_adr_i[19] = 1
+ | wbs_adr_i[18] = 1
+ | wbs_adr_i[17] = 1
+ | wbs_adr_i[16] = 1
+ | wbs_adr_i[15] = 1
+ | wbs_adr_i[14] = 1
+ | wbs_adr_i[13] = 1
+ | wbs_adr_i[12] = 1
+ | wbs_adr_i[11] = 1
+ | wbs_adr_i[10] = 1
+ | wbs_adr_i[9] = 1
+ | wbs_adr_i[8] = 1
+ | wbs_adr_i[7] = 1
+ | wbs_adr_i[6] = 1
+ | wbs_adr_i[5] = 1
+ | wbs_adr_i[4] = 1
+ | wbs_adr_i[3] = 1
+ | wbs_adr_i[2] = 1
+ | wbs_adr_i[1] = 1
+ | wbs_adr_i[0] = 1
+ | wbs_dat_i[31] = 1
+ | wbs_dat_i[30] = 1
+ | wbs_dat_i[29] = 1
+ | wbs_dat_i[28] = 1
+ | wbs_dat_i[27] = 1
+ | wbs_dat_i[26] = 1
+ | wbs_dat_i[25] = 1
+ | wbs_dat_i[24] = 1
+ | wbs_dat_i[23] = 1
+ | wbs_dat_i[22] = 1
+ | wbs_dat_i[21] = 1
+ | wbs_dat_i[20] = 1
+ | wbs_dat_i[19] = 1
+ | wbs_dat_i[18] = 1
+ | wbs_dat_i[17] = 1
+ | wbs_dat_i[16] = 1
+ | wbs_dat_i[15] = 1
+ | wbs_dat_i[14] = 1
+ | wbs_dat_i[13] = 1
+ | wbs_dat_i[12] = 1
+ | wbs_dat_i[11] = 1
+ | wbs_dat_i[10] = 1
+ | wbs_dat_i[9] = 1
+ | wbs_dat_i[8] = 1
+ | wbs_dat_i[7] = 1
+ | wbs_dat_i[6] = 1
+ | wbs_dat_i[5] = 1
+ | wbs_dat_i[4] = 1
+ | wbs_dat_i[3] = 1
+ | wbs_dat_i[2] = 1
+ | wbs_dat_i[1] = 1
+ | wbs_dat_i[0] = 1
+ | wbs_ack_o = 1
+ | wbs_dat_o[31] = 1
+ | wbs_dat_o[30] = 1
+ | wbs_dat_o[29] = 1
+ | wbs_dat_o[28] = 1
+ | wbs_dat_o[27] = 1
+ | wbs_dat_o[26] = 1
+ | wbs_dat_o[25] = 1
+ | wbs_dat_o[24] = 1
+ | wbs_dat_o[23] = 1
+ | wbs_dat_o[22] = 1
+ | wbs_dat_o[21] = 1
+ | wbs_dat_o[20] = 1
+ | wbs_dat_o[19] = 1
+ | wbs_dat_o[18] = 1
+ | wbs_dat_o[17] = 1
+ | wbs_dat_o[16] = 1
+ | wbs_dat_o[15] = 1
+ | wbs_dat_o[14] = 1
+ | wbs_dat_o[13] = 1
+ | wbs_dat_o[12] = 1
+ | wbs_dat_o[11] = 1
+ | wbs_dat_o[10] = 1
+ | wbs_dat_o[9] = 1
+ | wbs_dat_o[8] = 1
+ | wbs_dat_o[7] = 1
+ | wbs_dat_o[6] = 1
+ | wbs_dat_o[5] = 1
+ | wbs_dat_o[4] = 1
+ | wbs_dat_o[3] = 1
+ | wbs_dat_o[2] = 1
+ | wbs_dat_o[1] = 1
+ | wbs_dat_o[0] = 1
+ | la_data_in[127] = 1
+ | la_data_in[126] = 1
+ | la_data_in[125] = 1
+ | la_data_in[124] = 1
+ | la_data_in[123] = 1
+ | la_data_in[122] = 1
+ | la_data_in[121] = 1
+ | la_data_in[120] = 1
+ | la_data_in[119] = 1
+ | la_data_in[118] = 1
+ | la_data_in[117] = 1
+ | la_data_in[116] = 1
+ | la_data_in[115] = 1
+ | la_data_in[114] = 1
+ | la_data_in[113] = 1
+ | la_data_in[112] = 1
+ | la_data_in[111] = 1
+ | la_data_in[110] = 1
+ | la_data_in[109] = 1
+ | la_data_in[108] = 1
+ | la_data_in[107] = 1
+ | la_data_in[106] = 1
+ | la_data_in[105] = 1
+ | la_data_in[104] = 1
+ | la_data_in[103] = 1
+ | la_data_in[102] = 1
+ | la_data_in[101] = 1
+ | la_data_in[100] = 1
+ | la_data_in[99] = 1
+ | la_data_in[98] = 1
+ | la_data_in[97] = 1
+ | la_data_in[96] = 1
+ | la_data_in[95] = 1
+ | la_data_in[94] = 1
+ | la_data_in[93] = 1
+ | la_data_in[92] = 1
+ | la_data_in[91] = 1
+ | la_data_in[90] = 1
+ | la_data_in[89] = 1
+ | la_data_in[88] = 1
+ | la_data_in[87] = 1
+ | la_data_in[86] = 1
+ | la_data_in[85] = 1
+ | la_data_in[84] = 1
+ | la_data_in[83] = 1
+ | la_data_in[82] = 1
+ | la_data_in[81] = 1
+ | la_data_in[80] = 1
+ | la_data_in[79] = 1
+ | la_data_in[78] = 1
+ | la_data_in[77] = 1
+ | la_data_in[76] = 1
+ | la_data_in[75] = 1
+ | la_data_in[74] = 1
+ | la_data_in[73] = 1
+ | la_data_in[72] = 1
+ | la_data_in[71] = 1
+ | la_data_in[70] = 1
+ | la_data_in[69] = 1
+ | la_data_in[68] = 1
+ | la_data_in[67] = 1
+ | la_data_in[66] = 1
+ | la_data_in[65] = 1
+ | la_data_in[64] = 1
+ | la_data_in[63] = 1
+ | la_data_in[62] = 1
+ | la_data_in[61] = 1
+ | la_data_in[60] = 1
+ | la_data_in[59] = 1
+ | la_data_in[58] = 1
+ | la_data_in[57] = 1
+ | la_data_in[56] = 1
+ | la_data_in[55] = 1
+ | la_data_in[54] = 1
+ | la_data_in[53] = 1
+ | la_data_in[52] = 1
+ | la_data_in[51] = 1
+ | la_data_in[50] = 1
+ | la_data_in[49] = 1
+ | la_data_in[48] = 1
+ | la_data_in[47] = 1
+ | la_data_in[46] = 1
+ | la_data_in[45] = 1
+ | la_data_in[44] = 1
+ | la_data_in[43] = 1
+ | la_data_in[42] = 1
+ | la_data_in[41] = 1
+ | la_data_in[40] = 1
+ | la_data_in[39] = 1
+ | la_data_in[38] = 1
+ | la_data_in[37] = 1
+ | la_data_in[36] = 1
+ | la_data_in[35] = 1
+ | la_data_in[34] = 1
+ | la_data_in[33] = 1
+ | la_data_in[32] = 1
+ | la_data_in[31] = 1
+ | la_data_in[30] = 1
+ | la_data_in[29] = 1
+ | la_data_in[28] = 1
+ | la_data_in[27] = 1
+ | la_data_in[26] = 1
+ | la_data_in[25] = 1
+ | la_data_in[24] = 1
+ | la_data_in[23] = 1
+ | la_data_in[22] = 1
+ | la_data_in[21] = 1
+ | la_data_in[20] = 1
+ | la_data_in[19] = 1
+ | la_data_in[18] = 1
+ | la_data_in[17] = 1
+ | la_data_in[16] = 1
+ | la_data_in[15] = 1
+ | la_data_in[14] = 1
+ | la_data_in[13] = 1
+ | la_data_in[12] = 1
+ | la_data_in[11] = 1
+ | la_data_in[10] = 1
+ | la_data_in[9] = 1
+ | la_data_in[8] = 1
+ | la_data_in[7] = 1
+ | la_data_in[6] = 1
+ | la_data_in[5] = 1
+ | la_data_in[4] = 1
+ | la_data_in[3] = 1
+ | la_data_in[2] = 1
+ | la_data_in[1] = 1
+ | la_data_in[0] = 1
+ | la_data_out[127] = 1
+ | la_data_out[126] = 1
+ | la_data_out[125] = 1
+ | la_data_out[124] = 1
+ | la_data_out[123] = 1
+ | la_data_out[122] = 1
+ | la_data_out[121] = 1
+ | la_data_out[120] = 1
+ | la_data_out[119] = 1
+ | la_data_out[118] = 1
+ | la_data_out[117] = 1
+ | la_data_out[116] = 1
+ | la_data_out[115] = 1
+ | la_data_out[114] = 1
+ | la_data_out[113] = 1
+ | la_data_out[112] = 1
+ | la_data_out[111] = 1
+ | la_data_out[110] = 1
+ | la_data_out[109] = 1
+ | la_data_out[108] = 1
+ | la_data_out[107] = 1
+ | la_data_out[106] = 1
+ | la_data_out[105] = 1
+ | la_data_out[104] = 1
+ | la_data_out[103] = 1
+ | la_data_out[102] = 1
+ | la_data_out[101] = 1
+ | la_data_out[100] = 1
+ | la_data_out[99] = 1
+ | la_data_out[98] = 1
+ | la_data_out[97] = 1
+ | la_data_out[96] = 1
+ | la_data_out[95] = 1
+ | la_data_out[94] = 1
+ | la_data_out[93] = 1
+ | la_data_out[92] = 1
+ | la_data_out[91] = 1
+ | la_data_out[90] = 1
+ | la_data_out[89] = 1
+ | la_data_out[88] = 1
+ | la_data_out[87] = 1
+ | la_data_out[86] = 1
+ | la_data_out[85] = 1
+ | la_data_out[84] = 1
+ | la_data_out[83] = 1
+ | la_data_out[82] = 1
+ | la_data_out[81] = 1
+ | la_data_out[80] = 1
+ | la_data_out[79] = 1
+ | la_data_out[78] = 1
+ | la_data_out[77] = 1
+ | la_data_out[76] = 1
+ | la_data_out[75] = 1
+ | la_data_out[74] = 1
+ | la_data_out[73] = 1
+ | la_data_out[72] = 1
+ | la_data_out[71] = 1
+ | la_data_out[70] = 1
+ | la_data_out[69] = 1
+ | la_data_out[68] = 1
+ | la_data_out[67] = 1
+ | la_data_out[66] = 1
+ | la_data_out[65] = 1
+ | la_data_out[64] = 1
+ | la_data_out[63] = 1
+ | la_data_out[62] = 1
+ | la_data_out[61] = 1
+ | la_data_out[60] = 1
+ | la_data_out[59] = 1
+ | la_data_out[58] = 1
+ | la_data_out[57] = 1
+ | la_data_out[56] = 1
+ | la_data_out[55] = 1
+ | la_data_out[54] = 1
+ | la_data_out[53] = 1
+ | la_data_out[52] = 1
+ | la_data_out[51] = 1
+ | la_data_out[50] = 1
+ | la_data_out[49] = 1
+ | la_data_out[48] = 1
+ | la_data_out[47] = 1
+ | la_data_out[46] = 1
+ | la_data_out[45] = 1
+ | la_data_out[44] = 1
+ | la_data_out[43] = 1
+ | la_data_out[42] = 1
+ | la_data_out[41] = 1
+ | la_data_out[40] = 1
+ | la_data_out[39] = 1
+ | la_data_out[38] = 1
+ | la_data_out[37] = 1
+ | la_data_out[36] = 1
+ | la_data_out[35] = 1
+ | la_data_out[34] = 1
+ | la_data_out[33] = 1
+ | la_data_out[32] = 1
+ | la_data_out[31] = 1
+ | la_data_out[30] = 1
+ | la_data_out[29] = 1
+ | la_data_out[28] = 1
+ | la_data_out[27] = 1
+ | la_data_out[26] = 1
+ | la_data_out[25] = 1
+ | la_data_out[24] = 1
+ | la_data_out[23] = 1
+ | la_data_out[22] = 1
+ | la_data_out[21] = 1
+ | la_data_out[20] = 1
+ | la_data_out[19] = 1
+ | la_data_out[18] = 1
+ | la_data_out[17] = 1
+ | la_data_out[16] = 1
+ | la_data_out[15] = 1
+ | la_data_out[14] = 1
+ | la_data_out[13] = 1
+ | la_data_out[12] = 1
+ | la_data_out[11] = 1
+ | la_data_out[10] = 1
+ | la_data_out[9] = 1
+ | la_data_out[8] = 1
+ | la_data_out[7] = 1
+ | la_data_out[6] = 1
+ | la_data_out[5] = 1
+ | la_data_out[4] = 1
+ | la_data_out[3] = 1
+ | la_data_out[2] = 1
+ | la_data_out[1] = 1
+ | la_data_out[0] = 1
+ | la_oenb[127] = 1
+ | la_oenb[126] = 1
+ | la_oenb[125] = 1
+ | la_oenb[124] = 1
+ | la_oenb[123] = 1
+ | la_oenb[122] = 1
+ | la_oenb[121] = 1
+ | la_oenb[120] = 1
+ | la_oenb[119] = 1
+ | la_oenb[118] = 1
+ | la_oenb[117] = 1
+ | la_oenb[116] = 1
+ | la_oenb[115] = 1
+ | la_oenb[114] = 1
+ | la_oenb[113] = 1
+ | la_oenb[112] = 1
+ | la_oenb[111] = 1
+ | la_oenb[110] = 1
+ | la_oenb[109] = 1
+ | la_oenb[108] = 1
+ | la_oenb[107] = 1
+ | la_oenb[106] = 1
+ | la_oenb[105] = 1
+ | la_oenb[104] = 1
+ | la_oenb[103] = 1
+ | la_oenb[102] = 1
+ | la_oenb[101] = 1
+ | la_oenb[100] = 1
+ | la_oenb[99] = 1
+ | la_oenb[98] = 1
+ | la_oenb[97] = 1
+ | la_oenb[96] = 1
+ | la_oenb[95] = 1
+ | la_oenb[94] = 1
+ | la_oenb[93] = 1
+ | la_oenb[92] = 1
+ | la_oenb[91] = 1
+ | la_oenb[90] = 1
+ | la_oenb[89] = 1
+ | la_oenb[88] = 1
+ | la_oenb[87] = 1
+ | la_oenb[86] = 1
+ | la_oenb[85] = 1
+ | la_oenb[84] = 1
+ | la_oenb[83] = 1
+ | la_oenb[82] = 1
+ | la_oenb[81] = 1
+ | la_oenb[80] = 1
+ | la_oenb[79] = 1
+ | la_oenb[78] = 1
+ | la_oenb[77] = 1
+ | la_oenb[76] = 1
+ | la_oenb[75] = 1
+ | la_oenb[74] = 1
+ | la_oenb[73] = 1
+ | la_oenb[72] = 1
+ | la_oenb[71] = 1
+ | la_oenb[70] = 1
+ | la_oenb[69] = 1
+ | la_oenb[68] = 1
+ | la_oenb[67] = 1
+ | la_oenb[66] = 1
+ | la_oenb[65] = 1
+ | la_oenb[64] = 1
+ | la_oenb[63] = 1
+ | la_oenb[62] = 1
+ | la_oenb[61] = 1
+ | la_oenb[60] = 1
+ | la_oenb[59] = 1
+ | la_oenb[58] = 1
+ | la_oenb[57] = 1
+ | la_oenb[56] = 1
+ | la_oenb[55] = 1
+ | la_oenb[54] = 1
+ | la_oenb[53] = 1
+ | la_oenb[52] = 1
+ | la_oenb[51] = 1
+ | la_oenb[50] = 1
+ | la_oenb[49] = 1
+ | la_oenb[48] = 1
+ | la_oenb[47] = 1
+ | la_oenb[46] = 1
+ | la_oenb[45] = 1
+ | la_oenb[44] = 1
+ | la_oenb[43] = 1
+ | la_oenb[42] = 1
+ | la_oenb[41] = 1
+ | la_oenb[40] = 1
+ | la_oenb[39] = 1
+ | la_oenb[38] = 1
+ | la_oenb[37] = 1
+ | la_oenb[36] = 1
+ | la_oenb[35] = 1
+ | la_oenb[34] = 1
+ | la_oenb[33] = 1
+ | la_oenb[32] = 1
+ | la_oenb[31] = 1
+ | la_oenb[30] = 1
+ | la_oenb[29] = 1
+ | la_oenb[28] = 1
+ | la_oenb[27] = 1
+ | la_oenb[26] = 1
+ | la_oenb[25] = 1
+ | la_oenb[24] = 1
+ | la_oenb[23] = 1
+ | la_oenb[22] = 1
+ | la_oenb[21] = 1
+ | la_oenb[20] = 1
+ | la_oenb[19] = 1
+ | la_oenb[18] = 1
+ | la_oenb[17] = 1
+ | la_oenb[16] = 1
+ | la_oenb[15] = 1
+ | la_oenb[14] = 1
+ | la_oenb[13] = 1
+ | la_oenb[12] = 1
+ | la_oenb[11] = 1
+ | la_oenb[10] = 1
+ | la_oenb[9] = 1
+ | la_oenb[8] = 1
+ | la_oenb[7] = 1
+ | la_oenb[6] = 1
+ | la_oenb[5] = 1
+ | la_oenb[4] = 1
+ | la_oenb[3] = 1
+ | la_oenb[2] = 1
+ | la_oenb[1] = 1
+ | la_oenb[0] = 1
+ | io_in = 1
+ | io_in_3v3 = 1
+ | io_out = 1
+ | io_oeb = 1
+ | gpio_analog = 1
+ | gpio_noesd = 1
+ | io_analog = 1
+ | io_clamp_high = 1
+ | io_clamp_low = 1
+ | user_clock2 = 1
+ | irq[2] = 1
+ | irq[1] = 1
+ | irq[0] = 1
+ |
+Instance: sky130_fd_sc_hd__buf_16_4/sky130 |(no matching instance)
+ (1,3) = (66,4) |
+ 2 = 4 |
+ 4 = 66 |
+ |
+ |
+Instance: sky130_fd_sc_hd__buf_2_4/sky130_ |(no matching instance)
+ (1,3) = (66,4) |
+ 2 = 4 |
+ 4 = 66 |
+ |
+ |
+Instance: sky130_fd_sc_hd__buf_2_4/sky130_ |(no matching instance)
+ (1,3) = (66,4) |
+ 2 = 2 |
+ 4 = 66 |
+ |
+ |
+Instance: sky130_fd_sc_hd__buf_16_4/sky130 |(no matching instance)
+ (1,3) = (62,4) |
+ 2 = 4 |
+ 4 = 62 |
+ |
+ |
+Instance: sky130_fd_sc_hd__buf_16_4/sky130 |(no matching instance)
+ (1,3) = (62,2) |
+ 2 = 4 |
+ 4 = 62 |
+ |
+ |
+Instance: sky130_fd_sc_hd__buf_2_4/sky130_ |(no matching instance)
+ (1,3) = (62,4) |
+ 2 = 4 |
+ 4 = 62 |
+ |
+ |
+Instance: sky130_fd_sc_hd__buf_2_4/sky130_ |(no matching instance)
+ (1,3) = (62,4) |
+ 2 = 2 |
+ 4 = 62 |
+ |
+ |
+Instance: comparator_v6_0//preamp_part12_0 |(no matching instance)
+ (1,3) = (62,3) |
+ 2 = 7 |
+ 4 = 62 |
+ |
+ |
+Instance: comparator_v6_0//latch_3_0//sky1 |(no matching instance)
+ (1,3) = (66,3) |
+ 2 = 5 |
+ 4 = 66 |
+ |
+ |
+Instance: sky130_fd_pr__diode_pd2nw_05v5:0 |(no matching instance)
+ pos = 66 |
+ neg = 1 |
+ |
+Instance: sky130_fd_pr__diode_pd2nw_05v5:0 |(no matching instance)
+ pos = 66 |
+ neg = 1 |
+ |
+Instance: sky130_fd_pr__diode_pd2nw_05v5:0 |(no matching instance)
+ pos = 62 |
+ neg = 1 |
+ |
+Instance: sky130_fd_pr__diode_pd2nw_05v5:0 |(no matching instance)
+ pos = 62 |
+ neg = 1 |
+---------------------------------------------------------------------------------------
+Netlists do not match.
+Netlists do not match.
diff --git a/netgen/example_por.spice b/netgen/example_por.spice
new file mode 100644
index 0000000..0c9cb9c
--- /dev/null
+++ b/netgen/example_por.spice
@@ -0,0 +1,397 @@
+* SPICE3 file created from user_analog_project_wrapper.ext - technology: sky130A
+
+.subckt sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y a_n100_n100# w_n238_n238#
+D0 w_n238_n238# a_n100_n100# sky130_fd_pr__diode_pw2nd_05v5 pj=4e+06u area=1e+12p
+.ends
+
+.subckt sky130_fd_pr__diode_pd2nw_05v5_G4XDRY w_n376_n376# a_n100_n100# w_n238_n238#
+D0 a_n100_n100# w_n238_n238# sky130_fd_pr__diode_pd2nw_05v5 pj=4e+06u area=1e+12p
+C0 li_n340_n340# w_n376_n376# 2.20fF **FLOATING
+.ends
+
+.subckt sky130_fd_sc_hd__buf_2 A VGND VPWR X VNB VPB
+X0 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=5.63e+11p pd=5.18e+06u as=2.7e+11p ps=2.54e+06u w=1e+06u l=150000u
+X1 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 VPWR A a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=1.664e+11p ps=1.8e+06u w=640000u l=150000u
+X3 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=1.755e+11p pd=1.84e+06u as=3.6625e+11p ps=3.78e+06u w=650000u l=150000u
+X4 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X5 VGND A a_27_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.092e+11p ps=1.36e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hd__buf_16 A VGND VPWR X VNB VPB
+X0 VGND A a_109_47# VNB sky130_fd_pr__nfet_01v8 ad=2.093e+12p pd=2.204e+07u as=5.265e+11p ps=5.52e+06u w=650000u l=150000u
+X1 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=2.16e+12p pd=2.032e+07u as=3.22e+12p ps=3.044e+07u w=1e+06u l=150000u
+X2 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.404e+12p ps=1.472e+07u w=650000u l=150000u
+X3 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X4 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X6 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_109_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=8.1e+11p pd=7.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 VPWR A a_109_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X11 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X12 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X13 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X14 a_109_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X17 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 VPWR A a_109_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 VGND A a_109_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X21 VGND A a_109_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X22 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X23 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X25 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X27 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X30 a_109_47# A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X31 a_109_47# A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X32 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X35 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X36 VPWR A a_109_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X39 a_109_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_109_47# A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X43 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_GJYUB2 a_207_n100# a_81_n126# a_n207_n128# a_15_n100#
++ a_n177_n100# a_111_n100# a_n15_n128# a_n111_n126# w_n305_n200# a_n81_n100# a_177_n128#
++ a_n269_n100# VSUBS
+X0 a_207_n100# a_177_n128# a_111_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=3.1e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_15_n100# a_n15_n128# a_n81_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_111_n100# a_81_n126# a_15_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n81_n100# a_n111_n126# a_n177_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_n177_n100# a_n207_n128# a_n269_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n15_n89# a_15_n69# VSUBS
+X0 a_15_n69# a_n15_n89# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u#0 sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89# sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n73_n69# VSUBS
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n73_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# VSUBS sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2#0 a_n139_n100# a_63_n100# a_33_n130# a_n33_n100# w_n319_n202# a_n63_n130#
++ VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n319_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n139_n100# w_n319_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W12 Vout Vin VDD GND pmos_2uf2_0/w_n319_n202# nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ VSUBS
+Xnmos_1u_0 Vin nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# GND VSUBS nmos_1u#0
+Xpmos_2uf2_0 VDD VDD Vin Vout pmos_2uf2_0/w_n319_n202# Vin VSUBS pmos_2uf2#0
+.ends
+
+.subckt latch_3 a_646_808# inv_W12_1/GND m1_686_734# w_n16_492# inv_W12_1/Vin VSUBS
++ inv_W12_0/Vin
+Xsky130_fd_pr__pfet_01v8_GJYUB2_0 m1_686_734# a_646_808# a_646_808# m1_686_734# m1_686_734#
++ inv_W12_1/VDD a_646_808# a_646_808# w_n16_492# inv_W12_1/VDD a_646_808# inv_W12_1/VDD
++ VSUBS sky130_fd_pr__pfet_01v8_GJYUB2
+Xinv_W12_0 inv_W12_1/Vin inv_W12_0/Vin inv_W12_1/VDD inv_W12_1/GND w_n16_492# inv_W12_1/Vin
++ VSUBS inv_W12
+Xinv_W12_1 inv_W12_0/Vin inv_W12_1/Vin inv_W12_1/VDD inv_W12_1/GND w_n16_492# inv_W12_0/Vin
++ VSUBS inv_W12
+
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_G6PLX8 a_n129_n500# a_63_n500# a_n221_n474# a_n33_n500#
++ a_n159_n522# a_159_n500# VSUBS
+X0 a_n33_n500# a_n159_n522# a_n129_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_159_n500# a_n159_n522# a_63_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_63_n500# a_n159_n522# a_n33_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n500# a_n159_n522# a_n221_n474# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_RFM3CD#0 a_n73_n100# w_n109_n162# a_15_n100# a_n15_n126#
++ VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# w_n109_n162# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#1 a_15_n500# a_n15_n526# a_n73_n500# VSUBS
+X0 a_15_n500# a_n15_n526# a_n73_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_RURP52 a_33_n370# a_63_n348# a_n63_n370# a_n33_n348#
++ a_n125_n348# VSUBS
+X0 a_n33_n348# a_n63_n370# a_n125_n348# VSUBS sky130_fd_pr__nfet_01v8 ad=4.95e+11p pd=3.66e+06u as=4.65e+11p ps=3.62e+06u w=1.5e+06u l=150000u
+X1 a_63_n348# a_33_n370# a_n33_n348# VSUBS sky130_fd_pr__nfet_01v8 ad=4.65e+11p pd=3.62e+06u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8FHE5N a_n125_n439# a_63_n450# a_n63_n476# a_n33_n450#
++ a_33_n476# VSUBS
+X0 a_63_n450# a_33_n476# a_n33_n450# VSUBS sky130_fd_pr__nfet_01v8 ad=1.528e+11p pd=1.62e+06u as=1.65e+11p ps=1.66e+06u w=500000u l=150000u
+X1 a_n33_n450# a_n63_n476# a_n125_n439# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.528e+11p ps=1.62e+06u w=500000u l=150000u
+.ends
+
+.subckt preamp_part12 li_n720_1336# a_n72_236# a_80_n658# a_n434_n660# m1_n692_n210#
++ a_n506_870# a_388_n660# w_n720_994# li_n720_n474# a_414_256# a_706_862# li_954_n358#
++ VSUBS
+Xsky130_fd_pr__nfet_01v8_G6PLX8_0 a_414_256# a_414_256# m1_n128_n164# m1_n128_n164#
++ a_n434_n660# m1_n128_n164# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__nfet_01v8_G6PLX8_1 a_n72_236# a_n72_236# m1_338_n220# m1_338_n220#
++ a_388_n660# m1_338_n220# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 li_n720_1336# w_n720_994# a_414_256# a_n506_870#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 a_n72_236# w_n720_994# li_n720_1336# a_706_862#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 li_n720_n474# a_414_256# m1_n692_n210# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 li_954_n358# a_n72_236# li_n720_n474# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_RURP52_0 a_n72_236# li_n218_192# a_n72_236# m1_n128_n164#
++ li_n218_192# VSUBS sky130_fd_pr__nfet_01v8_RURP52
+Xsky130_fd_pr__nfet_01v8_RURP52_1 a_414_256# li_n218_192# a_414_256# m1_338_n220#
++ li_n218_192# VSUBS sky130_fd_pr__nfet_01v8_RURP52
+Xsky130_fd_pr__nfet_01v8_8FHE5N_0 li_n720_n474# li_n720_n474# a_80_n658# li_n218_192#
++ a_80_n658# VSUBS sky130_fd_pr__nfet_01v8_8FHE5N
+
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5E9B w_n161_n200# a_33_n126# a_63_n100# a_n125_n74#
++ a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n126# a_n33_n100# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n125_n74# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt SR_latch a_648_848# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ a_262_508# VDD w_0_524# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 a_648_848# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND a_262_508# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__pfet_01v8_AC5E9B_0 w_0_524# a_262_508# VDD VDD a_648_848# a_262_508#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+Xsky130_fd_pr__pfet_01v8_AC5E9B_1 w_0_524# a_648_848# VDD VDD a_262_508# a_648_848#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+.ends
+
+.subckt preamp_part22 w_78_306# a_392_716# sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#
++ sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126# sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n15_n126#
++ sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_n15_n126# a_810_594# li_116_1034# sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_15_n100#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n73_n100#
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_0 li_214_402# w_78_306# a_810_594# sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_1 a_392_716# w_78_306# li_1016_536# sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_2 sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n73_n100#
++ w_78_306# li_214_402# sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_3 li_1016_536# w_78_306# sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_15_n100#
++ sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 li_214_402# w_78_306# li_116_1034# a_392_716# VSUBS
++ sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 li_116_1034# w_78_306# li_1016_536# a_810_594# VSUBS
++ sky130_fd_pr__pfet_01v8_RFM3CD#0
+
+.ends
+
+.subckt comparator_v6 Outn Vp Vn CLK VDD GND Outp CLKBAR
+Xlatch_3_0 CLKBAR GND VDD VDD Dp GND Dn latch_3
+Xpreamp_part12_0 VDD fp CLK Vn Dp CLK Vp VDD GND fn CLK Dn GND preamp_part12
+XSR_latch_0 Outp Dn Dp Outn VDD VDD GND GND SR_latch
+Xpreamp_part22_0 VDD fp CLKBAR CLKBAR CLK CLK fn VDD VDD GND VDD preamp_part22
+.GLOBAL GND
+.GLOBAL VDD
+.ends
+
+.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[5] io_analog[6] io_analog[7] io_analog[8]
++ io_analog[9] io_analog[4] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
++ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
++ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
++ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
++ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
++ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
++ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
++ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
++ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
++ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
++ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
++ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
++ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
++ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
++ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
++ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
++ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
++ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
++ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
++ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
++ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
++ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
++ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
++ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
++ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
++ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
++ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
++ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
++ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
++ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
++ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
++ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
++ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
++ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
++ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
++ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
++ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
++ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
++ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
++ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
++ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
++ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
++ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
++ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
++ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
++ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
++ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
++ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
++ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
++ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
++ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
++ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
++ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
++ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
++ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
++ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
++ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
++ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
++ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
++ vccd2 vdda1 vdda2 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] wbs_adr_i[10]
++ wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15] wbs_adr_i[16]
++ wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20] wbs_adr_i[21]
++ wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26] wbs_adr_i[27]
++ wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31] wbs_adr_i[3]
++ wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9] wbs_cyc_i
++ wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i vccd1 vssa1
+Xsky130_fd_pr__diode_pw2nd_05v5_3P6M5Y_0 io_analog[7] vssa1 sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y
+Xsky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0 vssa1 io_analog[7] vccd1 sky130_fd_pr__diode_pd2nw_05v5_G4XDRY
+Xsky130_fd_sc_hd__buf_2_0 comparator_v6_0/Outn vssa1 vccd1 L1 vssa1 vccd1 sky130_fd_sc_hd__buf_2
+Xsky130_fd_sc_hd__buf_16_0 L1 vssa1 vccd1 io_analog[3] vssa1 vccd1 sky130_fd_sc_hd__buf_16
+Xsky130_fd_sc_hd__buf_16_1 L2 vssa1 vccd1 io_analog[2] vssa1 vccd1 sky130_fd_sc_hd__buf_16
+Xsky130_fd_sc_hd__buf_2_1 comparator_v6_0/Outp vssa1 vccd1 L2 vssa1 vccd1 sky130_fd_sc_hd__buf_2
+Xsky130_fd_sc_hd__buf_16_2 sky130_fd_sc_hd__buf_2_3/X vssa1 vccd1 comparator_v6_0/CLKBAR
++ vssa1 vccd1 sky130_fd_sc_hd__buf_16
+Xsky130_fd_sc_hd__buf_2_2 io_analog[8] vssa1 vccd1 sky130_fd_sc_hd__buf_2_2/X vssa1
++ vccd1 sky130_fd_sc_hd__buf_2
+Xsky130_fd_sc_hd__buf_16_3 sky130_fd_sc_hd__buf_2_2/X vssa1 vccd1 comparator_v6_0/CLK
++ vssa1 vccd1 sky130_fd_sc_hd__buf_16
+Xsky130_fd_sc_hd__buf_2_3 io_analog[7] vssa1 vccd1 sky130_fd_sc_hd__buf_2_3/X vssa1
++ vccd1 sky130_fd_sc_hd__buf_2
+Xsky130_fd_sc_hd__buf_16_4 sky130_fd_sc_hd__buf_2_4/X vssa1 vccd1 io_analog[0] vssa1
++ vccd1 sky130_fd_sc_hd__buf_16
+Xsky130_fd_sc_hd__buf_2_4 io_analog[1] vssa1 vccd1 sky130_fd_sc_hd__buf_2_4/X vssa1
++ vccd1 sky130_fd_sc_hd__buf_2
+Xcomparator_v6_0 comparator_v6_0/Outn io_analog[5] io_analog[6] comparator_v6_0/CLK
++ vccd1 vssa1 comparator_v6_0/Outp comparator_v6_0/CLKBAR comparator_v6
+R0 vccd1 io_clamp_high[1] 0.000000
+R1 vccd1 io_clamp_high[2] 0.000000
+R2 vssa1 io_clamp_low[2] 0.000000
+D0 vssa1 io_analog[8] sky130_fd_pr__diode_pw2nd_05v5 pj=4e+06u area=1e+12p
+D1 io_analog[8] vccd1 sky130_fd_pr__diode_pd2nw_05v5 pj=4e+06u area=1e+12p
+R3 vssa1 io_clamp_low[1] 0.000000
+C0 io_analog[6] vccd1 523.50fF
+C1 io_analog[5] sky130_fd_sc_hd__buf_2_3/X 75.68fF
+C2 io_analog[6] comparator_v6_0/CLK 2.17fF
+C3 comparator_v6_0/CLKBAR io_analog[5] 2.23fF
+C4 vccd1 L1 66.26fF
+C5 L2 vccd1 66.14fF
+C6 m4_165510_677212# io_analog[6] 766.31fF
+C7 vccd1 sky130_fd_sc_hd__buf_2_2/X 4.31fF
+C8 vccd1 io_analog[0] 65.54fF
+C9 vccd1 comparator_v6_0/Outn 9.36fF
+C10 io_analog[5] vccd1 573.17fF
+C11 sky130_fd_sc_hd__buf_2_3/X vccd1 131.01fF
+C12 m4_165510_677212# vccd1 30.18fF
+C13 io_analog[3] vccd1 34.41fF
+C14 io_analog[4] vssa1 25.05fF
+C15 vssd2 vssa1 13.04fF
+C16 vssd1 vssa1 13.62fF
+C17 vdda2 vssa1 13.04fF
+C18 vdda1 vssa1 26.08fF
+C19 vssa2 vssa1 13.04fF
+C20 vccd2 vssa1 13.04fF
+C21 io_analog[10] vssa1 6.83fF
+C22 io_clamp_high[0] vssa1 3.58fF
+C23 io_clamp_low[0] vssa1 3.58fF
+C24 io_analog[9] vssa1 6.83fF
+C25 m4_141154_541976# vssa1 136.63fF **FLOATING
+C26 m4_165510_677212# vssa1 110.87fF **FLOATING
+C27 li_73093_686955# vssa1 2.20fF **FLOATING
+C28 io_analog[3] vssa1 26.43fF
+C29 vccd1 vssa1 2923.93fF
+C30 comparator_v6_0/Outp vssa1 26.62fF
+C31 comparator_v6_0/Outn vssa1 19.87fF
+C32 comparator_v6_0/CLK vssa1 17.79fF
+C33 comparator_v6_0/fp vssa1 2.32fF
+C34 comparator_v6_0/fn vssa1 2.31fF
+C35 io_analog[5] vssa1 337.44fF
+C36 io_analog[6] vssa1 234.19fF
+C37 comparator_v6_0/Dp vssa1 3.53fF
+C38 comparator_v6_0/Dn vssa1 3.23fF
+C39 comparator_v6_0/CLKBAR vssa1 7.21fF
+C40 io_analog[1] vssa1 397.14fF
+C41 io_analog[0] vssa1 35.98fF
+C42 io_analog[7] vssa1 63.99fF
+C43 sky130_fd_sc_hd__buf_2_2/X vssa1 354.67fF
+C44 io_analog[8] vssa1 68.96fF
+C45 sky130_fd_sc_hd__buf_2_3/X vssa1 303.55fF
+C46 L2 vssa1 190.71fF
+C47 io_analog[2] vssa1 25.67fF
+C48 L1 vssa1 195.71fF
+C49 sky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0/li_n340_n340# vssa1 2.20fF **FLOATING
+.ends
+
diff --git a/netgen/run_lvs_por.sh b/netgen/run_lvs_por.sh
new file mode 100755
index 0000000..80db2e7
--- /dev/null
+++ b/netgen/run_lvs_por.sh
@@ -0,0 +1,24 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#--------------------------------------------------------------------------------
+# Run LVS on the example_por layout
+#
+# NOTE: By specifying the testbench for the schematic-side netlist, the proper
+# includes used by the testbench simulation are picked up. Otherwise, the LVS
+# itself compares just the simple_por subcircuit from the testbench.
+#--------------------------------------------------------------------------------
+netgen -batch lvs "example_por.spice comparator_v6" "../xschem/comparator_lvs.spice comparator" /usr/local/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl comp.out
diff --git a/netgen/run_lvs_wrapper_verilog.sh b/netgen/run_lvs_wrapper_verilog.sh
new file mode 100755
index 0000000..f093ac3
--- /dev/null
+++ b/netgen/run_lvs_wrapper_verilog.sh
@@ -0,0 +1,22 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#--------------------------------------------------------------------------------
+# Run LVS on the user_analog_project_wrapper layout, comparing against the
+# top-level verilog module.
+#
+#--------------------------------------------------------------------------------
+netgen -batch lvs "user_analog_project_wrapper.spice user_analog_project_wrapper" "../verilog/rtl/user_analog_project_wrapper.v user_analog_project_wrapper" /usr/local/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl comp.out
diff --git a/netgen/run_lvs_wrapper_xschem.sh b/netgen/run_lvs_wrapper_xschem.sh
new file mode 100755
index 0000000..c741050
--- /dev/null
+++ b/netgen/run_lvs_wrapper_xschem.sh
@@ -0,0 +1,22 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#--------------------------------------------------------------------------------
+# Run LVS on the user_analog_project_wrapper layout, comparing against the
+# top-level xschem subcircuit from the wrapper testbench.
+#
+#--------------------------------------------------------------------------------
+netgen -batch lvs "user_analog_project_wrapper.spice user_analog_project_wrapper" "../xschem/analog_wrapper_tb.spice user_analog_project_wrapper" /usr/local/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl comp.out
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
new file mode 100644
index 0000000..7956138
--- /dev/null
+++ b/netgen/user_analog_project_wrapper.spice
@@ -0,0 +1,350 @@
+* SPICE3 file created from user_analog_project_wrapper.ext - technology: sky130A
+
+.subckt sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y a_n100_n100# w_n238_n238#
+D0 w_n238_n238# a_n100_n100# sky130_fd_pr__diode_pw2nd_05v5 pj=4e+06u area=1e+12p
+.ends
+
+.subckt sky130_fd_pr__diode_pd2nw_05v5_G4XDRY w_n376_n376# a_n100_n100# w_n238_n238#
+D0 a_n100_n100# w_n238_n238# sky130_fd_pr__diode_pd2nw_05v5 pj=4e+06u area=1e+12p
+
+.ends
+
+.subckt sky130_fd_sc_hd__buf_2 A VGND VPWR X VNB VPB
+X0 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=5.63e+11p pd=5.18e+06u as=2.7e+11p ps=2.54e+06u w=1e+06u l=150000u
+X1 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 VPWR A a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=1.664e+11p ps=1.8e+06u w=640000u l=150000u
+X3 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=1.755e+11p pd=1.84e+06u as=3.6625e+11p ps=3.78e+06u w=650000u l=150000u
+X4 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X5 VGND A a_27_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.092e+11p ps=1.36e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hd__buf_16 A VGND VPWR X VNB VPB
+X0 VGND A a_109_47# VNB sky130_fd_pr__nfet_01v8 ad=2.093e+12p pd=2.204e+07u as=5.265e+11p ps=5.52e+06u w=650000u l=150000u
+X1 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=2.16e+12p pd=2.032e+07u as=3.22e+12p ps=3.044e+07u w=1e+06u l=150000u
+X2 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.404e+12p ps=1.472e+07u w=650000u l=150000u
+X3 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X4 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X6 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_109_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=8.1e+11p pd=7.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 VPWR A a_109_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X11 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X12 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X13 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X14 a_109_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X17 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 VPWR A a_109_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 VGND A a_109_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X21 VGND A a_109_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X22 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X23 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X25 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X27 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X30 a_109_47# A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X31 a_109_47# A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X32 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X35 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X36 VPWR A a_109_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 X a_109_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 X a_109_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X39 a_109_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 VPWR a_109_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_109_47# A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+X43 VGND a_109_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
+
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_GJYUB2 a_207_n100# a_81_n126# a_n207_n128# a_15_n100#
++ a_n177_n100# a_111_n100# a_n15_n128# a_n111_n126# w_n305_n200# a_n81_n100# a_177_n128#
++ a_n269_n100# VSUBS
+X0 a_207_n100# a_177_n128# a_111_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=3.1e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_15_n100# a_n15_n128# a_n81_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_111_n100# a_81_n126# a_15_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n81_n100# a_n111_n126# a_n177_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_n177_n100# a_n207_n128# a_n269_n100# w_n305_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n15_n89# a_15_n69# VSUBS
+X0 a_15_n69# a_n15_n89# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u#0 sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89# sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n73_n69# VSUBS
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n73_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# VSUBS sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2#0 a_n139_n100# a_63_n100# a_33_n130# a_n33_n100# w_n319_n202# a_n63_n130#
++ VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n319_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n139_n100# w_n319_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W12 Vout Vin VDD GND pmos_2uf2_0/w_n319_n202# nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ VSUBS
+Xnmos_1u_0 Vin nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# GND VSUBS nmos_1u#0
+Xpmos_2uf2_0 VDD VDD Vin Vout pmos_2uf2_0/w_n319_n202# Vin VSUBS pmos_2uf2#0
+.ends
+
+.subckt latch_3 a_646_808# inv_W12_1/GND m1_686_734# w_n16_492# inv_W12_1/Vin VSUBS
++ inv_W12_0/Vin
+Xsky130_fd_pr__pfet_01v8_GJYUB2_0 m1_686_734# a_646_808# a_646_808# m1_686_734# m1_686_734#
++ inv_W12_1/VDD a_646_808# a_646_808# w_n16_492# inv_W12_1/VDD a_646_808# inv_W12_1/VDD
++ VSUBS sky130_fd_pr__pfet_01v8_GJYUB2
+Xinv_W12_0 inv_W12_1/Vin inv_W12_0/Vin inv_W12_1/VDD inv_W12_1/GND w_n16_492# inv_W12_1/Vin
++ VSUBS inv_W12
+Xinv_W12_1 inv_W12_0/Vin inv_W12_1/Vin inv_W12_1/VDD inv_W12_1/GND w_n16_492# inv_W12_0/Vin
++ VSUBS inv_W12
+
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_G6PLX8 a_n129_n500# a_63_n500# a_n221_n474# a_n33_n500#
++ a_n159_n522# a_159_n500# VSUBS
+X0 a_n33_n500# a_n159_n522# a_n129_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_159_n500# a_n159_n522# a_63_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_63_n500# a_n159_n522# a_n33_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n500# a_n159_n522# a_n221_n474# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_RFM3CD#0 a_n73_n100# w_n109_n162# a_15_n100# a_n15_n126#
++ VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# w_n109_n162# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#1 a_15_n500# a_n15_n526# a_n73_n500# VSUBS
+X0 a_15_n500# a_n15_n526# a_n73_n500# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_RURP52 a_33_n370# a_63_n348# a_n63_n370# a_n33_n348#
++ a_n125_n348# VSUBS
+X0 a_n33_n348# a_n63_n370# a_n125_n348# VSUBS sky130_fd_pr__nfet_01v8 ad=4.95e+11p pd=3.66e+06u as=4.65e+11p ps=3.62e+06u w=1.5e+06u l=150000u
+X1 a_63_n348# a_33_n370# a_n33_n348# VSUBS sky130_fd_pr__nfet_01v8 ad=4.65e+11p pd=3.62e+06u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8FHE5N a_n125_n439# a_63_n450# a_n63_n476# a_n33_n450#
++ a_33_n476# VSUBS
+X0 a_63_n450# a_33_n476# a_n33_n450# VSUBS sky130_fd_pr__nfet_01v8 ad=1.528e+11p pd=1.62e+06u as=1.65e+11p ps=1.66e+06u w=500000u l=150000u
+X1 a_n33_n450# a_n63_n476# a_n125_n439# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.528e+11p ps=1.62e+06u w=500000u l=150000u
+.ends
+
+.subckt preamp_part12 li_n720_1336# a_n72_236# a_80_n658# a_n434_n660# m1_n692_n210#
++ a_n506_870# a_388_n660# w_n720_994# li_n720_n474# a_414_256# a_706_862# li_954_n358#
++ VSUBS
+Xsky130_fd_pr__nfet_01v8_G6PLX8_0 a_414_256# a_414_256# m1_n128_n164# m1_n128_n164#
++ a_n434_n660# m1_n128_n164# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__nfet_01v8_G6PLX8_1 a_n72_236# a_n72_236# m1_338_n220# m1_338_n220#
++ a_388_n660# m1_338_n220# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 li_n720_1336# w_n720_994# a_414_256# a_n506_870#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 a_n72_236# w_n720_994# li_n720_1336# a_706_862#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 li_n720_n474# a_414_256# m1_n692_n210# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 li_954_n358# a_n72_236# li_n720_n474# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_RURP52_0 a_n72_236# li_n218_192# a_n72_236# m1_n128_n164#
++ li_n218_192# VSUBS sky130_fd_pr__nfet_01v8_RURP52
+Xsky130_fd_pr__nfet_01v8_RURP52_1 a_414_256# li_n218_192# a_414_256# m1_338_n220#
++ li_n218_192# VSUBS sky130_fd_pr__nfet_01v8_RURP52
+Xsky130_fd_pr__nfet_01v8_8FHE5N_0 li_n720_n474# li_n720_n474# a_80_n658# li_n218_192#
++ a_80_n658# VSUBS sky130_fd_pr__nfet_01v8_8FHE5N
+
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5E9B w_n161_n200# a_33_n126# a_63_n100# a_n125_n74#
++ a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n126# a_n33_n100# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n125_n74# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt SR_latch a_648_848# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ a_262_508# VDD w_0_524# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 a_648_848# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND a_262_508# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__pfet_01v8_AC5E9B_0 w_0_524# a_262_508# VDD VDD a_648_848# a_262_508#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+Xsky130_fd_pr__pfet_01v8_AC5E9B_1 w_0_524# a_648_848# VDD VDD a_262_508# a_648_848#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+.ends
+
+.subckt preamp_part22 w_78_306# a_392_716# sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#
++ sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126# sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n15_n126#
++ sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_n15_n126# a_810_594# li_116_1034# sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_15_n100#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n73_n100#
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_0 li_214_402# w_78_306# a_810_594# sky130_fd_pr__pfet_01v8_RFM3CD#0_0/a_n15_n126#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_1 a_392_716# w_78_306# li_1016_536# sky130_fd_pr__pfet_01v8_RFM3CD#0_1/a_n15_n126#
++ VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_2 sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n73_n100#
++ w_78_306# li_214_402# sky130_fd_pr__pfet_01v8_RFM3CD#0_2/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD#0_3 li_1016_536# w_78_306# sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_15_n100#
++ sky130_fd_pr__pfet_01v8_RFM3CD#0_3/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 li_214_402# w_78_306# li_116_1034# a_392_716# VSUBS
++ sky130_fd_pr__pfet_01v8_RFM3CD#0
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 li_116_1034# w_78_306# li_1016_536# a_810_594# VSUBS
++ sky130_fd_pr__pfet_01v8_RFM3CD#0
+
+.ends
+
+.subckt comparator_v6 Outn Vp Vn CLK VDD GND Outp CLKBAR
+Xlatch_3_0 CLKBAR GND VDD VDD Dp GND Dn latch_3
+Xpreamp_part12_0 VDD fp CLK Vn Dp CLK Vp VDD GND fn CLK Dn GND preamp_part12
+XSR_latch_0 Outp Dn Dp Outn VDD VDD GND GND SR_latch
+Xpreamp_part22_0 VDD fp CLKBAR CLKBAR CLK CLK fn VDD VDD GND VDD preamp_part22
+
+.ends
+
+.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[5] io_analog[6] io_analog[7] io_analog[8]
++ io_analog[9] io_analog[4] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
++ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
++ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
++ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
++ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
++ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
++ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
++ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
++ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
++ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
++ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
++ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
++ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
++ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
++ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
++ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
++ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
++ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
++ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
++ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
++ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
++ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
++ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
++ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
++ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
++ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
++ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
++ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
++ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
++ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
++ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
++ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
++ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
++ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
++ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
++ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
++ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
++ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
++ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
++ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
++ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
++ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
++ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
++ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
++ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
++ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
++ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
++ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
++ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
++ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
++ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
++ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
++ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
++ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
++ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
++ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
++ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
++ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
++ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
++ vccd2 vdda1 vdda2 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] wbs_adr_i[10]
++ wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15] wbs_adr_i[16]
++ wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20] wbs_adr_i[21]
++ wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26] wbs_adr_i[27]
++ wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31] wbs_adr_i[3]
++ wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9] wbs_cyc_i
++ wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i vccd1 vssa1
+Xsky130_fd_pr__diode_pw2nd_05v5_3P6M5Y_0 io_analog[7] vssa1 sky130_fd_pr__diode_pw2nd_05v5_3P6M5Y
+Xsky130_fd_pr__diode_pd2nw_05v5_G4XDRY_0 vssa1 io_analog[7] vccd1 sky130_fd_pr__diode_pd2nw_05v5_G4XDRY
+Xsky130_fd_sc_hd__buf_2_0 comparator_v6_0/Outn vssa1 vccd1 L1 vssa1 vccd1 sky130_fd_sc_hd__buf_2
+Xsky130_fd_sc_hd__buf_16_0 L1 vssa1 vccd1 io_analog[3] vssa1 vccd1 sky130_fd_sc_hd__buf_16
+Xsky130_fd_sc_hd__buf_16_1 L2 vssa1 vccd1 io_analog[2] vssa1 vccd1 sky130_fd_sc_hd__buf_16
+Xsky130_fd_sc_hd__buf_2_1 comparator_v6_0/Outp vssa1 vccd1 L2 vssa1 vccd1 sky130_fd_sc_hd__buf_2
+Xsky130_fd_sc_hd__buf_16_2 sky130_fd_sc_hd__buf_2_3/X vssa1 vccd1 comparator_v6_0/CLKBAR
++ vssa1 vccd1 sky130_fd_sc_hd__buf_16
+Xsky130_fd_sc_hd__buf_2_2 io_analog[8] vssa1 vccd1 sky130_fd_sc_hd__buf_2_2/X vssa1
++ vccd1 sky130_fd_sc_hd__buf_2
+Xsky130_fd_sc_hd__buf_16_3 sky130_fd_sc_hd__buf_2_2/X vssa1 vccd1 comparator_v6_0/CLK
++ vssa1 vccd1 sky130_fd_sc_hd__buf_16
+Xsky130_fd_sc_hd__buf_2_3 io_analog[7] vssa1 vccd1 sky130_fd_sc_hd__buf_2_3/X vssa1
++ vccd1 sky130_fd_sc_hd__buf_2
+Xsky130_fd_sc_hd__buf_16_4 sky130_fd_sc_hd__buf_2_4/X vssa1 vccd1 io_analog[0] vssa1
++ vccd1 sky130_fd_sc_hd__buf_16
+Xsky130_fd_sc_hd__buf_2_4 io_analog[1] vssa1 vccd1 sky130_fd_sc_hd__buf_2_4/X vssa1
++ vccd1 sky130_fd_sc_hd__buf_2
+Xcomparator_v6_0 comparator_v6_0/Outn io_analog[5] io_analog[6] comparator_v6_0/CLK
++ vccd1 vssa1 comparator_v6_0/Outp comparator_v6_0/CLKBAR comparator_v6
+V0 vccd1 io_clamp_high[1] 0.0
+V1 vccd1 io_clamp_high[2] 0.0
+V2 vssa1 io_clamp_low[2] 0.0
+
+V3 vssa1 io_clamp_low[1] 0.0
+
+D0 vssa1 io_analog[8] sky130_fd_pr__diode_pw2nd_05v5 pj=4e+06u area=1e+12p
+D1 io_analog[8] vccd1 sky130_fd_pr__diode_pd2nw_05v5 pj=4e+06u area=1e+12p
+
+
+.ends
+
diff --git a/openlane/.gitignore b/openlane/.gitignore
new file mode 100644
index 0000000..e4867d8
--- /dev/null
+++ b/openlane/.gitignore
@@ -0,0 +1,2 @@
+*/runs
+default.cvcrc
diff --git a/openlane/Makefile b/openlane/Makefile
new file mode 120000
index 0000000..48e5b4a
--- /dev/null
+++ b/openlane/Makefile
@@ -0,0 +1 @@
+../caravel/openlane/Makefile
\ No newline at end of file
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
new file mode 100644
index 0000000..a9c2027
--- /dev/null
+++ b/verilog/dv/Makefile
@@ -0,0 +1,39 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = mprj_por
+
+all: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ done
+
+DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
+$(DV_PATTERNS): verify-% :
+ cd $* && make
+
+clean: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make clean ) ; \
+ done
+ rm -rf *.log
+
+.PHONY: clean all
diff --git a/verilog/dv/README.md b/verilog/dv/README.md
new file mode 100644
index 0000000..6be9cd3
--- /dev/null
+++ b/verilog/dv/README.md
@@ -0,0 +1,131 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+
+# Simulation Environment Setup
+
+There are two options for setting up the simulation environment:
+
+* Pulling a pre-built docker image
+* Installing the dependecies locally
+
+## 1. Docker
+
+There is an available docker setup with the needed tools at [efabless/dockerized-verification-setup](https://github.com/efabless/dockerized-verification-setup)
+
+Run the following to pull the image:
+
+```
+docker pull efabless/dv_setup:latest
+```
+
+## 2. Local Installion (Linux)
+
+You will need to fullfil these dependecies:
+
+* Icarus Verilog (10.2+)
+* RV32I Toolchain
+
+Using apt, you can install Icarus Verilog:
+
+```bash
+sudo apt-get install iverilog
+```
+
+Next, you will need to build the RV32I toolchain. Firstly, export the installation path for the RV32I toolchain,
+
+```bash
+export GCC_PATH=<gcc-installation-path>
+```
+
+Then, run the following:
+
+```bash
+# packages needed:
+sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \
+ libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo \
+ gperf libtool patchutils bc zlib1g-dev git libexpat1-dev
+
+sudo mkdir $GCC_PATH
+sudo chown $USER $GCC_PATH
+
+git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i
+cd riscv-gnu-toolchain-rv32i
+git checkout 411d134
+git submodule update --init --recursive
+
+mkdir build; cd build
+../configure --with-arch=rv32i --prefix=$GCC_PATH
+make -j$(nproc)
+```
+
+# Running Simulation
+
+## Docker
+
+First, you will need to export a number of environment variables:
+
+```bash
+export PDK_PATH=<pdk-location/sky130A>
+export CARAVEL_ROOT=<caravel_root>
+export UPRJ_ROOT=<user_project_root>
+```
+
+Then, run the following command to start the docker container :
+
+```
+docker run -it -v $CARAVEL_ROOT:$CARAVEL_ROOT -v $PDK_PATH:$PDK_PATH -v $UPRJ_ROOT:$UPRJ_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -e PDK_PATH=$PDK_PATH -e UPRJ_ROOT=$UPRJ_ROOT -u $(id -u $USER):$(id -g $USER) efabless/dv_setup:latest
+```
+
+Then, navigate to the directory where the DV tests reside :
+
+```bash
+cd $UPRJ_ROOT/verilog/dv/
+```
+
+Then, follow the instructions at [Both](#both) to run RTL/GL simulation.
+
+## Local
+
+You will need to export these environment variables:
+
+```bash
+export GCC_PATH=<gcc-installation-path>
+export PDK_PATH=<pdk-location/sky130A>
+```
+
+Then, follow the instruction at [Both](#both) to run RTL/GL simulation.
+
+## Both
+
+To run RTL simulation for one of the DV tests,
+
+```bash
+cd <dv-test>
+make
+```
+
+To run gate level simulation for one of the DV tests,
+
+```bash
+cd <dv-test>
+SIM=GL make
+```
+
+# User Analog Project Example DV
+
+> :construction: Under construction :construction:
diff --git a/verilog/dv/mprj_por/Makefile b/verilog/dv/mprj_por/Makefile
new file mode 100644
index 0000000..5d0825f
--- /dev/null
+++ b/verilog/dv/mprj_por/Makefile
@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## PDK
+PDK_PATH = $(PDK_ROOT)/sky130A
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_BEHAVIOURAL_MODELS = ../
+
+## RISCV GCC
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+## Simulation mode: RTL/GL
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = mprj_por
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ $< -o $@
+else
+ iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/mprj_por/mprj_por.c b/verilog/dv/mprj_por/mprj_por.c
new file mode 100644
index 0000000..9a51fc5
--- /dev/null
+++ b/verilog/dv/mprj_por/mprj_por.c
@@ -0,0 +1,49 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+
+// --------------------------------------------------------
+
+void main()
+{
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2
+
+ reg_mprj_datal = 0x00000000;
+ reg_mprj_datah = 0x00000000;
+
+ // Configure mprj_io 10 and 25 as analog (digital in/out = off)
+ // Configure mprj_io 11, 12, 26, and 27 as digital output
+ // mprj_io 14 to 24 are analog pads and cannot be configured
+
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_ANALOG;
+
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_ANALOG;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ /* Block until end of test */
+ while (1);
+}
+
diff --git a/verilog/dv/mprj_por/mprj_por_tb.v b/verilog/dv/mprj_por/mprj_por_tb.v
new file mode 100644
index 0000000..39e4a36
--- /dev/null
+++ b/verilog/dv/mprj_por/mprj_por_tb.v
@@ -0,0 +1,170 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_analog_netlists.v"
+`include "caravan_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module mprj_por_tb;
+ // Signals declaration
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+ reg power3;
+
+ wire HIGH;
+ wire LOW;
+ wire TRI;
+ assign HIGH = 1'b1;
+ assign LOW = 1'b0;
+ assign TRI = 1'bz;
+
+ wire gpio;
+ wire uart_tx;
+ wire [37:0] mprj_io;
+ wire [3:0] checkbits;
+ wire [1:0] status;
+
+ // Signals Assignment
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ // Power supply for POR
+ assign mprj_io[18] = power3;
+
+ // Readback from POR (digital HV through analog pad connection)
+ assign status = {mprj_io[25], mprj_io[10]};
+
+ // Readback from POR (digital LV)
+ assign checkbits = {mprj_io[27:26], mprj_io[12:11]};
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("mprj_por.vcd");
+ $dumpvars(0, mprj_por_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (150) begin
+ repeat (1000) @(posedge clock);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ wait(status == 2'h1);
+ $display("Monitor: mprj_por test started");
+ #100;
+ if (checkbits != 4'h9) begin
+ $display("Monitor: mprj_por test failed");
+ $finish;
+ end
+ wait(status == 2'h3);
+ #100;
+ if (checkbits != 4'h5) begin
+ $display("Monitor: mprj_por test failed");
+ $finish;
+ end
+ $display("Monitor: mprj_por test Passed");
+ #10000;
+ $finish;
+ end
+
+ // Reset Operation
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ power3 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ #150000; // Need time to run the managment SoC setup.
+ power3 <= 1'b1; // Power up the 2nd POR.
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD3V3 = power1;
+ wire VDD1V8 = power2;
+ wire VSS = 1'b0;
+
+ caravan uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+
+ spiflash #(
+ .FILENAME("mprj_por.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ // Testbench UART
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/comparator.v b/verilog/rtl/comparator.v
new file mode 100644
index 0000000..9d691b6
--- /dev/null
+++ b/verilog/rtl/comparator.v
@@ -0,0 +1,37 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+`timescale 1 ns / 1 ps
+
+// This is just a copy of simple_por.v from the Caravel project, used
+// as an analog user project example.
+
+module comparator(
+`ifdef USE_POWER_PINS
+ inout VDD,
+ inout GND,
+`endif
+ input Vn,
+ input Vp,
+ input CLK,
+ input CLKBAR,
+ output Outn,
+ output Outp
+);
+
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/example_por.v b/verilog/rtl/example_por.v
new file mode 100644
index 0000000..d318fba
--- /dev/null
+++ b/verilog/rtl/example_por.v
@@ -0,0 +1,95 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+`timescale 1 ns / 1 ps
+
+// This is just a copy of simple_por.v from the Caravel project, used
+// as an analog user project example.
+
+module example_por(
+`ifdef USE_POWER_PINS
+ inout vdd3v3,
+ inout vdd1v8,
+ inout vss,
+`endif
+ output porb_h,
+ output porb_l,
+ output por_l
+);
+
+ wire mid, porb_h;
+ reg inode;
+
+ // This is a behavioral model! Actual circuit is a resitor dumping
+ // current (slowly) from vdd3v3 onto a capacitor, and this fed into
+ // two schmitt triggers for strong hysteresis/glitch tolerance.
+
+ initial begin
+ inode <= 1'b0;
+ end
+
+ // Emulate current source on capacitor as a 500ns delay either up or
+ // down. Note that this is sped way up for verilog simulation; the
+ // actual circuit is set to a 15ms delay.
+
+ always @(posedge vdd3v3) begin
+ #500 inode <= 1'b1;
+ end
+ always @(negedge vdd3v3) begin
+ #500 inode <= 1'b0;
+ end
+
+ // Instantiate two shmitt trigger buffers in series
+
+ sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VGND(vss),
+ .VPB(vdd3v3),
+ .VNB(vss),
+`endif
+ .A(inode),
+ .X(mid)
+ );
+
+ sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VGND(vss),
+ .VPB(vdd3v3),
+ .VNB(vss),
+`endif
+ .A(mid),
+ .X(porb_h)
+ );
+
+ sky130_fd_sc_hvl__lsbufhv2lv_1 porb_level (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VPB(vdd3v3),
+ .LVPWR(vdd1v8),
+ .VNB(vss),
+ .VGND(vss),
+`endif
+ .A(porb_h),
+ .X(porb_l)
+ );
+
+ // since this is behavioral anyway, but this should be
+ // replaced by a proper inverter
+ assign por_l = ~porb_l;
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/uprj_analog_netlists.v b/verilog/rtl/uprj_analog_netlists.v
new file mode 100644
index 0000000..062a873
--- /dev/null
+++ b/verilog/rtl/uprj_analog_netlists.v
@@ -0,0 +1,38 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+/*--------------------------------------------------------------*/
+/* caravel, a project harness for the Google/SkyWater sky130 */
+/* fabrication process and open source PDK */
+/* */
+/* Copyright 2020 efabless, Inc. */
+/* Written by Tim Edwards, December 2019 */
+/* and Mohamed Shalan, August 2020 */
+/* This file is open source hardware released under the */
+/* Apache 2.0 license. See file LICENSE. */
+/* */
+/*--------------------------------------------------------------*/
+
+`include "defines.v"
+`define USE_POWER_PINS
+
+`ifdef GL
+ `default_nettype wire
+ // Use behavorial model with gate-level simulation
+ `include "rtl/user_analog_project_wrapper.v"
+ `include "rtl/user_analog_proj_example.v"
+`else
+ `include "user_analog_project_wrapper.v"
+ `include "user_analog_proj_example.v"
+`endif
diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/user_analog_proj_example.v
new file mode 100644
index 0000000..9ee51f0
--- /dev/null
+++ b/verilog/rtl/user_analog_proj_example.v
@@ -0,0 +1,190 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`include "comparator.v"
+
+
+/*
+ * I/O mapping for analog
+ *
+ * mprj_io[37] io_in/out/oeb/in_3v3[26] --- ---
+ * mprj_io[36] io_in/out/oeb/in_3v3[25] --- ---
+ * mprj_io[35] io_in/out/oeb/in_3v3[24] gpio_analog/noesd[17] ---
+ * mprj_io[34] io_in/out/oeb/in_3v3[23] gpio_analog/noesd[16] ---
+ * mprj_io[33] io_in/out/oeb/in_3v3[22] gpio_analog/noesd[15] ---
+ * mprj_io[32] io_in/out/oeb/in_3v3[21] gpio_analog/noesd[14] ---
+ * mprj_io[31] io_in/out/oeb/in_3v3[20] gpio_analog/noesd[13] ---
+ * mprj_io[30] io_in/out/oeb/in_3v3[19] gpio_analog/noesd[12] ---
+ * mprj_io[29] io_in/out/oeb/in_3v3[18] gpio_analog/noesd[11] ---
+ * mprj_io[28] io_in/out/oeb/in_3v3[17] gpio_analog/noesd[10] ---
+ * mprj_io[27] io_in/out/oeb/in_3v3[16] gpio_analog/noesd[9] ---
+ * mprj_io[26] io_in/out/oeb/in_3v3[15] gpio_analog/noesd[8] ---
+ * mprj_io[25] io_in/out/oeb/in_3v3[14] gpio_analog/noesd[7] ---
+ * mprj_io[24] --- --- user_analog[10]
+ * mprj_io[23] --- --- user_analog[9]
+ * mprj_io[22] --- --- user_analog[8]
+ * mprj_io[21] --- --- user_analog[7]
+ * mprj_io[20] --- --- user_analog[6] clamp[2]
+ * mprj_io[19] --- --- user_analog[5] clamp[1]
+ * mprj_io[18] --- --- user_analog[4] clamp[0]
+ * mprj_io[17] --- --- user_analog[3]
+ * mprj_io[16] --- --- user_analog[2]
+ * mprj_io[15] --- --- user_analog[1]
+ * mprj_io[14] --- --- user_analog[0]
+ * mprj_io[13] io_in/out/oeb/in_3v3[13] gpio_analog/noesd[6] ---
+ * mprj_io[12] io_in/out/oeb/in_3v3[12] gpio_analog/noesd[5] ---
+ * mprj_io[11] io_in/out/oeb/in_3v3[11] gpio_analog/noesd[4] ---
+ * mprj_io[10] io_in/out/oeb/in_3v3[10] gpio_analog/noesd[3] ---
+ * mprj_io[9] io_in/out/oeb/in_3v3[9] gpio_analog/noesd[2] ---
+ * mprj_io[8] io_in/out/oeb/in_3v3[8] gpio_analog/noesd[1] ---
+ * mprj_io[7] io_in/out/oeb/in_3v3[7] gpio_analog/noesd[0] ---
+ * mprj_io[6] io_in/out/oeb/in_3v3[6] --- ---
+ * mprj_io[5] io_in/out/oeb/in_3v3[5] --- ---
+ * mprj_io[4] io_in/out/oeb/in_3v3[4] --- ---
+ * mprj_io[3] io_in/out/oeb/in_3v3[3] --- ---
+ * mprj_io[2] io_in/out/oeb/in_3v3[2] --- ---
+ * mprj_io[1] io_in/out/oeb/in_3v3[1] --- ---
+ * mprj_io[0] io_in/out/oeb/in_3v3[0] --- ---
+ *
+ */
+
+/*
+ *----------------------------------------------------------------
+ *
+ * user_analog_proj_example
+ *
+ * This is an example of a (trivially simple) analog user project,
+ * showing how the user project can connect to the I/O pads, both
+ * the digital pads, the analog connection on the digital pads,
+ * and the dedicated analog pins used as an additional power supply
+ * input, with a connected ESD clamp.
+ *
+ * See the testbench in directory "mprj_por" for the example
+ * program that drives this user project.
+ *
+ *----------------------------------------------------------------
+ */
+
+module user_analog_proj_example (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+ // GPIO-analog
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+ // Dedicated analog
+ inout [`ANALOG_PADS-1:0] io_analog,
+ inout [2:0] io_clamp_high,
+ inout [2:0] io_clamp_low,
+
+ // Clock
+ input user_clock2,
+
+ // IRQ
+ output [2:0] irq
+);
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;
+ wire [`ANALOG_PADS-1:0] io_analog;
+
+ // wire [31:0] rdata;
+ // wire [31:0] wdata;
+
+ // wire valid;
+ // wire [3:0] wstrb;
+ `ifdef USE_POWER_PINS
+
+ assign io_clamp_high[2:1] = vccd1;
+ assign io_clamp_low[2:1] = vssa1;
+ `endif
+ wire analog0, analog2, analog3, ;
+
+ // WB MI A
+ // assign valid = wbs_cyc_i && wbs_stb_i;
+ // assign wstrb = wbs_sel_i & {4{wbs_we_i}};
+ // assign wbs_dat_o = rdata;
+ // assign wdata = wbs_dat_i;
+
+ // IO --- unused (no need to connect to anything)
+ // assign io_out[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = 0;
+ // assign io_out[14:13] = 11'b0;
+ // assign io_out[10:0] = 11'b0;
+
+ // assign io_oeb[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = -1;
+ // assign io_oeb[14:13] = 11'b1;
+ // assign io_oeb[10:0] = 11'b1;
+
+ // IO --- enable outputs on 11, 12, 15, and 16
+ assign io_analog[2] = analog2;
+ assign io_analog[3] = analog3;
+ assign io_analog[5] = analog5;
+ assign io_analog[6] = analog6;
+ assign io_analog[7] = analog7;
+ assign io_analog[8] = analog8;
+
+
+ comparator comp1 (
+ `ifdef USE_POWER_PINS
+ .VDD(vccd1),
+ .GND(vssa1),
+ `endif
+ .Vp(analog5), // 3.3V domain output
+ .Vn(analog6), // 1.8V domain output
+ .CLK(analog8),
+ .CLKBAR(analog7),
+ .Outn(analog3),
+ .Outp(analog2) // 1.8V domain output
+ );
+
+
+endmodule
+
+`default_nettype wire
diff --git a/verilog/rtl/user_analog_project_wrapper.v b/verilog/rtl/user_analog_project_wrapper.v
new file mode 100644
index 0000000..7ee4c33
--- /dev/null
+++ b/verilog/rtl/user_analog_project_wrapper.v
@@ -0,0 +1,182 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+/*
+ *-------------------------------------------------------------
+ *
+ * user_analog_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user analog project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_analog_project_wrapper (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ /* GPIOs. There are 27 GPIOs, on either side of the analog.
+ * These have the following mapping to the GPIO padframe pins
+ * and memory-mapped registers, since the numbering remains the
+ * same as caravel but skips over the analog I/O:
+ *
+ * io_in/out/oeb/in_3v3 [26:14] <---> mprj_io[37:25]
+ * io_in/out/oeb/in_3v3 [13:0] <---> mprj_io[13:0]
+ *
+ * When the GPIOs are configured by the Management SoC for
+ * user use, they have three basic bidirectional controls:
+ * in, out, and oeb (output enable, sense inverted). For
+ * analog projects, a 3.3V copy of the signal input is
+ * available. out and oeb must be 1.8V signals.
+ */
+
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+ /* Analog (direct connection to GPIO pad---not for high voltage or
+ * high frequency use). The management SoC must turn off both
+ * input and output buffers on these GPIOs to allow analog access.
+ * These signals may drive a voltage up to the value of VDDIO
+ * (3.3V typical, 5.5V maximum).
+ *
+ * Note that analog I/O is not available on the 7 lowest-numbered
+ * GPIO pads, and so the analog_io indexing is offset from the
+ * GPIO indexing by 7, as follows:
+ *
+ * gpio_analog/noesd [17:7] <---> mprj_io[35:25]
+ * gpio_analog/noesd [6:0] <---> mprj_io[13:7]
+ *
+ */
+
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+ /* Analog signals, direct through to pad. These have no ESD at all,
+ * so ESD protection is the responsibility of the designer.
+ *
+ * user_analog[10:0] <---> mprj_io[24:14]
+ *
+ */
+ inout [`ANALOG_PADS-1:0] io_analog,
+
+ /* Additional power supply ESD clamps, one per analog pad. The
+ * high side should be connected to a 3.3-5.5V power supply.
+ * The low side should be connected to ground.
+ *
+ * clamp_high[2:0] <---> mprj_io[20:18]
+ * clamp_low[2:0] <---> mprj_io[20:18]
+ *
+ */
+ inout [2:0] io_clamp_high,
+ inout [2:0] io_clamp_low,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2,
+
+ // User maskable interrupt signals
+ output [2:0] user_irq
+);
+
+/*--------------------------------------*/
+/* User project is instantiated here */
+/*--------------------------------------*/
+
+user_analog_proj_example mprj (
+ `ifdef USE_POWER_PINS
+ .vdda1(vdda1), // User area 1 3.3V power
+ .vdda2(vdda2), // User area 2 3.3V power
+ .vssa1(vssa1), // User area 1 analog ground
+ .vssa2(vssa2), // User area 2 analog ground
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vccd2(vccd2), // User area 2 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+ .vssd2(vssd2), // User area 2 digital ground
+ `endif
+
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ // MGMT SoC Wishbone Slave
+
+ .wbs_cyc_i(wbs_cyc_i),
+ .wbs_stb_i(wbs_stb_i),
+ .wbs_we_i(wbs_we_i),
+ .wbs_sel_i(wbs_sel_i),
+ .wbs_adr_i(wbs_adr_i),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_ack_o(wbs_ack_o),
+ .wbs_dat_o(wbs_dat_o),
+
+ // Logic Analyzer
+
+ .la_data_in(la_data_in),
+ .la_data_out(la_data_out),
+ .la_oenb (la_oenb),
+
+ // IO Pads
+ .io_in (io_in),
+ .io_in_3v3 (io_in_3v3),
+ .io_out(io_out),
+ .io_oeb(io_oeb),
+
+ // GPIO-analog
+ .gpio_analog(gpio_analog),
+ .gpio_noesd(gpio_noesd),
+
+ // Dedicated analog
+ .io_analog(io_analog),
+ .io_clamp_high(vccd1),
+ .io_clamp_low(vssa1),
+
+ // Clock
+ .user_clock2(user_clock2),
+
+ // IRQ
+ .irq(user_irq)
+);
+
+endmodule // user_analog_project_wrapper
+
+`default_nettype wire
diff --git a/xschem/.spiceinit b/xschem/.spiceinit
new file mode 100644
index 0000000..6bc157f
--- /dev/null
+++ b/xschem/.spiceinit
@@ -0,0 +1 @@
+set ngbehavior=hs
diff --git a/xschem/SR_latch.sch b/xschem/SR_latch.sch
new file mode 100644
index 0000000..ac40ada
--- /dev/null
+++ b/xschem/SR_latch.sch
@@ -0,0 +1,126 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 190 -240 220 -240 {
+lab=Outn}
+N 310 -240 350 -240 {
+lab=#net1}
+N 150 -210 150 -130 {
+lab=#net1}
+N 390 -210 390 -130 {
+lab=Outn}
+N 150 -70 150 -50 {
+lab=VDD}
+N 150 -50 390 -50 {
+lab=VDD}
+N 390 -70 390 -50 {
+lab=VDD}
+N 150 -290 150 -270 {
+lab=VDD}
+N 150 -290 390 -290 {
+lab=VDD}
+N 390 -290 390 -270 {
+lab=VDD}
+N 120 -240 150 -240 {
+lab=VDD}
+N 120 -290 120 -240 {
+lab=VDD}
+N 120 -290 150 -290 {
+lab=VDD}
+N 390 -240 420 -240 {
+lab=VDD}
+N 420 -290 420 -240 {
+lab=VDD}
+N 390 -290 420 -290 {
+lab=VDD}
+N 80 -100 110 -100 {
+lab=S}
+N 430 -100 460 -100 {
+lab=R}
+N 220 -240 290 -170 {
+lab=Outn}
+N 290 -170 390 -170 {
+lab=Outn}
+N 220 -170 310 -240 {
+lab=#net1}
+N 150 -170 220 -170 {
+lab=#net1}
+N 150 -100 170 -100 {
+lab=VDD}
+N 170 -100 170 -50 {
+lab=VDD}
+N 370 -100 390 -100 {
+lab=VDD}
+N 370 -100 370 -50 {
+lab=VDD}
+N 230 -330 230 -290 {
+lab=VDD}
+N 270 -50 270 -30 {
+lab=VDD}
+C {sky130_fd_pr/nfet_01v8.sym} 410 -100 0 1 {name=M20
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 130 -100 0 0 {name=M21
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 370 -240 0 0 {name=M22
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 170 -240 0 1 {name=M23
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/opin.sym} 390 -170 0 0 {name=p7 lab=Outn}
+C {devices/ipin.sym} 80 -100 0 0 {name=p1 lab=S}
+C {devices/ipin.sym} 460 -100 2 0 {name=p2 lab=R}
+C {devices/iopin.sym} 230 -320 3 0 {name=p3 lab=VDD
+}
+C {devices/iopin.sym} 270 -40 1 0 {name=p4 lab=GND
+
+}
diff --git a/xschem/SR_latch.sym b/xschem/SR_latch.sym
new file mode 100644
index 0000000..d81ffd5
--- /dev/null
+++ b/xschem/SR_latch.sym
@@ -0,0 +1,33 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -30 -130 30 {}
+L 4 -40 -20 -20 -20 {}
+L 4 -150 10 -130 10 {}
+L 4 -150 -40 -130 -40 {}
+L 7 -90 -80 -90 -60 {}
+L 7 -90 30 -90 50 {}
+B 5 -92.5 -82.5 -87.5 -77.5 {name=VDD dir=inout }
+B 5 -22.5 -22.5 -17.5 -17.5 {name=Outn dir=out }
+B 5 -152.5 7.5 -147.5 12.5 {name=R dir=in }
+B 5 -152.5 -42.5 -147.5 -37.5 {name=S dir=in }
+B 5 -92.5 47.5 -87.5 52.5 {name=GND dir=inout }
+T {@symname} -134 -16 0 0 0.3 0.3 {}
+T {@name} -105 -42 0 0 0.2 0.2 {}
+T {VDD} -114 -95 3 1 0.2 0.2 {}
+T {Outn} -5 -44 0 1 0.2 0.2 {}
+T {R} -125 6 0 0 0.2 0.2 {}
+T {S} -125 -44 0 0 0.2 0.2 {}
+T {GND} -96 65 1 1 0.2 0.2 {}
+N -130 -60 -130 -30 {}
+N -130 30 -60 30 {}
+N -40 -60 -40 30 {}
+N -130 -60 -60 -60 {}
+N -60 -60 -40 -60 {}
+N -60 30 -40 30 {}
diff --git a/xschem/analog_wrapper_tb.sch b/xschem/analog_wrapper_tb.sch
new file mode 100644
index 0000000..8a6deea
--- /dev/null
+++ b/xschem/analog_wrapper_tb.sch
@@ -0,0 +1,234 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 800 -820 800 -800 {
+lab=GND}
+N 800 -910 800 -880 {
+lab=VDD}
+N 1010 -710 1010 -690 {
+lab=io_analog[5]}
+N 1010 -790 1010 -770 {
+lab=io_analog[6]}
+N 1010 -690 1100 -690 {
+lab=io_analog[5]}
+N 1100 -690 1100 -670 {
+lab=io_analog[5]}
+N 1100 -610 1100 -590 {
+lab=GND}
+N 1100 -690 1170 -690 {
+lab=io_analog[5]}
+N 1170 -790 1170 -690 {
+lab=io_analog[5]}
+N 910 -1020 910 -990 {
+lab=io_analog[8]}
+N 800 -650 800 -630 {
+lab=GND}
+N 800 -740 800 -710 {
+lab=io_analog[7]}
+N 910 -930 910 -900 {
+lab=GND}
+N 1330 -710 1330 -670 {
+lab=GND}
+N 1330 -810 1330 -770 {
+lab=GND}
+N 1490 -1210 1540 -1210 {
+lab=#net1}
+N 1490 -1190 1540 -1190 {
+lab=#net2}
+N 1490 -1170 1540 -1170 {
+lab=GND}
+N 1490 -1150 1540 -1150 {
+lab=#net3}
+N 1490 -1130 1540 -1130 {
+lab=VDD}
+N 1490 -1110 1540 -1110 {
+lab=#net4}
+N 1490 -1090 1540 -1090 {
+lab=#net5}
+N 1490 -1070 1540 -1070 {
+lab=#net6}
+N 1490 -1050 1540 -1050 {
+lab=#net7}
+N 1490 -1030 1540 -1030 {
+lab=#net8}
+N 1490 -1010 1540 -1010 {
+lab=#net9}
+N 1490 -990 1540 -990 {
+lab=#net10}
+N 1490 -970 1540 -970 {
+lab=#net11}
+N 1490 -950 1540 -950 {
+lab=#net12}
+N 1490 -930 1540 -930 {
+lab=#net13}
+N 1490 -910 1540 -910 {
+lab=io_analog[10:0]}
+N 1490 -890 1540 -890 {
+lab=#net14}
+N 1490 -870 1540 -870 {
+lab=#net15}
+N 1490 -850 1540 -850 {
+lab=#net16}
+N 1840 -1210 1890 -1210 {
+lab=#net17}
+N 1840 -1190 1890 -1190 {
+lab=#net18}
+N 1840 -1170 1890 -1170 {
+lab=#net19}
+N 1840 -1150 1890 -1150 {
+lab=#net20}
+N 1840 -1130 1890 -1130 {
+lab=#net21}
+N 1840 -1110 1890 -1110 {
+lab=#net22}
+N 1840 -1090 1890 -1090 {
+lab=#net23}
+N 1840 -1070 1890 -1070 {
+lab=#net24}
+N 1840 -1050 1890 -1050 {
+lab=#net25}
+N 1840 -1030 1890 -1030 {
+lab=#net26}
+N 1840 -1010 1890 -1010 {
+lab=#net27}
+N 1840 -990 1890 -990 {
+lab=#net28}
+N 1840 -970 1890 -970 {
+lab=#net29}
+N 2030 -990 2030 -950 {
+lab=GND}
+N 2130 -990 2130 -940 {
+lab=GND}
+N 2030 -1120 2030 -1050 {
+lab=io_analog[3]}
+N 2130 -1120 2130 -1050 {
+lab=io_analog[2]}
+N 4680 -450 4680 -430 {
+lab=vccd1}
+N 4680 -370 4680 -340 {
+lab=#net7}
+N 4680 -120 4680 -110 {
+lab=vssa1}
+N 4680 -200 4680 -180 {
+lab=#net8}
+N 4680 -280 4680 -260 {
+lab=#net9}
+N 4910 -420 4910 -410 {
+lab=vccd1}
+N 4910 -350 4910 -330 {
+lab=#net10}
+N 4910 -270 4910 -250 {
+lab=#net11}
+N 4910 -190 4910 -160 {
+lab=#net12}
+N 4910 -100 4910 -80 {
+lab=vssa1}
+C {devices/TT_models.sym} 950 -1180 0 0 {name=TT_MODELS
+only_toplevel=true
+format="tcleval( @value )"
+value="
+** opencircuitdesign pdks install
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+"
+spice_ignore=falsename=s1 only_toplevel=false value=blabla}
+C {devices/vsource.sym} 800 -850 0 0 {name=Vdd value=1.8}
+C {devices/vsource.sym} 1010 -740 0 0 {name=Vn value="pulse(-10m 10m 1ps 1ps 1ps 4ns 8ns)"}
+C {devices/lab_pin.sym} 1010 -790 0 0 {name=l24 sig_type=std_logic lab=io_analog[6]}
+C {devices/vsource.sym} 1100 -640 0 0 {name=Vcm value=1.2}
+C {devices/lab_pin.sym} 1170 -790 2 0 {name=l25 sig_type=std_logic lab=io_analog[5]}
+C {devices/code_shown.sym} 2030 -770 0 0 {name=SPICE only_toplevel=false value=".control
+save ALL @m.x1.x1.xm3.msky130_fd_pr__nfet_01v8[id]
+tran 0.01n 10n
+write analogwrapper_tb.raw
+set filetype=ascii
+run
+meas tran area INTEG @m.x1.x1.xm3.msky130_fd_pr__nfet_01v8[id] from=0 to=4ns
+let ecbit = area*1.8
+let vdiff= v(op)
+meas tran delaytime WHEN vdiff = 0.9 FALL=LAST
+meas tran clk WHEN v(clk) = 0.9 RISE=2
+let clkdelay=clk-6ns
+#meas tran tdiff TRIG AT=2ns TARG vdiff VAL=0.9 CROSS=1
+let compdelay=delaytime-6ns-clkdelay-0.385ns
+let tdelay=delaytime-6ns
+write output_comptran.txt delaytime clkdelay tdelay
+print clkdelay tdelay compdelay ecbit
+.endc
+"}
+C {devices/vsource.sym} 910 -960 0 0 {name=V1 value="pulse(1.8 0 1ps 1ps 1ps 2ns 4ns)"}
+C {devices/lab_pin.sym} 910 -1020 0 0 {name=l22 sig_type=std_logic lab=io_analog[8]}
+C {devices/vsource.sym} 800 -680 0 0 {name=V2 value="pulse(0 1.8 1ps 1ps 1ps 2ns 4ns)"}
+C {devices/lab_pin.sym} 800 -740 0 0 {name=l27 sig_type=std_logic lab=io_analog[7]}
+C {devices/gnd.sym} 1330 -670 0 0 {name=l3 lab=GND}
+C {devices/lab_pin.sym} 1330 -810 2 0 {name=l4 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 1100 -590 2 0 {name=l5 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 800 -630 2 0 {name=l6 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 800 -800 2 0 {name=l7 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 910 -900 2 0 {name=l8 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 800 -910 0 0 {name=l9 sig_type=std_logic lab=VDD}
+C {devices/res.sym} 1330 -740 0 0 {name=R1
+value=0
+footprint=1206
+device=resistor
+m=1}
+C {user_analog_project_wrapper.sym} 1690 -1030 0 1 {name=x1}
+C {devices/lab_pin.sym} 1490 -1130 0 0 {name=l1 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 1490 -1170 0 0 {name=l2 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 2030 -1120 1 0 {name=l12 sig_type=std_logic lab=io_analog[3]}
+C {devices/lab_pin.sym} 2130 -1120 1 0 {name=l13 sig_type=std_logic lab=io_analog[2]}
+C {devices/capa.sym} 2030 -1020 0 0 {name=C1
+m=1
+value=0.1p
+footprint=1206
+device="ceramic capacitor"}
+C {devices/capa.sym} 2130 -1020 0 0 {name=C2
+m=1
+value=0.1p
+footprint=1206
+device="ceramic capacitor"}
+C {devices/lab_pin.sym} 2030 -950 0 0 {name=l10 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 2130 -940 0 0 {name=l11 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 1490 -910 0 0 {name=l14 sig_type=std_logic lab=io_analog[10:0]}
+C {devices/lab_pin.sym} 3880 150 0 0 {name=l15 sig_type=std_logic lab=io_analog[5]}
+C {sky130_fd_pr/diode.sym} 4680 -310 0 0 {name=D9
+model=diode_pd2nw_05v5
+area=1e12
+}
+C {sky130_fd_pr/diode.sym} 4680 -230 0 0 {name=D10
+model=diode_pw2nd_05v5
+area=1e12
+}
+C {devices/lab_pin.sym} 4680 -110 3 0 {name=l31 sig_type=std_logic lab=vssa1
+}
+C {devices/lab_pin.sym} 4680 -450 2 0 {name=l32 sig_type=std_logic lab=vccd1}
+C {sky130_fd_pr/diode.sym} 4680 -400 0 0 {name=D11
+model=diode_pd2nw_05v5
+area=1e12
+}
+C {sky130_fd_pr/diode.sym} 4680 -150 0 0 {name=D12
+model=diode_pw2nd_05v5
+area=1e12
+}
+C {sky130_fd_pr/diode.sym} 4910 -220 2 0 {name=D13
+model=diode_pd2nw_05v5
+area=1e12
+}
+C {sky130_fd_pr/diode.sym} 4910 -300 2 0 {name=D14
+model=diode_pw2nd_05v5
+area=1e12
+}
+C {devices/lab_pin.sym} 4910 -80 0 0 {name=l33 sig_type=std_logic lab=vssa1
+}
+C {devices/lab_pin.sym} 4910 -420 0 0 {name=l34 sig_type=std_logic lab=vccd1}
+C {sky130_fd_pr/diode.sym} 4910 -130 2 0 {name=D15
+model=diode_pd2nw_05v5
+area=1e12
+}
+C {sky130_fd_pr/diode.sym} 4910 -380 2 0 {name=D16
+model=diode_pw2nd_05v5
+area=1e12
+}
diff --git a/xschem/analog_wrapper_tb.spice b/xschem/analog_wrapper_tb.spice
new file mode 100644
index 0000000..d40d69b
--- /dev/null
+++ b/xschem/analog_wrapper_tb.spice
@@ -0,0 +1,348 @@
+** sch_path: /home/krishna/Documents/Comparator_MPW6/xschem/analog_wrapper_tb.sch
+**.subckt analog_wrapper_tb
+Vdd VDD GND 1.8
+Vn io_analog[6] io_analog[5] pulse(-10m 10m 1ps 1ps 1ps 4ns 8ns)
+Vcm io_analog[5] GND 1.2
+V1 io_analog[8] GND pulse(1.8 0 1ps 1ps 1ps 2ns 4ns)
+V2 io_analog[7] GND pulse(0 1.8 1ps 1ps 1ps 2ns 4ns)
+R1 GND GND 0 m=1
+x1 net1 net2 GND net3 VDD net4 net5 net6 net17 net18 net19 net20 net21 net22[3] net22[2] net22[1]
++ net22[0] net23[31] net23[30] net23[29] net23[28] net23[27] net23[26] net23[25] net23[24] net23[23] net23[22]
++ net23[21] net23[20] net23[19] net23[18] net23[17] net23[16] net23[15] net23[14] net23[13] net23[12] net23[11]
++ net23[10] net23[9] net23[8] net23[7] net23[6] net23[5] net23[4] net23[3] net23[2] net23[1] net23[0] net24[31]
++ net24[30] net24[29] net24[28] net24[27] net24[26] net24[25] net24[24] net24[23] net24[22] net24[21] net24[20]
++ net24[19] net24[18] net24[17] net24[16] net24[15] net24[14] net24[13] net24[12] net24[11] net24[10] net24[9]
++ net24[8] net24[7] net24[6] net24[5] net24[4] net24[3] net24[2] net24[1] net24[0] net7 net8[31] net8[30]
++ net8[29] net8[28] net8[27] net8[26] net8[25] net8[24] net8[23] net8[22] net8[21] net8[20] net8[19] net8[18]
++ net8[17] net8[16] net8[15] net8[14] net8[13] net8[12] net8[11] net8[10] net8[9] net8[8] net8[7] net8[6]
++ net8[5] net8[4] net8[3] net8[2] net8[1] net8[0] net25[127] net25[126] net25[125] net25[124] net25[123]
++ net25[122] net25[121] net25[120] net25[119] net25[118] net25[117] net25[116] net25[115] net25[114] net25[113]
++ net25[112] net25[111] net25[110] net25[109] net25[108] net25[107] net25[106] net25[105] net25[104] net25[103]
++ net25[102] net25[101] net25[100] net25[99] net25[98] net25[97] net25[96] net25[95] net25[94] net25[93]
++ net25[92] net25[91] net25[90] net25[89] net25[88] net25[87] net25[86] net25[85] net25[84] net25[83] net25[82]
++ net25[81] net25[80] net25[79] net25[78] net25[77] net25[76] net25[75] net25[74] net25[73] net25[72] net25[71]
++ net25[70] net25[69] net25[68] net25[67] net25[66] net25[65] net25[64] net25[63] net25[62] net25[61] net25[60]
++ net25[59] net25[58] net25[57] net25[56] net25[55] net25[54] net25[53] net25[52] net25[51] net25[50] net25[49]
++ net25[48] net25[47] net25[46] net25[45] net25[44] net25[43] net25[42] net25[41] net25[40] net25[39] net25[38]
++ net25[37] net25[36] net25[35] net25[34] net25[33] net25[32] net25[31] net25[30] net25[29] net25[28] net25[27]
++ net25[26] net25[25] net25[24] net25[23] net25[22] net25[21] net25[20] net25[19] net25[18] net25[17] net25[16]
++ net25[15] net25[14] net25[13] net25[12] net25[11] net25[10] net25[9] net25[8] net25[7] net25[6] net25[5]
++ net25[4] net25[3] net25[2] net25[1] net25[0] net9[127] net9[126] net9[125] net9[124] net9[123] net9[122]
++ net9[121] net9[120] net9[119] net9[118] net9[117] net9[116] net9[115] net9[114] net9[113] net9[112] net9[111]
++ net9[110] net9[109] net9[108] net9[107] net9[106] net9[105] net9[104] net9[103] net9[102] net9[101] net9[100]
++ net9[99] net9[98] net9[97] net9[96] net9[95] net9[94] net9[93] net9[92] net9[91] net9[90] net9[89] net9[88]
++ net9[87] net9[86] net9[85] net9[84] net9[83] net9[82] net9[81] net9[80] net9[79] net9[78] net9[77] net9[76]
++ net9[75] net9[74] net9[73] net9[72] net9[71] net9[70] net9[69] net9[68] net9[67] net9[66] net9[65] net9[64]
++ net9[63] net9[62] net9[61] net9[60] net9[59] net9[58] net9[57] net9[56] net9[55] net9[54] net9[53] net9[52]
++ net9[51] net9[50] net9[49] net9[48] net9[47] net9[46] net9[45] net9[44] net9[43] net9[42] net9[41] net9[40]
++ net9[39] net9[38] net9[37] net9[36] net9[35] net9[34] net9[33] net9[32] net9[31] net9[30] net9[29] net9[28]
++ net9[27] net9[26] net9[25] net9[24] net9[23] net9[22] net9[21] net9[20] net9[19] net9[18] net9[17] net9[16]
++ net9[15] net9[14] net9[13] net9[12] net9[11] net9[10] net9[9] net9[8] net9[7] net9[6] net9[5] net9[4]
++ net9[3] net9[2] net9[1] net9[0] net26[127] net26[126] net26[125] net26[124] net26[123] net26[122]
++ net26[121] net26[120] net26[119] net26[118] net26[117] net26[116] net26[115] net26[114] net26[113] net26[112]
++ net26[111] net26[110] net26[109] net26[108] net26[107] net26[106] net26[105] net26[104] net26[103] net26[102]
++ net26[101] net26[100] net26[99] net26[98] net26[97] net26[96] net26[95] net26[94] net26[93] net26[92]
++ net26[91] net26[90] net26[89] net26[88] net26[87] net26[86] net26[85] net26[84] net26[83] net26[82] net26[81]
++ net26[80] net26[79] net26[78] net26[77] net26[76] net26[75] net26[74] net26[73] net26[72] net26[71] net26[70]
++ net26[69] net26[68] net26[67] net26[66] net26[65] net26[64] net26[63] net26[62] net26[61] net26[60] net26[59]
++ net26[58] net26[57] net26[56] net26[55] net26[54] net26[53] net26[52] net26[51] net26[50] net26[49] net26[48]
++ net26[47] net26[46] net26[45] net26[44] net26[43] net26[42] net26[41] net26[40] net26[39] net26[38] net26[37]
++ net26[36] net26[35] net26[34] net26[33] net26[32] net26[31] net26[30] net26[29] net26[28] net26[27] net26[26]
++ net26[25] net26[24] net26[23] net26[22] net26[21] net26[20] net26[19] net26[18] net26[17] net26[16] net26[15]
++ net26[14] net26[13] net26[12] net26[11] net26[10] net26[9] net26[8] net26[7] net26[6] net26[5] net26[4]
++ net26[3] net26[2] net26[1] net26[0] net27[26] net27[25] net27[24] net27[23] net27[22] net27[21] net27[20]
++ net27[19] net27[18] net27[17] net27[16] net27[15] net27[14] net27[13] net27[12] net27[11] net27[10] net27[9]
++ net27[8] net27[7] net27[6] net27[5] net27[4] net27[3] net27[2] net27[1] net27[0] net28[26] net28[25]
++ net28[24] net28[23] net28[22] net28[21] net28[20] net28[19] net28[18] net28[17] net28[16] net28[15] net28[14]
++ net28[13] net28[12] net28[11] net28[10] net28[9] net28[8] net28[7] net28[6] net28[5] net28[4] net28[3]
++ net28[2] net28[1] net28[0] net10[26] net10[25] net10[24] net10[23] net10[22] net10[21] net10[20] net10[19]
++ net10[18] net10[17] net10[16] net10[15] net10[14] net10[13] net10[12] net10[11] net10[10] net10[9] net10[8]
++ net10[7] net10[6] net10[5] net10[4] net10[3] net10[2] net10[1] net10[0] net11[26] net11[25] net11[24]
++ net11[23] net11[22] net11[21] net11[20] net11[19] net11[18] net11[17] net11[16] net11[15] net11[14] net11[13]
++ net11[12] net11[11] net11[10] net11[9] net11[8] net11[7] net11[6] net11[5] net11[4] net11[3] net11[2]
++ net11[1] net11[0] net12[17] net12[16] net12[15] net12[14] net12[13] net12[12] net12[11] net12[10] net12[9]
++ net12[8] net12[7] net12[6] net12[5] net12[4] net12[3] net12[2] net12[1] net12[0] net13[17] net13[16]
++ net13[15] net13[14] net13[13] net13[12] net13[11] net13[10] net13[9] net13[8] net13[7] net13[6] net13[5]
++ net13[4] net13[3] net13[2] net13[1] net13[0] io_analog[10] io_analog[9] io_analog[8] io_analog[7]
++ io_analog[6] io_analog[5] io_analog[4] io_analog[3] io_analog[2] io_analog[1] io_analog[0] net14[2] net14[1]
++ net14[0] net15[2] net15[1] net15[0] net29 net16[2] net16[1] net16[0] user_analog_project_wrapper
+C1 io_analog[3] GND 0.1p m=1
+C2 io_analog[2] GND 0.1p m=1
+
+**** begin user architecture code
+
+** opencircuitdesign pdks install
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+
+
+.control
+save ALL @m.x1.x1.xm3.msky130_fd_pr__nfet_01v8[id]
+tran 0.01n 10n
+write analogwrapper_tb.raw
+set filetype=ascii
+run
+meas tran area INTEG @m.x1.x1.xm3.msky130_fd_pr__nfet_01v8[id] from=0 to=4ns
+let ecbit = area*1.8
+let vdiff= v(op)
+meas tran delaytime WHEN vdiff = 0.9 FALL=LAST
+meas tran clk WHEN v(clk) = 0.9 RISE=2
+let clkdelay=clk-6ns
+#meas tran tdiff TRIG AT=2ns TARG vdiff VAL=0.9 CROSS=1
+let compdelay=delaytime-6ns-clkdelay-0.385ns
+let tdelay=delaytime-6ns
+write output_comptran.txt delaytime clkdelay tdelay
+print clkdelay tdelay compdelay ecbit
+.endc
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: user_analog_project_wrapper.sym # of pins=32
+** sym_path: /home/krishna/Documents/Comparator_MPW6/xschem/user_analog_project_wrapper.sym
+** sch_path: /home/krishna/Documents/Comparator_MPW6/xschem/user_analog_project_wrapper.sch
+.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2 wb_clk_i
++ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3] wbs_sel_i[2] wbs_sel_i[1] wbs_sel_i[0] wbs_dat_i[31]
++ wbs_dat_i[30] wbs_dat_i[29] wbs_dat_i[28] wbs_dat_i[27] wbs_dat_i[26] wbs_dat_i[25] wbs_dat_i[24] wbs_dat_i[23]
++ wbs_dat_i[22] wbs_dat_i[21] wbs_dat_i[20] wbs_dat_i[19] wbs_dat_i[18] wbs_dat_i[17] wbs_dat_i[16] wbs_dat_i[15]
++ wbs_dat_i[14] wbs_dat_i[13] wbs_dat_i[12] wbs_dat_i[11] wbs_dat_i[10] wbs_dat_i[9] wbs_dat_i[8] wbs_dat_i[7]
++ wbs_dat_i[6] wbs_dat_i[5] wbs_dat_i[4] wbs_dat_i[3] wbs_dat_i[2] wbs_dat_i[1] wbs_dat_i[0] wbs_adr_i[31]
++ wbs_adr_i[30] wbs_adr_i[29] wbs_adr_i[28] wbs_adr_i[27] wbs_adr_i[26] wbs_adr_i[25] wbs_adr_i[24] wbs_adr_i[23]
++ wbs_adr_i[22] wbs_adr_i[21] wbs_adr_i[20] wbs_adr_i[19] wbs_adr_i[18] wbs_adr_i[17] wbs_adr_i[16] wbs_adr_i[15]
++ wbs_adr_i[14] wbs_adr_i[13] wbs_adr_i[12] wbs_adr_i[11] wbs_adr_i[10] wbs_adr_i[9] wbs_adr_i[8] wbs_adr_i[7]
++ wbs_adr_i[6] wbs_adr_i[5] wbs_adr_i[4] wbs_adr_i[3] wbs_adr_i[2] wbs_adr_i[1] wbs_adr_i[0] wbs_ack_o
++ wbs_dat_o[31] wbs_dat_o[30] wbs_dat_o[29] wbs_dat_o[28] wbs_dat_o[27] wbs_dat_o[26] wbs_dat_o[25] wbs_dat_o[24]
++ wbs_dat_o[23] wbs_dat_o[22] wbs_dat_o[21] wbs_dat_o[20] wbs_dat_o[19] wbs_dat_o[18] wbs_dat_o[17] wbs_dat_o[16]
++ wbs_dat_o[15] wbs_dat_o[14] wbs_dat_o[13] wbs_dat_o[12] wbs_dat_o[11] wbs_dat_o[10] wbs_dat_o[9] wbs_dat_o[8]
++ wbs_dat_o[7] wbs_dat_o[6] wbs_dat_o[5] wbs_dat_o[4] wbs_dat_o[3] wbs_dat_o[2] wbs_dat_o[1] wbs_dat_o[0]
++ la_data_in[127] la_data_in[126] la_data_in[125] la_data_in[124] la_data_in[123] la_data_in[122] la_data_in[121]
++ la_data_in[120] la_data_in[119] la_data_in[118] la_data_in[117] la_data_in[116] la_data_in[115] la_data_in[114]
++ la_data_in[113] la_data_in[112] la_data_in[111] la_data_in[110] la_data_in[109] la_data_in[108] la_data_in[107]
++ la_data_in[106] la_data_in[105] la_data_in[104] la_data_in[103] la_data_in[102] la_data_in[101] la_data_in[100]
++ la_data_in[99] la_data_in[98] la_data_in[97] la_data_in[96] la_data_in[95] la_data_in[94] la_data_in[93]
++ la_data_in[92] la_data_in[91] la_data_in[90] la_data_in[89] la_data_in[88] la_data_in[87] la_data_in[86]
++ la_data_in[85] la_data_in[84] la_data_in[83] la_data_in[82] la_data_in[81] la_data_in[80] la_data_in[79]
++ la_data_in[78] la_data_in[77] la_data_in[76] la_data_in[75] la_data_in[74] la_data_in[73] la_data_in[72]
++ la_data_in[71] la_data_in[70] la_data_in[69] la_data_in[68] la_data_in[67] la_data_in[66] la_data_in[65]
++ la_data_in[64] la_data_in[63] la_data_in[62] la_data_in[61] la_data_in[60] la_data_in[59] la_data_in[58]
++ la_data_in[57] la_data_in[56] la_data_in[55] la_data_in[54] la_data_in[53] la_data_in[52] la_data_in[51]
++ la_data_in[50] la_data_in[49] la_data_in[48] la_data_in[47] la_data_in[46] la_data_in[45] la_data_in[44]
++ la_data_in[43] la_data_in[42] la_data_in[41] la_data_in[40] la_data_in[39] la_data_in[38] la_data_in[37]
++ la_data_in[36] la_data_in[35] la_data_in[34] la_data_in[33] la_data_in[32] la_data_in[31] la_data_in[30]
++ la_data_in[29] la_data_in[28] la_data_in[27] la_data_in[26] la_data_in[25] la_data_in[24] la_data_in[23]
++ la_data_in[22] la_data_in[21] la_data_in[20] la_data_in[19] la_data_in[18] la_data_in[17] la_data_in[16]
++ la_data_in[15] la_data_in[14] la_data_in[13] la_data_in[12] la_data_in[11] la_data_in[10] la_data_in[9]
++ la_data_in[8] la_data_in[7] la_data_in[6] la_data_in[5] la_data_in[4] la_data_in[3] la_data_in[2] la_data_in[1]
++ la_data_in[0] la_data_out[127] la_data_out[126] la_data_out[125] la_data_out[124] la_data_out[123]
++ la_data_out[122] la_data_out[121] la_data_out[120] la_data_out[119] la_data_out[118] la_data_out[117]
++ la_data_out[116] la_data_out[115] la_data_out[114] la_data_out[113] la_data_out[112] la_data_out[111]
++ la_data_out[110] la_data_out[109] la_data_out[108] la_data_out[107] la_data_out[106] la_data_out[105]
++ la_data_out[104] la_data_out[103] la_data_out[102] la_data_out[101] la_data_out[100] la_data_out[99] la_data_out[98]
++ la_data_out[97] la_data_out[96] la_data_out[95] la_data_out[94] la_data_out[93] la_data_out[92] la_data_out[91]
++ la_data_out[90] la_data_out[89] la_data_out[88] la_data_out[87] la_data_out[86] la_data_out[85] la_data_out[84]
++ la_data_out[83] la_data_out[82] la_data_out[81] la_data_out[80] la_data_out[79] la_data_out[78] la_data_out[77]
++ la_data_out[76] la_data_out[75] la_data_out[74] la_data_out[73] la_data_out[72] la_data_out[71] la_data_out[70]
++ la_data_out[69] la_data_out[68] la_data_out[67] la_data_out[66] la_data_out[65] la_data_out[64] la_data_out[63]
++ la_data_out[62] la_data_out[61] la_data_out[60] la_data_out[59] la_data_out[58] la_data_out[57] la_data_out[56]
++ la_data_out[55] la_data_out[54] la_data_out[53] la_data_out[52] la_data_out[51] la_data_out[50] la_data_out[49]
++ la_data_out[48] la_data_out[47] la_data_out[46] la_data_out[45] la_data_out[44] la_data_out[43] la_data_out[42]
++ la_data_out[41] la_data_out[40] la_data_out[39] la_data_out[38] la_data_out[37] la_data_out[36] la_data_out[35]
++ la_data_out[34] la_data_out[33] la_data_out[32] la_data_out[31] la_data_out[30] la_data_out[29] la_data_out[28]
++ la_data_out[27] la_data_out[26] la_data_out[25] la_data_out[24] la_data_out[23] la_data_out[22] la_data_out[21]
++ la_data_out[20] la_data_out[19] la_data_out[18] la_data_out[17] la_data_out[16] la_data_out[15] la_data_out[14]
++ la_data_out[13] la_data_out[12] la_data_out[11] la_data_out[10] la_data_out[9] la_data_out[8] la_data_out[7]
++ la_data_out[6] la_data_out[5] la_data_out[4] la_data_out[3] la_data_out[2] la_data_out[1] la_data_out[0]
++ la_oenb[127] la_oenb[126] la_oenb[125] la_oenb[124] la_oenb[123] la_oenb[122] la_oenb[121] la_oenb[120]
++ la_oenb[119] la_oenb[118] la_oenb[117] la_oenb[116] la_oenb[115] la_oenb[114] la_oenb[113] la_oenb[112]
++ la_oenb[111] la_oenb[110] la_oenb[109] la_oenb[108] la_oenb[107] la_oenb[106] la_oenb[105] la_oenb[104]
++ la_oenb[103] la_oenb[102] la_oenb[101] la_oenb[100] la_oenb[99] la_oenb[98] la_oenb[97] la_oenb[96] la_oenb[95]
++ la_oenb[94] la_oenb[93] la_oenb[92] la_oenb[91] la_oenb[90] la_oenb[89] la_oenb[88] la_oenb[87] la_oenb[86]
++ la_oenb[85] la_oenb[84] la_oenb[83] la_oenb[82] la_oenb[81] la_oenb[80] la_oenb[79] la_oenb[78] la_oenb[77]
++ la_oenb[76] la_oenb[75] la_oenb[74] la_oenb[73] la_oenb[72] la_oenb[71] la_oenb[70] la_oenb[69] la_oenb[68]
++ la_oenb[67] la_oenb[66] la_oenb[65] la_oenb[64] la_oenb[63] la_oenb[62] la_oenb[61] la_oenb[60] la_oenb[59]
++ la_oenb[58] la_oenb[57] la_oenb[56] la_oenb[55] la_oenb[54] la_oenb[53] la_oenb[52] la_oenb[51] la_oenb[50]
++ la_oenb[49] la_oenb[48] la_oenb[47] la_oenb[46] la_oenb[45] la_oenb[44] la_oenb[43] la_oenb[42] la_oenb[41]
++ la_oenb[40] la_oenb[39] la_oenb[38] la_oenb[37] la_oenb[36] la_oenb[35] la_oenb[34] la_oenb[33] la_oenb[32]
++ la_oenb[31] la_oenb[30] la_oenb[29] la_oenb[28] la_oenb[27] la_oenb[26] la_oenb[25] la_oenb[24] la_oenb[23]
++ la_oenb[22] la_oenb[21] la_oenb[20] la_oenb[19] la_oenb[18] la_oenb[17] la_oenb[16] la_oenb[15] la_oenb[14]
++ la_oenb[13] la_oenb[12] la_oenb[11] la_oenb[10] la_oenb[9] la_oenb[8] la_oenb[7] la_oenb[6] la_oenb[5]
++ la_oenb[4] la_oenb[3] la_oenb[2] la_oenb[1] la_oenb[0] io_in[26] io_in[25] io_in[24] io_in[23] io_in[22]
++ io_in[21] io_in[20] io_in[19] io_in[18] io_in[17] io_in[16] io_in[15] io_in[14] io_in[13] io_in[12] io_in[11]
++ io_in[10] io_in[9] io_in[8] io_in[7] io_in[6] io_in[5] io_in[4] io_in[3] io_in[2] io_in[1] io_in[0]
++ io_in_3v3[26] io_in_3v3[25] io_in_3v3[24] io_in_3v3[23] io_in_3v3[22] io_in_3v3[21] io_in_3v3[20] io_in_3v3[19]
++ io_in_3v3[18] io_in_3v3[17] io_in_3v3[16] io_in_3v3[15] io_in_3v3[14] io_in_3v3[13] io_in_3v3[12] io_in_3v3[11]
++ io_in_3v3[10] io_in_3v3[9] io_in_3v3[8] io_in_3v3[7] io_in_3v3[6] io_in_3v3[5] io_in_3v3[4] io_in_3v3[3]
++ io_in_3v3[2] io_in_3v3[1] io_in_3v3[0] io_out[26] io_out[25] io_out[24] io_out[23] io_out[22] io_out[21]
++ io_out[20] io_out[19] io_out[18] io_out[17] io_out[16] io_out[15] io_out[14] io_out[13] io_out[12] io_out[11]
++ io_out[10] io_out[9] io_out[8] io_out[7] io_out[6] io_out[5] io_out[4] io_out[3] io_out[2] io_out[1] io_out[0]
++ io_oeb[26] io_oeb[25] io_oeb[24] io_oeb[23] io_oeb[22] io_oeb[21] io_oeb[20] io_oeb[19] io_oeb[18] io_oeb[17]
++ io_oeb[16] io_oeb[15] io_oeb[14] io_oeb[13] io_oeb[12] io_oeb[11] io_oeb[10] io_oeb[9] io_oeb[8] io_oeb[7]
++ io_oeb[6] io_oeb[5] io_oeb[4] io_oeb[3] io_oeb[2] io_oeb[1] io_oeb[0] gpio_analog[17] gpio_analog[16]
++ gpio_analog[15] gpio_analog[14] gpio_analog[13] gpio_analog[12] gpio_analog[11] gpio_analog[10] gpio_analog[9]
++ gpio_analog[8] gpio_analog[7] gpio_analog[6] gpio_analog[5] gpio_analog[4] gpio_analog[3] gpio_analog[2]
++ gpio_analog[1] gpio_analog[0] gpio_noesd[17] gpio_noesd[16] gpio_noesd[15] gpio_noesd[14] gpio_noesd[13]
++ gpio_noesd[12] gpio_noesd[11] gpio_noesd[10] gpio_noesd[9] gpio_noesd[8] gpio_noesd[7] gpio_noesd[6] gpio_noesd[5]
++ gpio_noesd[4] gpio_noesd[3] gpio_noesd[2] gpio_noesd[1] gpio_noesd[0] io_analog[10] io_analog[9] io_analog[8]
++ io_analog[7] io_analog[6] io_analog[5] io_analog[4] io_analog[3] io_analog[2] io_analog[1] io_analog[0]
++ io_clamp_high[2] io_clamp_high[1] io_clamp_high[0] io_clamp_low[2] io_clamp_low[1] io_clamp_low[0] user_clock2
++ user_irq[2] user_irq[1] user_irq[0]
+*.iopin vdda1
+*.iopin vdda2
+*.iopin vssa1
+*.iopin vssa2
+*.iopin vccd1
+*.iopin vccd2
+*.iopin vssd1
+*.iopin vssd2
+*.ipin wb_clk_i
+*.ipin wb_rst_i
+*.ipin wbs_stb_i
+*.ipin wbs_cyc_i
+*.ipin wbs_we_i
+*.ipin wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
+*.ipin
+*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
+*.ipin
+*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0]
+*.opin wbs_ack_o
+*.opin
+*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
+*.ipin
+*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
+*.opin
+*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
+*.ipin
+*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
+*.ipin
+*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0]
+*.ipin user_clock2
+*.opin
+*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
+*.opin
+*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
+*.iopin
+*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
+*.iopin
+*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
+*.iopin
+*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0]
+*.iopin io_clamp_high[2],io_clamp_high[1],io_clamp_high[0]
+*.iopin io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
+*.opin user_irq[2],user_irq[1],user_irq[0]
+*.ipin
+*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
+x1 vccd1 vssa1 net2 net8 net9 io_analog[5] io_analog[6] net1 comparator
+D1 io_analog[8] vccd1 sky130_fd_pr__diode_pd2nw_05v5 pj=4e+06u area=1e+12p
+D2 vssa1 io_analog[8] sky130_fd_pr__diode_pw2nd_05v5 pj=4e+06u area=1e+12p
+D3 io_analog[7] vccd1 sky130_fd_pr__diode_pd2nw_05v5 pj=4e+06u area=1e+12p
+D4 vssa1 io_analog[7] sky130_fd_pr__diode_pw2nd_05v5 pj=4e+06u area=1e+12p
+x2 net8 vssa1 vssa1 vccd1 vccd1 net4 sky130_fd_sc_hd__buf_2
+x3 net4 vssa1 vssa1 vccd1 vccd1 io_analog[3] sky130_fd_sc_hd__buf_16
+x4 net9 vssa1 vssa1 vccd1 vccd1 net5 sky130_fd_sc_hd__buf_2
+x5 net5 vssa1 vssa1 vccd1 vccd1 io_analog[2] sky130_fd_sc_hd__buf_16
+x6 io_analog[7] vssa1 vssa1 vccd1 vccd1 net3 sky130_fd_sc_hd__buf_2
+x7 net3 vssa1 vssa1 vccd1 vccd1 net2 sky130_fd_sc_hd__buf_16
+x8 io_analog[8] vssa1 vssa1 vccd1 vccd1 net6 sky130_fd_sc_hd__buf_2
+x9 net6 vssa1 vssa1 vccd1 vccd1 net1 sky130_fd_sc_hd__buf_16
+*D5 io_analog[5] vccd1 sky130_fd_pr__diode_pd2nw_05v5 pj=4e+06u area=1e+12p
+*D6 vssa1 io_analog[5] sky130_fd_pr__diode_pw2nd_05v5 pj=4e+06u area=1e+12p
+*D7 io_analog[6] vccd1 sky130_fd_pr__diode_pd2nw_05v5 pj=4e+06u area=1e+12p
+*D8 vssa1 io_analog[6] sky130_fd_pr__diode_pw2nd_05v5 pj=4e+06u area=1e+12p
+x10 io_analog[1] vssa1 vssa1 vccd1 vccd1 net7 sky130_fd_sc_hd__buf_2
+x11 net7 vssa1 vssa1 vccd1 vccd1 io_analog[0] sky130_fd_sc_hd__buf_16
+V0 vccd1 io_clamp_high[1] 0.0
+V1 vccd1 io_clamp_high[2] 0.0
+V2 vssa1 io_clamp_low[2] 0.0
+V3 vssa1 io_clamp_low[1] 0.0
+.ends
+
+
+* expanding symbol: comparator.sym # of pins=8
+** sym_path: /home/krishna/Documents/Comparator_MPW6/xschem/comparator.sym
+** sch_path: /home/krishna/Documents/Comparator_MPW6/xschem/comparator.sch
+.subckt comparator VDD GND CLKBAR Outn Outp Vp Vn CLK
+*.iopin VDD
+*.iopin GND
+*.ipin Vp
+*.ipin Vn
+*.iopin CLK
+*.opin Outp
+*.opin Outn
+*.iopin CLKBAR
+XM1 fn Vn net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 fp Vp net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net2 CLK GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 Dp fn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 fp CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net5 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net6 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 fn CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM15 Dp Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 Dn Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM17 Dp Dn net4 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM18 Dn Dp net4 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM19 net4 CLKBAR VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 Outp Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 Outn Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 Outp Outn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 Outn Outp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 net5 fp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 fn CLKBAR net5 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 fp CLKBAR net6 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 net6 fn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 Dn fp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM10 net1 fp net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM56 net3 fn net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+.end
diff --git a/xschem/buffer.sch b/xschem/buffer.sch
new file mode 100644
index 0000000..7aaa0d9
--- /dev/null
+++ b/xschem/buffer.sch
@@ -0,0 +1,276 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 920 -290 990 -290 {
+lab=BUFOUT}
+N 200 -290 270 -290 {
+lab=BUFIN}
+N 360 -290 360 -270 {
+lab=#net1}
+N 300 -340 320 -340 {
+lab=BUFIN}
+N 300 -290 300 -240 {
+lab=BUFIN}
+N 300 -240 320 -240 {
+lab=BUFIN}
+N 360 -380 360 -370 {
+lab=VDD}
+N 360 -340 390 -340 {
+lab=VDD}
+N 390 -380 390 -340 {
+lab=VDD}
+N 360 -380 390 -380 {
+lab=VDD}
+N 360 -200 360 -190 {
+lab=GND}
+N 360 -240 390 -240 {
+lab=GND}
+N 390 -240 390 -200 {
+lab=GND}
+N 360 -200 390 -200 {
+lab=GND}
+N 520 -290 520 -270 {
+lab=#net2}
+N 460 -340 480 -340 {
+lab=#net1}
+N 460 -290 460 -240 {
+lab=#net1}
+N 460 -240 480 -240 {
+lab=#net1}
+N 520 -380 520 -370 {
+lab=VDD}
+N 520 -340 550 -340 {
+lab=VDD}
+N 550 -380 550 -340 {
+lab=VDD}
+N 520 -380 550 -380 {
+lab=VDD}
+N 520 -200 520 -190 {
+lab=GND}
+N 520 -240 550 -240 {
+lab=GND}
+N 550 -240 550 -200 {
+lab=GND}
+N 520 -200 550 -200 {
+lab=GND}
+N 680 -290 680 -270 {
+lab=#net3}
+N 620 -340 640 -340 {
+lab=#net2}
+N 620 -290 620 -240 {
+lab=#net2}
+N 620 -240 640 -240 {
+lab=#net2}
+N 680 -380 680 -370 {
+lab=VDD}
+N 680 -340 710 -340 {
+lab=VDD}
+N 710 -380 710 -340 {
+lab=VDD}
+N 680 -380 710 -380 {
+lab=VDD}
+N 680 -200 680 -190 {
+lab=GND}
+N 680 -240 710 -240 {
+lab=GND}
+N 710 -240 710 -200 {
+lab=GND}
+N 680 -200 710 -200 {
+lab=GND}
+N 830 -290 830 -270 {
+lab=BUFOUT}
+N 770 -340 790 -340 {
+lab=#net3}
+N 770 -290 770 -240 {
+lab=#net3}
+N 770 -240 790 -240 {
+lab=#net3}
+N 830 -380 830 -370 {
+lab=VDD}
+N 830 -340 860 -340 {
+lab=VDD}
+N 860 -380 860 -340 {
+lab=VDD}
+N 830 -380 860 -380 {
+lab=VDD}
+N 830 -200 830 -190 {
+lab=GND}
+N 830 -240 860 -240 {
+lab=GND}
+N 860 -240 860 -200 {
+lab=GND}
+N 830 -200 860 -200 {
+lab=GND}
+N 360 -290 460 -290 {
+lab=#net1}
+N 520 -290 620 -290 {
+lab=#net2}
+N 680 -290 770 -290 {
+lab=#net3}
+N 830 -290 920 -290 {
+lab=BUFOUT}
+N 270 -290 300 -290 {
+lab=BUFIN}
+N 360 -410 360 -380 {
+lab=VDD}
+N 680 -410 830 -410 {
+lab=VDD}
+N 830 -410 830 -380 {
+lab=VDD}
+N 520 -410 520 -380 {
+lab=VDD}
+N 680 -410 680 -380 {
+lab=VDD}
+N 360 -210 360 -200 {
+lab=GND}
+N 520 -210 520 -200 {
+lab=GND}
+N 680 -210 680 -200 {
+lab=GND}
+N 830 -210 830 -200 {
+lab=GND}
+N 360 -310 360 -290 {
+lab=#net1}
+N 460 -340 460 -290 {
+lab=#net1}
+N 520 -310 520 -290 {
+lab=#net2}
+N 620 -340 620 -290 {
+lab=#net2}
+N 680 -310 680 -290 {
+lab=#net3}
+N 770 -340 770 -290 {
+lab=#net3}
+N 830 -310 830 -290 {
+lab=BUFOUT}
+N 300 -340 300 -290 {
+lab=BUFIN}
+N 360 -410 520 -410 {
+lab=VDD}
+N 520 -410 680 -410 {
+lab=VDD}
+N 360 -190 830 -190 {
+lab=GND}
+N 590 -460 590 -410 {
+lab=VDD}
+N 600 -190 600 -160 {
+lab=GND}
+C {sky130_fd_pr/nfet_01v8.sym} 340 -240 0 0 {name=M56
+L=0.15
+W=0.65
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 340 -340 0 0 {name=M57
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 500 -240 0 0 {name=M58
+L=0.15
+W=1.95
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 500 -340 0 0 {name=M59
+L=0.15
+W=3
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 660 -240 0 0 {name=M60
+L=0.15
+W=3.9
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 660 -340 0 0 {name=M61
+L=0.15
+W=6
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 810 -240 0 0 {name=M62
+L=0.15
+W=10.4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 810 -340 0 0 {name=M63
+L=0.15
+W=16
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/iopin.sym} 210 -290 2 0 {name=p1 lab=BUFIN}
+C {devices/iopin.sym} 980 -290 0 0 {name=p2 lab=BUFOUT}
+C {devices/iopin.sym} 590 -450 3 0 {name=p3 lab=VDD}
+C {devices/iopin.sym} 600 -170 1 0 {name=p4 lab=GND}
diff --git a/xschem/buffer.sym b/xschem/buffer.sym
new file mode 100644
index 0000000..ef83b42
--- /dev/null
+++ b/xschem/buffer.sym
@@ -0,0 +1,29 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -40 -130 40 {}
+L 4 -130 -40 -70 0 {}
+L 4 -130 40 -70 0 {}
+L 4 -160 -20 -160 20 {}
+L 4 -160 -20 -130 0 {}
+L 4 -160 20 -130 0 {}
+L 7 -100 -40 -100 -20 {}
+L 7 -180 0 -160 0 {}
+L 7 -70 0 -50 0 {}
+L 7 -100 20 -100 40 {}
+B 5 -102.5 -42.5 -97.5 -37.5 {name=VDD dir=inout }
+B 5 -182.5 -2.5 -177.5 2.5 {name=BUFIN dir=inout }
+B 5 -52.5 -2.5 -47.5 2.5 {name=BUFOUT dir=inout }
+B 5 -102.5 37.5 -97.5 42.5 {name=GND dir=inout }
+T {@symname} -165 -86 0 0 0.3 0.3 {}
+T {@name} -125 -2 0 0 0.2 0.2 {}
+T {VDD} -106 -35 1 1 0.2 0.2 {}
+T {BUFIN} -175 -24 0 1 0.2 0.2 {}
+T {BUFOUT} -25 -24 0 1 0.2 0.2 {}
+T {GND} -106 55 1 1 0.2 0.2 {}
diff --git a/xschem/comparator.sch b/xschem/comparator.sch
new file mode 100644
index 0000000..7f68ab4
--- /dev/null
+++ b/xschem/comparator.sch
@@ -0,0 +1,727 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 1370 -860 1370 -820 {
+lab=#net1}
+N 1370 -680 1790 -680 {
+lab=#net2}
+N 1790 -850 1790 -820 {
+lab=#net3}
+N 1590 -680 1590 -660 {
+lab=#net2}
+N 1590 -600 1590 -570 {
+lab=GND}
+N 1590 -630 1610 -630 {
+lab=GND}
+N 1610 -630 1610 -590 {
+lab=GND}
+N 1590 -590 1610 -590 {
+lab=GND}
+N 1370 -890 1560 -890 {
+lab=GND}
+N 1610 -880 1790 -880 {
+lab=GND}
+N 1170 -940 1190 -940 {
+lab=GND}
+N 1170 -940 1170 -890 {
+lab=GND}
+N 1170 -890 1190 -890 {
+lab=GND}
+N 1190 -910 1190 -890 {
+lab=GND}
+N 1190 -1000 1190 -970 {
+lab=Dp}
+N 1340 -1250 1380 -1250 {
+lab=CLK}
+N 1530 -1250 1530 -1210 {
+lab=CLK}
+N 1420 -1250 1420 -1210 {
+lab=CLK}
+N 1600 -1250 1620 -1250 {
+lab=CLK}
+N 1600 -1250 1600 -1210 {
+lab=CLK}
+N 1480 -1210 1600 -1210 {
+lab=CLK}
+N 1600 -1210 1710 -1210 {
+lab=CLK}
+N 1420 -1290 1440 -1290 {
+lab=VDD}
+N 1440 -1290 1760 -1290 {
+lab=VDD}
+N 1660 -1290 1660 -1280 {
+lab=VDD}
+N 1570 -1290 1570 -1280 {
+lab=VDD}
+N 1570 -1250 1580 -1250 {
+lab=VDD}
+N 1580 -1250 1590 -1250 {
+lab=VDD}
+N 1590 -1290 1590 -1250 {
+lab=VDD}
+N 1660 -1250 1680 -1250 {
+lab=VDD}
+N 1680 -1290 1680 -1250 {
+lab=VDD}
+N 1760 -1250 1780 -1250 {
+lab=VDD}
+N 1780 -1290 1780 -1250 {
+lab=VDD}
+N 1760 -1290 1780 -1290 {
+lab=VDD}
+N 1510 -630 1550 -630 {
+lab=CLK}
+N 1300 -890 1330 -890 {
+lab=Vn}
+N 1830 -880 1880 -880 {
+lab=Vp}
+N 2190 -1060 2220 -1060 {
+lab=Dp}
+N 2220 -1060 2220 -920 {
+lab=Dp}
+N 2190 -920 2220 -920 {
+lab=Dp}
+N 2310 -1060 2350 -1060 {
+lab=Dn}
+N 2310 -1060 2310 -920 {
+lab=Dn}
+N 2150 -1030 2150 -950 {
+lab=Dn}
+N 2310 -920 2350 -920 {
+lab=Dn}
+N 2390 -1030 2390 -950 {
+lab=Dp}
+N 2150 -890 2150 -870 {
+lab=GND}
+N 2150 -870 2390 -870 {
+lab=GND}
+N 2390 -890 2390 -870 {
+lab=GND}
+N 2150 -1110 2150 -1090 {
+lab=#net4}
+N 2150 -1110 2390 -1110 {
+lab=#net4}
+N 2390 -1110 2390 -1090 {
+lab=#net4}
+N 2150 -1010 2310 -1010 {
+lab=Dn}
+N 2220 -970 2390 -970 {
+lab=Dp}
+N 2120 -920 2150 -920 {
+lab=GND}
+N 2120 -920 2120 -870 {
+lab=GND}
+N 2120 -870 2150 -870 {
+lab=GND}
+N 2390 -920 2410 -920 {
+lab=GND}
+N 2410 -920 2420 -920 {
+lab=GND}
+N 2420 -920 2420 -870 {
+lab=GND}
+N 2390 -870 2420 -870 {
+lab=GND}
+N 2260 -1150 2260 -1110 {
+lab=#net4}
+N 2260 -1180 2300 -1180 {
+lab=VDD}
+N 2300 -1230 2300 -1180 {
+lab=VDD}
+N 2260 -1230 2300 -1230 {
+lab=VDD}
+N 2260 -1230 2260 -1210 {
+lab=VDD}
+N 2120 -1060 2150 -1060 {
+lab=VDD}
+N 2120 -1110 2120 -1060 {
+lab=VDD}
+N 2390 -1060 2420 -1060 {
+lab=VDD}
+N 2420 -1110 2420 -1060 {
+lab=VDD}
+N 2190 -1180 2220 -1180 {
+lab=CLKBAR}
+N 2640 -1050 2670 -1050 {
+lab=Outp}
+N 2760 -1050 2800 -1050 {
+lab=Outp}
+N 2600 -1020 2600 -940 {
+lab=Outp}
+N 2840 -1020 2840 -940 {
+lab=Outp}
+N 2600 -880 2600 -860 {
+lab=GND}
+N 2600 -860 2840 -860 {
+lab=GND}
+N 2840 -880 2840 -860 {
+lab=GND}
+N 2600 -1100 2600 -1080 {
+lab=VDD}
+N 2600 -1100 2840 -1100 {
+lab=VDD}
+N 2840 -1100 2840 -1080 {
+lab=VDD}
+N 2710 -1140 2710 -1100 {
+lab=VDD}
+N 2570 -1050 2600 -1050 {
+lab=VDD}
+N 2570 -1100 2570 -1050 {
+lab=VDD}
+N 2570 -1100 2600 -1100 {
+lab=VDD}
+N 2840 -1050 2870 -1050 {
+lab=VDD}
+N 2870 -1100 2870 -1050 {
+lab=VDD}
+N 2840 -1100 2870 -1100 {
+lab=VDD}
+N 2530 -910 2560 -910 {
+lab=Dn}
+N 2880 -910 2910 -910 {
+lab=Dp}
+N 2670 -1050 2740 -980 {
+lab=Outp}
+N 2740 -980 2840 -980 {
+lab=Outp}
+N 2670 -980 2760 -1050 {
+lab=Outp}
+N 2600 -980 2670 -980 {
+lab=Outp}
+N 2600 -910 2620 -910 {
+lab=GND}
+N 2620 -910 2620 -860 {
+lab=GND}
+N 2820 -910 2840 -910 {
+lab=GND}
+N 2820 -910 2820 -860 {
+lab=GND}
+N 2120 -1130 2120 -1110 {
+lab=VDD}
+N 2120 -1130 2420 -1130 {
+lab=VDD}
+N 2420 -1130 2420 -1110 {
+lab=VDD}
+N 2300 -1180 2300 -1130 {
+lab=VDD}
+N 2180 -1360 2180 -1180 {
+lab=CLKBAR}
+N 2180 -1180 2190 -1180 {
+lab=CLKBAR}
+N 1610 -880 1610 -770 {
+lab=GND}
+N 1560 -890 1610 -890 {
+lab=GND}
+N 1610 -890 1610 -870 {
+lab=GND}
+N 1370 -980 1370 -920 {
+lab=fn}
+N 1370 -1070 1370 -1040 {
+lab=#net5}
+N 1790 -980 1790 -910 {
+lab=fp}
+N 1790 -1070 1790 -1040 {
+lab=#net6}
+N 1370 -1150 1370 -1130 {
+lab=VDD}
+N 1790 -1150 1790 -1130 {
+lab=VDD}
+N 1410 -1010 1750 -1010 {
+lab=CLKBAR}
+N 1410 -1100 1480 -1100 {
+lab=fp}
+N 1480 -1100 1650 -940 {
+lab=fp}
+N 1650 -940 1790 -940 {
+lab=fp}
+N 1680 -1100 1750 -1100 {
+lab=fn}
+N 1480 -940 1680 -1100 {
+lab=fn}
+N 1370 -940 1480 -940 {
+lab=fn}
+N 1370 -1160 1370 -1150 {
+lab=VDD}
+N 1790 -1160 1790 -1150 {
+lab=VDD}
+N 1750 -1290 1750 -1280 {
+lab=VDD}
+N 1750 -1250 1760 -1250 {
+lab=VDD}
+N 1710 -1250 1710 -1210 {
+lab=CLK}
+N 1750 -1220 1750 -1100 {
+lab=fn}
+N 1370 -1050 1520 -1050 {
+lab=#net5}
+N 1570 -1220 1570 -1050 {
+lab=#net5}
+N 1660 -1220 1660 -1050 {
+lab=#net6}
+N 1660 -1050 1790 -1050 {
+lab=#net6}
+N 1230 -940 1370 -940 {
+lab=fn}
+N 1950 -910 1950 -890 {
+lab=GND}
+N 1950 -940 1970 -940 {
+lab=GND}
+N 1970 -940 1970 -900 {
+lab=GND}
+N 1950 -900 1970 -900 {
+lab=GND}
+N 1950 -990 1950 -970 {
+lab=Dn}
+N 1950 -1000 1950 -990 {
+lab=Dn}
+N 1790 -940 1910 -940 {
+lab=fp}
+N 1520 -1050 1570 -1050 {
+lab=#net5}
+N 1430 -1250 1440 -1250 {
+lab=CLK}
+N 1380 -1250 1430 -1250 {
+lab=CLK}
+N 1420 -1210 1480 -1210 {
+lab=CLK}
+N 1370 -1290 1370 -1160 {
+lab=VDD}
+N 1370 -1290 1420 -1290 {
+lab=VDD}
+N 1790 -1290 1790 -1160 {
+lab=VDD}
+N 1780 -1290 1790 -1290 {
+lab=VDD}
+N 1480 -1290 1480 -1280 {
+lab=VDD}
+N 1480 -1250 1500 -1250 {
+lab=VDD}
+N 1500 -1290 1500 -1250 {
+lab=VDD}
+N 1610 -770 1610 -630 {
+lab=GND}
+N 1370 -730 1370 -680 {
+lab=#net2}
+N 1790 -730 1790 -680 {
+lab=#net2}
+N 1370 -820 1370 -790 {
+lab=#net1}
+N 1790 -820 1790 -790 {
+lab=#net3}
+N 1410 -760 1460 -760 {
+lab=fp}
+N 1690 -760 1750 -760 {
+lab=fn}
+N 1790 -1010 1840 -1010 {
+lab=VDD}
+N 1840 -1100 1840 -1010 {
+lab=VDD}
+N 1790 -1100 1840 -1100 {
+lab=VDD}
+N 1840 -1290 1840 -1100 {
+lab=VDD}
+N 1790 -1290 1840 -1290 {
+lab=VDD}
+N 1330 -1010 1370 -1010 {
+lab=VDD}
+N 1330 -1100 1330 -1010 {
+lab=VDD}
+N 1330 -1100 1370 -1100 {
+lab=VDD}
+N 1330 -1290 1330 -1100 {
+lab=VDD}
+N 1330 -1290 1370 -1290 {
+lab=VDD}
+N 1330 -760 1370 -760 {
+lab=GND}
+N 1330 -760 1330 -590 {
+lab=GND}
+N 1330 -590 1330 -580 {
+lab=GND}
+N 1330 -580 1590 -580 {
+lab=GND}
+N 1590 -580 1830 -580 {
+lab=GND}
+N 1830 -760 1830 -580 {
+lab=GND}
+N 1790 -760 1830 -760 {
+lab=GND}
+N 1470 -1220 1480 -1220 {
+lab=fp}
+N 1470 -1220 1470 -1200 {
+lab=fp}
+N 1470 -1200 1470 -1100 {
+lab=fp}
+N 1640 -1010 1640 -980 {
+lab=CLKBAR}
+N 1300 -1250 1340 -1250 {
+lab=CLK}
+C {sky130_fd_pr/nfet_01v8.sym} 1350 -890 0 0 {name=M1
+L=0.15
+W=4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1810 -880 0 1 {name=M2
+L=0.15
+W=4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1570 -630 0 0 {name=M3
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1210 -940 0 1 {name=M9
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1460 -1250 0 0 {name=M11
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1550 -1250 0 0 {name=M12
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1640 -1250 0 0 {name=M13
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1730 -1250 0 0 {name=M14
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 2370 -920 0 0 {name=M15
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 2170 -920 0 1 {name=M16
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2370 -1060 0 0 {name=M17
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2170 -1060 0 1 {name=M18
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2240 -1180 0 0 {name=M19
+L=0.15
+W=5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 1190 -1000 0 0 {name=l12 sig_type=std_logic lab=Dp}
+C {devices/lab_pin.sym} 2150 -970 0 0 {name=l14 sig_type=std_logic lab=Dn}
+C {devices/lab_pin.sym} 2390 -990 2 0 {name=l15 sig_type=std_logic lab=Dp}
+C {sky130_fd_pr/nfet_01v8.sym} 2860 -910 0 1 {name=M20
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 2580 -910 0 0 {name=M21
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2820 -1050 0 0 {name=M22
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2620 -1050 0 1 {name=M23
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/iopin.sym} 1020 -1510 0 0 {name=p1 lab=VDD}
+C {devices/iopin.sym} 1020 -1470 0 0 {name=p2 lab=GND
+}
+C {devices/ipin.sym} 1870 -880 2 0 {name=p3 lab=Vp
+}
+C {devices/ipin.sym} 1310 -890 0 0 {name=p4 lab=Vn}
+C {devices/iopin.sym} 1460 -530 2 0 {name=p5 lab=CLK}
+C {devices/opin.sym} 2840 -980 0 0 {name=p7 lab=Outp}
+C {devices/opin.sym} 2600 -980 2 0 {name=p8 lab=Outn}
+C {devices/lab_pin.sym} 1590 -1290 1 0 {name=l9 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 2260 -1230 1 0 {name=l11 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 2710 -1140 1 0 {name=l27 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 1590 -570 3 0 {name=l10 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 2260 -870 3 0 {name=l2 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 2690 -860 3 0 {name=l19 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 1180 -890 3 0 {name=l3 sig_type=std_logic lab=GND}
+C {devices/lab_wire.sym} 2180 -1340 0 0 {name=l28 sig_type=std_logic lab=CLKBAR}
+C {devices/iopin.sym} 1640 -990 1 0 {name=p9 lab=CLKBAR}
+C {sky130_fd_pr/pfet_01v8.sym} 1390 -1100 0 1 {name=M4
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1390 -1010 0 1 {name=M5
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1770 -1010 0 0 {name=M6
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1770 -1100 0 0 {name=M7
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1930 -940 0 0 {name=M8
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 1950 -1000 2 0 {name=l6 sig_type=std_logic lab=Dn}
+C {devices/lab_pin.sym} 1950 -890 3 0 {name=l7 sig_type=std_logic lab=GND}
+C {sky130_fd_pr/nfet_01v8.sym} 1390 -760 0 1 {name=M10
+L=0.15
+W=3
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1770 -760 0 0 {name=M56
+L=0.15
+W=3
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 1290 -940 0 0 {name=l13 sig_type=std_logic lab=fn}
+C {devices/lab_pin.sym} 1730 -940 0 0 {name=l35 sig_type=std_logic lab=fp}
+C {devices/lab_pin.sym} 1460 -760 2 0 {name=l36 sig_type=std_logic lab=fp}
+C {devices/lab_pin.sym} 1690 -760 0 0 {name=l37 sig_type=std_logic lab=fn}
+C {devices/lab_pin.sym} 2530 -910 0 0 {name=l30 sig_type=std_logic lab=Dn}
+C {devices/lab_pin.sym} 2910 -910 2 0 {name=l31 sig_type=std_logic lab=Dp}
+C {devices/lab_pin.sym} 1300 -1250 0 0 {name=l5 sig_type=std_logic lab=CLK}
+C {devices/lab_pin.sym} 1510 -630 0 0 {name=l8 sig_type=std_logic lab=CLK}
diff --git a/xschem/comparator.spice b/xschem/comparator.spice
new file mode 100644
index 0000000..03a383a
--- /dev/null
+++ b/xschem/comparator.spice
@@ -0,0 +1,84 @@
+** sch_path: /home/krishna/Documents/Comparator_MPW6/xschem/comparator.sch
+**.subckt comparator VDD GND Vp Vn CLK Outp Outn CLKBAR
+*.iopin VDD
+*.iopin GND
+*.ipin Vp
+*.ipin Vn
+*.iopin CLK
+*.opin Outp
+*.opin Outn
+*.iopin CLKBAR
+XM1 fn Vn net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 fp Vp net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net2 CLK GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 Dp fn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 fp CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net5 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net6 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 fn CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM15 Dp Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 Dn Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM17 Dp Dn net4 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM18 Dn Dp net4 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM19 net4 CLKBAR VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 Outp Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 Outn Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 Outp Outn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 Outn Outp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 net5 fp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 fn CLKBAR net5 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 fp CLKBAR net6 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 net6 fn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 Dn fp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM10 net1 fp net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM56 net3 fn net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+**.ends
+.end
diff --git a/xschem/comparator.sym b/xschem/comparator.sym
new file mode 100644
index 0000000..13c71ef
--- /dev/null
+++ b/xschem/comparator.sym
@@ -0,0 +1,39 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -60 -130 60 {}
+L 4 40 -30 60 -30 {}
+L 4 -150 -40 -130 -40 {}
+L 4 -150 30 -130 30 {}
+L 4 -130 -60 40 -0 {}
+L 4 -130 60 40 0 {}
+L 4 -40 30 60 30 {}
+L 4 -40 -30 40 -30 {}
+L 7 -100 -70 -100 -50 {}
+L 7 -100 50 -100 70 {}
+L 7 -50 30 -50 50 {}
+L 7 -50 -50 -50 -30 {}
+B 5 -102.5 -72.5 -97.5 -67.5 {name=VDD dir=inout }
+B 5 -102.5 67.5 -97.5 72.5 {name=GND dir=inout }
+B 5 -52.5 47.5 -47.5 52.5 {name=CLKBAR dir=inout }
+B 5 57.5 -32.5 62.5 -27.5 {name=Outn dir=out }
+B 5 57.5 27.5 62.5 32.5 {name=Outp dir=out }
+B 5 -152.5 -42.5 -147.5 -37.5 {name=Vp dir=in }
+B 5 -152.5 27.5 -147.5 32.5 {name=Vn dir=in }
+B 5 -52.5 -52.5 -47.5 -47.5 {name=CLK dir=inout }
+T {@symname} -113 4 0 0 0.3 0.3 {}
+T {@name} -85 -12 0 0 0.2 0.2 {}
+T {VDD} -94 -75 3 1 0.2 0.2 {}
+T {GND} -86 75 1 1 0.2 0.2 {}
+T {CLKBAR} -56 85 1 1 0.2 0.2 {}
+T {Outn} 65 -44 0 1 0.2 0.2 {}
+T {Outp} 65 36 0 1 0.2 0.2 {}
+T {Vp} -125 -44 0 0 0.2 0.2 {}
+T {Vn} -125 26 0 0 0.2 0.2 {}
+T {CLK} -64 -65 3 1 0.2 0.2 {}
diff --git a/xschem/comparator_lvs.spice b/xschem/comparator_lvs.spice
new file mode 100644
index 0000000..b4b9abd
--- /dev/null
+++ b/xschem/comparator_lvs.spice
@@ -0,0 +1,86 @@
+** sch_path: /home/krishna/Documents/Comparator_MPW6/xschem/comparator.sch
+**.subckt comparator VDD GND Vp Vn CLK Outp Outn CLKBAR
+*.iopin VDD
+*.iopin GND
+*.ipin Vp
+*.ipin Vn
+*.iopin CLK
+*.opin Outp
+*.opin Outn
+*.iopin CLKBAR
+XM1 fn Vn net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 fp Vp net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net2 CLK GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 Dp fn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 fp CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net5 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net6 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 fn CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM15 Dp Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 Dn Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM17 Dp Dn net4 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM18 Dn Dp net4 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM19 net4 CLKBAR VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 Outp Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 Outn Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 Outp Outn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 Outn Outp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 net5 fp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 fn CLKBAR net5 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 fp CLKBAR net6 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 net6 fn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 Dn fp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM10 net1 fp net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM56 net3 fn net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+**.ends
+.GLOBAL VDD
+.GLOBAL GND
+.end
diff --git a/xschem/comparator_tb.sch b/xschem/comparator_tb.sch
new file mode 100644
index 0000000..dd08f51
--- /dev/null
+++ b/xschem/comparator_tb.sch
@@ -0,0 +1,217 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 800 -820 800 -800 {
+lab=GND}
+N 800 -910 800 -880 {
+lab=VDD}
+N 490 -740 490 -720 {
+lab=Vp}
+N 490 -820 490 -800 {
+lab=Vn}
+N 490 -720 580 -720 {
+lab=Vp}
+N 580 -720 580 -700 {
+lab=Vp}
+N 580 -640 580 -620 {
+lab=GND}
+N 580 -720 650 -720 {
+lab=Vp}
+N 650 -820 650 -720 {
+lab=Vp}
+N 910 -910 910 -880 {
+lab=CLKIN}
+N 800 -650 800 -630 {
+lab=GND}
+N 800 -740 800 -710 {
+lab=CLKBARIN}
+N 1370 -1000 1430 -1000 {
+lab=Vp}
+N 1370 -930 1430 -930 {
+lab=Vn}
+N 910 -820 910 -790 {
+lab=GND}
+N 1360 -720 1360 -680 {
+lab=GND}
+N 1360 -820 1360 -780 {
+lab=GND}
+N 1480 -1120 1480 -1030 {
+lab=VDD}
+N 1480 -890 1480 -800 {
+lab=GND}
+N 1530 -910 1530 -840 {
+lab=CLKBAR}
+N 1530 -1080 1530 -1010 {
+lab=CLK}
+N 1640 -990 1690 -990 {
+lab=#net1}
+N 1640 -930 1700 -930 {
+lab=#net2}
+N 1870 -990 1900 -990 {
+lab=On}
+N 1870 -930 1890 -930 {
+lab=Op}
+N 1070 -1320 1130 -1320 {
+lab=CLKIN}
+N 1530 -1190 1530 -1080 {
+lab=CLK}
+N 1230 -550 1250 -550 {
+lab=CLKBARIN}
+N 1530 -840 1530 -800 {
+lab=CLKBAR}
+N 1690 -1050 1690 -990 {
+lab=#net1}
+N 1700 -930 1700 -880 {
+lab=#net2}
+N 1870 -1050 1870 -990 {
+lab=On}
+N 1870 -930 1870 -880 {
+lab=Op}
+N 1530 -800 1530 -710 {
+lab=CLKBAR}
+N 1530 -710 1540 -710 {
+lab=CLKBAR}
+N 1250 -550 1280 -550 {
+lab=CLKBARIN}
+N 1130 -1320 1150 -1320 {
+lab=CLKIN}
+N 1510 -1260 1530 -1260 {
+lab=CLK}
+N 1530 -1260 1530 -1190 {
+lab=CLK}
+N 1540 -710 1590 -710 {
+lab=CLKBAR}
+N 1750 -1200 1770 -1200 {
+lab=#net3}
+N 1850 -1200 1870 -1200 {
+lab=#net3}
+N 1950 -1200 1970 -1200 {
+lab=On}
+N 1650 -1200 1670 -1200 {
+lab=#net1}
+N 1650 -1200 1650 -1050 {
+lab=#net1}
+N 1650 -1050 1690 -1050 {
+lab=#net1}
+N 1970 -1200 1970 -1050 {
+lab=On}
+N 1870 -1050 1970 -1050 {
+lab=On}
+N 1730 -800 1750 -800 {
+lab=#net4}
+N 1830 -800 1850 -800 {
+lab=#net4}
+N 1630 -800 1650 -800 {
+lab=#net2}
+N 1630 -880 1630 -800 {
+lab=#net2}
+N 1630 -880 1700 -880 {
+lab=#net2}
+N 1870 -880 1970 -880 {
+lab=Op}
+N 1970 -880 1970 -800 {
+lab=Op}
+N 1930 -800 1970 -800 {
+lab=Op}
+N 1250 -1320 1270 -1320 {
+lab=#net5}
+N 1350 -1320 1370 -1320 {
+lab=#net5}
+N 1450 -1320 1470 -1320 {
+lab=CLK}
+N 1150 -1320 1170 -1320 {
+lab=CLKIN}
+N 1470 -1320 1470 -1260 {
+lab=CLK}
+N 1470 -1260 1510 -1260 {
+lab=CLK}
+N 1380 -550 1400 -550 {
+lab=#net6}
+N 1480 -550 1500 -550 {
+lab=#net6}
+N 1280 -550 1300 -550 {
+lab=CLKBARIN}
+N 1580 -550 1600 -550 {
+lab=CLKBAR}
+N 1600 -710 1600 -550 {
+lab=CLKBAR}
+N 1590 -710 1600 -710 {
+lab=CLKBAR}
+N 1770 -1200 1850 -1200 {
+lab=#net3}
+N 1750 -800 1830 -800 {
+lab=#net4}
+N 1270 -1320 1350 -1320 {
+lab=#net5}
+N 1400 -550 1480 -550 {
+lab=#net6}
+C {devices/TT_models.sym} 720 -1220 0 0 {name=TT_MODELS
+only_toplevel=true
+format="tcleval( @value )"
+value="
+** opencircuitdesign pdks install
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+"
+spice_ignore=falsename=s1 only_toplevel=false value=blabla}
+C {devices/vsource.sym} 800 -850 0 0 {name=Vdd value=1.8}
+C {devices/vsource.sym} 490 -770 0 0 {name=Vn value="pulse(-10m 10m 1ps 1ps 1ps 4ns 8ns)"}
+C {devices/lab_pin.sym} 490 -820 0 0 {name=l24 sig_type=std_logic lab=Vn}
+C {devices/vsource.sym} 580 -670 0 0 {name=Vcm value=1.2}
+C {devices/lab_pin.sym} 650 -820 2 0 {name=l25 sig_type=std_logic lab=Vp}
+C {devices/code_shown.sym} 2060 -780 0 0 {name=SPICE only_toplevel=false value=".control
+save ALL @m.x1.xm3.msky130_fd_pr__nfet_01v8[id]
+tran 0.01n 10n
+write comparator_tb.raw
+set filetype=ascii
+run
+meas tran area INTEG @m.x1.xm3.msky130_fd_pr__nfet_01v8[id] from=0 to=4ns
+let ecbit = area*1.8
+let vdiff= v(op)
+meas tran delaytime WHEN vdiff = 0.9 FALL=LAST
+meas tran clk WHEN v(clk) = 0.9 RISE=2
+let clkdelay=clk-6ns
+#meas tran tdiff TRIG AT=2ns TARG vdiff VAL=0.9 CROSS=1
+let compdelay=delaytime-6ns-clkdelay-0.385ns
+let tdelay=delaytime-6ns
+write output_comptran.txt delaytime clkdelay tdelay
+print clkdelay tdelay compdelay ecbit
+.endc"}
+C {devices/vsource.sym} 910 -850 0 0 {name=V1 value="pulse(1.8 0 1ps 1ps 1ps 2ns 4ns)"}
+C {devices/lab_pin.sym} 910 -910 0 0 {name=l22 sig_type=std_logic lab=CLKIN}
+C {devices/vsource.sym} 800 -680 0 0 {name=V2 value="pulse(0 1.8 1ps 1ps 1ps 2ns 4ns)"}
+C {devices/lab_pin.sym} 800 -740 0 0 {name=l27 sig_type=std_logic lab=CLKBARIN}
+C {devices/lab_pin.sym} 1370 -930 0 0 {name=l1 sig_type=std_logic lab=Vn}
+C {devices/lab_pin.sym} 1370 -1000 0 0 {name=l2 sig_type=std_logic lab=Vp}
+C {devices/gnd.sym} 1360 -680 0 0 {name=l3 lab=GND}
+C {devices/lab_pin.sym} 1360 -820 2 0 {name=l4 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 580 -620 2 0 {name=l5 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 800 -630 2 0 {name=l6 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 800 -800 2 0 {name=l7 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 910 -790 2 0 {name=l8 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 800 -910 0 0 {name=l9 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 1480 -1120 2 0 {name=l10 sig_type=std_logic lab=VDD}
+C {devices/res.sym} 1360 -750 0 0 {name=R1
+value=0
+footprint=1206
+device=resistor
+m=1}
+C {comparator.sym} 1580 -960 0 0 {name=x1}
+C {devices/lab_pin.sym} 1480 -800 0 0 {name=l11 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 1530 -1080 2 0 {name=l12 sig_type=std_logic lab=CLK}
+C {devices/lab_pin.sym} 1530 -840 0 0 {name=l13 sig_type=std_logic lab=CLKBAR}
+C {devices/lab_pin.sym} 1900 -990 2 0 {name=l14 sig_type=std_logic lab=On}
+C {devices/lab_pin.sym} 1890 -930 2 0 {name=l15 sig_type=std_logic lab=Op}
+C {devices/lab_pin.sym} 1070 -1320 0 0 {name=l16 sig_type=std_logic lab=CLKIN}
+C {devices/lab_pin.sym} 1230 -550 0 0 {name=l17 sig_type=std_logic lab=CLKBARIN}
+C {sky130_stdcells/buf_2.sym} 1710 -1200 0 0 {name=x2 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130_stdcells/buf_2.sym} 1690 -800 0 0 {name=x3 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130_stdcells/buf_2.sym} 1210 -1320 0 0 {name=x4 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130_stdcells/buf_16.sym} 1410 -1320 0 0 {name=x11 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__}
+C {sky130_stdcells/buf_2.sym} 1340 -550 0 0 {name=x5 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {sky130_stdcells/buf_16.sym} 1540 -550 0 0 {name=x13 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__}
+C {sky130_stdcells/buf_16.sym} 1910 -1200 0 0 {name=x6 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__}
+C {sky130_stdcells/buf_16.sym} 1890 -800 0 0 {name=x7 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__}
diff --git a/xschem/comparator_tb.spice b/xschem/comparator_tb.spice
new file mode 100644
index 0000000..3cbfc12
--- /dev/null
+++ b/xschem/comparator_tb.spice
@@ -0,0 +1,134 @@
+** sch_path: /home/krishna/Documents/Comparator_MPW6/xschem/comparator_tb1.sch
+**.subckt comparator_tb1
+Vdd VDD GND 1.8
+Vn Vn Vp pulse(-10m 10m 1ps 1ps 1ps 4ns 8ns)
+Vcm Vp GND 1.2
+V1 CLKIN GND pulse(1.8 0 1ps 1ps 1ps 2ns 4ns)
+V2 CLKBARIN GND pulse(0 1.8 1ps 1ps 1ps 2ns 4ns)
+R1 GND GND 0 m=1
+x1 VDD GND CLKBAR net1 net2 Vp Vn CLK comparator
+x2 net1 GND GND VDD VDD net3 sky130_fd_sc_hd__buf_2
+x3 net2 GND GND VDD VDD net4 sky130_fd_sc_hd__buf_2
+x4 CLKIN GND GND VDD VDD net5 sky130_fd_sc_hd__buf_2
+x11 net5 GND GND VDD VDD CLK sky130_fd_sc_hd__buf_16
+x5 CLKBARIN GND GND VDD VDD net6 sky130_fd_sc_hd__buf_2
+x13 net6 GND GND VDD VDD CLKBAR sky130_fd_sc_hd__buf_16
+x6 net3 GND GND VDD VDD On sky130_fd_sc_hd__buf_16
+x7 net4 GND GND VDD VDD Op sky130_fd_sc_hd__buf_16
+**** begin user architecture code
+
+** opencircuitdesign pdks install
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+
+
+.control
+save ALL @m.x1.xm3.msky130_fd_pr__nfet_01v8[id]
+tran 0.01n 10n
+write comparator_tb.raw
+set filetype=ascii
+run
+meas tran area INTEG @m.x1.xm3.msky130_fd_pr__nfet_01v8[id] from=0 to=4ns
+let ecbit = area*1.8
+let vdiff= v(op)
+meas tran delaytime WHEN vdiff = 0.9 FALL=LAST
+meas tran clk WHEN v(clk) = 0.9 RISE=2
+let clkdelay=clk-6ns
+#meas tran tdiff TRIG AT=2ns TARG vdiff VAL=0.9 CROSS=1
+let compdelay=delaytime-6ns-clkdelay-0.385ns
+let tdelay=delaytime-6ns
+write output_comptran.txt delaytime clkdelay tdelay
+print clkdelay tdelay compdelay ecbit
+.endc
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: comparator.sym # of pins=8
+** sym_path: /home/krishna/Documents/Comparator_MPW6/xschem/comparator.sym
+** sch_path: /home/krishna/Documents/Comparator_MPW6/xschem/comparator.sch
+.subckt comparator VDD GND CLKBAR Outn Outp Vp Vn CLK
+*.iopin VDD
+*.iopin GND
+*.ipin Vn
+*.ipin Vp
+*.iopin CLK
+*.opin Outn
+*.opin Outp
+*.iopin CLKBAR
+XM1 fn Vp net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 fp Vn net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net2 CLK GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 Dn fn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 fp CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net5 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net6 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 fn CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM15 Dp Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 Dn Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM17 Dp Dn net4 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM18 Dn Dp net4 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM19 net4 CLKBAR VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 Outn Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 Outp Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 Outn Outp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 Outp Outn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 net5 fp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 fn CLKBAR net5 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 fp CLKBAR net6 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 net6 fn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 Dp fp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM10 net1 fp net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM56 net3 fn net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+.end
diff --git a/xschem/user_analog_project_wrapper.sch b/xschem/user_analog_project_wrapper.sch
new file mode 100644
index 0000000..d431b9a
--- /dev/null
+++ b/xschem/user_analog_project_wrapper.sch
@@ -0,0 +1,213 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 5060 160 5130 160 {
+lab=io_analog[3]}
+N 5060 220 5130 220 {
+lab=io_analog[2]}
+N 4380 50 4450 50 {
+lab=io_analog[8]}
+N 3530 500 3580 500 {
+lab=io_clamp_high[2:1]}
+N 3530 540 3580 540 {
+lab=io_clamp_high[2:1]}
+N 4150 -200 4150 -160 {
+lab=io_analog[8]}
+N 4150 -300 4150 -260 {
+lab=vccd1}
+N 4150 -100 4150 -60 {
+lab=vssa1}
+N 4090 -180 4150 -180 {
+lab=io_analog[8]}
+N 4150 -180 4210 -180 {
+lab=io_analog[8]}
+N 4150 700 4150 740 {
+lab=io_analog[7]}
+N 4150 600 4150 640 {
+lab=vccd1}
+N 4150 800 4150 840 {
+lab=vssa1}
+N 4090 720 4150 720 {
+lab=io_analog[7]}
+N 4150 720 4210 720 {
+lab=io_analog[7]}
+N 4640 90 4640 120 {
+lab=vccd1}
+N 4690 120 4690 140 {
+lab=#net1}
+N 4640 260 4640 290 {
+lab=vssa1}
+N 4750 350 4770 350 {
+lab=#net2}
+N 4770 250 4770 350 {
+lab=#net2}
+N 4690 250 4770 250 {
+lab=#net2}
+N 4690 240 4690 250 {
+lab=#net2}
+N 4690 50 4690 120 {
+lab=#net1}
+N 3940 130 3940 170 {
+lab=io_analog[5]}
+N 3940 30 3940 70 {
+lab=vccd1}
+N 3940 230 3940 270 {
+lab=vssa1}
+N 3880 150 3940 150 {
+lab=io_analog[5]}
+N 3940 150 4000 150 {
+lab=io_analog[5]}
+N 4180 310 4180 350 {
+lab=io_analog[6]}
+N 4180 210 4180 250 {
+lab=vccd1}
+N 4180 410 4180 450 {
+lab=vssa1}
+N 4120 330 4180 330 {
+lab=io_analog[6]}
+N 4180 330 4240 330 {
+lab=io_analog[6]}
+N 4560 150 4590 150 {
+lab=io_analog[5]}
+N 4560 220 4590 220 {
+lab=io_analog[6]}
+N 4210 -180 4360 -180 {
+lab=io_analog[8]}
+N 4360 -180 4360 50 {
+lab=io_analog[8]}
+N 4360 50 4380 50 {
+lab=io_analog[8]}
+N 4210 720 4490 720 {
+lab=io_analog[7]}
+N 4490 360 4490 720 {
+lab=io_analog[7]}
+N 4490 350 4490 360 {
+lab=io_analog[7]}
+N 4490 350 4520 350 {
+lab=io_analog[7]}
+N 4000 150 4560 150 {
+lab=io_analog[5]}
+N 4240 330 4400 330 {
+lab=io_analog[6]}
+N 4400 220 4400 330 {
+lab=io_analog[6]}
+N 4400 220 4560 220 {
+lab=io_analog[6]}
+N 4600 350 4670 350 {
+lab=#net3}
+N 4880 160 4980 160 {
+lab=#net4}
+N 4880 220 4980 220 {
+lab=#net5}
+N 4530 50 4610 50 {
+lab=#net6}
+N 4890 -80 4990 -80 {
+lab=#net7}
+N 4770 -80 4810 -80 {
+lab=io_analog[1]}
+N 5070 -80 5120 -80 {
+lab=io_analog[0]}
+C {devices/iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1}
+C {devices/iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2}
+C {devices/iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1}
+C {devices/iopin.sym} 3240 -380 0 0 {name=p4 lab=vssa2}
+C {devices/iopin.sym} 3240 -350 0 0 {name=p5 lab=vccd1}
+C {devices/iopin.sym} 3240 -320 0 0 {name=p6 lab=vccd2}
+C {devices/iopin.sym} 3240 -290 0 0 {name=p7 lab=vssd1}
+C {devices/iopin.sym} 3240 -260 0 0 {name=p8 lab=vssd2}
+C {devices/ipin.sym} 3290 -190 0 0 {name=p9 lab=wb_clk_i}
+C {devices/ipin.sym} 3290 -160 0 0 {name=p10 lab=wb_rst_i}
+C {devices/ipin.sym} 3290 -130 0 0 {name=p11 lab=wbs_stb_i}
+C {devices/ipin.sym} 3290 -100 0 0 {name=p12 lab=wbs_cyc_i}
+C {devices/ipin.sym} 3290 -70 0 0 {name=p13 lab=wbs_we_i}
+C {devices/ipin.sym} 3290 -40 0 0 {name=p14 lab=wbs_sel_i[3:0]}
+C {devices/ipin.sym} 3290 -10 0 0 {name=p15 lab=wbs_dat_i[31:0]}
+C {devices/ipin.sym} 3290 20 0 0 {name=p16 lab=wbs_adr_i[31:0]}
+C {devices/opin.sym} 3280 80 0 0 {name=p17 lab=wbs_ack_o}
+C {devices/opin.sym} 3280 110 0 0 {name=p18 lab=wbs_dat_o[31:0]}
+C {devices/ipin.sym} 3290 150 0 0 {name=p19 lab=la_data_in[127:0]}
+C {devices/opin.sym} 3280 180 0 0 {name=p20 lab=la_data_out[127:0]}
+C {devices/ipin.sym} 3290 260 0 0 {name=p21 lab=io_in[26:0]}
+C {devices/ipin.sym} 3290 290 0 0 {name=p22 lab=io_in_3v3[26:0]}
+C {devices/ipin.sym} 3280 570 0 0 {name=p23 lab=user_clock2}
+C {devices/opin.sym} 3280 320 0 0 {name=p24 lab=io_out[26:0]}
+C {devices/opin.sym} 3280 350 0 0 {name=p25 lab=io_oeb[26:0]}
+C {devices/iopin.sym} 3250 410 0 0 {name=p26 lab=gpio_analog[17:0]}
+C {devices/iopin.sym} 3250 440 0 0 {name=p27 lab=gpio_noesd[17:0]}
+C {devices/iopin.sym} 3250 470 0 0 {name=p29 lab=io_analog[10:0]}
+C {devices/iopin.sym} 3250 500 0 0 {name=p30 lab=io_clamp_high[2:0]}
+C {devices/iopin.sym} 3250 530 0 0 {name=p31 lab=io_clamp_low[2:0]}
+C {devices/opin.sym} 3270 600 0 0 {name=p32 lab=user_irq[2:0]}
+C {devices/ipin.sym} 3290 210 0 0 {name=p28 lab=la_oenb[127:0]}
+C {comparator.sym} 4740 190 0 0 {name=x1}
+C {devices/lab_pin.sym} 4640 90 0 0 {name=l1 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 4640 290 2 1 {name=l2 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 5130 160 2 0 {name=l3 sig_type=std_logic lab=io_analog[3]}
+C {devices/lab_pin.sym} 5130 220 2 0 {name=l4 sig_type=std_logic lab=io_analog[2]}
+C {devices/lab_pin.sym} 3530 500 0 0 {name=l9 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 3530 540 2 1 {name=l10 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 3580 500 2 0 {name=l11 sig_type=std_logic lab=io_clamp_high[2:1]}
+C {devices/lab_pin.sym} 3580 540 2 0 {name=l12 sig_type=std_logic lab=io_clamp_high[2:1]}
+C {sky130_fd_pr/diode.sym} 4150 -230 0 0 {name=D1
+model=diode_pd2nw_05v5
+area=1e12
+}
+C {sky130_fd_pr/diode.sym} 4150 -130 0 0 {name=D2
+model=diode_pw2nd_05v5
+area=1e12
+}
+C {devices/lab_pin.sym} 4150 -60 3 0 {name=l15 sig_type=std_logic lab=vssa1
+}
+C {devices/lab_pin.sym} 4150 -300 2 0 {name=l16 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 4090 -180 0 0 {name=l17 sig_type=std_logic lab=io_analog[8]}
+C {sky130_fd_pr/diode.sym} 4150 670 0 0 {name=D3
+model=diode_pd2nw_05v5
+area=1e12
+}
+C {sky130_fd_pr/diode.sym} 4150 770 0 0 {name=D4
+model=diode_pw2nd_05v5
+area=1e12
+}
+C {devices/lab_pin.sym} 4150 840 3 0 {name=l18 sig_type=std_logic lab=vssa1
+}
+C {devices/lab_pin.sym} 4150 600 2 0 {name=l19 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 4090 720 0 0 {name=l20 sig_type=std_logic lab=io_analog[7]}
+C {sky130_stdcells/buf_2.sym} 4840 160 0 0 {name=x2 VGND=vssa1 VNB=vssa1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__}
+C {sky130_stdcells/buf_16.sym} 5020 160 0 0 {name=x3 VGND=vssa1 VNB=vssa1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__}
+C {sky130_stdcells/buf_2.sym} 4840 220 0 0 {name=x4 VGND=vssa1 VNB=vssa1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__}
+C {sky130_stdcells/buf_16.sym} 5020 220 0 0 {name=x5 VGND=vssa1 VNB=vssa1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__}
+C {sky130_stdcells/buf_2.sym} 4560 350 0 0 {name=x6 VGND=vssa1 VNB=vssa1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__}
+C {sky130_stdcells/buf_16.sym} 4710 350 0 0 {name=x7 VGND=vssa1 VNB=vssa1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__}
+C {sky130_stdcells/buf_2.sym} 4490 50 0 0 {name=x8 VGND=vssa1 VNB=vssa1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__}
+C {sky130_stdcells/buf_16.sym} 4650 50 0 0 {name=x9 VGND=vssa1 VNB=vssa1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__}
+C {sky130_fd_pr/diode.sym} 3940 100 0 0 {name=D5
+model=diode_pd2nw_05v5
+area=1e12
+}
+C {sky130_fd_pr/diode.sym} 3940 200 0 0 {name=D6
+model=diode_pw2nd_05v5
+area=1e12
+}
+C {devices/lab_pin.sym} 3940 270 3 0 {name=l23 sig_type=std_logic lab=vssa1
+}
+C {devices/lab_pin.sym} 3940 30 2 0 {name=l24 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 3880 150 0 0 {name=l25 sig_type=std_logic lab=io_analog[5]}
+C {sky130_fd_pr/diode.sym} 4180 280 0 0 {name=D7
+model=diode_pd2nw_05v5
+area=1e12
+}
+C {sky130_fd_pr/diode.sym} 4180 380 0 0 {name=D8
+model=diode_pw2nd_05v5
+area=1e12
+}
+C {devices/lab_pin.sym} 4180 450 3 0 {name=l26 sig_type=std_logic lab=vssa1
+}
+C {devices/lab_pin.sym} 4180 210 2 0 {name=l27 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 4120 330 0 0 {name=l28 sig_type=std_logic lab=io_analog[6]}
+C {sky130_stdcells/buf_2.sym} 4850 -80 0 0 {name=x10 VGND=vssa1 VNB=vssa1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__}
+C {sky130_stdcells/buf_16.sym} 5030 -80 0 0 {name=x11 VGND=vssa1 VNB=vssa1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__}
+C {devices/lab_pin.sym} 4770 -80 0 0 {name=l5 sig_type=std_logic lab=io_analog[1]}
+C {devices/lab_pin.sym} 5120 -80 2 0 {name=l6 sig_type=std_logic lab=io_analog[0]}
diff --git a/xschem/user_analog_project_wrapper.spice b/xschem/user_analog_project_wrapper.spice
new file mode 100644
index 0000000..90f2447
--- /dev/null
+++ b/xschem/user_analog_project_wrapper.spice
@@ -0,0 +1,170 @@
+** sch_path: /home/krishna/Documents/Comparator_MPW6/xschem/user_analog_project_wrapper.sch
+**.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2 wb_clk_i
+*+ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
+*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
+*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0] wbs_ack_o
+*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
+*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
+*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
+*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
+*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0] user_clock2
+*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
+*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
+*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
+*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
+*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0] io_clamp_high[2],io_clamp_high[1],io_clamp_high[0] io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
+*+ user_irq[2],user_irq[1],user_irq[0]
+*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
+*.iopin vdda1
+*.iopin vdda2
+*.iopin vssa1
+*.iopin vssa2
+*.iopin vccd1
+*.iopin vccd2
+*.iopin vssd1
+*.iopin vssd2
+*.ipin wb_clk_i
+*.ipin wb_rst_i
+*.ipin wbs_stb_i
+*.ipin wbs_cyc_i
+*.ipin wbs_we_i
+*.ipin wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
+*.ipin
+*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
+*.ipin
+*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0]
+*.opin wbs_ack_o
+*.opin
+*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
+*.ipin
+*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
+*.opin
+*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
+*.ipin
+*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
+*.ipin
+*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0]
+*.ipin user_clock2
+*.opin
+*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
+*.opin
+*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
+*.iopin
+*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
+*.iopin
+*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
+*.iopin
+*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0]
+*.iopin io_clamp_high[2],io_clamp_high[1],io_clamp_high[0]
+*.iopin io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
+*.opin user_irq[2],user_irq[1],user_irq[0]
+*.ipin
+*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
+x1 vccd1 vssa1 net2 net8 net9 io_analog[5] io_analog[6] net1 comparator
+D1 io_analog[8] vccd1 sky130_fd_pr__diode_pd2nw_05v5 area=1e12
+D2 vssa1 io_analog[8] sky130_fd_pr__diode_pw2nd_05v5 area=1e12
+D3 io_analog[7] vccd1 sky130_fd_pr__diode_pd2nw_05v5 area=1e12
+D4 vssa1 io_analog[7] sky130_fd_pr__diode_pw2nd_05v5 area=1e12
+x2 net8 vssa1 vssa1 vccd1 vccd1 net4 sky130_fd_sc_hd__buf_2
+x3 net4 vssa1 vssa1 vccd1 vccd1 io_analog[3] sky130_fd_sc_hd__buf_16
+x4 net9 vssa1 vssa1 vccd1 vccd1 net5 sky130_fd_sc_hd__buf_2
+x5 net5 vssa1 vssa1 vccd1 vccd1 io_analog[2] sky130_fd_sc_hd__buf_16
+x6 io_analog[7] vssa1 vssa1 vccd1 vccd1 net3 sky130_fd_sc_hd__buf_2
+x7 net3 vssa1 vssa1 vccd1 vccd1 net2 sky130_fd_sc_hd__buf_16
+x8 io_analog[8] vssa1 vssa1 vccd1 vccd1 net6 sky130_fd_sc_hd__buf_2
+x9 net6 vssa1 vssa1 vccd1 vccd1 net1 sky130_fd_sc_hd__buf_16
+D5 io_analog[5] vccd1 sky130_fd_pr__diode_pd2nw_05v5 area=1e12
+D6 vssa1 io_analog[5] sky130_fd_pr__diode_pw2nd_05v5 area=1e12
+D7 io_analog[6] vccd1 sky130_fd_pr__diode_pd2nw_05v5 area=1e12
+D8 vssa1 io_analog[6] sky130_fd_pr__diode_pw2nd_05v5 area=1e12
+x10 io_analog[1] vssa1 vssa1 vccd1 vccd1 net7 sky130_fd_sc_hd__buf_2
+x11 net7 vssa1 vssa1 vccd1 vccd1 io_analog[0] sky130_fd_sc_hd__buf_16
+**.ends
+
+* expanding symbol: comparator.sym # of pins=8
+** sym_path: /home/krishna/Documents/Comparator_MPW6/xschem/comparator.sym
+** sch_path: /home/krishna/Documents/Comparator_MPW6/xschem/comparator.sch
+.subckt comparator VDD GND CLKBAR Outn Outp Vp Vn CLK
+*.iopin VDD
+*.iopin GND
+*.ipin Vp
+*.ipin Vn
+*.iopin CLK
+*.opin Outp
+*.opin Outn
+*.iopin CLKBAR
+XM1 fn Vn net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 fp Vp net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net2 CLK GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 Dp fn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 fp CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net5 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net6 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 fn CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM15 Dp Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 Dn Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM17 Dp Dn net4 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM18 Dn Dp net4 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM19 net4 CLKBAR VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 Outp Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 Outn Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 Outp Outn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 Outn Outp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 net5 fp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 fn CLKBAR net5 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 fp CLKBAR net6 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 net6 fn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 Dn fp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM10 net1 fp net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM56 net3 fn net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.end
diff --git a/xschem/user_analog_project_wrapper.sym b/xschem/user_analog_project_wrapper.sym
new file mode 100644
index 0000000..6cb4d88
--- /dev/null
+++ b/xschem/user_analog_project_wrapper.sym
@@ -0,0 +1,108 @@
+v {xschem version=3.0.0 file_version=1.2}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+
+T {@symname} -139.5 -6 0 0 0.3 0.3 {}
+T {@name} 135 -202 0 0 0.2 0.2 {}
+L 4 -130 -190 130 -190 {}
+L 4 -130 190 130 190 {}
+L 4 -130 -190 -130 190 {}
+L 4 130 -190 130 190 {}
+B 5 147.5 -182.5 152.5 -177.5 {name=vdda1 dir=inout }
+L 7 130 -180 150 -180 {}
+T {vdda1} 125 -184 0 1 0.2 0.2 {}
+B 5 147.5 -162.5 152.5 -157.5 {name=vdda2 dir=inout }
+L 7 130 -160 150 -160 {}
+T {vdda2} 125 -164 0 1 0.2 0.2 {}
+B 5 147.5 -142.5 152.5 -137.5 {name=vssa1 dir=inout }
+L 7 130 -140 150 -140 {}
+T {vssa1} 125 -144 0 1 0.2 0.2 {}
+B 5 147.5 -122.5 152.5 -117.5 {name=vssa2 dir=inout }
+L 7 130 -120 150 -120 {}
+T {vssa2} 125 -124 0 1 0.2 0.2 {}
+B 5 147.5 -102.5 152.5 -97.5 {name=vccd1 dir=inout }
+L 7 130 -100 150 -100 {}
+T {vccd1} 125 -104 0 1 0.2 0.2 {}
+B 5 147.5 -82.5 152.5 -77.5 {name=vccd2 dir=inout }
+L 7 130 -80 150 -80 {}
+T {vccd2} 125 -84 0 1 0.2 0.2 {}
+B 5 147.5 -62.5 152.5 -57.5 {name=vssd1 dir=inout }
+L 7 130 -60 150 -60 {}
+T {vssd1} 125 -64 0 1 0.2 0.2 {}
+B 5 147.5 -42.5 152.5 -37.5 {name=vssd2 dir=inout }
+L 7 130 -40 150 -40 {}
+T {vssd2} 125 -44 0 1 0.2 0.2 {}
+B 5 -152.5 -182.5 -147.5 -177.5 {name=wb_clk_i dir=in }
+L 4 -150 -180 -130 -180 {}
+T {wb_clk_i} -125 -184 0 0 0.2 0.2 {}
+B 5 -152.5 -162.5 -147.5 -157.5 {name=wb_rst_i dir=in }
+L 4 -150 -160 -130 -160 {}
+T {wb_rst_i} -125 -164 0 0 0.2 0.2 {}
+B 5 -152.5 -142.5 -147.5 -137.5 {name=wbs_stb_i dir=in }
+L 4 -150 -140 -130 -140 {}
+T {wbs_stb_i} -125 -144 0 0 0.2 0.2 {}
+B 5 -152.5 -122.5 -147.5 -117.5 {name=wbs_cyc_i dir=in }
+L 4 -150 -120 -130 -120 {}
+T {wbs_cyc_i} -125 -124 0 0 0.2 0.2 {}
+B 5 -152.5 -102.5 -147.5 -97.5 {name=wbs_we_i dir=in }
+L 4 -150 -100 -130 -100 {}
+T {wbs_we_i} -125 -104 0 0 0.2 0.2 {}
+B 5 -152.5 -82.5 -147.5 -77.5 {name=wbs_sel_i[3:0] dir=in }
+L 4 -150 -80 -130 -80 {}
+T {wbs_sel_i[3:0]} -125 -84 0 0 0.2 0.2 {}
+B 5 -152.5 -62.5 -147.5 -57.5 {name=wbs_dat_i[31:0] dir=in }
+L 4 -150 -60 -130 -60 {}
+T {wbs_dat_i[31:0]} -125 -64 0 0 0.2 0.2 {}
+B 5 -152.5 -42.5 -147.5 -37.5 {name=wbs_adr_i[31:0] dir=in }
+L 4 -150 -40 -130 -40 {}
+T {wbs_adr_i[31:0]} -125 -44 0 0 0.2 0.2 {}
+B 5 147.5 -22.5 152.5 -17.5 {name=wbs_ack_o dir=out }
+L 4 130 -20 150 -20 {}
+T {wbs_ack_o} 125 -24 0 1 0.2 0.2 {}
+B 5 147.5 -2.5 152.5 2.5 {name=wbs_dat_o[31:0] dir=out }
+L 4 130 0 150 0 {}
+T {wbs_dat_o[31:0]} 125 -4 0 1 0.2 0.2 {}
+B 5 -152.5 -22.5 -147.5 -17.5 {name=la_data_in[127:0] dir=in }
+L 4 -150 -20 -130 -20 {}
+T {la_data_in[127:0]} -125 -24 0 0 0.2 0.2 {}
+B 5 147.5 17.5 152.5 22.5 {name=la_data_out[127:0] dir=out }
+L 4 130 20 150 20 {}
+T {la_data_out[127:0]} 125 16 0 1 0.2 0.2 {}
+B 5 -152.5 -2.5 -147.5 2.5 {name=la_oenb[127:0] dir=in }
+L 4 -150 0 -130 0 {}
+T {la_oenb[127:0]} -125 -4 0 0 0.2 0.2 {}
+B 5 -152.5 17.5 -147.5 22.5 {name=io_in[26:0] dir=in }
+L 4 -150 20 -130 20 {}
+T {io_in[26:0]} -125 16 0 0 0.2 0.2 {}
+B 5 -152.5 37.5 -147.5 42.5 {name=io_in_3v3[26:0] dir=in }
+L 4 -150 40 -130 40 {}
+T {io_in_3v3[26:0]} -125 36 0 0 0.2 0.2 {}
+B 5 147.5 37.5 152.5 42.5 {name=io_out[26:0] dir=out }
+L 4 130 40 150 40 {}
+T {io_out[26:0]} 125 36 0 1 0.2 0.2 {}
+B 5 147.5 57.5 152.5 62.5 {name=io_oeb[26:0] dir=out }
+L 4 130 60 150 60 {}
+T {io_oeb[26:0]} 125 56 0 1 0.2 0.2 {}
+B 5 147.5 77.5 152.5 82.5 {name=gpio_analog[17:0] dir=inout }
+L 7 130 80 150 80 {}
+T {gpio_analog[17:0]} 125 76 0 1 0.2 0.2 {}
+B 5 147.5 97.5 152.5 102.5 {name=gpio_noesd[17:0] dir=inout }
+L 7 130 100 150 100 {}
+T {gpio_noesd[17:0]} 125 96 0 1 0.2 0.2 {}
+B 5 147.5 117.5 152.5 122.5 {name=io_analog[10:0] dir=inout }
+L 7 130 120 150 120 {}
+T {io_analog[10:0]} 125 116 0 1 0.2 0.2 {}
+B 5 147.5 137.5 152.5 142.5 {name=io_clamp_high[2:0] dir=inout }
+L 7 130 140 150 140 {}
+T {io_clamp_high[2:0]} 125 136 0 1 0.2 0.2 {}
+B 5 147.5 157.5 152.5 162.5 {name=io_clamp_low[2:0] dir=inout }
+L 7 130 160 150 160 {}
+T {io_clamp_low[2:0]} 125 156 0 1 0.2 0.2 {}
+B 5 -152.5 57.5 -147.5 62.5 {name=user_clock2 dir=in }
+L 4 -150 60 -130 60 {}
+T {user_clock2} -125 56 0 0 0.2 0.2 {}
+B 5 147.5 177.5 152.5 182.5 {name=user_irq[2:0] dir=out }
+L 4 130 180 150 180 {}
+T {user_irq[2:0]} 125 176 0 1 0.2 0.2 {}
diff --git a/xschem/xschemrc b/xschem/xschemrc
new file mode 100755
index 0000000..7e7fb8b
--- /dev/null
+++ b/xschem/xschemrc
@@ -0,0 +1,322 @@
+#### xschemrc system configuration file
+
+#### values may be overridden by user's ~/.xschem/xschemrc configuration file
+#### or by project-local ./xschemrc
+
+###########################################################################
+#### XSCHEM INSTALLATION DIRECTORY: XSCHEM_SHAREDIR
+###########################################################################
+#### Normally there is no reason to set this variable if using standard
+#### installation. Location of files is set at compile time but may be overridden
+#### with following line:
+# set XSCHEM_SHAREDIR $env(HOME)/share/xschem
+
+###########################################################################
+#### XSCHEM SYSTEM-WIDE DESIGN LIBRARY PATHS: XSCHEM_LIBRARY_PATH
+###########################################################################
+#### If unset xschem starts with XSCHEM_LIBRARY_PATH set to the default, typically:
+# /home/schippes/.xschem/xschem_library
+# /home/schippes/share/xschem/xschem_library/devices
+# /home/schippes/share/doc/xschem/examples
+# /home/schippes/share/doc/xschem/ngspice
+# /home/schippes/share/doc/xschem/logic
+# /home/schippes/share/doc/xschem/xschem_simulator
+# /home/schippes/share/doc/xschem/binto7seg
+# /home/schippes/share/doc/xschem/pcb
+# /home/schippes/share/doc/xschem/rom8k
+
+
+#### Flush any previous definition
+set XSCHEM_LIBRARY_PATH {}
+#### include devices/*.sym
+append XSCHEM_LIBRARY_PATH :${XSCHEM_SHAREDIR}/xschem_library
+#### include skywater libraries. Here i use [pwd]. This works if i start xschem from here.
+append XSCHEM_LIBRARY_PATH :$env(PWD)
+append XSCHEM_LIBRARY_PATH :/usr/local/share/pdk/sky130A/libs.tech/xschem
+# append XSCHEM_LIBRARY_PATH :/mnt/sda7/home/schippes/pdks/sky130A/libs.tech/xschem
+#### add ~/.xschem/xschem_library (USER_CONF_DIR is normally ~/.xschem)
+append XSCHEM_LIBRARY_PATH :$USER_CONF_DIR/xschem_library
+
+###########################################################################
+#### SET CUSTOM COLORS FOR XSCHEM LIBRARIES MATCHING CERTAIN PATTERNS
+###########################################################################
+#### each line contains a dircolor(pattern) followed by a color
+#### color can be an ordinary name (grey, brown, blue) or a hex code {#77aaff}
+#### hex code must be enclosed in braces
+array unset dircolor
+set dircolor(sky130_fd_pr$) blue
+set dircolor(sky130_tests$) blue
+set dircolor(xschem_sky130$) blue
+set dircolor(xschem_library$) red
+set dircolor(devices$) red
+
+###########################################################################
+#### WINDOW TO OPEN ON STARTUP: XSCHEM_START_WINDOW
+###########################################################################
+#### Start without a design if no filename given on command line:
+#### To avoid absolute paths, use a path that is relative to one of the
+#### XSCHEM_LIBRARY_PATH directories. Default: empty
+set XSCHEM_START_WINDOW {sky130_tests/top.sch}
+
+###########################################################################
+#### DIRECTORY WHERE SIMULATIONS, NETLIST AND SIMULATOR OUTPUTS ARE PLACED
+###########################################################################
+#### If unset $USER_CONF_DIR/simulations is assumed (normally ~/.xschem/simulations)
+# set netlist_dir $env(HOME)/.xschem/simulations
+set netlist_dir $env(PWD)
+
+###########################################################################
+#### NETLIST AND HIERARCHICAL PRINT EXCLUDE PATTERNS
+###########################################################################
+#### xschem_libs is a list of patterns of cells to exclude from netlisting.
+#### Matching is done as regular expression on full cell path
+#### Example:
+#### set xschem_libs { {/cmoslib/} {/analoglib/.*pass} buffer }
+#### in this case all schematic cells of directory cmoslib and cells containing
+#### /analoglib/...pass and buffer will be excluded from netlisting
+#### default value: empty
+# set xschem_libs {}
+#### noprint_libs is a list with same rules as for xschem_libs. This
+#### variable controls hierarchical print
+#### default value: empty
+# set noprint_libs {}
+
+###########################################################################
+#### CHANGE DEFAULT [] WITH SOME OTHER CHARACTERS FOR BUSSED SIGNALS
+#### IN SPICE NETLISTS (EXAMPLE: DATA[7] --> DATA<7>)
+###########################################################################
+#### default: empty (use xschem default, [ ])
+# set bus_replacement_char {<>}
+#### for XSPICE: replace square brackets as the are used for XSPICE vector nodes.
+# set bus_replacement_char {__}
+
+###########################################################################
+#### SOME DEFAULT BEHAVIOR
+###########################################################################
+#### Allowed values: spice, verilog, vhdl, tedax, default: spice
+# set netlist_type spice
+
+#### Some netlisting options (these are the defaults)
+# set hspice_netlist 1
+# set verilog_2001 1
+
+#### to use a fixed line with set change_lw to 0 and set some value to line_width
+#### these are the defaults
+# set line_width 0
+# set change_lw 1
+
+#### allow color postscript and svg exports. Default: 1, enable color
+# set color_ps 1
+
+#### initial size of xschem window you can specify also position with (wxh+x+y)
+#### this is the default:
+# set initial_geometry {900x600}
+
+#### if set to 0, when zooming out allow the viewport do drift toward the mouse position,
+#### allowing to move away by zooming / unzooming with mouse wheel
+#### default setting: 0
+# set unzoom_nodrift 0
+
+#### if set to 1 allow to place multiple components with same name.
+#### Warning: this is normally not allowed in any simulation netlist.
+#### default: 0, do not allow place multiple elements with same name (refdes)
+# set disable_unique_names 0
+
+#### if set to 1 continue drawing lines / wires after click
+#### default: 0
+# set persistent_command 1
+
+#### if set to 1 a wire is inserted when separating components that are
+#### connected by pins. Default: not enabled (0)
+# set connect_by_kissing 1
+
+#### if set to 1 automatically join/trim wires while editing
+#### this may slow down on rally big designs. Can be disabled via menu
+#### default: 0
+# set autotrim_wires 0
+
+#### set widget scaling (mainly for font display), this is useful on 4K displays
+#### default: unset (tk uses its default) > 1.0 ==> bigger
+# set tk_scaling 1.7
+
+#### disable some symbol layers. Default: none, all layers are visible.
+# set enable_layer(5) 0 ;# example to disable pin red boxes
+
+#### enable to scale grid point size as done with lines at close zoom, default: 0
+# set big_grid_points 0
+
+###########################################################################
+#### EXPORT FORMAT TRANSLATORS, PNG AND PDF
+###########################################################################
+#### command to translate xpm to png; (assumes command takes source
+#### and dest file as arguments, example: gm convert plot.xpm plot.png)
+#### default: {gm convert}
+# set to_png {gm convert}
+
+#### command to translate ps to pdf; (assumes command takes source
+#### and dest file as arguments, example: ps2pdf plot.ps plot.pdf)
+#### default: ps2pdf
+# set to_pdf ps2pdf
+set to_pdf {ps2pdf -dAutoRotatePages=/None}
+
+###########################################################################
+#### UNDO: SAVE ON DISK OR KEEP IN MEMORY
+###########################################################################
+#### Alloved: 'disk'or 'memory'.
+#### Saving undo on disk is safer but slower on extremely big schematics.
+#### In most cases you won't notice any delay. Undo on disk allows previous
+#### state recovery in case of crashes. In-memory undo is extremely fast
+#### but should a crash occur everything is lost.
+#### It is highly recommended to keep undo on disk.
+#### Default: disk
+# set undo_type disk
+
+###########################################################################
+#### CUSTOM GRID / SNAP VALUE SETTINGS
+###########################################################################
+#### Warning: changing these values will likely break compatibility
+#### with existing symbol libraries. Defaults: grid 20, snap 10.
+# set grid 20
+# set snap 10
+
+###########################################################################
+#### CUSTOM COLORS MAY BE DEFINED HERE
+###########################################################################
+# set cadlayers 22
+# set light_colors {
+# "#ffffff" "#0044ee" "#aaaaaa" "#222222" "#229900"
+# "#bb2200" "#00ccee" "#ff0000" "#888800" "#00aaaa"
+# "#880088" "#00ff00" "#0000cc" "#666600" "#557755"
+# "#aa2222" "#7ccc40" "#00ffcc" "#ce0097" "#d2d46b"
+# "#ef6158" "#fdb200" }
+
+# set dark_colors {
+# "#000000" "#00ccee" "#3f3f3f" "#cccccc" "#88dd00"
+# "#bb2200" "#00ccee" "#ff0000" "#ffff00" "#ffffff"
+# "#ff00ff" "#00ff00" "#0000cc" "#aaaa00" "#aaccaa"
+# "#ff7777" "#bfff81" "#00ffcc" "#ce0097" "#d2d46b"
+# "#ef6158" "#fdb200" }
+
+###########################################################################
+#### CAIRO STUFF
+###########################################################################
+#### Scale all fonts by this number
+# set cairo_font_scale 1.0
+
+#### default for following two is 0.85 (xscale) and 0.88 (yscale) to
+#### match cairo font spacing
+# set nocairo_font_xscale 1.0
+#### set nocairo_font_yscale 1.0
+
+#### Scale line spacing by this number
+# set cairo_font_line_spacing 1.0
+
+#### Specify a font
+# set cairo_font_name {Sans-Serif}
+# set svg_font_name {Sans-Serif}
+
+#### Lift up text by some zoom-corrected pixels for
+#### better compatibility wrt no cairo version.
+#### Useful values in the range [-1, 3]
+# set cairo_vert_correct 0
+# set nocairo_vert_correct 0
+
+###########################################################################
+#### KEYBINDINGS
+###########################################################################
+#### General format for specifying a replacement for a keybind
+#### Replace Ctrl-d with Escape (so you wont kill the program)
+# set replace_key(Control-d) Escape
+
+#### swap w and W keybinds; Always specify Shift for capital letters
+# set replace_key(Shift-W) w
+# set replace_key(w) Shift-W
+
+###########################################################################
+#### TERMINAL
+###########################################################################
+#### default for linux: xterm
+# set terminal {xterm -geometry 100x35 -fn 9x15 -bg black -fg white -cr white -ms white }
+#### lxterminal is not OK since it will not inherit env vars:
+#### In order to reduce memory usage and increase the performance, all instances
+#### of the lxterminal are sharing a single process. LXTerminal is part of LXDE
+
+###########################################################################
+#### EDITOR
+###########################################################################
+#### editor must not detach from launching shell (-f mandatory for gvim)
+#### default for linux: gvim -f
+# set editor {gvim -f -geometry 90x28}
+# set editor { xterm -geometry 100x40 -e nano }
+# set editor { xterm -geometry 100x40 -e pico }
+
+#### For Windows
+# set editor {notepad.exe}
+
+###########################################################################
+#### SHOW ERC INFO WINDOW (erc errors, warnings etc)
+###########################################################################
+#### default: 0 (can be enabled by menu)
+# set show_infowindow 0
+
+###########################################################################
+#### CONFIGURE COMPUTER FARM JOB REDIRECTORS FOR SIMULATIONS
+###########################################################################
+#### RTDA NC
+# set computerfarm {nc run -Il}
+#### LSF BSUB
+# set computerfarm {bsub -Is}
+
+###########################################################################
+#### TCP CONNECTION WITH GAW
+###########################################################################
+#### set gaw address for socket connection: {host port}
+#### default: set to localhost, port 2020
+# set gaw_tcp_address {localhost 2020}
+
+###########################################################################
+#### XSCHEM LISTEN TO TCP PORT
+###########################################################################
+#### set xschem listening port; default: not enabled
+# set xschem_listen_port 2021
+
+###########################################################################
+#### BESPICE WAVE SOCKET CONNECTION
+###########################################################################
+#### set bespice wave listening port; default: not enabled
+set bespice_listen_port 2022
+
+###########################################################################
+#### TCL FILES TO LOAD AT STARTUP
+###########################################################################
+#### list of tcl files to preload.
+# lappend tcl_files ${XSCHEM_SHAREDIR}/change_index.tcl
+lappend tcl_files ${XSCHEM_SHAREDIR}/ngspice_backannotate.tcl
+
+###########################################################################
+#### XSCHEM TOOLBAR
+###########################################################################
+#### default: not enabled.
+set toolbar_visible 1
+# set toolbar_horiz 1
+
+###########################################################################
+#### TABBED WINDOWS
+###########################################################################
+# default: not enabled. Interface can be changed runtime if only one window
+# or tab is open.
+set tabbed_interface 1
+
+###########################################################################
+#### SKYWATER PDK SPECIFIC VARIABLES
+###########################################################################
+
+## (spice patched) skywater-pdk install
+# set SKYWATER_MODELS ~/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest
+# set SKYWATER_STDCELLS ~/skywater-pdk/libraries/sky130_fd_sc_hd/latest
+
+## opencircuitdesign pdks install. You need to change these to point to your open_pdks installation
+set SKYWATER_MODELS /usr/local/share/pdk/sky130A/libs.tech/ngspice
+set SKYWATER_STDCELLS /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice
+#set SKYWATER_MODELS $env(HOME)/share/pdk/sky130A/libs.tech/ngspice
+#set SKYWATER_STDCELLS $env(HOME)/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice
