blob: 98f672ee1a6479ea606d3c6503c5c12185ef080c [file] [log] [blame]
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
0,/home/hung/caravel_mpw6b/caravel_example/openlane/user_proj_example,user_proj_example,user_proj_example,flow completed,1h7m50s0ms,0h37m33s0ms,98401.80789845923,1.1144104193000002,29520.54236953777,30.64,5461.5,32898,0,0,0,0,0,0,0,26,0,0,-1,1702529,263185,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,1438232445.0,0.0,48.31,45.04,18.31,19.74,-1,35815,40688,941,5550,0,0,0,36946,261,334,170,1801,4769,10081,2702,1574,1041,1035,40,764,15360,0,16124,14.285714285714286,70.0,70,AREA 0,8,30,1,153.6,153.18,0.35,0.3,sky130_fd_sc_hd,4,4