updated to mpw-6c
diff --git a/Makefile b/Makefile index 6e936b8..25b3ce0 100644 --- a/Makefile +++ b/Makefile
@@ -26,9 +26,9 @@ export OPENLANE_TAG=2022.02.23_02.50.41 # Install lite version of caravel, (1): caravel-lite, (0): caravel -CARAVEL_LITE?=1 +CARAVEL_LITE?=0 -MPW_TAG ?= mpw-6b +MPW_TAG ?= mpw-6c ifeq ($(CARAVEL_LITE),1) CARAVEL_NAME := caravel-lite
diff --git a/gds/pwm_top.gds.gz b/gds/pwm_top.gds.gz index 558aa8b..c61bb26 100644 --- a/gds/pwm_top.gds.gz +++ b/gds/pwm_top.gds.gz Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz index 92ac4d1..5c8cfe5 100644 --- a/gds/user_project_wrapper.gds.gz +++ b/gds/user_project_wrapper.gds.gz Binary files differ
diff --git a/sdc/pwm_top.sdc b/sdc/pwm_top.sdc index fd039d3..3ca6d9a 100644 --- a/sdc/pwm_top.sdc +++ b/sdc/pwm_top.sdc
@@ -1,6 +1,6 @@ ############################################################################### # Created by write_sdc -# Wed Apr 27 11:55:03 2022 +# Fri May 6 16:54:16 2022 ############################################################################### current_design pwm_top ###############################################################################
diff --git a/sdc/user_project_wrapper.sdc b/sdc/user_project_wrapper.sdc index 92ec600..a5cd96f 100644 --- a/sdc/user_project_wrapper.sdc +++ b/sdc/user_project_wrapper.sdc
@@ -1,6 +1,6 @@ ############################################################################### # Created by write_sdc -# Wed Apr 27 12:31:43 2022 +# Fri May 6 17:23:26 2022 ############################################################################### current_design user_project_wrapper ###############################################################################
diff --git a/sdf/pwm_top.sdf b/sdf/pwm_top.sdf index fcc8428..3adeb1a 100644 --- a/sdf/pwm_top.sdf +++ b/sdf/pwm_top.sdf
@@ -1,7 +1,7 @@ (DELAYFILE (SDFVERSION "3.0") (DESIGN "pwm_top") - (DATE "Wed Apr 27 12:08:58 2022") + (DATE "Fri May 6 17:03:58 2022") (VENDOR "Parallax") (PROGRAM "STA") (VERSION "2.3.1")
diff --git a/sdf/user_project_wrapper.sdf b/sdf/user_project_wrapper.sdf index 2ad5369..2b0b157 100644 --- a/sdf/user_project_wrapper.sdf +++ b/sdf/user_project_wrapper.sdf
@@ -1,7 +1,7 @@ (DELAYFILE (SDFVERSION "3.0") (DESIGN "user_project_wrapper") - (DATE "Wed Apr 27 12:33:53 2022") + (DATE "Fri May 6 17:25:19 2022") (VENDOR "Parallax") (PROGRAM "STA") (VERSION "2.3.1")
diff --git a/signoff/pwm/final_summary_report.csv b/signoff/pwm/final_summary_report.csv index 6d6fb04..740295a 100644 --- a/signoff/pwm/final_summary_report.csv +++ b/signoff/pwm/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/home/serdar/Desktop/pwm/pwm_openmpw/openlane/pwm,pwm_top,pwm,flow completed,0h41m57s0ms,0h21m38s0ms,22280.193236714982,2.3,4010.4347826086964,3.46,8027.53,9224,0,0,0,0,0,0,0,66,0,0,-1,940312,112816,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,785513655.0,0.0,14.95,5.87,6.31,0.23,-1,6885,15864,382,9291,0,0,0,7477,154,0,245,304,647,814,417,898,918,875,27,718,31948,0,32666,26.31578947368421,38.0,38,AREA 1,3,18,1,100,153.18,0.14,0.3,sky130_fd_sc_hd,8,3 +0,/home/serdar/Desktop/pwm/pwm_openmpw/openlane/pwm,pwm_top,pwm,flow completed,0h33m52s0ms,0h16m25s0ms,22280.193236714982,2.3,4010.4347826086964,3.46,8711.29,9224,0,0,0,0,0,0,0,66,0,0,-1,940312,112816,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,785513655.0,0.0,14.95,5.87,6.31,0.23,-1,6885,15864,382,9291,0,0,0,7477,154,0,245,304,647,814,417,898,918,875,27,718,31948,0,32666,26.31578947368421,38.0,38,AREA 1,3,18,1,100,153.18,0.14,0.3,sky130_fd_sc_hd,8,3
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index 8ee5b94..5bf5713 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/home/serdar/Desktop/pwm/pwm_openmpw/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h18m43s0ms,0h3m51s0ms,-2.0,-1,-1,-1,477.62,1,0,0,0,0,0,0,0,0,0,-1,-1,864104,1788,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,0.76,6.24,0.02,0.0,0.0,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,26.31578947368421,38.0,38,AREA 0,5,50,1,180,180,0.55,0.3,sky130_fd_sc_hd,4,0 +0,/home/serdar/Desktop/pwm/pwm_openmpw/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h16m8s0ms,0h3m12s0ms,-2.0,-1,-1,-1,477.73,1,0,0,0,0,0,0,0,0,0,-1,-1,864104,1788,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,0.76,6.24,0.02,0.0,0.0,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,26.31578947368421,38.0,38,AREA 0,5,50,1,180,180,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v index 2f6c7fd..5734d7f 100644 --- a/verilog/dv/wb_port/wb_port_tb.v +++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -17,9 +17,9 @@ `timescale 1 ns / 1 ps `define MPRJ_IO_PADS 38 -//`include "uprj_netlists.v" -`include "../../../caravel/verilog/rtl/caravel_netlists.v" -`include "../../../mgmt_core_wrapper/verilog/dv/vip/spiflash.v" // uncomment if RTL, comment if GL +// `include "uprj_netlists.v" +// `include "../../../caravel/verilog/rtl/caravel_netlists.v" +// `include "../../../mgmt_core_wrapper/verilog/dv/vip/spiflash.v" // uncomment if RTL, comment if GL module wb_port_tb; reg clock;