| |
| /----------------------------------------------------------------------------\ |
| | | |
| | yosys -- Yosys Open SYnthesis Suite | |
| | | |
| | Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> | |
| | | |
| | Permission to use, copy, modify, and/or distribute this software for any | |
| | purpose with or without fee is hereby granted, provided that the above | |
| | copyright notice and this permission notice appear in all copies. | |
| | | |
| | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| | | |
| \----------------------------------------------------------------------------/ |
| |
| Yosys 0.12+45 (git sha1 UNKNOWN, gcc 8.3.1 -fPIC -Os) |
| |
| [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. |
| |
| 1. Executing Verilog-2005 frontend: /home/serdar/Desktop/openram_demo/openram_openmpw/caravel/verilog/rtl/defines.v |
| Parsing SystemVerilog input from `/home/serdar/Desktop/openram_demo/openram_openmpw/caravel/verilog/rtl/defines.v' to AST representation. |
| Successfully finished Verilog frontend. |
| |
| 2. Executing Verilog-2005 frontend: /home/serdar/pdks/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v |
| Parsing SystemVerilog input from `/home/serdar/pdks/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v' to AST representation. |
| Generating RTLIL representation for module `\sky130_sram_2kbyte_1rw1r_32x512_8'. |
| /home/serdar/pdks/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v:0: Warning: System task `$display' outside initial block is unsupported. |
| /home/serdar/pdks/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v:0: Warning: System task `$display' outside initial block is unsupported. |
| /home/serdar/pdks/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v:0: Warning: System task `$display' outside initial block is unsupported. |
| /home/serdar/pdks/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v:0: Warning: System task `$display' outside initial block is unsupported. |
| Successfully finished Verilog frontend. |
| |
| 3. Executing Verilog-2005 frontend: /home/serdar/Desktop/openram_demo/openram_openmpw/caravel/verilog/rtl/defines.v |
| Parsing SystemVerilog input from `/home/serdar/Desktop/openram_demo/openram_openmpw/caravel/verilog/rtl/defines.v' to AST representation. |
| Successfully finished Verilog frontend. |
| |
| 4. Executing Verilog-2005 frontend: /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v |
| Parsing SystemVerilog input from `/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v' to AST representation. |
| Generating RTLIL representation for module `\user_project_wrapper'. |
| Successfully finished Verilog frontend. |
| |
| 5. Generating Graphviz representation of design. |
| Writing dot description to `/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/synthesis/hierarchy.dot'. |
| Dumping module user_project_wrapper to page 1. |
| |
| 6. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 6.1. Analyzing design hierarchy.. |
| Top module: \user_project_wrapper |
| |
| 6.2. Analyzing design hierarchy.. |
| Top module: \user_project_wrapper |
| Removed 0 unused modules. |
| |
| 7. Executing TRIBUF pass. |
| |
| 8. Executing SYNTH pass. |
| |
| 8.1. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 8.1.1. Analyzing design hierarchy.. |
| Top module: \user_project_wrapper |
| |
| 8.1.2. Analyzing design hierarchy.. |
| Top module: \user_project_wrapper |
| Removed 0 unused modules. |
| |
| 8.2. Executing PROC pass (convert processes to netlists). |
| |
| 8.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Cleaned up 0 empty switches. |
| |
| 8.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). |
| Removed 1 dead cases from process $proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:0$101 in module user_project_wrapper. |
| Marked 1 switch rules as full_case in process $proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:0$101 in module user_project_wrapper. |
| Marked 1 switch rules as full_case in process $proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:200$36 in module user_project_wrapper. |
| Removed a total of 1 dead cases. |
| |
| 8.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). |
| Removed 1 redundant assignment. |
| Promoted 9 assignments to connections. |
| |
| 8.2.4. Executing PROC_INIT pass (extract init attributes). |
| |
| 8.2.5. Executing PROC_ARST pass (detect async resets in processes). |
| |
| 8.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers). |
| Creating decoders for process `\user_project_wrapper.$proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:0$104'. |
| Creating decoders for process `\user_project_wrapper.$proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:0$101'. |
| 1/1: $1$mem2reg_rd$\sram0_dout1$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:116$29_DATA[31:0]$103 |
| Creating decoders for process `\user_project_wrapper.$proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:200$36'. |
| 1/1: $0\ready_q[0:0] |
| |
| 8.2.7. Executing PROC_DLATCH pass (convert process syncs to latches). |
| No latch inferred for signal `\user_project_wrapper.\sram0_dout0[0]' from process `\user_project_wrapper.$proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:0$104'. |
| No latch inferred for signal `\user_project_wrapper.\sram0_dout0[1]' from process `\user_project_wrapper.$proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:0$104'. |
| No latch inferred for signal `\user_project_wrapper.\sram0_dout0[2]' from process `\user_project_wrapper.$proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:0$104'. |
| No latch inferred for signal `\user_project_wrapper.\sram0_dout0[3]' from process `\user_project_wrapper.$proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:0$104'. |
| No latch inferred for signal `\user_project_wrapper.\sram0_dout1[0]' from process `\user_project_wrapper.$proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:0$104'. |
| No latch inferred for signal `\user_project_wrapper.\sram0_dout1[1]' from process `\user_project_wrapper.$proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:0$104'. |
| No latch inferred for signal `\user_project_wrapper.\sram0_dout1[2]' from process `\user_project_wrapper.$proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:0$104'. |
| No latch inferred for signal `\user_project_wrapper.\sram0_dout1[3]' from process `\user_project_wrapper.$proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:0$104'. |
| No latch inferred for signal `\user_project_wrapper.$mem2reg_rd$\sram0_dout1$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:116$29_DATA' from process `\user_project_wrapper.$proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:0$101'. |
| |
| 8.2.8. Executing PROC_DFF pass (convert process syncs to FFs). |
| Creating register for signal `\user_project_wrapper.\ready_q' using process `\user_project_wrapper.$proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:200$36'. |
| created $dff cell `$procdff$115' with positive edge clock. |
| |
| 8.2.9. Executing PROC_MEMWR pass (convert process memory writes to cells). |
| |
| 8.2.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Removing empty process `user_project_wrapper.$proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:0$104'. |
| Found and cleaned up 1 empty switch in `\user_project_wrapper.$proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:0$101'. |
| Removing empty process `user_project_wrapper.$proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:0$101'. |
| Found and cleaned up 2 empty switches in `\user_project_wrapper.$proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:200$36'. |
| Removing empty process `user_project_wrapper.$proc$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:200$36'. |
| Cleaned up 3 empty switches. |
| |
| 8.2.11. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module user_project_wrapper. |
| <suppressed ~5 debug messages> |
| |
| 8.3. Executing FLATTEN pass (flatten design). |
| |
| 8.4. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module user_project_wrapper. |
| |
| 8.5. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| Removed 2 unused cells and 47 unused wires. |
| <suppressed ~4 debug messages> |
| |
| 8.6. Executing CHECK pass (checking for obvious problems). |
| Checking module user_project_wrapper... |
| Found and reported 0 problems. |
| |
| 8.7. Executing OPT pass (performing simple optimizations). |
| |
| 8.7.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module user_project_wrapper. |
| |
| 8.7.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\user_project_wrapper'. |
| <suppressed ~87 debug messages> |
| Removed a total of 29 cells. |
| |
| 8.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \user_project_wrapper.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~4 debug messages> |
| |
| 8.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \user_project_wrapper. |
| Performed a total of 0 changes. |
| |
| 8.7.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\user_project_wrapper'. |
| Removed a total of 0 cells. |
| |
| 8.7.6. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 8.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| Removed 0 unused cells and 29 unused wires. |
| <suppressed ~1 debug messages> |
| |
| 8.7.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module user_project_wrapper. |
| |
| 8.7.9. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 8.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \user_project_wrapper.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~4 debug messages> |
| |
| 8.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \user_project_wrapper. |
| Performed a total of 0 changes. |
| |
| 8.7.12. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\user_project_wrapper'. |
| Removed a total of 0 cells. |
| |
| 8.7.13. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 8.7.14. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| |
| 8.7.15. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module user_project_wrapper. |
| |
| 8.7.16. Finished OPT passes. (There is nothing left to do.) |
| |
| 8.8. Executing FSM pass (extract and optimize FSM). |
| |
| 8.8.1. Executing FSM_DETECT pass (finding FSMs in design). |
| |
| 8.8.2. Executing FSM_EXTRACT pass (extracting FSM from design). |
| |
| 8.8.3. Executing FSM_OPT pass (simple optimizations of FSMs). |
| |
| 8.8.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| |
| 8.8.5. Executing FSM_OPT pass (simple optimizations of FSMs). |
| |
| 8.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). |
| |
| 8.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). |
| |
| 8.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). |
| |
| 8.9. Executing OPT pass (performing simple optimizations). |
| |
| 8.9.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module user_project_wrapper. |
| |
| 8.9.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\user_project_wrapper'. |
| Removed a total of 0 cells. |
| |
| 8.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \user_project_wrapper.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~4 debug messages> |
| |
| 8.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \user_project_wrapper. |
| Performed a total of 0 changes. |
| |
| 8.9.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\user_project_wrapper'. |
| Removed a total of 0 cells. |
| |
| 8.9.6. Executing OPT_DFF pass (perform DFF optimizations). |
| Adding SRST signal on $procdff$115 ($dff) from module user_project_wrapper (D = $procmux$110_Y, Q = \ready_q, rval = 1'0). |
| |
| 8.9.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| Removed 1 unused cells and 1 unused wires. |
| <suppressed ~2 debug messages> |
| |
| 8.9.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module user_project_wrapper. |
| |
| 8.9.9. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 8.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \user_project_wrapper.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~4 debug messages> |
| |
| 8.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \user_project_wrapper. |
| Performed a total of 0 changes. |
| |
| 8.9.12. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\user_project_wrapper'. |
| Removed a total of 0 cells. |
| |
| 8.9.13. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 8.9.14. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| |
| 8.9.15. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module user_project_wrapper. |
| |
| 8.9.16. Finished OPT passes. (There is nothing left to do.) |
| |
| 8.10. Executing WREDUCE pass (reducing word size of cells). |
| Removed top 1 bits (of 2) from port B of cell user_project_wrapper.$procmux$108_CMP0 ($eq). |
| Removed top 31 bits (of 32) from wire user_project_wrapper.$logic_not$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:201$37_Y. |
| |
| 8.11. Executing PEEPOPT pass (run peephole optimizers). |
| |
| 8.12. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| Removed 0 unused cells and 1 unused wires. |
| <suppressed ~1 debug messages> |
| |
| 8.13. Executing ALUMACC pass (create $alu and $macc cells). |
| Extracting $alu and $macc cells in module user_project_wrapper: |
| created 0 $alu and 0 $macc cells. |
| |
| 8.14. Executing SHARE pass (SAT-based resource sharing). |
| |
| 8.15. Executing OPT pass (performing simple optimizations). |
| |
| 8.15.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module user_project_wrapper. |
| |
| 8.15.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\user_project_wrapper'. |
| Removed a total of 0 cells. |
| |
| 8.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \user_project_wrapper.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~4 debug messages> |
| |
| 8.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \user_project_wrapper. |
| Performed a total of 0 changes. |
| |
| 8.15.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\user_project_wrapper'. |
| Removed a total of 0 cells. |
| |
| 8.15.6. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 8.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| |
| 8.15.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module user_project_wrapper. |
| |
| 8.15.9. Finished OPT passes. (There is nothing left to do.) |
| |
| 8.16. Executing MEMORY pass. |
| |
| 8.16.1. Executing OPT_MEM pass (optimize memories). |
| Performed a total of 0 transformations. |
| |
| 8.16.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). |
| Performed a total of 0 transformations. |
| |
| 8.16.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). |
| |
| 8.16.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd). |
| |
| 8.16.5. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| |
| 8.16.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). |
| |
| 8.16.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). |
| Performed a total of 0 transformations. |
| |
| 8.16.8. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| |
| 8.16.9. Executing MEMORY_COLLECT pass (generating $mem cells). |
| |
| 8.17. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| |
| 8.18. Executing OPT pass (performing simple optimizations). |
| |
| 8.18.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module user_project_wrapper. |
| <suppressed ~4 debug messages> |
| |
| 8.18.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\user_project_wrapper'. |
| Removed a total of 0 cells. |
| |
| 8.18.3. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 8.18.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| Removed 2 unused cells and 4 unused wires. |
| <suppressed ~3 debug messages> |
| |
| 8.18.5. Finished fast OPT passes. |
| |
| 8.19. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). |
| |
| 8.20. Executing OPT pass (performing simple optimizations). |
| |
| 8.20.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module user_project_wrapper. |
| |
| 8.20.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\user_project_wrapper'. |
| Removed a total of 0 cells. |
| |
| 8.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \user_project_wrapper.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~3 debug messages> |
| |
| 8.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \user_project_wrapper. |
| Performed a total of 0 changes. |
| |
| 8.20.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\user_project_wrapper'. |
| Removed a total of 0 cells. |
| |
| 8.20.6. Executing OPT_SHARE pass. |
| |
| 8.20.7. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 8.20.8. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| |
| 8.20.9. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module user_project_wrapper. |
| |
| 8.20.10. Finished OPT passes. (There is nothing left to do.) |
| |
| 8.21. Executing TECHMAP pass (map to technology primitives). |
| |
| 8.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v |
| Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation. |
| Generating RTLIL representation for module `\_90_simplemap_bool_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_logic_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_compare_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_various'. |
| Generating RTLIL representation for module `\_90_simplemap_registers'. |
| Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. |
| Generating RTLIL representation for module `\_90_shift_shiftx'. |
| Generating RTLIL representation for module `\_90_fa'. |
| Generating RTLIL representation for module `\_90_lcu'. |
| Generating RTLIL representation for module `\_90_alu'. |
| Generating RTLIL representation for module `\_90_macc'. |
| Generating RTLIL representation for module `\_90_alumacc'. |
| Generating RTLIL representation for module `\$__div_mod_u'. |
| Generating RTLIL representation for module `\$__div_mod_trunc'. |
| Generating RTLIL representation for module `\_90_div'. |
| Generating RTLIL representation for module `\_90_mod'. |
| Generating RTLIL representation for module `\$__div_mod_floor'. |
| Generating RTLIL representation for module `\_90_divfloor'. |
| Generating RTLIL representation for module `\_90_modfloor'. |
| Generating RTLIL representation for module `\_90_pow'. |
| Generating RTLIL representation for module `\_90_pmux'. |
| Generating RTLIL representation for module `\_90_lut'. |
| Successfully finished Verilog frontend. |
| |
| 8.21.2. Continuing TECHMAP pass. |
| Using extmapper simplemap for cells of type $logic_and. |
| Using extmapper simplemap for cells of type $mux. |
| Using extmapper simplemap for cells of type $logic_not. |
| Using extmapper simplemap for cells of type $and. |
| Using extmapper simplemap for cells of type $sdff. |
| Using extmapper simplemap for cells of type $eq. |
| Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux. |
| Using extmapper simplemap for cells of type $reduce_or. |
| No more expansions possible. |
| <suppressed ~160 debug messages> |
| |
| 8.22. Executing OPT pass (performing simple optimizations). |
| |
| 8.22.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module user_project_wrapper. |
| <suppressed ~6 debug messages> |
| |
| 8.22.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\user_project_wrapper'. |
| <suppressed ~12 debug messages> |
| Removed a total of 4 cells. |
| |
| 8.22.3. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 8.22.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| Removed 0 unused cells and 117 unused wires. |
| <suppressed ~1 debug messages> |
| |
| 8.22.5. Finished fast OPT passes. |
| |
| 8.23. Executing ABC pass (technology mapping using ABC). |
| |
| 8.23.1. Extracting gate netlist of module `\user_project_wrapper' to `<abc-temp-dir>/input.blif'.. |
| Extracted 236 gates and 376 wires to a netlist network with 140 inputs and 43 outputs. |
| |
| 8.23.1.1. Executing ABC. |
| Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 |
| ABC: ABC command line: "source <abc-temp-dir>/abc.script". |
| ABC: |
| ABC: + read_blif <abc-temp-dir>/input.blif |
| ABC: + read_library <abc-temp-dir>/stdcells.genlib |
| ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib". |
| ABC: + strash |
| ABC: + dretime |
| ABC: + map |
| ABC: + write_blif <abc-temp-dir>/output.blif |
| |
| 8.23.1.2. Re-integrating ABC results. |
| ABC RESULTS: ANDNOT cells: 96 |
| ABC RESULTS: MUX cells: 34 |
| ABC RESULTS: NAND cells: 2 |
| ABC RESULTS: NOR cells: 2 |
| ABC RESULTS: NOT cells: 1 |
| ABC RESULTS: OR cells: 81 |
| ABC RESULTS: ORNOT cells: 2 |
| ABC RESULTS: internal signals: 193 |
| ABC RESULTS: input signals: 140 |
| ABC RESULTS: output signals: 43 |
| Removing temp directory. |
| |
| 8.24. Executing OPT pass (performing simple optimizations). |
| |
| 8.24.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module user_project_wrapper. |
| |
| 8.24.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\user_project_wrapper'. |
| Removed a total of 0 cells. |
| |
| 8.24.3. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 8.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| Removed 0 unused cells and 248 unused wires. |
| <suppressed ~2 debug messages> |
| |
| 8.24.5. Finished fast OPT passes. |
| |
| 8.25. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 8.25.1. Analyzing design hierarchy.. |
| Top module: \user_project_wrapper |
| |
| 8.25.2. Analyzing design hierarchy.. |
| Top module: \user_project_wrapper |
| Removed 0 unused modules. |
| |
| 8.26. Printing statistics. |
| |
| === user_project_wrapper === |
| |
| Number of wires: 219 |
| Number of wire bits: 1156 |
| Number of public wires: 35 |
| Number of public wire bits: 972 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 223 |
| $_ANDNOT_ 96 |
| $_MUX_ 34 |
| $_NAND_ 2 |
| $_NOR_ 2 |
| $_NOT_ 1 |
| $_ORNOT_ 2 |
| $_OR_ 81 |
| $_SDFF_PP0_ 1 |
| sky130_sram_2kbyte_1rw1r_32x512_8 4 |
| |
| 8.27. Executing CHECK pass (checking for obvious problems). |
| Checking module user_project_wrapper... |
| Found and reported 0 problems. |
| |
| 9. Generating Graphviz representation of design. |
| Writing dot description to `/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/synthesis/post_techmap.dot'. |
| Dumping module user_project_wrapper to page 1. |
| |
| 10. Executing SHARE pass (SAT-based resource sharing). |
| |
| 11. Executing OPT pass (performing simple optimizations). |
| |
| 11.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module user_project_wrapper. |
| |
| 11.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\user_project_wrapper'. |
| Removed a total of 0 cells. |
| |
| 11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \user_project_wrapper.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \user_project_wrapper. |
| Performed a total of 0 changes. |
| |
| 11.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\user_project_wrapper'. |
| Removed a total of 0 cells. |
| |
| 11.6. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 11.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| |
| 11.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module user_project_wrapper. |
| |
| 11.9. Finished OPT passes. (There is nothing left to do.) |
| |
| 12. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| Removed 0 unused cells and 6 unused wires. |
| <suppressed ~6 debug messages> |
| |
| 13. Printing statistics. |
| |
| === user_project_wrapper === |
| |
| Number of wires: 213 |
| Number of wire bits: 1079 |
| Number of public wires: 29 |
| Number of public wire bits: 895 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 223 |
| $_ANDNOT_ 96 |
| $_MUX_ 34 |
| $_NAND_ 2 |
| $_NOR_ 2 |
| $_NOT_ 1 |
| $_ORNOT_ 2 |
| $_OR_ 81 |
| $_SDFF_PP0_ 1 |
| sky130_sram_2kbyte_1rw1r_32x512_8 4 |
| |
| mapping tbuf |
| |
| 14. Executing TECHMAP pass (map to technology primitives). |
| |
| 14.1. Executing Verilog-2005 frontend: /home/serdar/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v |
| Parsing Verilog input from `/home/serdar/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v' to AST representation. |
| Generating RTLIL representation for module `\$_TBUF_'. |
| Successfully finished Verilog frontend. |
| |
| 14.2. Continuing TECHMAP pass. |
| No more expansions possible. |
| <suppressed ~3 debug messages> |
| |
| 15. Executing SIMPLEMAP pass (map simple cells to gate primitives). |
| |
| 16. Executing TECHMAP pass (map to technology primitives). |
| |
| 16.1. Executing Verilog-2005 frontend: /home/serdar/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v |
| Parsing Verilog input from `/home/serdar/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v' to AST representation. |
| Generating RTLIL representation for module `\$_DLATCH_P_'. |
| Generating RTLIL representation for module `\$_DLATCH_N_'. |
| Successfully finished Verilog frontend. |
| |
| 16.2. Continuing TECHMAP pass. |
| No more expansions possible. |
| <suppressed ~4 debug messages> |
| |
| 17. Executing SIMPLEMAP pass (map simple cells to gate primitives). |
| |
| 18. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). |
| cell sky130_fd_sc_hd__dfxtp_2 (noninv, pins=3, area=21.27) is a direct match for cell type $_DFF_P_. |
| cell sky130_fd_sc_hd__dfrtp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN0_. |
| cell sky130_fd_sc_hd__dfstp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN1_. |
| cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_. |
| final dff cell mappings: |
| unmapped dff cell: $_DFF_N_ |
| \sky130_fd_sc_hd__dfxtp_2 _DFF_P_ (.CLK( C), .D( D), .Q( Q)); |
| unmapped dff cell: $_DFF_NN0_ |
| unmapped dff cell: $_DFF_NN1_ |
| unmapped dff cell: $_DFF_NP0_ |
| unmapped dff cell: $_DFF_NP1_ |
| \sky130_fd_sc_hd__dfrtp_2 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R)); |
| \sky130_fd_sc_hd__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R)); |
| unmapped dff cell: $_DFF_PP0_ |
| unmapped dff cell: $_DFF_PP1_ |
| \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S)); |
| unmapped dff cell: $_DFFSR_NNP_ |
| unmapped dff cell: $_DFFSR_NPN_ |
| unmapped dff cell: $_DFFSR_NPP_ |
| unmapped dff cell: $_DFFSR_PNN_ |
| unmapped dff cell: $_DFFSR_PNP_ |
| unmapped dff cell: $_DFFSR_PPN_ |
| unmapped dff cell: $_DFFSR_PPP_ |
| |
| 18.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). |
| Mapping DFF cells in module `\user_project_wrapper': |
| mapped 1 $_DFF_P_ cells to \sky130_fd_sc_hd__dfxtp_2 cells. |
| |
| 19. Printing statistics. |
| |
| === user_project_wrapper === |
| |
| Number of wires: 214 |
| Number of wire bits: 1080 |
| Number of public wires: 29 |
| Number of public wire bits: 895 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 224 |
| $_ANDNOT_ 96 |
| $_MUX_ 35 |
| $_NAND_ 2 |
| $_NOR_ 2 |
| $_NOT_ 1 |
| $_ORNOT_ 2 |
| $_OR_ 81 |
| sky130_fd_sc_hd__dfxtp_2 1 |
| sky130_sram_2kbyte_1rw1r_32x512_8 4 |
| |
| [INFO]: USING STRATEGY AREA 1 |
| |
| 20. Executing ABC pass (technology mapping using ABC). |
| |
| 20.1. Extracting gate netlist of module `\user_project_wrapper' to `/tmp/yosys-abc-YMcTnN/input.blif'.. |
| Extracted 219 gates and 360 wires to a netlist network with 140 inputs and 42 outputs. |
| |
| 20.1.1. Executing ABC. |
| Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-YMcTnN/abc.script 2>&1 |
| ABC: ABC command line: "source /tmp/yosys-abc-YMcTnN/abc.script". |
| ABC: |
| ABC: + read_blif /tmp/yosys-abc-YMcTnN/input.blif |
| ABC: + read_lib -w /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/synthesis/trimmed.lib |
| ABC: Parsing finished successfully. Parsing time = 0.08 sec |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8". |
| ABC: Library "sky130A_merged" from "/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/synthesis/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use). Time = 0.11 sec |
| ABC: Memory = 7.77 MB. Time = 0.11 sec |
| ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1"). |
| ABC: + read_constr -v /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/synthesis/synthesis.sdc |
| ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_2". |
| ABC: Setting output load to be 33.442001. |
| ABC: + read_constr /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/synthesis/synthesis.sdc |
| ABC: + fx |
| ABC: + mfs |
| ABC: + strash |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + retime -D -D 20000 -M 5 |
| ABC: + scleanup |
| ABC: Error: The network is combinational. |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + fraig_restore |
| ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + fraig_restore |
| ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 |
| ABC: + retime -D -D 20000 |
| ABC: + &get -n |
| ABC: + &st |
| ABC: + &dch |
| ABC: + &nf |
| ABC: + &put |
| ABC: + buffer -N 5 -S 750.0 |
| ABC: + upsize -D 20000 |
| ABC: Current delay (1256.99 ps) does not exceed the target delay (20000.00 ps). Upsizing is not performed. |
| ABC: + dnsize -D 20000 |
| ABC: + stime -p |
| ABC: WireLoad = "none" Gates = 163 ( 32.5 %) Cap = 8.0 ff ( 7.9 %) Area = 1241.19 ( 67.5 %) Delay = 1184.87 ps ( 4.9 %) |
| ABC: Path 0 -- 2 : 0 5 pi A = 0.00 Df = 38.2 -21.5 ps S = 58.6 ps Cin = 0.0 ff Cout = 11.3 ff Cmax = 0.0 ff G = 0 |
| ABC: Path 1 -- 192 : 1 2 sky130_fd_sc_hd__inv_2 A = 3.75 Df = 70.5 -16.5 ps S = 27.7 ps Cin = 4.5 ff Cout = 4.4 ff Cmax = 331.4 ff G = 94 |
| ABC: Path 2 -- 193 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df = 193.4 -13.1 ps S = 138.7 ps Cin = 2.1 ff Cout = 11.0 ff Cmax = 130.0 ff G = 499 |
| ABC: Path 3 -- 194 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df = 367.3 -54.9 ps S = 145.4 ps Cin = 2.1 ff Cout = 11.5 ff Cmax = 130.0 ff G = 525 |
| ABC: Path 4 -- 195 : 4 1 sky130_fd_sc_hd__or4_2 A = 8.76 Df = 944.4 -440.6 ps S = 94.4 ps Cin = 1.5 ff Cout = 2.2 ff Cmax = 310.4 ff G = 140 |
| ABC: Path 5 -- 196 : 1 1 sky130_fd_sc_hd__buf_1 A = 3.75 Df =1184.9 -364.6 ps S = 395.8 ps Cin = 2.1 ff Cout = 33.4 ff Cmax = 130.0 ff G = 1590 |
| ABC: Start-point = pi1 (\wbs_adr_i [11]). End-point = po2 ($abc$563$indirect$\csb0$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:146$11). |
| ABC: + print_stats -m |
| ABC: netlist : i/o = 140/ 42 lat = 0 nd = 163 edge = 448 area =1241.10 delay = 6.00 lev = 6 |
| ABC: + write_blif /tmp/yosys-abc-YMcTnN/output.blif |
| |
| 20.1.2. Re-integrating ABC results. |
| ABC RESULTS: sky130_fd_sc_hd__a22o_2 cells: 32 |
| ABC RESULTS: sky130_fd_sc_hd__and2_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__buf_1 cells: 50 |
| ABC RESULTS: sky130_fd_sc_hd__inv_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__mux2_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__nand3b_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__nor2_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o21a_2 cells: 32 |
| ABC RESULTS: sky130_fd_sc_hd__o22a_2 cells: 32 |
| ABC RESULTS: sky130_fd_sc_hd__or2_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__or3_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__or3b_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__or4_2 cells: 4 |
| ABC RESULTS: internal signals: 178 |
| ABC RESULTS: input signals: 140 |
| ABC RESULTS: output signals: 42 |
| Removing temp directory. |
| |
| 21. Executing SETUNDEF pass (replace undef values with defined constants). |
| |
| 22. Executing HILOMAP pass (mapping to constant drivers). |
| |
| 23. Executing SPLITNETS pass (splitting up multi-bit signals). |
| |
| 24. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \user_project_wrapper.. |
| Removed 0 unused cells and 502 unused wires. |
| <suppressed ~2 debug messages> |
| |
| 25. Executing INSBUF pass (insert buffer cells for connected wires). |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1275: \wbs_dat_i [0] -> \la_data_out [32] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1276: \wbs_dat_i [1] -> \la_data_out [33] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1277: \wbs_dat_i [2] -> \la_data_out [34] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1278: \wbs_dat_i [3] -> \la_data_out [35] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1279: \wbs_dat_i [4] -> \la_data_out [36] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1280: \wbs_dat_i [5] -> \la_data_out [37] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1281: \wbs_dat_i [6] -> \la_data_out [38] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1282: \wbs_dat_i [7] -> \la_data_out [39] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1283: \wbs_dat_i [8] -> \la_data_out [40] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1284: \wbs_dat_i [9] -> \la_data_out [41] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1285: \wbs_dat_i [10] -> \la_data_out [42] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1286: \wbs_dat_i [11] -> \la_data_out [43] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1287: \wbs_dat_i [12] -> \la_data_out [44] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1288: \wbs_dat_i [13] -> \la_data_out [45] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1289: \wbs_dat_i [14] -> \la_data_out [46] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1290: \wbs_dat_i [15] -> \la_data_out [47] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1291: \wbs_dat_i [16] -> \la_data_out [48] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1292: \wbs_dat_i [17] -> \la_data_out [49] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1293: \wbs_dat_i [18] -> \la_data_out [50] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1294: \wbs_dat_i [19] -> \la_data_out [51] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1295: \wbs_dat_i [20] -> \la_data_out [52] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1296: \wbs_dat_i [21] -> \la_data_out [53] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1297: \wbs_dat_i [22] -> \la_data_out [54] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1298: \wbs_dat_i [23] -> \la_data_out [55] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1299: \wbs_dat_i [24] -> \la_data_out [56] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1300: \wbs_dat_i [25] -> \la_data_out [57] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1301: \wbs_dat_i [26] -> \la_data_out [58] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1302: \wbs_dat_i [27] -> \la_data_out [59] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1303: \wbs_dat_i [28] -> \la_data_out [60] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1304: \wbs_dat_i [29] -> \la_data_out [61] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1305: \wbs_dat_i [30] -> \la_data_out [62] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1306: \wbs_dat_i [31] -> \la_data_out [63] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1307: \la_data_out [0] -> \wbs_dat_o [0] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1308: \la_data_out [1] -> \wbs_dat_o [1] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1309: \la_data_out [2] -> \wbs_dat_o [2] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1310: \la_data_out [3] -> \wbs_dat_o [3] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1311: \la_data_out [4] -> \wbs_dat_o [4] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1312: \la_data_out [5] -> \wbs_dat_o [5] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1313: \la_data_out [6] -> \wbs_dat_o [6] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1314: \la_data_out [7] -> \wbs_dat_o [7] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1315: \la_data_out [8] -> \wbs_dat_o [8] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1316: \la_data_out [9] -> \wbs_dat_o [9] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1317: \la_data_out [10] -> \wbs_dat_o [10] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1318: \la_data_out [11] -> \wbs_dat_o [11] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1319: \la_data_out [12] -> \wbs_dat_o [12] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1320: \la_data_out [13] -> \wbs_dat_o [13] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1321: \la_data_out [14] -> \wbs_dat_o [14] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1322: \la_data_out [15] -> \wbs_dat_o [15] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1323: \la_data_out [16] -> \wbs_dat_o [16] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1324: \la_data_out [17] -> \wbs_dat_o [17] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1325: \la_data_out [18] -> \wbs_dat_o [18] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1326: \la_data_out [19] -> \wbs_dat_o [19] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1327: \la_data_out [20] -> \wbs_dat_o [20] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1328: \la_data_out [21] -> \wbs_dat_o [21] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1329: \la_data_out [22] -> \wbs_dat_o [22] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1330: \la_data_out [23] -> \wbs_dat_o [23] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1331: \la_data_out [24] -> \wbs_dat_o [24] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1332: \la_data_out [25] -> \wbs_dat_o [25] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1333: \la_data_out [26] -> \wbs_dat_o [26] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1334: \la_data_out [27] -> \wbs_dat_o [27] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1335: \la_data_out [28] -> \wbs_dat_o [28] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1336: \la_data_out [29] -> \wbs_dat_o [29] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1337: \la_data_out [30] -> \wbs_dat_o [30] |
| Added user_project_wrapper.$auto$insbuf.cc:79:execute$1338: \la_data_out [31] -> \wbs_dat_o [31] |
| |
| 26. Executing CHECK pass (checking for obvious problems). |
| Checking module user_project_wrapper... |
| Warning: Wire user_project_wrapper.\wbs_dat_o [31] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [30] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [29] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [28] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [27] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [26] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [25] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [24] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [23] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [22] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [21] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [20] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [19] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [18] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [17] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [16] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [15] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [14] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [13] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [12] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [11] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [10] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [9] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [8] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [7] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [6] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [5] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [4] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [3] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [2] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [1] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_dat_o [0] is used but has no driver. |
| Warning: Wire user_project_wrapper.\wbs_ack_o is used but has no driver. |
| Warning: Wire user_project_wrapper.\user_irq [2] is used but has no driver. |
| Warning: Wire user_project_wrapper.\user_irq [1] is used but has no driver. |
| Warning: Wire user_project_wrapper.\user_irq [0] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [127] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [126] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [125] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [124] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [123] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [122] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [121] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [120] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [119] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [118] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [117] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [116] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [115] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [114] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [113] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [112] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [111] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [110] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [109] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [108] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [107] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [106] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [105] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [104] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [103] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [102] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [101] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [100] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [99] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [98] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [97] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [96] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [95] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [94] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [93] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [92] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [91] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [90] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [89] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [88] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [87] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [86] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [85] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [84] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [83] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [82] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [81] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [80] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [79] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [78] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [77] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [76] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [75] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [74] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [73] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [72] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [71] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [70] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [69] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [68] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [67] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [66] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [65] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [64] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [63] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [62] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [61] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [60] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [59] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [58] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [57] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [56] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [55] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [54] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [53] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [52] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [51] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [50] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [49] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [48] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [47] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [46] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [45] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [44] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [43] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [42] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [41] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [40] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [39] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [38] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [37] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [36] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [35] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [34] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [33] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [32] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [31] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [30] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [29] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [28] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [27] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [26] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [25] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [24] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [23] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [22] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [21] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [20] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [19] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [18] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [17] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [16] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [15] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [14] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [13] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [12] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [11] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [10] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [9] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [8] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [7] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [6] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [5] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [4] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [3] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [2] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [1] is used but has no driver. |
| Warning: Wire user_project_wrapper.\la_data_out [0] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [37] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [36] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [35] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [34] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [33] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [32] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [31] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [30] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [29] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [28] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [27] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [26] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [25] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [24] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [23] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [22] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [21] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [20] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [19] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [18] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [17] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [16] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [15] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [14] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [13] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [12] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [11] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [10] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [9] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [8] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [7] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [6] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [5] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [4] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [3] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [2] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [1] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_out [0] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [37] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [36] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [35] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [34] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [33] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [32] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [31] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [30] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [29] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [28] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [27] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [26] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [25] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [24] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [23] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [22] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [21] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [20] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [19] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [18] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [17] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [16] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [15] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [14] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [13] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [12] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [11] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [10] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [9] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [8] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [7] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [6] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [5] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [4] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [3] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [2] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [1] is used but has no driver. |
| Warning: Wire user_project_wrapper.\io_oeb [0] is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:39:hilomap_worker$987 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:39:hilomap_worker$985 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:39:hilomap_worker$983 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:39:hilomap_worker$981 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:47:hilomap_worker$979 is used but has no driver. |
| Warning: Wire user_project_wrapper.$abc$563$indirect$\csb1$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:182$27 is used but has no driver. |
| Warning: Wire user_project_wrapper.$abc$563$indirect$\csb0$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:182$23 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:39:hilomap_worker$977 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:39:hilomap_worker$975 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:39:hilomap_worker$973 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:39:hilomap_worker$971 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:47:hilomap_worker$969 is used but has no driver. |
| Warning: Wire user_project_wrapper.$abc$563$indirect$\csb1$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:164$21 is used but has no driver. |
| Warning: Wire user_project_wrapper.$abc$563$indirect$\csb0$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:164$17 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:39:hilomap_worker$967 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:39:hilomap_worker$965 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:39:hilomap_worker$963 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:39:hilomap_worker$961 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:47:hilomap_worker$959 is used but has no driver. |
| Warning: Wire user_project_wrapper.$abc$563$indirect$\csb1$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:146$15 is used but has no driver. |
| Warning: Wire user_project_wrapper.$abc$563$indirect$\csb0$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:146$11 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:39:hilomap_worker$957 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:39:hilomap_worker$955 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:39:hilomap_worker$953 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:39:hilomap_worker$951 is used but has no driver. |
| Warning: Wire user_project_wrapper.$auto$hilomap.cc:47:hilomap_worker$949 is used but has no driver. |
| Warning: Wire user_project_wrapper.$abc$563$indirect$\csb1$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:128$9 is used but has no driver. |
| Warning: Wire user_project_wrapper.$abc$563$indirect$\csb0$/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v:128$5 is used but has no driver. |
| Warning: Wire user_project_wrapper.\clk is used but has no driver. |
| Found and reported 269 problems. |
| |
| 27. Printing statistics. |
| |
| === user_project_wrapper === |
| |
| Number of wires: 426 |
| Number of wire bits: 1044 |
| Number of public wires: 276 |
| Number of public wire bits: 894 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 395 |
| sky130_fd_sc_hd__a22o_2 32 |
| sky130_fd_sc_hd__and2_2 1 |
| sky130_fd_sc_hd__buf_1 50 |
| sky130_fd_sc_hd__buf_4 64 |
| sky130_fd_sc_hd__conb_1 163 |
| sky130_fd_sc_hd__dfxtp_2 1 |
| sky130_fd_sc_hd__inv_2 3 |
| sky130_fd_sc_hd__mux2_2 2 |
| sky130_fd_sc_hd__nand3b_2 1 |
| sky130_fd_sc_hd__nor2_2 1 |
| sky130_fd_sc_hd__o21a_2 32 |
| sky130_fd_sc_hd__o22a_2 32 |
| sky130_fd_sc_hd__or2_2 1 |
| sky130_fd_sc_hd__or3_2 2 |
| sky130_fd_sc_hd__or3b_2 2 |
| sky130_fd_sc_hd__or4_2 4 |
| sky130_sram_2kbyte_1rw1r_32x512_8 4 |
| |
| Area for cell type \sky130_sram_2kbyte_1rw1r_32x512_8 is unknown! |
| |
| Chip area for module '\user_project_wrapper': 2354.758400 |
| |
| 28. Executing Verilog backend. |
| Dumping module `\user_project_wrapper'. |
| |
| Warnings: 270 unique messages, 273 total |
| End of script. Logfile hash: b58532c585, CPU: user 0.76s system 0.06s, MEM: 47.30 MB peak |
| Yosys 0.12+45 (git sha1 UNKNOWN, gcc 8.3.1 -fPIC -Os) |
| Time spent: 37% 2x abc (0 sec), 23% 4x stat (0 sec), ... |