| OpenROAD 79a46b62da64bbebc18f06b20c42211046de719a |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| [INFO ODB-0222] Reading LEF file: /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.unpadded.nom.lef |
| [INFO ODB-0223] Created 13 technology layers |
| [INFO ODB-0224] Created 25 technology vias |
| [INFO ODB-0225] Created 442 library cells |
| [INFO ODB-0226] Finished LEF file: /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.unpadded.nom.lef |
| [INFO ODB-0127] Reading DEF file: /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/routing/20-fill.def |
| [INFO ODB-0128] Design: user_project_wrapper |
| [INFO ODB-0094] Created 100000 Insts |
| [INFO ODB-0094] Created 200000 Insts |
| [INFO ODB-0094] Created 300000 Insts |
| [INFO ODB-0094] Created 400000 Insts |
| [INFO ODB-0094] Created 500000 Insts |
| [INFO ODB-0094] Created 600000 Insts |
| [INFO ODB-0094] Created 700000 Insts |
| [INFO ODB-0094] Created 800000 Insts |
| [INFO ODB-0130] Created 645 pins. |
| [INFO ODB-0131] Created 899260 components and 3347606 component-terminals. |
| [INFO ODB-0132] Created 8 special nets and 3341864 connections. |
| [INFO ODB-0133] Created 2927 nets and 5579 connections. |
| [INFO ODB-0134] Finished DEF file: /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/routing/20-fill.def |
| [INFO ORD-0030] Using 8 thread(s). |
| [INFO DRT-0149] Reading tech and libs. |
| |
| Units: 1000 |
| Number of layers: 13 |
| Number of macros: 442 |
| Number of vias: 25 |
| Number of viarulegen: 25 |
| |
| [INFO DRT-0150] Reading design. |
| |
| Design: user_project_wrapper |
| Die area: ( 0 0 ) ( 2920000 3520000 ) |
| Number of track patterns: 12 |
| Number of DEF vias: 8 |
| Number of components: 899260 |
| Number of terminals: 645 |
| Number of snets: 8 |
| Number of nets: 2927 |
| |
| [INFO DRT-0167] List of default vias: |
| Layer mcon |
| default via: L1M1_PR |
| Layer via |
| default via: M1M2_PR |
| Layer via2 |
| default via: M2M3_PR |
| Layer via3 |
| default via: M3M4_PR |
| Layer via4 |
| default via: M4M5_PR |
| [INFO DRT-0162] Library cell analysis. |
| [INFO DRT-0163] Instance analysis. |
| Complete 10000 instances. |
| Complete 20000 instances. |
| Complete 30000 instances. |
| Complete 40000 instances. |
| Complete 50000 instances. |
| Complete 60000 instances. |
| Complete 70000 instances. |
| Complete 80000 instances. |
| Complete 90000 instances. |
| Complete 100000 instances. |
| Complete 200000 instances. |
| Complete 300000 instances. |
| Complete 400000 instances. |
| Complete 500000 instances. |
| Complete 600000 instances. |
| Complete 700000 instances. |
| Complete 800000 instances. |
| [INFO DRT-0164] Number of unique instances = 73. |
| [INFO DRT-0168] Init region query. |
| [INFO DRT-0018] Complete 10000 insts. |
| [INFO DRT-0018] Complete 20000 insts. |
| [INFO DRT-0018] Complete 30000 insts. |
| [INFO DRT-0018] Complete 40000 insts. |
| [INFO DRT-0018] Complete 50000 insts. |
| [INFO DRT-0018] Complete 60000 insts. |
| [INFO DRT-0018] Complete 70000 insts. |
| [INFO DRT-0018] Complete 80000 insts. |
| [INFO DRT-0018] Complete 90000 insts. |
| [INFO DRT-0019] Complete 100000 insts. |
| [INFO DRT-0019] Complete 200000 insts. |
| [INFO DRT-0019] Complete 300000 insts. |
| [INFO DRT-0019] Complete 400000 insts. |
| [INFO DRT-0019] Complete 500000 insts. |
| [INFO DRT-0019] Complete 600000 insts. |
| [INFO DRT-0019] Complete 700000 insts. |
| [INFO DRT-0019] Complete 800000 insts. |
| [INFO DRT-0024] Complete FR_MASTERSLICE. |
| [INFO DRT-0024] Complete FR_VIA. |
| [INFO DRT-0024] Complete li1. |
| [INFO DRT-0024] Complete mcon. |
| [INFO DRT-0024] Complete met1. |
| [INFO DRT-0024] Complete via. |
| [INFO DRT-0024] Complete met2. |
| [INFO DRT-0024] Complete via2. |
| [INFO DRT-0024] Complete met3. |
| [INFO DRT-0024] Complete via3. |
| [INFO DRT-0024] Complete met4. |
| [INFO DRT-0024] Complete via4. |
| [INFO DRT-0024] Complete met5. |
| [INFO DRT-0033] FR_MASTERSLICE shape region query size = 0. |
| [INFO DRT-0033] FR_VIA shape region query size = 0. |
| [INFO DRT-0033] li1 shape region query size = 4672699. |
| [INFO DRT-0033] mcon shape region query size = 14287294. |
| [INFO DRT-0033] met1 shape region query size = 1819770. |
| [INFO DRT-0033] via shape region query size = 173639. |
| [INFO DRT-0033] met2 shape region query size = 58467. |
| [INFO DRT-0033] via2 shape region query size = 135017. |
| [INFO DRT-0033] met3 shape region query size = 58364. |
| [INFO DRT-0033] via3 shape region query size = 135017. |
| [INFO DRT-0033] met4 shape region query size = 23688. |
| [INFO DRT-0033] via4 shape region query size = 11332. |
| [INFO DRT-0033] met5 shape region query size = 3195. |
| [INFO DRT-0165] Start pin access. |
| [INFO DRT-0076] Complete 100 pins. |
| [INFO DRT-0076] Complete 200 pins. |
| [INFO DRT-0076] Complete 300 pins. |
| [INFO DRT-0076] Complete 400 pins. |
| [INFO DRT-0076] Complete 500 pins. |
| [INFO DRT-0076] Complete 600 pins. |
| [INFO DRT-0078] Complete 637 pins. |
| [INFO DRT-0081] Complete 63 unique inst patterns. |
| [INFO DRT-0082] Complete 1000 groups. |
| [INFO DRT-0082] Complete 2000 groups. |
| [INFO DRT-0084] Complete 2679 groups. |
| #scanned instances = 899260 |
| #unique instances = 73 |
| #stdCellGenAp = 1017 |
| #stdCellValidPlanarAp = 0 |
| #stdCellValidViaAp = 806 |
| #stdCellPinNoAp = 0 |
| #stdCellPinCnt = 5087 |
| #instTermValidViaApCnt = 0 |
| #macroGenAp = 808 |
| #macroValidPlanarAp = 808 |
| #macroValidViaAp = 0 |
| #macroNoAp = 0 |
| [INFO DRT-0166] Complete pin access. |
| [INFO DRT-0267] cpu time = 00:00:03, elapsed time = 00:00:01, memory = 3029.29 (MB), peak = 3455.97 (MB) |
| [INFO DRT-0151] Reading guide. |
| |
| Number of guides: 13750 |
| |
| [INFO DRT-0169] Post process guides. |
| [INFO DRT-0176] GCELLGRID X 0 DO 423 STEP 6900 ; |
| [INFO DRT-0177] GCELLGRID Y 0 DO 510 STEP 6900 ; |
| [INFO DRT-0026] Complete 10000 origin guides. |
| [INFO DRT-0028] Complete FR_MASTERSLICE. |
| [INFO DRT-0028] Complete FR_VIA. |
| [INFO DRT-0028] Complete li1. |
| [INFO DRT-0028] Complete mcon. |
| [INFO DRT-0028] Complete met1. |
| [INFO DRT-0028] Complete via. |
| [INFO DRT-0028] Complete met2. |
| [INFO DRT-0028] Complete via2. |
| [INFO DRT-0028] Complete met3. |
| [INFO DRT-0028] Complete via3. |
| [INFO DRT-0028] Complete met4. |
| [INFO DRT-0028] Complete via4. |
| [INFO DRT-0028] Complete met5. |
| [INFO DRT-0178] Init guide query. |
| [INFO DRT-0035] Complete FR_MASTERSLICE (guide). |
| [INFO DRT-0035] Complete FR_VIA (guide). |
| [INFO DRT-0035] Complete li1 (guide). |
| [INFO DRT-0035] Complete mcon (guide). |
| [INFO DRT-0035] Complete met1 (guide). |
| [INFO DRT-0035] Complete via (guide). |
| [INFO DRT-0035] Complete met2 (guide). |
| [INFO DRT-0035] Complete via2 (guide). |
| [INFO DRT-0035] Complete met3 (guide). |
| [INFO DRT-0035] Complete via3 (guide). |
| [INFO DRT-0035] Complete met4 (guide). |
| [INFO DRT-0035] Complete via4 (guide). |
| [INFO DRT-0035] Complete met5 (guide). |
| [INFO DRT-0036] FR_MASTERSLICE guide region query size = 0. |
| [INFO DRT-0036] FR_VIA guide region query size = 0. |
| [INFO DRT-0036] li1 guide region query size = 4754. |
| [INFO DRT-0036] mcon guide region query size = 0. |
| [INFO DRT-0036] met1 guide region query size = 4762. |
| [INFO DRT-0036] via guide region query size = 0. |
| [INFO DRT-0036] met2 guide region query size = 2736. |
| [INFO DRT-0036] via2 guide region query size = 0. |
| [INFO DRT-0036] met3 guide region query size = 478. |
| [INFO DRT-0036] via3 guide region query size = 0. |
| [INFO DRT-0036] met4 guide region query size = 300. |
| [INFO DRT-0036] via4 guide region query size = 0. |
| [INFO DRT-0036] met5 guide region query size = 0. |
| [INFO DRT-0179] Init gr pin query. |
| [INFO DRT-0185] Post process initialize RPin region query. |
| [INFO DRT-0181] Start track assignment. |
| [INFO DRT-0184] Done with 7790 vertical wires in 9 frboxes and 5240 horizontal wires in 11 frboxes. |
| [INFO DRT-0186] Done with 548 vertical wires in 9 frboxes and 1911 horizontal wires in 11 frboxes. |
| [INFO DRT-0182] Complete track assignment. |
| [INFO DRT-0267] cpu time = 00:01:25, elapsed time = 00:00:16, memory = 3309.45 (MB), peak = 5589.45 (MB) |
| [INFO DRT-0187] Start routing data preparation. |
| [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 3309.65 (MB), peak = 5589.45 (MB) |
| [INFO DRT-0194] Start detail routing. |
| [INFO DRT-0195] Start 0th optimization iteration. |
| Completing 10% with 0 violations. |
| elapsed time = 00:00:20, memory = 12734.55 (MB). |
| Completing 20% with 0 violations. |
| elapsed time = 00:00:45, memory = 21605.88 (MB). |
| Completing 30% with 1814 violations. |
| elapsed time = 00:01:42, memory = 11087.17 (MB). |
| Completing 40% with 1814 violations. |
| elapsed time = 00:01:54, memory = 18026.91 (MB). |
| Completing 50% with 3671 violations. |
| elapsed time = 00:02:50, memory = 11883.17 (MB). |
| Completing 60% with 3671 violations. |
| elapsed time = 00:03:01, memory = 14708.20 (MB). |
| Completing 70% with 3671 violations. |
| elapsed time = 00:03:10, memory = 21700.44 (MB). |
| Completing 80% with 5245 violations. |
| elapsed time = 00:03:45, memory = 16449.47 (MB). |
| Completing 90% with 5245 violations. |
| elapsed time = 00:03:54, memory = 18552.79 (MB). |
| Completing 100% with 6599 violations. |
| elapsed time = 00:04:24, memory = 17376.21 (MB). |
| [INFO DRT-0199] Number of violations = 6787. |
| [INFO DRT-0267] cpu time = 00:15:50, elapsed time = 00:04:24, memory = 17376.27 (MB), peak = 25471.87 (MB) |
| Total wire length = 447057 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 239551 um. |
| Total wire length on LAYER met2 = 177234 um. |
| Total wire length on LAYER met3 = 22318 um. |
| Total wire length on LAYER met4 = 7952 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 14959. |
| Up-via summary (total 14959):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 5087 |
| met1 7877 |
| met2 1521 |
| met3 474 |
| met4 0 |
| ------------------------ |
| 14959 |
| |
| |
| [INFO DRT-0195] Start 1st optimization iteration. |
| Completing 10% with 6787 violations. |
| elapsed time = 00:00:09, memory = 17552.88 (MB). |
| Completing 20% with 6787 violations. |
| elapsed time = 00:00:17, memory = 22759.95 (MB). |
| Completing 30% with 5306 violations. |
| elapsed time = 00:00:35, memory = 17376.71 (MB). |
| Completing 40% with 5306 violations. |
| elapsed time = 00:00:42, memory = 19248.15 (MB). |
| Completing 50% with 4251 violations. |
| elapsed time = 00:01:01, memory = 17376.63 (MB). |
| Completing 60% with 4251 violations. |
| elapsed time = 00:01:11, memory = 18018.28 (MB). |
| Completing 70% with 4251 violations. |
| elapsed time = 00:01:20, memory = 22000.66 (MB). |
| Completing 80% with 2528 violations. |
| elapsed time = 00:01:41, memory = 17550.72 (MB). |
| Completing 90% with 2528 violations. |
| elapsed time = 00:01:49, memory = 19832.60 (MB). |
| Completing 100% with 1084 violations. |
| elapsed time = 00:02:10, memory = 17519.30 (MB). |
| [INFO DRT-0199] Number of violations = 1084. |
| [INFO DRT-0267] cpu time = 00:11:15, elapsed time = 00:02:10, memory = 17519.30 (MB), peak = 25471.87 (MB) |
| Total wire length = 447338 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 237239 um. |
| Total wire length on LAYER met2 = 177244 um. |
| Total wire length on LAYER met3 = 24647 um. |
| Total wire length on LAYER met4 = 8207 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 15987. |
| Up-via summary (total 15987):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 5087 |
| met1 8555 |
| met2 1754 |
| met3 591 |
| met4 0 |
| ------------------------ |
| 15987 |
| |
| |
| [INFO DRT-0195] Start 2nd optimization iteration. |
| Completing 10% with 1084 violations. |
| elapsed time = 00:00:00, memory = 17519.30 (MB). |
| Completing 20% with 1084 violations. |
| elapsed time = 00:00:01, memory = 17519.39 (MB). |
| Completing 30% with 1039 violations. |
| elapsed time = 00:00:02, memory = 17519.39 (MB). |
| Completing 40% with 1039 violations. |
| elapsed time = 00:00:03, memory = 17519.42 (MB). |
| Completing 50% with 946 violations. |
| elapsed time = 00:00:04, memory = 17519.42 (MB). |
| Completing 60% with 946 violations. |
| elapsed time = 00:00:06, memory = 17519.42 (MB). |
| Completing 70% with 946 violations. |
| elapsed time = 00:00:06, memory = 17519.48 (MB). |
| Completing 80% with 897 violations. |
| elapsed time = 00:00:08, memory = 17519.66 (MB). |
| Completing 90% with 897 violations. |
| elapsed time = 00:00:10, memory = 17519.66 (MB). |
| Completing 100% with 775 violations. |
| elapsed time = 00:00:13, memory = 17519.66 (MB). |
| [INFO DRT-0199] Number of violations = 775. |
| [INFO DRT-0267] cpu time = 00:01:19, elapsed time = 00:00:13, memory = 17519.66 (MB), peak = 25471.87 (MB) |
| Total wire length = 447763 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 237107 um. |
| Total wire length on LAYER met2 = 177499 um. |
| Total wire length on LAYER met3 = 24750 um. |
| Total wire length on LAYER met4 = 8405 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 16133. |
| Up-via summary (total 16133):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 5087 |
| met1 8725 |
| met2 1783 |
| met3 538 |
| met4 0 |
| ------------------------ |
| 16133 |
| |
| |
| [INFO DRT-0195] Start 3rd optimization iteration. |
| Completing 10% with 775 violations. |
| elapsed time = 00:00:00, memory = 17519.66 (MB). |
| Completing 20% with 775 violations. |
| elapsed time = 00:00:00, memory = 17519.66 (MB). |
| Completing 30% with 566 violations. |
| elapsed time = 00:00:00, memory = 17519.66 (MB). |
| Completing 40% with 566 violations. |
| elapsed time = 00:00:01, memory = 17519.66 (MB). |
| Completing 50% with 351 violations. |
| elapsed time = 00:00:02, memory = 17519.66 (MB). |
| Completing 60% with 351 violations. |
| elapsed time = 00:00:02, memory = 17519.77 (MB). |
| Completing 70% with 351 violations. |
| elapsed time = 00:00:02, memory = 17519.77 (MB). |
| Completing 80% with 222 violations. |
| elapsed time = 00:00:05, memory = 17519.77 (MB). |
| Completing 90% with 222 violations. |
| elapsed time = 00:00:06, memory = 17519.77 (MB). |
| Completing 100% with 22 violations. |
| elapsed time = 00:00:08, memory = 17519.88 (MB). |
| [INFO DRT-0199] Number of violations = 22. |
| [INFO DRT-0267] cpu time = 00:00:27, elapsed time = 00:00:08, memory = 17519.88 (MB), peak = 25471.87 (MB) |
| Total wire length = 447890 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 233389 um. |
| Total wire length on LAYER met2 = 177892 um. |
| Total wire length on LAYER met3 = 28379 um. |
| Total wire length on LAYER met4 = 8228 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 16516. |
| Up-via summary (total 16516):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 5087 |
| met1 8913 |
| met2 1978 |
| met3 538 |
| met4 0 |
| ------------------------ |
| 16516 |
| |
| |
| [INFO DRT-0195] Start 4th optimization iteration. |
| Completing 10% with 22 violations. |
| elapsed time = 00:00:00, memory = 17519.88 (MB). |
| Completing 20% with 22 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 30% with 16 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 40% with 16 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 50% with 14 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 60% with 14 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 70% with 14 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 80% with 7 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 90% with 7 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 100% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| [INFO DRT-0199] Number of violations = 0. |
| [INFO DRT-0267] cpu time = 00:00:01, elapsed time = 00:00:00, memory = 17520.00 (MB), peak = 25471.87 (MB) |
| Total wire length = 447910 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 233287 um. |
| Total wire length on LAYER met2 = 177916 um. |
| Total wire length on LAYER met3 = 28488 um. |
| Total wire length on LAYER met4 = 8217 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 16525. |
| Up-via summary (total 16525):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 5087 |
| met1 8918 |
| met2 1982 |
| met3 538 |
| met4 0 |
| ------------------------ |
| 16525 |
| |
| |
| [INFO DRT-0195] Start 17th optimization iteration. |
| Completing 10% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 20% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 30% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 40% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 50% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 60% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 70% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 80% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 90% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 100% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| [INFO DRT-0199] Number of violations = 0. |
| [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 17520.00 (MB), peak = 25471.87 (MB) |
| Total wire length = 447910 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 233287 um. |
| Total wire length on LAYER met2 = 177916 um. |
| Total wire length on LAYER met3 = 28488 um. |
| Total wire length on LAYER met4 = 8217 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 16525. |
| Up-via summary (total 16525):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 5087 |
| met1 8918 |
| met2 1982 |
| met3 538 |
| met4 0 |
| ------------------------ |
| 16525 |
| |
| |
| [INFO DRT-0195] Start 25th optimization iteration. |
| Completing 10% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 20% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 30% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 40% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 50% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 60% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 70% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 80% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 90% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 100% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| [INFO DRT-0199] Number of violations = 0. |
| [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 17520.00 (MB), peak = 25471.87 (MB) |
| Total wire length = 447910 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 233287 um. |
| Total wire length on LAYER met2 = 177916 um. |
| Total wire length on LAYER met3 = 28488 um. |
| Total wire length on LAYER met4 = 8217 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 16525. |
| Up-via summary (total 16525):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 5087 |
| met1 8918 |
| met2 1982 |
| met3 538 |
| met4 0 |
| ------------------------ |
| 16525 |
| |
| |
| [INFO DRT-0195] Start 33rd optimization iteration. |
| Completing 10% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 20% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 30% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 40% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 50% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 60% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 70% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 80% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 90% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 100% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| [INFO DRT-0199] Number of violations = 0. |
| [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 17520.00 (MB), peak = 25471.87 (MB) |
| Total wire length = 447910 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 233287 um. |
| Total wire length on LAYER met2 = 177916 um. |
| Total wire length on LAYER met3 = 28488 um. |
| Total wire length on LAYER met4 = 8217 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 16525. |
| Up-via summary (total 16525):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 5087 |
| met1 8918 |
| met2 1982 |
| met3 538 |
| met4 0 |
| ------------------------ |
| 16525 |
| |
| |
| [INFO DRT-0195] Start 41st optimization iteration. |
| Completing 10% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 20% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 30% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 40% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 50% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 60% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 70% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 80% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 90% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| Completing 100% with 0 violations. |
| elapsed time = 00:00:00, memory = 17520.00 (MB). |
| [INFO DRT-0199] Number of violations = 0. |
| [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 17520.00 (MB), peak = 25471.87 (MB) |
| Total wire length = 447910 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 233287 um. |
| Total wire length on LAYER met2 = 177916 um. |
| Total wire length on LAYER met3 = 28488 um. |
| Total wire length on LAYER met4 = 8217 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 16525. |
| Up-via summary (total 16525):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 5087 |
| met1 8918 |
| met2 1982 |
| met3 538 |
| met4 0 |
| ------------------------ |
| 16525 |
| |
| |
| [INFO DRT-0198] Complete detail routing. |
| Total wire length = 447910 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 233287 um. |
| Total wire length on LAYER met2 = 177916 um. |
| Total wire length on LAYER met3 = 28488 um. |
| Total wire length on LAYER met4 = 8217 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 16525. |
| Up-via summary (total 16525):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 5087 |
| met1 8918 |
| met2 1982 |
| met3 538 |
| met4 0 |
| ------------------------ |
| 16525 |
| |
| |
| [INFO DRT-0267] cpu time = 00:28:55, elapsed time = 00:06:57, memory = 17520.00 (MB), peak = 25471.87 (MB) |
| |
| [INFO DRT-0180] Post processing. |
| Saving to /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/results/routing/user_project_wrapper.def |