| OpenROAD 79a46b62da64bbebc18f06b20c42211046de719a |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| [INFO ODB-0222] Reading LEF file: /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.unpadded.nom.lef |
| [INFO ODB-0223] Created 13 technology layers |
| [INFO ODB-0224] Created 25 technology vias |
| [INFO ODB-0225] Created 442 library cells |
| [INFO ODB-0226] Finished LEF file: /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.unpadded.nom.lef |
| [INFO ODB-0127] Reading DEF file: /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/results/cts/user_project_wrapper.def |
| [INFO ODB-0128] Design: user_project_wrapper |
| [INFO ODB-0094] Created 100000 Insts |
| [INFO ODB-0130] Created 645 pins. |
| [INFO ODB-0131] Created 133726 components and 285054 component-terminals. |
| [INFO ODB-0132] Created 8 special nets and 279728 connections. |
| [INFO ODB-0133] Created 2927 nets and 5163 connections. |
| [INFO ODB-0134] Finished DEF file: /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/results/cts/user_project_wrapper.def |
| ############################################################################### |
| # Created by write_sdc |
| # Fri May 27 08:37:55 2022 |
| ############################################################################### |
| current_design user_project_wrapper |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name wb_clk_i -period 20.0000 [get_ports {wb_clk_i}] |
| set_clock_transition 0.1500 [get_clocks {wb_clk_i}] |
| set_clock_uncertainty 0.2500 wb_clk_i |
| set_propagated_clock [get_clocks {wb_clk_i}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[32]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[33]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[34]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[35]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[36]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[37]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[100]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[101]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[102]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[103]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[104]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[105]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[106]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[107]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[108]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[109]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[110]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[111]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[112]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[113]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[114]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[115]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[116]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[117]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[118]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[119]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[120]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[121]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[122]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[123]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[124]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[125]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[126]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[127]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[32]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[33]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[34]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[35]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[36]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[37]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[38]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[39]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[40]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[41]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[42]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[43]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[44]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[45]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[46]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[47]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[48]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[49]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[50]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[51]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[52]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[53]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[54]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[55]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[56]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[57]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[58]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[59]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[60]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[61]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[62]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[63]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[64]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[65]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[66]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[67]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[68]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[69]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[70]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[71]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[72]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[73]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[74]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[75]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[76]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[77]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[78]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[79]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[80]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[81]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[82]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[83]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[84]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[85]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[86]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[87]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[88]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[89]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[90]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[91]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[92]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[93]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[94]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[95]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[96]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[97]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[98]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[99]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[100]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[101]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[102]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[103]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[104]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[105]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[106]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[107]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[108]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[109]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[110]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[111]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[112]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[113]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[114]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[115]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[116]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[117]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[118]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[119]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[120]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[121]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[122]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[123]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[124]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[125]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[126]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[127]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[32]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[33]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[34]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[35]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[36]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[37]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[38]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[39]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[40]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[41]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[42]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[43]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[44]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[45]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[46]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[47]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[48]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[49]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[50]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[51]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[52]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[53]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[54]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[55]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[56]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[57]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[58]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[59]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[60]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[61]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[62]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[63]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[64]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[65]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[66]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[67]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[68]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[69]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[70]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[71]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[72]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[73]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[74]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[75]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[76]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[77]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[78]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[79]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[80]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[81]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[82]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[83]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[84]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[85]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[86]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[87]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[88]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[89]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[90]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[91]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[92]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[93]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[94]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[95]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[96]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[97]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[98]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[99]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {user_clock2}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_rst_i}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_cyc_i}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_stb_i}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_we_i}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[32]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[33]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[34]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[35]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[36]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[37]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[32]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[33]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[34]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[35]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[36]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[37]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[100]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[101]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[102]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[103]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[104]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[105]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[106]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[107]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[108]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[109]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[110]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[111]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[112]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[113]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[114]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[115]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[116]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[117]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[118]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[119]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[120]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[121]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[122]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[123]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[124]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[125]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[126]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[127]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[32]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[33]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[34]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[35]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[36]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[37]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[38]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[39]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[40]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[41]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[42]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[43]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[44]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[45]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[46]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[47]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[48]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[49]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[50]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[51]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[52]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[53]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[54]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[55]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[56]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[57]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[58]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[59]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[60]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[61]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[62]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[63]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[64]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[65]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[66]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[67]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[68]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[69]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[70]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[71]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[72]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[73]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[74]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[75]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[76]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[77]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[78]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[79]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[80]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[81]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[82]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[83]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[84]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[85]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[86]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[87]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[88]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[89]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[90]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[91]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[92]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[93]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[94]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[95]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[96]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[97]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[98]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[99]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {user_irq[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {user_irq[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {user_irq[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_ack_o}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}] |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_load -pin_load 0.0334 [get_ports {wbs_ack_o}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[28]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[27]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[26]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[25]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[24]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[23]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[22]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[21]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[20]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[19]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[18]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[17]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[16]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[15]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[14]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[13]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[12]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[11]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[10]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[9]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[8]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[7]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[6]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[5]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[4]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[3]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[2]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[1]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[37]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[36]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[35]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[34]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[33]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[32]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[31]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[30]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[29]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[28]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[27]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[26]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[25]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[24]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[23]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[22]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[21]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[20]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[19]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[18]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[17]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[16]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[15]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[14]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[13]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[12]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[11]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[10]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[9]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[8]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[7]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[6]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[5]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[4]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[37]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[36]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[35]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[34]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[33]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[32]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[31]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[30]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[29]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[28]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[27]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[26]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[25]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[24]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[23]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[22]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[21]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[20]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[19]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[18]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[17]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[16]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[15]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[14]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[13]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[12]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[11]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[10]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[9]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[8]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[7]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[6]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[5]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[4]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[0]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[127]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[126]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[125]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[124]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[123]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[122]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[121]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[120]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[119]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[118]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[117]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[116]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[115]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[114]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[113]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[112]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[111]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[110]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[109]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[108]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[107]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[106]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[105]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[104]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[103]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[102]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[101]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[100]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[99]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[98]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[97]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[96]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[95]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[94]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[93]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[92]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[91]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[90]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[89]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[88]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[87]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[86]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[85]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[84]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[83]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[82]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[81]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[80]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[79]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[78]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[77]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[76]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[75]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[74]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[73]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[72]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[71]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[70]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[69]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[68]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[67]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[66]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[65]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[64]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[63]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[62]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[61]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[60]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[59]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[58]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[57]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[56]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[55]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[54]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[53]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[52]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[51]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[50]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[49]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[48]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[47]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[46]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[45]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[44]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[43]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[42]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[41]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[40]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[39]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[38]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[37]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[36]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[35]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[34]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[33]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[32]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[31]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[30]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[29]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[28]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[27]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[26]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[25]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[24]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[23]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[22]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[21]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[20]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[19]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[18]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[17]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[16]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[15]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[14]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[13]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[12]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[11]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[10]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[9]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[8]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[7]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[6]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[5]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[4]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[3]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[2]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[1]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[0]}] |
| set_load -pin_load 0.0334 [get_ports {user_irq[2]}] |
| set_load -pin_load 0.0334 [get_ports {user_irq[1]}] |
| set_load -pin_load 0.0334 [get_ports {user_irq[0]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock2}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_cyc_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_stb_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_we_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[127]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[126]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[125]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[124]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[123]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[122]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[121]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[120]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[119]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[118]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[117]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[116]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[115]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[114]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[113]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[112]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[111]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[110]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[109]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[108]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[107]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[106]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[105]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[104]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[103]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[102]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[101]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[100]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[99]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[98]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[97]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[96]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[95]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[94]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[93]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[92]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[91]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[90]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[89]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[88]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[87]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[86]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[85]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[84]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[83]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[82]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[81]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[80]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[79]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[78]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[77]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[76]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[75]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[74]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[73]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[72]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[71]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[70]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[69]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[68]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[67]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[66]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[65]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[64]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[63]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[62]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[61]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[60]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[59]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[58]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[57]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[56]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[55]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[54]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[53]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[52]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[51]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[50]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[49]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[48]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[47]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[46]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[45]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[44]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[43]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[42]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[41]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[40]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[39]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[38]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[127]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[126]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[125]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[124]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[123]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[122]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[121]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[120]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[119]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[118]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[117]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[116]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[115]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[114]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[113]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[112]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[111]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[110]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[109]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[108]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[107]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[106]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[105]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[104]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[103]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[102]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[101]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[100]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[99]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[98]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[97]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[96]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[95]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[94]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[93]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[92]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[91]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[90]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[89]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[88]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[87]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[86]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[85]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[84]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[83]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[82]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[81]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[80]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[79]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[78]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[77]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[76]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[75]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[74]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[73]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[72]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[71]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[70]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[69]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[68]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[67]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[66]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[65]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[64]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[63]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[62]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[61]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[60]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[59]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[58]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[57]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[56]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[55]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[54]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[53]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[52]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[51]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[50]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[49]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[48]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[47]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[46]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[45]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[44]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[43]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[42]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[41]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[40]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[39]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[38]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[0]}] |
| set_timing_derate -early 0.9500 |
| set_timing_derate -late 1.0500 |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |
| set_max_fanout 5.0000 [current_design] |
| [INFO]: Setting RC values... |
| [INFO RSZ-0033] No hold violations found. |
| Placement Analysis |
| --------------------------------- |
| total displacement 326.8 u |
| average displacement 0.0 u |
| max displacement 10.1 u |
| original HPWL 375892.7 u |
| legalized HPWL 378471.2 u |
| delta HPWL 1 % |
| |
| [INFO DPL-0020] Mirrored 1020 instances |
| [INFO DPL-0021] HPWL before 378471.2 u |
| [INFO DPL-0022] HPWL after 376012.5 u |
| [INFO DPL-0023] HPWL delta -0.6 % |
| min_report |
| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: la_data_in[65] (input port clocked by wb_clk_i) |
| Endpoint: _313_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 4.00 4.00 ^ input external delay |
| 0.04 0.02 4.02 ^ la_data_in[65] (in) |
| 1 0.01 la_data_in[65] (net) |
| 0.04 0.00 4.02 ^ input2/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.09 4.12 ^ input2/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net2 (net) |
| 0.05 0.00 4.12 ^ repeater1254/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.07 0.15 4.26 ^ repeater1254/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.02 net1254 (net) |
| 0.07 0.00 4.27 ^ repeater1253/A (sky130_fd_sc_hd__buf_4) |
| 0.07 0.13 4.40 ^ repeater1253/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net1253 (net) |
| 0.07 0.00 4.40 ^ repeater1252/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.10 4.50 ^ repeater1252/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net1252 (net) |
| 0.05 0.00 4.51 ^ _311_/A0 (sky130_fd_sc_hd__mux2_1) |
| 0.09 0.15 4.65 ^ _311_/X (sky130_fd_sc_hd__mux2_1) |
| 1 0.01 _129_ (net) |
| 0.09 0.00 4.65 ^ repeater510/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.11 0.24 4.89 ^ repeater510/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 1 0.02 net510 (net) |
| 0.11 0.00 4.89 ^ repeater509/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.05 0.15 5.05 ^ repeater509/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.01 net509 (net) |
| 0.05 0.00 5.05 ^ repeater508/A (sky130_fd_sc_hd__buf_4) |
| 0.13 0.16 5.21 ^ repeater508/X (sky130_fd_sc_hd__buf_4) |
| 1 0.04 net508 (net) |
| 0.13 0.01 5.22 ^ repeater507/A (sky130_fd_sc_hd__buf_6) |
| 0.02 0.10 5.32 ^ repeater507/X (sky130_fd_sc_hd__buf_6) |
| 1 0.00 net507 (net) |
| 0.02 0.00 5.32 ^ _312_/B (sky130_fd_sc_hd__nor2_1) |
| 0.04 0.04 5.36 v _312_/Y (sky130_fd_sc_hd__nor2_1) |
| 1 0.01 _008_ (net) |
| 0.04 0.00 5.36 v _313_/D (sky130_fd_sc_hd__dfxtp_1) |
| 5.36 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.02 0.01 0.01 ^ wb_clk_i (in) |
| 1 0.00 wb_clk_i (net) |
| 0.02 0.00 0.01 ^ _179_/A1 (sky130_fd_sc_hd__mux2_2) |
| 0.15 0.23 0.25 ^ _179_/X (sky130_fd_sc_hd__mux2_2) |
| 1 0.03 _030_ (net) |
| 0.15 0.00 0.25 ^ _180_/A (sky130_fd_sc_hd__buf_1) |
| 0.14 0.18 0.43 ^ _180_/X (sky130_fd_sc_hd__buf_1) |
| 1 0.01 clk (net) |
| 0.14 0.00 0.43 ^ repeater7/A (sky130_fd_sc_hd__buf_2) |
| 0.13 0.22 0.65 ^ repeater7/X (sky130_fd_sc_hd__buf_2) |
| 1 0.03 net2020 (net) |
| 0.14 0.00 0.65 ^ repeater6/A (sky130_fd_sc_hd__buf_4) |
| 0.09 0.18 0.84 ^ repeater6/X (sky130_fd_sc_hd__buf_4) |
| 1 0.03 net2019 (net) |
| 0.09 0.00 0.84 ^ repeater5/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.12 0.96 ^ repeater5/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net2018 (net) |
| 0.05 0.00 0.97 ^ repeater4/A (sky130_fd_sc_hd__buf_6) |
| 0.13 0.16 1.13 ^ repeater4/X (sky130_fd_sc_hd__buf_6) |
| 1 0.06 net2017 (net) |
| 0.13 0.02 1.15 ^ repeater3/A (sky130_fd_sc_hd__buf_12) |
| 0.04 0.13 1.28 ^ repeater3/X (sky130_fd_sc_hd__buf_12) |
| 1 0.02 net2016 (net) |
| 0.04 0.00 1.28 ^ repeater2/A (sky130_fd_sc_hd__buf_6) |
| 0.06 0.12 1.40 ^ repeater2/X (sky130_fd_sc_hd__buf_6) |
| 1 0.03 net2015 (net) |
| 0.06 0.00 1.40 ^ repeater1/A (sky130_fd_sc_hd__buf_12) |
| 0.05 0.12 1.52 ^ repeater1/X (sky130_fd_sc_hd__buf_12) |
| 1 0.03 net2014 (net) |
| 0.05 0.01 1.52 ^ clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_16) |
| 0.04 0.13 1.66 ^ clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_16) |
| 2 0.02 clknet_0_clk (net) |
| 0.04 0.00 1.66 ^ clkbuf_1_0_0_clk/A (sky130_fd_sc_hd__clkbuf_8) |
| 0.04 0.12 1.78 ^ clkbuf_1_0_0_clk/X (sky130_fd_sc_hd__clkbuf_8) |
| 1 0.01 clknet_1_0_0_clk (net) |
| 0.04 0.00 1.78 ^ clkbuf_1_0_1_clk/A (sky130_fd_sc_hd__clkbuf_8) |
| 0.04 0.12 1.90 ^ clkbuf_1_0_1_clk/X (sky130_fd_sc_hd__clkbuf_8) |
| 1 0.01 clknet_1_0_1_clk (net) |
| 0.04 0.00 1.90 ^ clkbuf_1_0_2_clk/A (sky130_fd_sc_hd__clkbuf_8) |
| 0.04 0.12 2.02 ^ clkbuf_1_0_2_clk/X (sky130_fd_sc_hd__clkbuf_8) |
| 1 0.01 clknet_1_0_2_clk (net) |
| 0.04 0.00 2.02 ^ clkbuf_1_0_3_clk/A (sky130_fd_sc_hd__clkbuf_8) |
| 0.05 0.13 2.15 ^ clkbuf_1_0_3_clk/X (sky130_fd_sc_hd__clkbuf_8) |
| 3 0.02 clknet_1_0_3_clk (net) |
| 0.05 0.00 2.15 ^ repeater16/A (sky130_fd_sc_hd__clkbuf_2) |
| 0.14 0.18 2.33 ^ repeater16/X (sky130_fd_sc_hd__clkbuf_2) |
| 2 0.02 net2029 (net) |
| 0.14 0.00 2.34 ^ repeater12/A (sky130_fd_sc_hd__buf_2) |
| 0.10 0.19 2.53 ^ repeater12/X (sky130_fd_sc_hd__buf_2) |
| 2 0.02 net2025 (net) |
| 0.10 0.00 2.53 ^ _313_/CLK (sky130_fd_sc_hd__dfxtp_1) |
| 0.25 2.78 clock uncertainty |
| 0.00 2.78 clock reconvergence pessimism |
| -0.04 2.74 library hold time |
| 2.74 data required time |
| ----------------------------------------------------------------------------- |
| 2.74 data required time |
| -5.36 data arrival time |
| ----------------------------------------------------------------------------- |
| 2.62 slack (MET) |
| |
| |
| Startpoint: _313_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: wbs_ack_o (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.02 0.01 0.01 ^ wb_clk_i (in) |
| 1 0.00 wb_clk_i (net) |
| 0.02 0.00 0.01 ^ _179_/A1 (sky130_fd_sc_hd__mux2_2) |
| 0.15 0.21 0.22 ^ _179_/X (sky130_fd_sc_hd__mux2_2) |
| 1 0.03 _030_ (net) |
| 0.15 0.00 0.23 ^ _180_/A (sky130_fd_sc_hd__buf_1) |
| 0.14 0.16 0.39 ^ _180_/X (sky130_fd_sc_hd__buf_1) |
| 1 0.01 clk (net) |
| 0.14 0.00 0.39 ^ repeater7/A (sky130_fd_sc_hd__buf_2) |
| 0.13 0.19 0.59 ^ repeater7/X (sky130_fd_sc_hd__buf_2) |
| 1 0.03 net2020 (net) |
| 0.14 0.00 0.59 ^ repeater6/A (sky130_fd_sc_hd__buf_4) |
| 0.09 0.17 0.76 ^ repeater6/X (sky130_fd_sc_hd__buf_4) |
| 1 0.03 net2019 (net) |
| 0.09 0.00 0.76 ^ repeater5/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.11 0.87 ^ repeater5/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net2018 (net) |
| 0.05 0.00 0.87 ^ repeater4/A (sky130_fd_sc_hd__buf_6) |
| 0.13 0.15 1.02 ^ repeater4/X (sky130_fd_sc_hd__buf_6) |
| 1 0.06 net2017 (net) |
| 0.13 0.02 1.04 ^ repeater3/A (sky130_fd_sc_hd__buf_12) |
| 0.04 0.11 1.15 ^ repeater3/X (sky130_fd_sc_hd__buf_12) |
| 1 0.02 net2016 (net) |
| 0.04 0.00 1.16 ^ repeater2/A (sky130_fd_sc_hd__buf_6) |
| 0.06 0.11 1.26 ^ repeater2/X (sky130_fd_sc_hd__buf_6) |
| 1 0.03 net2015 (net) |
| 0.06 0.00 1.26 ^ repeater1/A (sky130_fd_sc_hd__buf_12) |
| 0.05 0.11 1.37 ^ repeater1/X (sky130_fd_sc_hd__buf_12) |
| 1 0.03 net2014 (net) |
| 0.05 0.00 1.38 ^ clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_16) |
| 0.04 0.12 1.50 ^ clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_16) |
| 2 0.02 clknet_0_clk (net) |
| 0.04 0.00 1.50 ^ clkbuf_1_0_0_clk/A (sky130_fd_sc_hd__clkbuf_8) |
| 0.04 0.11 1.61 ^ clkbuf_1_0_0_clk/X (sky130_fd_sc_hd__clkbuf_8) |
| 1 0.01 clknet_1_0_0_clk (net) |
| 0.04 0.00 1.61 ^ clkbuf_1_0_1_clk/A (sky130_fd_sc_hd__clkbuf_8) |
| 0.04 0.11 1.72 ^ clkbuf_1_0_1_clk/X (sky130_fd_sc_hd__clkbuf_8) |
| 1 0.01 clknet_1_0_1_clk (net) |
| 0.04 0.00 1.72 ^ clkbuf_1_0_2_clk/A (sky130_fd_sc_hd__clkbuf_8) |
| 0.04 0.11 1.83 ^ clkbuf_1_0_2_clk/X (sky130_fd_sc_hd__clkbuf_8) |
| 1 0.01 clknet_1_0_2_clk (net) |
| 0.04 0.00 1.83 ^ clkbuf_1_0_3_clk/A (sky130_fd_sc_hd__clkbuf_8) |
| 0.05 0.12 1.95 ^ clkbuf_1_0_3_clk/X (sky130_fd_sc_hd__clkbuf_8) |
| 3 0.02 clknet_1_0_3_clk (net) |
| 0.05 0.00 1.95 ^ repeater16/A (sky130_fd_sc_hd__clkbuf_2) |
| 0.14 0.16 2.11 ^ repeater16/X (sky130_fd_sc_hd__clkbuf_2) |
| 2 0.02 net2029 (net) |
| 0.14 0.00 2.11 ^ repeater12/A (sky130_fd_sc_hd__buf_2) |
| 0.10 0.17 2.29 ^ repeater12/X (sky130_fd_sc_hd__buf_2) |
| 2 0.02 net2025 (net) |
| 0.10 0.00 2.29 ^ _313_/CLK (sky130_fd_sc_hd__dfxtp_1) |
| 0.06 0.32 2.61 ^ _313_/Q (sky130_fd_sc_hd__dfxtp_1) |
| 1 0.00 net116 (net) |
| 0.06 0.00 2.61 ^ repeater485/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.13 0.15 2.75 ^ repeater485/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.01 net485 (net) |
| 0.13 0.00 2.75 ^ repeater484/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.12 0.21 2.97 ^ repeater484/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.04 net484 (net) |
| 0.12 0.01 2.97 ^ repeater483/A (sky130_fd_sc_hd__buf_4) |
| 0.05 0.13 3.11 ^ repeater483/X (sky130_fd_sc_hd__buf_4) |
| 1 0.01 net483 (net) |
| 0.05 0.00 3.11 ^ repeater482/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.10 3.21 ^ repeater482/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net482 (net) |
| 0.05 0.00 3.21 ^ repeater481/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.10 3.31 ^ repeater481/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net481 (net) |
| 0.05 0.00 3.31 ^ repeater480/A (sky130_fd_sc_hd__buf_4) |
| 0.06 0.12 3.43 ^ repeater480/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net480 (net) |
| 0.06 0.00 3.43 ^ repeater479/A (sky130_fd_sc_hd__buf_4) |
| 0.06 0.13 3.56 ^ repeater479/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net479 (net) |
| 0.06 0.00 3.56 ^ repeater478/A (sky130_fd_sc_hd__buf_4) |
| 0.06 0.12 3.68 ^ repeater478/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net478 (net) |
| 0.06 0.00 3.68 ^ repeater477/A (sky130_fd_sc_hd__buf_4) |
| 0.06 0.13 3.81 ^ repeater477/X (sky130_fd_sc_hd__buf_4) |
| 2 0.02 net477 (net) |
| 0.06 0.00 3.81 ^ output116/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.11 0.18 4.00 ^ output116/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.03 wbs_ack_o (net) |
| 0.11 0.00 4.00 ^ wbs_ack_o (out) |
| 4.00 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| -4.00 -3.75 output external delay |
| -3.75 data required time |
| ----------------------------------------------------------------------------- |
| -3.75 data required time |
| -4.00 data arrival time |
| ----------------------------------------------------------------------------- |
| 7.75 slack (MET) |
| |
| |
| Startpoint: wbs_dat_i[20] (input port clocked by wb_clk_i) |
| Endpoint: la_data_out[52] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 4.00 4.00 ^ input external delay |
| 0.02 0.01 4.01 ^ wbs_dat_i[20] (in) |
| 1 0.00 wbs_dat_i[20] (net) |
| 0.02 0.00 4.01 ^ input30/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.08 0.10 4.11 ^ input30/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 2 0.01 net30 (net) |
| 0.08 0.00 4.11 ^ repeater1027/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.20 0.20 4.32 ^ repeater1027/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.02 net1027 (net) |
| 0.20 0.00 4.32 ^ repeater1026/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.07 0.20 4.52 ^ repeater1026/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.02 net1026 (net) |
| 0.07 0.00 4.52 ^ repeater1025/A (sky130_fd_sc_hd__buf_4) |
| 0.07 0.13 4.65 ^ repeater1025/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net1025 (net) |
| 0.07 0.00 4.65 ^ repeater1024/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.11 4.76 ^ repeater1024/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net1024 (net) |
| 0.05 0.00 4.76 ^ repeater1023/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.10 4.87 ^ repeater1023/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net1023 (net) |
| 0.05 0.00 4.87 ^ repeater1022/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.10 4.97 ^ repeater1022/X (sky130_fd_sc_hd__buf_6) |
| 2 0.02 net1022 (net) |
| 0.05 0.00 4.97 ^ _497_/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.06 0.09 5.07 ^ _497_/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.00 net99 (net) |
| 0.06 0.00 5.07 ^ output99/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.11 0.18 5.25 ^ output99/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.03 la_data_out[52] (net) |
| 0.11 0.00 5.25 ^ la_data_out[52] (out) |
| 5.25 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| -4.00 -3.75 output external delay |
| -3.75 data required time |
| ----------------------------------------------------------------------------- |
| -3.75 data required time |
| -5.25 data arrival time |
| ----------------------------------------------------------------------------- |
| 9.00 slack (MET) |
| |
| |
| Startpoint: wbs_dat_i[3] (input port clocked by wb_clk_i) |
| Endpoint: la_data_out[35] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 4.00 4.00 ^ input external delay |
| 0.02 0.01 4.01 ^ wbs_dat_i[3] (in) |
| 1 0.00 wbs_dat_i[3] (net) |
| 0.02 0.00 4.01 ^ input43/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.04 0.11 4.12 ^ input43/X (sky130_fd_sc_hd__clkbuf_4) |
| 2 0.01 net43 (net) |
| 0.04 0.00 4.12 ^ repeater763/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.20 0.19 4.31 ^ repeater763/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.02 net763 (net) |
| 0.20 0.00 4.32 ^ repeater762/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.07 0.20 4.51 ^ repeater762/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.02 net762 (net) |
| 0.07 0.00 4.51 ^ repeater761/A (sky130_fd_sc_hd__buf_4) |
| 0.07 0.13 4.65 ^ repeater761/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net761 (net) |
| 0.07 0.00 4.65 ^ repeater760/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.11 4.76 ^ repeater760/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net760 (net) |
| 0.05 0.00 4.76 ^ repeater759/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.10 4.86 ^ repeater759/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net759 (net) |
| 0.05 0.00 4.87 ^ repeater758/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.10 4.97 ^ repeater758/X (sky130_fd_sc_hd__buf_6) |
| 2 0.02 net758 (net) |
| 0.05 0.00 4.97 ^ _480_/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.06 0.10 5.07 ^ _480_/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.00 net80 (net) |
| 0.06 0.00 5.07 ^ output80/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.12 0.18 5.25 ^ output80/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.03 la_data_out[35] (net) |
| 0.12 0.00 5.25 ^ la_data_out[35] (out) |
| 5.25 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| -4.00 -3.75 output external delay |
| -3.75 data required time |
| ----------------------------------------------------------------------------- |
| -3.75 data required time |
| -5.25 data arrival time |
| ----------------------------------------------------------------------------- |
| 9.00 slack (MET) |
| |
| |
| Startpoint: wbs_dat_i[5] (input port clocked by wb_clk_i) |
| Endpoint: la_data_out[37] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 4.00 4.00 ^ input external delay |
| 0.02 0.01 4.01 ^ wbs_dat_i[5] (in) |
| 1 0.00 wbs_dat_i[5] (net) |
| 0.02 0.00 4.01 ^ input45/A (sky130_fd_sc_hd__buf_4) |
| 0.06 0.11 4.13 ^ input45/X (sky130_fd_sc_hd__buf_4) |
| 2 0.02 net45 (net) |
| 0.06 0.00 4.13 ^ repeater717/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.20 0.19 4.32 ^ repeater717/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.02 net717 (net) |
| 0.20 0.00 4.32 ^ repeater716/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.07 0.20 4.52 ^ repeater716/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.02 net716 (net) |
| 0.07 0.00 4.52 ^ repeater715/A (sky130_fd_sc_hd__buf_4) |
| 0.07 0.13 4.65 ^ repeater715/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net715 (net) |
| 0.07 0.00 4.65 ^ repeater714/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.11 4.76 ^ repeater714/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net714 (net) |
| 0.05 0.00 4.76 ^ repeater713/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.10 4.87 ^ repeater713/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net713 (net) |
| 0.05 0.00 4.87 ^ repeater712/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.10 4.97 ^ repeater712/X (sky130_fd_sc_hd__buf_6) |
| 2 0.02 net712 (net) |
| 0.05 0.00 4.97 ^ _482_/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.06 0.10 5.07 ^ _482_/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.00 net82 (net) |
| 0.06 0.00 5.07 ^ output82/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.11 0.18 5.25 ^ output82/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.03 la_data_out[37] (net) |
| 0.11 0.00 5.25 ^ la_data_out[37] (out) |
| 5.25 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| -4.00 -3.75 output external delay |
| -3.75 data required time |
| ----------------------------------------------------------------------------- |
| -3.75 data required time |
| -5.25 data arrival time |
| ----------------------------------------------------------------------------- |
| 9.00 slack (MET) |
| |
| |
| min_report_end |
| max_report |
| |
| =========================================================================== |
| report_checks -path_delay max (Setup) |
| ============================================================================ |
| Startpoint: wbs_adr_i[11] (input port clocked by wb_clk_i) |
| Endpoint: wbs_dat_o[29] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 4.00 4.00 ^ input external delay |
| 0.02 0.01 4.01 ^ wbs_adr_i[11] (in) |
| 1 0.00 wbs_adr_i[11] (net) |
| 0.02 0.00 4.01 ^ input7/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.06 0.10 4.11 ^ input7/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.00 net7 (net) |
| 0.06 0.00 4.11 ^ repeater562/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.20 0.21 4.32 ^ repeater562/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.02 net562 (net) |
| 0.20 0.00 4.33 ^ repeater561/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.07 0.22 4.54 ^ repeater561/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.02 net561 (net) |
| 0.07 0.00 4.54 ^ repeater560/A (sky130_fd_sc_hd__buf_4) |
| 0.07 0.15 4.69 ^ repeater560/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net560 (net) |
| 0.07 0.00 4.69 ^ repeater559/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.12 4.81 ^ repeater559/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net559 (net) |
| 0.05 0.00 4.81 ^ repeater558/A (sky130_fd_sc_hd__buf_6) |
| 0.04 0.10 4.92 ^ repeater558/X (sky130_fd_sc_hd__buf_6) |
| 1 0.01 net558 (net) |
| 0.04 0.00 4.92 ^ repeater557/A (sky130_fd_sc_hd__buf_6) |
| 0.04 0.10 5.01 ^ repeater557/X (sky130_fd_sc_hd__buf_6) |
| 1 0.01 net557 (net) |
| 0.04 0.00 5.01 ^ repeater556/A (sky130_fd_sc_hd__buf_4) |
| 0.12 0.17 5.18 ^ repeater556/X (sky130_fd_sc_hd__buf_4) |
| 1 0.04 net556 (net) |
| 0.12 0.01 5.19 ^ repeater555/A (sky130_fd_sc_hd__buf_4) |
| 0.05 0.15 5.34 ^ repeater555/X (sky130_fd_sc_hd__buf_4) |
| 2 0.01 net555 (net) |
| 0.05 0.00 5.34 ^ repeater554/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.19 0.20 5.54 ^ repeater554/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 4 0.02 net554 (net) |
| 0.19 0.00 5.54 ^ _159_/A (sky130_fd_sc_hd__inv_2) |
| 0.05 0.06 5.61 v _159_/Y (sky130_fd_sc_hd__inv_2) |
| 2 0.01 _016_ (net) |
| 0.05 0.00 5.61 v _160_/A (sky130_fd_sc_hd__buf_6) |
| 0.02 0.12 5.72 v _160_/X (sky130_fd_sc_hd__buf_6) |
| 1 0.01 _017_ (net) |
| 0.02 0.00 5.72 v repeater506/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.08 0.25 5.97 v repeater506/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 2 0.02 net506 (net) |
| 0.08 0.00 5.97 v repeater505/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.04 0.17 6.14 v repeater505/X (sky130_fd_sc_hd__clkbuf_4) |
| 2 0.01 net505 (net) |
| 0.04 0.00 6.14 v _161_/A (sky130_fd_sc_hd__buf_6) |
| 0.02 0.11 6.26 v _161_/X (sky130_fd_sc_hd__buf_6) |
| 2 0.01 _018_ (net) |
| 0.02 0.00 6.26 v repeater493/A (sky130_fd_sc_hd__clkdlybuf4s18_2) |
| 0.07 0.25 6.51 v repeater493/X (sky130_fd_sc_hd__clkdlybuf4s18_2) |
| 3 0.02 net493 (net) |
| 0.07 0.00 6.51 v repeater492/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.15 0.32 6.83 v repeater492/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 1 0.04 net492 (net) |
| 0.15 0.01 6.84 v repeater491/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.03 0.19 7.03 v repeater491/X (sky130_fd_sc_hd__clkbuf_4) |
| 2 0.01 net491 (net) |
| 0.03 0.00 7.03 v _303_/A1 (sky130_fd_sc_hd__a22o_1) |
| 0.04 0.20 7.24 v _303_/X (sky130_fd_sc_hd__a22o_1) |
| 1 0.00 _124_ (net) |
| 0.04 0.00 7.24 v repeater401/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.15 0.31 7.55 v repeater401/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 1 0.04 net401 (net) |
| 0.15 0.01 7.56 v repeater400/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.03 0.20 7.75 v repeater400/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.01 net400 (net) |
| 0.03 0.00 7.75 v repeater399/A (sky130_fd_sc_hd__buf_4) |
| 0.04 0.15 7.91 v repeater399/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net399 (net) |
| 0.04 0.00 7.91 v _304_/B2 (sky130_fd_sc_hd__o22a_2) |
| 0.12 0.28 8.18 v _304_/X (sky130_fd_sc_hd__o22a_2) |
| 1 0.03 net73 (net) |
| 0.12 0.01 8.19 v repeater343/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.09 0.23 8.42 v repeater343/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.04 net343 (net) |
| 0.09 0.01 8.43 v repeater342/A (sky130_fd_sc_hd__buf_4) |
| 0.04 0.17 8.60 v repeater342/X (sky130_fd_sc_hd__buf_4) |
| 1 0.01 net342 (net) |
| 0.04 0.00 8.60 v repeater341/A (sky130_fd_sc_hd__buf_6) |
| 0.03 0.13 8.73 v repeater341/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net341 (net) |
| 0.03 0.00 8.74 v repeater340/A (sky130_fd_sc_hd__buf_6) |
| 0.03 0.13 8.86 v repeater340/X (sky130_fd_sc_hd__buf_6) |
| 2 0.02 net340 (net) |
| 0.03 0.00 8.86 v _538_/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.04 0.14 9.00 v _538_/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.01 net138 (net) |
| 0.04 0.00 9.01 v repeater187/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.08 0.25 9.25 v repeater187/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 1 0.02 net187 (net) |
| 0.08 0.00 9.26 v repeater186/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.05 0.18 9.44 v repeater186/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.02 net186 (net) |
| 0.05 0.00 9.44 v output138/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.08 0.20 9.64 v output138/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.03 wbs_dat_o[29] (net) |
| 0.08 0.00 9.64 v wbs_dat_o[29] (out) |
| 9.64 data arrival time |
| |
| 20.00 20.00 clock wb_clk_i (rise edge) |
| 0.00 20.00 clock network delay (propagated) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -9.64 data arrival time |
| ----------------------------------------------------------------------------- |
| 6.11 slack (MET) |
| |
| |
| Startpoint: wbs_adr_i[11] (input port clocked by wb_clk_i) |
| Endpoint: wbs_dat_o[28] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 4.00 4.00 ^ input external delay |
| 0.02 0.01 4.01 ^ wbs_adr_i[11] (in) |
| 1 0.00 wbs_adr_i[11] (net) |
| 0.02 0.00 4.01 ^ input7/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.06 0.10 4.11 ^ input7/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.00 net7 (net) |
| 0.06 0.00 4.11 ^ repeater562/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.20 0.21 4.32 ^ repeater562/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.02 net562 (net) |
| 0.20 0.00 4.33 ^ repeater561/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.07 0.22 4.54 ^ repeater561/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.02 net561 (net) |
| 0.07 0.00 4.54 ^ repeater560/A (sky130_fd_sc_hd__buf_4) |
| 0.07 0.15 4.69 ^ repeater560/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net560 (net) |
| 0.07 0.00 4.69 ^ repeater559/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.12 4.81 ^ repeater559/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net559 (net) |
| 0.05 0.00 4.81 ^ repeater558/A (sky130_fd_sc_hd__buf_6) |
| 0.04 0.10 4.92 ^ repeater558/X (sky130_fd_sc_hd__buf_6) |
| 1 0.01 net558 (net) |
| 0.04 0.00 4.92 ^ repeater557/A (sky130_fd_sc_hd__buf_6) |
| 0.04 0.10 5.01 ^ repeater557/X (sky130_fd_sc_hd__buf_6) |
| 1 0.01 net557 (net) |
| 0.04 0.00 5.01 ^ repeater556/A (sky130_fd_sc_hd__buf_4) |
| 0.12 0.17 5.18 ^ repeater556/X (sky130_fd_sc_hd__buf_4) |
| 1 0.04 net556 (net) |
| 0.12 0.01 5.19 ^ repeater555/A (sky130_fd_sc_hd__buf_4) |
| 0.05 0.15 5.34 ^ repeater555/X (sky130_fd_sc_hd__buf_4) |
| 2 0.01 net555 (net) |
| 0.05 0.00 5.34 ^ repeater554/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.19 0.20 5.54 ^ repeater554/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 4 0.02 net554 (net) |
| 0.19 0.00 5.54 ^ _159_/A (sky130_fd_sc_hd__inv_2) |
| 0.05 0.06 5.61 v _159_/Y (sky130_fd_sc_hd__inv_2) |
| 2 0.01 _016_ (net) |
| 0.05 0.00 5.61 v _160_/A (sky130_fd_sc_hd__buf_6) |
| 0.02 0.12 5.72 v _160_/X (sky130_fd_sc_hd__buf_6) |
| 1 0.01 _017_ (net) |
| 0.02 0.00 5.72 v repeater506/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.08 0.25 5.97 v repeater506/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 2 0.02 net506 (net) |
| 0.08 0.00 5.97 v repeater505/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.04 0.17 6.14 v repeater505/X (sky130_fd_sc_hd__clkbuf_4) |
| 2 0.01 net505 (net) |
| 0.04 0.00 6.14 v _161_/A (sky130_fd_sc_hd__buf_6) |
| 0.02 0.11 6.26 v _161_/X (sky130_fd_sc_hd__buf_6) |
| 2 0.01 _018_ (net) |
| 0.02 0.00 6.26 v repeater493/A (sky130_fd_sc_hd__clkdlybuf4s18_2) |
| 0.07 0.25 6.51 v repeater493/X (sky130_fd_sc_hd__clkdlybuf4s18_2) |
| 3 0.02 net493 (net) |
| 0.07 0.00 6.51 v repeater492/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.15 0.32 6.83 v repeater492/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 1 0.04 net492 (net) |
| 0.15 0.01 6.84 v repeater491/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.03 0.19 7.03 v repeater491/X (sky130_fd_sc_hd__clkbuf_4) |
| 2 0.01 net491 (net) |
| 0.03 0.00 7.03 v _300_/A1 (sky130_fd_sc_hd__a22o_1) |
| 0.04 0.20 7.24 v _300_/X (sky130_fd_sc_hd__a22o_1) |
| 1 0.00 _122_ (net) |
| 0.04 0.00 7.24 v repeater404/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.15 0.31 7.55 v repeater404/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 1 0.04 net404 (net) |
| 0.15 0.01 7.56 v repeater403/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.03 0.19 7.75 v repeater403/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.01 net403 (net) |
| 0.03 0.00 7.75 v repeater402/A (sky130_fd_sc_hd__buf_4) |
| 0.04 0.15 7.90 v repeater402/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net402 (net) |
| 0.04 0.00 7.91 v _301_/B2 (sky130_fd_sc_hd__o22a_2) |
| 0.03 0.18 8.08 v _301_/X (sky130_fd_sc_hd__o22a_2) |
| 1 0.00 net72 (net) |
| 0.03 0.00 8.08 v repeater347/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.09 0.19 8.28 v repeater347/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.04 net347 (net) |
| 0.09 0.01 8.29 v repeater346/A (sky130_fd_sc_hd__buf_4) |
| 0.04 0.17 8.46 v repeater346/X (sky130_fd_sc_hd__buf_4) |
| 1 0.01 net346 (net) |
| 0.04 0.00 8.46 v repeater345/A (sky130_fd_sc_hd__buf_6) |
| 0.03 0.13 8.59 v repeater345/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net345 (net) |
| 0.03 0.00 8.59 v repeater344/A (sky130_fd_sc_hd__buf_6) |
| 0.03 0.13 8.72 v repeater344/X (sky130_fd_sc_hd__buf_6) |
| 2 0.02 net344 (net) |
| 0.03 0.00 8.72 v _537_/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.04 0.14 8.86 v _537_/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.01 net137 (net) |
| 0.04 0.00 8.86 v repeater189/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.08 0.25 9.11 v repeater189/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 1 0.02 net189 (net) |
| 0.08 0.00 9.11 v repeater188/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.05 0.18 9.29 v repeater188/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.02 net188 (net) |
| 0.05 0.00 9.30 v output137/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.08 0.20 9.49 v output137/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.03 wbs_dat_o[28] (net) |
| 0.08 0.00 9.49 v wbs_dat_o[28] (out) |
| 9.49 data arrival time |
| |
| 20.00 20.00 clock wb_clk_i (rise edge) |
| 0.00 20.00 clock network delay (propagated) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -9.49 data arrival time |
| ----------------------------------------------------------------------------- |
| 6.26 slack (MET) |
| |
| |
| Startpoint: wbs_adr_i[11] (input port clocked by wb_clk_i) |
| Endpoint: wbs_dat_o[14] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 4.00 4.00 ^ input external delay |
| 0.02 0.01 4.01 ^ wbs_adr_i[11] (in) |
| 1 0.00 wbs_adr_i[11] (net) |
| 0.02 0.00 4.01 ^ input7/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.06 0.10 4.11 ^ input7/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.00 net7 (net) |
| 0.06 0.00 4.11 ^ repeater562/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.20 0.21 4.32 ^ repeater562/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.02 net562 (net) |
| 0.20 0.00 4.33 ^ repeater561/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.07 0.22 4.54 ^ repeater561/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.02 net561 (net) |
| 0.07 0.00 4.54 ^ repeater560/A (sky130_fd_sc_hd__buf_4) |
| 0.07 0.15 4.69 ^ repeater560/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net560 (net) |
| 0.07 0.00 4.69 ^ repeater559/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.12 4.81 ^ repeater559/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net559 (net) |
| 0.05 0.00 4.81 ^ repeater558/A (sky130_fd_sc_hd__buf_6) |
| 0.04 0.10 4.92 ^ repeater558/X (sky130_fd_sc_hd__buf_6) |
| 1 0.01 net558 (net) |
| 0.04 0.00 4.92 ^ repeater557/A (sky130_fd_sc_hd__buf_6) |
| 0.04 0.10 5.01 ^ repeater557/X (sky130_fd_sc_hd__buf_6) |
| 1 0.01 net557 (net) |
| 0.04 0.00 5.01 ^ repeater556/A (sky130_fd_sc_hd__buf_4) |
| 0.12 0.17 5.18 ^ repeater556/X (sky130_fd_sc_hd__buf_4) |
| 1 0.04 net556 (net) |
| 0.12 0.01 5.19 ^ repeater555/A (sky130_fd_sc_hd__buf_4) |
| 0.05 0.15 5.34 ^ repeater555/X (sky130_fd_sc_hd__buf_4) |
| 2 0.01 net555 (net) |
| 0.05 0.00 5.34 ^ repeater554/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.19 0.20 5.54 ^ repeater554/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 4 0.02 net554 (net) |
| 0.19 0.00 5.54 ^ _159_/A (sky130_fd_sc_hd__inv_2) |
| 0.05 0.06 5.61 v _159_/Y (sky130_fd_sc_hd__inv_2) |
| 2 0.01 _016_ (net) |
| 0.05 0.00 5.61 v _160_/A (sky130_fd_sc_hd__buf_6) |
| 0.02 0.12 5.72 v _160_/X (sky130_fd_sc_hd__buf_6) |
| 1 0.01 _017_ (net) |
| 0.02 0.00 5.72 v repeater506/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.08 0.25 5.97 v repeater506/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 2 0.02 net506 (net) |
| 0.08 0.00 5.97 v repeater505/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.04 0.17 6.14 v repeater505/X (sky130_fd_sc_hd__clkbuf_4) |
| 2 0.01 net505 (net) |
| 0.04 0.00 6.15 v repeater504/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.09 0.20 6.34 v repeater504/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.04 net504 (net) |
| 0.09 0.01 6.35 v repeater503/A (sky130_fd_sc_hd__buf_4) |
| 0.03 0.17 6.52 v repeater503/X (sky130_fd_sc_hd__buf_4) |
| 3 0.01 net503 (net) |
| 0.03 0.00 6.52 v _240_/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.09 0.19 6.71 v _240_/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 5 0.02 _077_ (net) |
| 0.09 0.00 6.71 v _244_/A1 (sky130_fd_sc_hd__a22o_1) |
| 0.04 0.23 6.94 v _244_/X (sky130_fd_sc_hd__a22o_1) |
| 1 0.00 _080_ (net) |
| 0.04 0.00 6.94 v repeater446/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.15 0.31 7.25 v repeater446/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 1 0.04 net446 (net) |
| 0.15 0.01 7.26 v repeater445/A (sky130_fd_sc_hd__buf_4) |
| 0.03 0.19 7.46 v repeater445/X (sky130_fd_sc_hd__buf_4) |
| 1 0.01 net445 (net) |
| 0.03 0.00 7.46 v repeater444/A (sky130_fd_sc_hd__buf_4) |
| 0.04 0.15 7.61 v repeater444/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net444 (net) |
| 0.04 0.00 7.61 v _245_/B2 (sky130_fd_sc_hd__o22a_1) |
| 0.04 0.15 7.76 v _245_/X (sky130_fd_sc_hd__o22a_1) |
| 1 0.00 net57 (net) |
| 0.04 0.00 7.76 v repeater234/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.04 0.14 7.89 v repeater234/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.00 net234 (net) |
| 0.04 0.00 7.89 v repeater233/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.09 0.20 8.09 v repeater233/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.04 net233 (net) |
| 0.09 0.01 8.10 v repeater232/A (sky130_fd_sc_hd__buf_4) |
| 0.04 0.18 8.28 v repeater232/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net232 (net) |
| 0.04 0.00 8.28 v repeater231/A (sky130_fd_sc_hd__buf_6) |
| 0.03 0.13 8.41 v repeater231/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net231 (net) |
| 0.03 0.00 8.41 v repeater230/A (sky130_fd_sc_hd__buf_6) |
| 0.03 0.13 8.54 v repeater230/X (sky130_fd_sc_hd__buf_6) |
| 2 0.02 net230 (net) |
| 0.03 0.00 8.54 v repeater229/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.08 0.25 8.79 v repeater229/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 1 0.02 net229 (net) |
| 0.08 0.00 8.79 v _523_/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.03 0.16 8.95 v _523_/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.01 net122 (net) |
| 0.03 0.00 8.95 v repeater156/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.08 0.25 9.20 v repeater156/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 1 0.02 net156 (net) |
| 0.08 0.00 9.20 v output122/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.08 0.21 9.41 v output122/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.03 wbs_dat_o[14] (net) |
| 0.08 0.00 9.41 v wbs_dat_o[14] (out) |
| 9.41 data arrival time |
| |
| 20.00 20.00 clock wb_clk_i (rise edge) |
| 0.00 20.00 clock network delay (propagated) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -9.41 data arrival time |
| ----------------------------------------------------------------------------- |
| 6.34 slack (MET) |
| |
| |
| Startpoint: wbs_adr_i[11] (input port clocked by wb_clk_i) |
| Endpoint: wbs_dat_o[19] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 4.00 4.00 v input external delay |
| 0.01 0.00 4.00 v wbs_adr_i[11] (in) |
| 1 0.00 wbs_adr_i[11] (net) |
| 0.01 0.00 4.00 v input7/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.04 0.13 4.13 v input7/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.00 net7 (net) |
| 0.04 0.00 4.13 v repeater562/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.10 0.20 4.33 v repeater562/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.02 net562 (net) |
| 0.10 0.00 4.34 v repeater561/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.05 0.19 4.53 v repeater561/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.02 net561 (net) |
| 0.05 0.00 4.53 v repeater560/A (sky130_fd_sc_hd__buf_4) |
| 0.04 0.16 4.69 v repeater560/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net560 (net) |
| 0.04 0.00 4.70 v repeater559/A (sky130_fd_sc_hd__buf_6) |
| 0.03 0.13 4.83 v repeater559/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net559 (net) |
| 0.03 0.00 4.83 v repeater558/A (sky130_fd_sc_hd__buf_6) |
| 0.03 0.12 4.95 v repeater558/X (sky130_fd_sc_hd__buf_6) |
| 1 0.01 net558 (net) |
| 0.03 0.00 4.95 v repeater557/A (sky130_fd_sc_hd__buf_6) |
| 0.03 0.12 5.06 v repeater557/X (sky130_fd_sc_hd__buf_6) |
| 1 0.01 net557 (net) |
| 0.03 0.00 5.06 v repeater556/A (sky130_fd_sc_hd__buf_4) |
| 0.07 0.17 5.24 v repeater556/X (sky130_fd_sc_hd__buf_4) |
| 1 0.04 net556 (net) |
| 0.07 0.01 5.25 v repeater555/A (sky130_fd_sc_hd__buf_4) |
| 0.04 0.16 5.40 v repeater555/X (sky130_fd_sc_hd__buf_4) |
| 2 0.01 net555 (net) |
| 0.04 0.00 5.41 v repeater554/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.09 0.19 5.60 v repeater554/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 4 0.02 net554 (net) |
| 0.09 0.00 5.60 v _159_/A (sky130_fd_sc_hd__inv_2) |
| 0.05 0.08 5.68 ^ _159_/Y (sky130_fd_sc_hd__inv_2) |
| 2 0.01 _016_ (net) |
| 0.05 0.00 5.68 ^ _160_/A (sky130_fd_sc_hd__buf_6) |
| 0.03 0.09 5.77 ^ _160_/X (sky130_fd_sc_hd__buf_6) |
| 1 0.01 _017_ (net) |
| 0.03 0.00 5.77 ^ repeater506/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.12 0.25 6.02 ^ repeater506/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 2 0.02 net506 (net) |
| 0.12 0.00 6.03 ^ repeater505/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.05 0.17 6.20 ^ repeater505/X (sky130_fd_sc_hd__clkbuf_4) |
| 2 0.01 net505 (net) |
| 0.05 0.00 6.20 ^ repeater504/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.13 0.21 6.41 ^ repeater504/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.04 net504 (net) |
| 0.13 0.01 6.42 ^ repeater503/A (sky130_fd_sc_hd__buf_4) |
| 0.05 0.15 6.57 ^ repeater503/X (sky130_fd_sc_hd__buf_4) |
| 3 0.01 net503 (net) |
| 0.05 0.00 6.57 ^ _260_/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.19 0.20 6.77 ^ _260_/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 5 0.02 _092_ (net) |
| 0.19 0.00 6.77 ^ _264_/A1 (sky130_fd_sc_hd__a22o_1) |
| 0.05 0.17 6.94 ^ _264_/X (sky130_fd_sc_hd__a22o_1) |
| 1 0.00 _095_ (net) |
| 0.05 0.00 6.94 ^ repeater431/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.22 0.34 7.27 ^ repeater431/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 1 0.04 net431 (net) |
| 0.22 0.01 7.28 ^ repeater430/A (sky130_fd_sc_hd__buf_4) |
| 0.04 0.17 7.45 ^ repeater430/X (sky130_fd_sc_hd__buf_4) |
| 1 0.01 net430 (net) |
| 0.04 0.00 7.45 ^ repeater429/A (sky130_fd_sc_hd__buf_4) |
| 0.06 0.13 7.58 ^ repeater429/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net429 (net) |
| 0.06 0.00 7.58 ^ _265_/B2 (sky130_fd_sc_hd__o22a_1) |
| 0.04 0.11 7.69 ^ _265_/X (sky130_fd_sc_hd__o22a_1) |
| 1 0.00 net62 (net) |
| 0.04 0.00 7.69 ^ repeater208/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.40 0.35 8.05 ^ repeater208/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.04 net208 (net) |
| 0.40 0.01 8.05 ^ repeater207/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.04 0.23 8.28 ^ repeater207/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.00 net207 (net) |
| 0.04 0.00 8.28 ^ repeater206/A (sky130_fd_sc_hd__buf_4) |
| 0.06 0.13 8.41 ^ repeater206/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net206 (net) |
| 0.06 0.00 8.41 ^ repeater205/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.12 8.53 ^ repeater205/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net205 (net) |
| 0.05 0.00 8.53 ^ repeater204/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.11 8.65 ^ repeater204/X (sky130_fd_sc_hd__buf_6) |
| 2 0.02 net204 (net) |
| 0.05 0.00 8.65 ^ _528_/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.07 0.11 8.76 ^ _528_/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.00 net127 (net) |
| 0.07 0.00 8.76 ^ repeater150/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.20 0.22 8.98 ^ repeater150/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.02 net150 (net) |
| 0.20 0.00 8.98 ^ repeater149/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.07 0.22 9.20 ^ repeater149/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.02 net149 (net) |
| 0.07 0.00 9.20 ^ output127/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.11 0.20 9.40 ^ output127/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.03 wbs_dat_o[19] (net) |
| 0.11 0.00 9.41 ^ wbs_dat_o[19] (out) |
| 9.41 data arrival time |
| |
| 20.00 20.00 clock wb_clk_i (rise edge) |
| 0.00 20.00 clock network delay (propagated) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -9.41 data arrival time |
| ----------------------------------------------------------------------------- |
| 6.34 slack (MET) |
| |
| |
| Startpoint: wbs_adr_i[11] (input port clocked by wb_clk_i) |
| Endpoint: wbs_dat_o[18] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 4.00 4.00 v input external delay |
| 0.01 0.00 4.00 v wbs_adr_i[11] (in) |
| 1 0.00 wbs_adr_i[11] (net) |
| 0.01 0.00 4.00 v input7/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.04 0.13 4.13 v input7/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.00 net7 (net) |
| 0.04 0.00 4.13 v repeater562/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.10 0.20 4.33 v repeater562/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.02 net562 (net) |
| 0.10 0.00 4.34 v repeater561/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.05 0.19 4.53 v repeater561/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.02 net561 (net) |
| 0.05 0.00 4.53 v repeater560/A (sky130_fd_sc_hd__buf_4) |
| 0.04 0.16 4.69 v repeater560/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net560 (net) |
| 0.04 0.00 4.70 v repeater559/A (sky130_fd_sc_hd__buf_6) |
| 0.03 0.13 4.83 v repeater559/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net559 (net) |
| 0.03 0.00 4.83 v repeater558/A (sky130_fd_sc_hd__buf_6) |
| 0.03 0.12 4.95 v repeater558/X (sky130_fd_sc_hd__buf_6) |
| 1 0.01 net558 (net) |
| 0.03 0.00 4.95 v repeater557/A (sky130_fd_sc_hd__buf_6) |
| 0.03 0.12 5.06 v repeater557/X (sky130_fd_sc_hd__buf_6) |
| 1 0.01 net557 (net) |
| 0.03 0.00 5.06 v repeater556/A (sky130_fd_sc_hd__buf_4) |
| 0.07 0.17 5.24 v repeater556/X (sky130_fd_sc_hd__buf_4) |
| 1 0.04 net556 (net) |
| 0.07 0.01 5.25 v repeater555/A (sky130_fd_sc_hd__buf_4) |
| 0.04 0.16 5.40 v repeater555/X (sky130_fd_sc_hd__buf_4) |
| 2 0.01 net555 (net) |
| 0.04 0.00 5.41 v repeater554/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.09 0.19 5.60 v repeater554/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 4 0.02 net554 (net) |
| 0.09 0.00 5.60 v _159_/A (sky130_fd_sc_hd__inv_2) |
| 0.05 0.08 5.68 ^ _159_/Y (sky130_fd_sc_hd__inv_2) |
| 2 0.01 _016_ (net) |
| 0.05 0.00 5.68 ^ _160_/A (sky130_fd_sc_hd__buf_6) |
| 0.03 0.09 5.77 ^ _160_/X (sky130_fd_sc_hd__buf_6) |
| 1 0.01 _017_ (net) |
| 0.03 0.00 5.77 ^ repeater506/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.12 0.25 6.02 ^ repeater506/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 2 0.02 net506 (net) |
| 0.12 0.00 6.03 ^ repeater505/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.05 0.17 6.20 ^ repeater505/X (sky130_fd_sc_hd__clkbuf_4) |
| 2 0.01 net505 (net) |
| 0.05 0.00 6.20 ^ repeater504/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.13 0.21 6.41 ^ repeater504/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.04 net504 (net) |
| 0.13 0.01 6.42 ^ repeater503/A (sky130_fd_sc_hd__buf_4) |
| 0.05 0.15 6.57 ^ repeater503/X (sky130_fd_sc_hd__buf_4) |
| 3 0.01 net503 (net) |
| 0.05 0.00 6.57 ^ _260_/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.19 0.20 6.77 ^ _260_/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 5 0.02 _092_ (net) |
| 0.19 0.00 6.77 ^ _261_/A1 (sky130_fd_sc_hd__a22o_1) |
| 0.05 0.17 6.94 ^ _261_/X (sky130_fd_sc_hd__a22o_1) |
| 1 0.00 _093_ (net) |
| 0.05 0.00 6.94 ^ repeater434/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.22 0.34 7.27 ^ repeater434/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 1 0.04 net434 (net) |
| 0.22 0.01 7.28 ^ repeater433/A (sky130_fd_sc_hd__buf_4) |
| 0.04 0.17 7.45 ^ repeater433/X (sky130_fd_sc_hd__buf_4) |
| 1 0.01 net433 (net) |
| 0.04 0.00 7.45 ^ repeater432/A (sky130_fd_sc_hd__buf_4) |
| 0.06 0.13 7.58 ^ repeater432/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net432 (net) |
| 0.06 0.00 7.58 ^ _262_/B2 (sky130_fd_sc_hd__o22a_1) |
| 0.04 0.11 7.69 ^ _262_/X (sky130_fd_sc_hd__o22a_1) |
| 1 0.00 net61 (net) |
| 0.04 0.00 7.69 ^ repeater213/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.40 0.35 8.05 ^ repeater213/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.04 net213 (net) |
| 0.40 0.01 8.06 ^ repeater212/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.04 0.23 8.29 ^ repeater212/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.00 net212 (net) |
| 0.04 0.00 8.29 ^ repeater211/A (sky130_fd_sc_hd__buf_4) |
| 0.06 0.13 8.42 ^ repeater211/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net211 (net) |
| 0.06 0.00 8.42 ^ repeater210/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.12 8.54 ^ repeater210/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net210 (net) |
| 0.05 0.00 8.54 ^ repeater209/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.11 8.65 ^ repeater209/X (sky130_fd_sc_hd__buf_6) |
| 2 0.02 net209 (net) |
| 0.05 0.00 8.65 ^ _527_/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.06 0.11 8.76 ^ _527_/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.00 net126 (net) |
| 0.06 0.00 8.76 ^ repeater152/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.20 0.22 8.98 ^ repeater152/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.02 net152 (net) |
| 0.20 0.00 8.98 ^ repeater151/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.07 0.22 9.20 ^ repeater151/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.02 net151 (net) |
| 0.07 0.00 9.20 ^ output126/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.11 0.20 9.40 ^ output126/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.03 wbs_dat_o[18] (net) |
| 0.11 0.00 9.40 ^ wbs_dat_o[18] (out) |
| 9.40 data arrival time |
| |
| 20.00 20.00 clock wb_clk_i (rise edge) |
| 0.00 20.00 clock network delay (propagated) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -9.40 data arrival time |
| ----------------------------------------------------------------------------- |
| 6.35 slack (MET) |
| |
| |
| max_report_end |
| check_report |
| |
| =========================================================================== |
| report_checks -unconstrained |
| ============================================================================ |
| Startpoint: wbs_adr_i[11] (input port clocked by wb_clk_i) |
| Endpoint: wbs_dat_o[29] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 4.00 4.00 ^ input external delay |
| 0.02 0.01 4.01 ^ wbs_adr_i[11] (in) |
| 1 0.00 wbs_adr_i[11] (net) |
| 0.02 0.00 4.01 ^ input7/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.06 0.10 4.11 ^ input7/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.00 net7 (net) |
| 0.06 0.00 4.11 ^ repeater562/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.20 0.21 4.32 ^ repeater562/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 1 0.02 net562 (net) |
| 0.20 0.00 4.33 ^ repeater561/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.07 0.22 4.54 ^ repeater561/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.02 net561 (net) |
| 0.07 0.00 4.54 ^ repeater560/A (sky130_fd_sc_hd__buf_4) |
| 0.07 0.15 4.69 ^ repeater560/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net560 (net) |
| 0.07 0.00 4.69 ^ repeater559/A (sky130_fd_sc_hd__buf_6) |
| 0.05 0.12 4.81 ^ repeater559/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net559 (net) |
| 0.05 0.00 4.81 ^ repeater558/A (sky130_fd_sc_hd__buf_6) |
| 0.04 0.10 4.92 ^ repeater558/X (sky130_fd_sc_hd__buf_6) |
| 1 0.01 net558 (net) |
| 0.04 0.00 4.92 ^ repeater557/A (sky130_fd_sc_hd__buf_6) |
| 0.04 0.10 5.01 ^ repeater557/X (sky130_fd_sc_hd__buf_6) |
| 1 0.01 net557 (net) |
| 0.04 0.00 5.01 ^ repeater556/A (sky130_fd_sc_hd__buf_4) |
| 0.12 0.17 5.18 ^ repeater556/X (sky130_fd_sc_hd__buf_4) |
| 1 0.04 net556 (net) |
| 0.12 0.01 5.19 ^ repeater555/A (sky130_fd_sc_hd__buf_4) |
| 0.05 0.15 5.34 ^ repeater555/X (sky130_fd_sc_hd__buf_4) |
| 2 0.01 net555 (net) |
| 0.05 0.00 5.34 ^ repeater554/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.19 0.20 5.54 ^ repeater554/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 4 0.02 net554 (net) |
| 0.19 0.00 5.54 ^ _159_/A (sky130_fd_sc_hd__inv_2) |
| 0.05 0.06 5.61 v _159_/Y (sky130_fd_sc_hd__inv_2) |
| 2 0.01 _016_ (net) |
| 0.05 0.00 5.61 v _160_/A (sky130_fd_sc_hd__buf_6) |
| 0.02 0.12 5.72 v _160_/X (sky130_fd_sc_hd__buf_6) |
| 1 0.01 _017_ (net) |
| 0.02 0.00 5.72 v repeater506/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.08 0.25 5.97 v repeater506/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 2 0.02 net506 (net) |
| 0.08 0.00 5.97 v repeater505/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.04 0.17 6.14 v repeater505/X (sky130_fd_sc_hd__clkbuf_4) |
| 2 0.01 net505 (net) |
| 0.04 0.00 6.14 v _161_/A (sky130_fd_sc_hd__buf_6) |
| 0.02 0.11 6.26 v _161_/X (sky130_fd_sc_hd__buf_6) |
| 2 0.01 _018_ (net) |
| 0.02 0.00 6.26 v repeater493/A (sky130_fd_sc_hd__clkdlybuf4s18_2) |
| 0.07 0.25 6.51 v repeater493/X (sky130_fd_sc_hd__clkdlybuf4s18_2) |
| 3 0.02 net493 (net) |
| 0.07 0.00 6.51 v repeater492/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.15 0.32 6.83 v repeater492/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 1 0.04 net492 (net) |
| 0.15 0.01 6.84 v repeater491/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.03 0.19 7.03 v repeater491/X (sky130_fd_sc_hd__clkbuf_4) |
| 2 0.01 net491 (net) |
| 0.03 0.00 7.03 v _303_/A1 (sky130_fd_sc_hd__a22o_1) |
| 0.04 0.20 7.24 v _303_/X (sky130_fd_sc_hd__a22o_1) |
| 1 0.00 _124_ (net) |
| 0.04 0.00 7.24 v repeater401/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.15 0.31 7.55 v repeater401/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 1 0.04 net401 (net) |
| 0.15 0.01 7.56 v repeater400/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.03 0.20 7.75 v repeater400/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.01 net400 (net) |
| 0.03 0.00 7.75 v repeater399/A (sky130_fd_sc_hd__buf_4) |
| 0.04 0.15 7.91 v repeater399/X (sky130_fd_sc_hd__buf_4) |
| 1 0.02 net399 (net) |
| 0.04 0.00 7.91 v _304_/B2 (sky130_fd_sc_hd__o22a_2) |
| 0.12 0.28 8.18 v _304_/X (sky130_fd_sc_hd__o22a_2) |
| 1 0.03 net73 (net) |
| 0.12 0.01 8.19 v repeater343/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.09 0.23 8.42 v repeater343/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.04 net343 (net) |
| 0.09 0.01 8.43 v repeater342/A (sky130_fd_sc_hd__buf_4) |
| 0.04 0.17 8.60 v repeater342/X (sky130_fd_sc_hd__buf_4) |
| 1 0.01 net342 (net) |
| 0.04 0.00 8.60 v repeater341/A (sky130_fd_sc_hd__buf_6) |
| 0.03 0.13 8.73 v repeater341/X (sky130_fd_sc_hd__buf_6) |
| 1 0.02 net341 (net) |
| 0.03 0.00 8.74 v repeater340/A (sky130_fd_sc_hd__buf_6) |
| 0.03 0.13 8.86 v repeater340/X (sky130_fd_sc_hd__buf_6) |
| 2 0.02 net340 (net) |
| 0.03 0.00 8.86 v _538_/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.04 0.14 9.00 v _538_/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.01 net138 (net) |
| 0.04 0.00 9.01 v repeater187/A (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 0.08 0.25 9.25 v repeater187/X (sky130_fd_sc_hd__clkdlybuf4s15_2) |
| 1 0.02 net187 (net) |
| 0.08 0.00 9.26 v repeater186/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.05 0.18 9.44 v repeater186/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.02 net186 (net) |
| 0.05 0.00 9.44 v output138/A (sky130_fd_sc_hd__clkbuf_4) |
| 0.08 0.20 9.64 v output138/X (sky130_fd_sc_hd__clkbuf_4) |
| 1 0.03 wbs_dat_o[29] (net) |
| 0.08 0.00 9.64 v wbs_dat_o[29] (out) |
| 9.64 data arrival time |
| |
| 20.00 20.00 clock wb_clk_i (rise edge) |
| 0.00 20.00 clock network delay (propagated) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -9.64 data arrival time |
| ----------------------------------------------------------------------------- |
| 6.11 slack (MET) |
| |
| |
| |
| =========================================================================== |
| report_checks --slack_max -0.01 |
| ============================================================================ |
| No paths found. |
| check_report_end |
| check_slew |
| |
| =========================================================================== |
| report_check_types -max_slew -max_cap -max_fanout -violators |
| ============================================================================ |
| |
| =========================================================================== |
| max slew violation count 0 |
| max fanout violation count 0 |
| max cap violation count 0 |
| ============================================================================ |
| check_slew_end |
| tns_report |
| |
| =========================================================================== |
| report_tns |
| ============================================================================ |
| tns 0.00 |
| tns_report_end |
| wns_report |
| |
| =========================================================================== |
| report_wns |
| ============================================================================ |
| wns 0.00 |
| wns_report_end |
| worst_slack |
| |
| =========================================================================== |
| report_worst_slack -max (Setup) |
| ============================================================================ |
| worst slack 6.11 |
| |
| =========================================================================== |
| report_worst_slack -min (Hold) |
| ============================================================================ |
| worst slack 2.62 |
| worst_slack_end |
| clock_skew |
| |
| =========================================================================== |
| report_clock_skew |
| ============================================================================ |
| Clock wb_clk_i |
| Latency CRPR Skew |
| _313_/CLK ^ |
| 8.22 |
| _313_/CLK ^ |
| 2.29 0.00 5.93 |
| |
| clock_skew_end |
| power_report |
| |
| =========================================================================== |
| report_power |
| ============================================================================ |
| Group Internal Switching Leakage Total |
| Power Power Power Power (Watts) |
| ---------------------------------------------------------------- |
| Sequential 2.06e-06 2.26e-08 8.44e-12 2.08e-06 0.2% |
| Combinational 4.03e-04 4.75e-04 2.54e-08 8.78e-04 99.8% |
| Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| ---------------------------------------------------------------- |
| Total 4.05e-04 4.75e-04 2.54e-08 8.80e-04 100.0% |
| 46.1% 53.9% 0.0% |
| power_report_end |
| area_report |
| |
| =========================================================================== |
| report_design_area |
| ============================================================================ |
| Design area 1332768 u^2 13% utilization. |
| area_report_end |