commit	db0fd75404224ae19bfdbc8dfa234c20bb04f64c	[log] [tgz]
author	Serdar Unal <serdar@DESKTOP-0L078IG.localdomain>	Thu May 19 22:32:07 2022 +0300
committer	Serdar Unal <serdar@DESKTOP-0L078IG.localdomain>	Thu May 19 22:32:07 2022 +0300
tree	091c14291d04ab07d6e4d6a6b2169d22d119b1e0
parent	a11292b5ad1ffdb085a7884807f9d9569dce13f5 [diff]

first try

.gitignore[diff]
Makefile[diff]
def/openram_demo.def[Added - diff]
def/user_proj_example.def[Deleted - diff]
def/user_project_wrapper.def[diff]
gds/openram_demo.gds.gz[Added - diff]
gds/sram_32_16_sky130.gds[Added - diff]
gds/user_proj_example.gds[Deleted - diff]
gds/user_project_wrapper.gds[Deleted - diff]
gds/user_project_wrapper.gds.gz[Added - diff]
lef/openram_demo.lef[Renamed from lef/user_proj_example.lef - diff]
lef/sram_32_16_sky130.lef[Added - diff]
lef/user_project_wrapper.lef[diff]
mag/user_proj_example.mag[Deleted - diff]
mag/user_project_wrapper.mag[diff]
maglef/user_proj_example.mag[Deleted - diff]
maglef/user_project_wrapper.mag[diff]
openlane/openram_demo/base.sdc[Added - diff]
openlane/openram_demo/config.json[Renamed from openlane/user_proj_example/config.json - diff]
openlane/openram_demo/config.tcl[Added - diff]
openlane/openram_demo/macro.cfg[Added - diff]
openlane/openram_demo/pin_order.cfg[Added - diff]
openlane/user_proj_example/config.tcl[Deleted - diff]
openlane/user_proj_example/pin_order.cfg[Deleted - diff]
openlane/user_project_wrapper/base.sdc[Added - diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/pin_order.cfg[diff]
sdc/openram_demo.sdc[Added - diff]
sdc/user_project_wrapper.sdc[Added - diff]
sdf/openram_demo.sdf[Added - diff]
sdf/user_project_wrapper.sdf[Added - diff]
signoff/openram_demo/OPENLANE_VERSION[Added - diff]
signoff/openram_demo/PDK_SOURCES[Added - diff]
signoff/user_project_wrapper/OPENLANE_VERSION[diff]
signoff/user_project_wrapper/PDK_SOURCES[diff]
spef/openram_demo.spef[Added - diff]
spef/user_project_wrapper.spef[Added - diff]
spi/lvs/openram_demo.spice[Renamed from spi/lvs/user_proj_example.spice - diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/dv/register_map.h[Added - diff]
verilog/dv/wb_port/wb_port.c[diff]
verilog/dv/wb_port/wb_port_tb.v[diff]
verilog/gl/openram_demo.v[Renamed from verilog/gl/user_proj_example.v - diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/includes/includes.rtl.caravel_user_project[diff]
verilog/rtl/openram_demo.v[Added - diff]
verilog/rtl/sram_32_16_sky130.v[Added - diff]
verilog/rtl/uprj_netlists.v[diff]
verilog/rtl/user_proj_example.v[Deleted - diff]
verilog/rtl/user_project_wrapper.v[diff]

50 files changed

tree: 091c14291d04ab07d6e4d6a6b2169d22d119b1e0

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quick start of how to use caravel_user_project

Refer to README for this sample project documentation.