| [INFO]: Current run directory is /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper |
| [INFO]: Preparing LEF files for the nom corner... |
| [INFO]: Preparing LEF files for the min corner... |
| [INFO]: Preparing LEF files for the max corner... |
| [INFO]: Looking for files defined in ::env(EXTRA_GDS_FILES) /home/serdar/pdks/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds ... |
| [INFO]: /home/serdar/pdks/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds exists. |
| [INFO]: Running Synthesis... |
| [INFO]: Running Single-Corner Static Timing Analysis... |
| [INFO]: Creating a netlist with power/ground pins. |
| [INFO]: Running Initial Floorplanning... |
| [INFO]: Setting Core Dimensions... |
| [INFO]: Running IO Placement... |
| [INFO]: Performing Manual Macro Placement... |
| [INFO]: Running Tap/Decap Insertion... |
| [INFO]: Power planning with power {vccd1 vccd2 vdda1 vdda2} and ground {vssd1 vssd2 vssa1 vssa2}... |
| [INFO]: Generating PDN... |
| [INFO]: Running Global Placement... |
| [INFO]: Running Placement Resizer Design Optimizations... |
| [INFO]: Writing Verilog... |
| [INFO]: Running Detailed Placement... |
| [INFO]: Running Clock Tree Synthesis... |
| [INFO]: Writing Verilog... |
| [INFO]: Running Placement Resizer Timing Optimizations... |
| [INFO]: Writing Verilog... |
| [INFO]: Routing... |
| [INFO]: Running Global Routing Resizer Timing Optimizations... |
| [INFO]: Writing Verilog... |
| [INFO]: Running Detailed Placement... |
| [INFO]: Running Global Routing... |
| [INFO]: Starting FastRoute Antenna Repair Iterations... |
| [INFO]: FastRoute Iteration 2 |
| [INFO]: Antenna Violations Previous: value |
| [INFO]: Antenna Violations Current: value |
| [INFO]: Running Fill Insertion... |
| [INFO]: Writing Verilog... |
| [INFO]: Running Detailed Routing... |
| [INFO]: Writing Verilog... |
| [INFO]: Running parasitics-based static timing analysis... |
| [INFO]: Running SPEF Extraction at the min process corner... |
| [INFO]: Running Multi-Corner Static Timing Analysis at the min process corner... |
| [INFO]: Running SPEF Extraction at the max process corner... |
| [INFO]: Running Multi-Corner Static Timing Analysis at the max process corner... |
| [INFO]: Running SPEF Extraction at the nom process corner... |
| [INFO]: Running Single-Corner Static Timing Analysis at the nom process corner... |
| [INFO]: Running Multi-Corner Static Timing Analysis at the nom process corner... |
| [INFO]: Running Magic to generate various views... |
| [INFO]: Streaming out GDS-II with Magic... |
| [INFO]: Generating MAGLEF views... |
| [INFO]: Streaming out GDS-II with Klayout... |
| [INFO]: Running XOR on the layouts using Klayout... |
| [INFO]: Running Magic Spice Export from GDS... |
| [INFO]: Writing Powered Verilog... |
| [INFO]: Writing Verilog... |
| [INFO]: Running GDS LVS... |
| [INFO]: Running Antenna Checks... |
| [INFO]: Running OpenROAD Antenna Rule Checker... |
| [INFO]: Skipping CVC... |
| [INFO]: Saving final set of views in '/home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/results/final'... |
| [INFO]: Saving final set of views in '/home/serdar/Desktop/openram_demo/openram_openmpw'... |
| [INFO]: Saving runtime environment... |
| [INFO]: Generating final set of reports... |
| [INFO]: Created manufacturability report at 'user_project_wrapper/runs/user_project_wrapper/reports/manufacturability.rpt'. |
| [INFO]: Created metrics report at 'user_project_wrapper/runs/user_project_wrapper/reports/metrics.csv'. |
| [WARNING]: There are max slew violations in the design at the typical corner. Please refer to 'user_project_wrapper/runs/user_project_wrapper/reports/signoff/29-rcx_sta.slew.rpt'. |
| [INFO]: There are no hold violations in the design at the typical corner. |
| [INFO]: There are no setup violations in the design at the typical corner. |
| [SUCCESS]: Flow complete. |
| [INFO]: Note that the following warnings have been generated: |
