| OpenROAD 79a46b62da64bbebc18f06b20c42211046de719a |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| [INFO ODB-0222] Reading LEF file: /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.unpadded.nom.lef |
| [INFO ODB-0223] Created 13 technology layers |
| [INFO ODB-0224] Created 25 technology vias |
| [INFO ODB-0225] Created 442 library cells |
| [INFO ODB-0226] Finished LEF file: /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.unpadded.nom.lef |
| [INFO ODB-0127] Reading DEF file: /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/7-pdn.def |
| [INFO ODB-0128] Design: user_project_wrapper |
| [INFO ODB-0094] Created 100000 Insts |
| [INFO ODB-0130] Created 645 pins. |
| [INFO ODB-0131] Created 131843 components and 273756 component-terminals. |
| [INFO ODB-0132] Created 8 special nets and 272196 connections. |
| [INFO ODB-0133] Created 1044 nets and 1397 connections. |
| [INFO ODB-0134] Finished DEF file: /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/7-pdn.def |
| [INFO]: Setting RC values... |
| [INFO]: Setting signal min routing layer to: met1 and clock min routing layer to met1. |
| [INFO]: Setting signal max routing layer to: met4 and clock max routing layer to met4. |
| [INFO GPL-0002] DBU: 1000 |
| [INFO GPL-0003] SiteSize: 460 2720 |
| [INFO GPL-0004] CoreAreaLxLy: 5520 10880 |
| [INFO GPL-0005] CoreAreaUxUy: 2914100 3508800 |
| [INFO GPL-0006] NumInstances: 133105 |
| [INFO GPL-0007] NumPlaceInstances: 391 |
| [INFO GPL-0008] NumFixedInstances: 131452 |
| [INFO GPL-0009] NumDummyInstances: 1262 |
| [INFO GPL-0010] NumNets: 1044 |
| [INFO GPL-0011] NumPins: 2034 |
| [INFO GPL-0012] DieAreaLxLy: 0 0 |
| [INFO GPL-0013] DieAreaUxUy: 2920000 3520000 |
| [INFO GPL-0014] CoreAreaLxLy: 5520 10880 |
| [INFO GPL-0015] CoreAreaUxUy: 2914100 3508800 |
| [INFO GPL-0016] CoreArea: 10173980153600 |
| [INFO GPL-0017] NonPlaceInstsArea: 1402825236800 |
| [INFO GPL-0018] PlaceInstsArea: 2354758400 |
| [INFO GPL-0019] Util(%): 0.03 |
| [INFO GPL-0020] StdInstsArea: 2354758400 |
| [INFO GPL-0021] MacroInstsArea: 0 |
| [InitialPlace] Iter: 1 CG residual: 0.00652198 HPWL: 1291446050 |
| [InitialPlace] Iter: 2 CG residual: 0.00001124 HPWL: 687606656 |
| [InitialPlace] Iter: 3 CG residual: 0.00000009 HPWL: 639626839 |
| [InitialPlace] Iter: 4 CG residual: 0.00000006 HPWL: 624988707 |
| [InitialPlace] Iter: 5 CG residual: 0.00000012 HPWL: 616011892 |
| [INFO GPL-0031] FillerInit: NumGCells: 268714 |
| [INFO GPL-0032] FillerInit: NumGNets: 1044 |
| [INFO GPL-0033] FillerInit: NumGPins: 2034 |
| [INFO GPL-0023] TargetDensity: 0.18 |
| [INFO GPL-0024] AveragePlaceInstArea: 6022400 |
| [INFO GPL-0025] IdealBinArea: 33457776 |
| [INFO GPL-0026] IdealBinCnt: 304084 |
| [INFO GPL-0027] TotalBinArea: 10173980153600 |
| [INFO GPL-0028] BinCnt: 512 512 |
| [INFO GPL-0029] BinSize: 5681 6832 |
| [INFO GPL-0030] NumBins: 262144 |
| [NesterovSolve] Iter: 1 overflow: 0.512662 HPWL: 322173530 |
| [INFO GPL-0100] worst slack 9.29e-09 |
| [INFO GPL-0103] Weighted 252 nets. |
| [NesterovSolve] Snapshot saved at iter = 0 |
| [NesterovSolve] Iter: 10 overflow: 0.497101 HPWL: 321753147 |
| [INFO GPL-0100] worst slack 9.34e-09 |
| [INFO GPL-0103] Weighted 252 nets. |
| [NesterovSolve] Iter: 20 overflow: 0.471164 HPWL: 318312048 |
| [NesterovSolve] Iter: 30 overflow: 0.389185 HPWL: 311772058 |
| [NesterovSolve] Iter: 40 overflow: 0.355507 HPWL: 300683330 |
| [NesterovSolve] Iter: 50 overflow: 0.321948 HPWL: 297222520 |
| [NesterovSolve] Iter: 60 overflow: 0.327141 HPWL: 296228046 |
| [NesterovSolve] Iter: 70 overflow: 0.338178 HPWL: 294201481 |
| [NesterovSolve] Iter: 80 overflow: 0.337717 HPWL: 293386480 |
| [NesterovSolve] Iter: 90 overflow: 0.399065 HPWL: 292457836 |
| [NesterovSolve] Iter: 100 overflow: 0.397572 HPWL: 291837208 |
| [NesterovSolve] Iter: 110 overflow: 0.396585 HPWL: 291336316 |
| [NesterovSolve] Iter: 120 overflow: 0.39742 HPWL: 290763306 |
| [NesterovSolve] Iter: 130 overflow: 0.398016 HPWL: 290329594 |
| [NesterovSolve] Iter: 140 overflow: 0.384223 HPWL: 290284234 |
| [NesterovSolve] Iter: 150 overflow: 0.396258 HPWL: 289717296 |
| [NesterovSolve] Iter: 160 overflow: 0.399575 HPWL: 289435569 |
| [NesterovSolve] Iter: 170 overflow: 0.396052 HPWL: 289196781 |
| [NesterovSolve] Iter: 180 overflow: 0.394981 HPWL: 288958188 |
| [NesterovSolve] Iter: 190 overflow: 0.396508 HPWL: 288707570 |
| [NesterovSolve] Iter: 200 overflow: 0.398214 HPWL: 288484868 |
| [NesterovSolve] Iter: 210 overflow: 0.400282 HPWL: 288272432 |
| [NesterovSolve] Iter: 220 overflow: 0.401717 HPWL: 288139480 |
| [NesterovSolve] Iter: 230 overflow: 0.398817 HPWL: 287990061 |
| [NesterovSolve] Iter: 240 overflow: 0.398937 HPWL: 287820498 |
| [NesterovSolve] Iter: 250 overflow: 0.396139 HPWL: 287675691 |
| [NesterovSolve] Iter: 260 overflow: 0.39763 HPWL: 287521032 |
| [NesterovSolve] Iter: 270 overflow: 0.398185 HPWL: 287354678 |
| [NesterovSolve] Iter: 280 overflow: 0.392727 HPWL: 287185148 |
| [NesterovSolve] Iter: 290 overflow: 0.395786 HPWL: 287025252 |
| [NesterovSolve] Iter: 300 overflow: 0.392884 HPWL: 286900074 |
| [NesterovSolve] Iter: 310 overflow: 0.398743 HPWL: 286855091 |
| [NesterovSolve] Iter: 320 overflow: 0.398065 HPWL: 286869528 |
| [NesterovSolve] Iter: 330 overflow: 0.396792 HPWL: 286958093 |
| [NesterovSolve] Iter: 340 overflow: 0.39467 HPWL: 287157801 |
| [NesterovSolve] Iter: 350 overflow: 0.394362 HPWL: 287558107 |
| [NesterovSolve] Iter: 360 overflow: 0.389177 HPWL: 288150487 |
| [NesterovSolve] Iter: 370 overflow: 0.379664 HPWL: 289110348 |
| [NesterovSolve] Iter: 380 overflow: 0.354836 HPWL: 291245507 |
| [NesterovSolve] Iter: 390 overflow: 0.316341 HPWL: 310156610 |
| [INFO GPL-0100] worst slack 9.29e-09 |
| [INFO GPL-0103] Weighted 251 nets. |
| [NesterovSolve] Iter: 400 overflow: 0.255913 HPWL: 330807996 |
| [NesterovSolve] Iter: 410 overflow: 0.331725 HPWL: 340015354 |
| [NesterovSolve] Iter: 420 overflow: 0.381075 HPWL: 325275984 |
| [NesterovSolve] Iter: 430 overflow: 0.371783 HPWL: 337053245 |
| [NesterovSolve] Iter: 440 overflow: 0.347322 HPWL: 336349931 |
| [NesterovSolve] Iter: 450 overflow: 0.1964 HPWL: 333962226 |
| [INFO GPL-0100] worst slack 9.23e-09 |
| [INFO GPL-0103] Weighted 251 nets. |
| [INFO GPL-0075] Routability numCall: 1 inflationIterCnt: 1 bloatIterCnt: 0 |
| [INFO GPL-0036] TileLxLy: 0 0 |
| [INFO GPL-0037] TileSize: 6900 6900 |
| [INFO GPL-0038] TileCnt: 423 510 |
| [INFO GPL-0039] numRoutingLayers: 6 |
| [INFO GPL-0040] NumTiles: 215730 |
| [INFO GPL-0063] TotalRouteOverflowH2: 0.0 |
| [INFO GPL-0064] TotalRouteOverflowV2: 0.0 |
| [INFO GPL-0065] OverflowTileCnt2: 0 |
| [INFO GPL-0066] 0.5%RC: 0.8044456061147247 |
| [INFO GPL-0067] 1.0%RC: 0.7179435702123468 |
| [INFO GPL-0068] 2.0%RC: 0.7161148895574839 |
| [INFO GPL-0069] 5.0%RC: 0.7150174519347756 |
| [INFO GPL-0070] 0.5rcK: 1.0 |
| [INFO GPL-0071] 1.0rcK: 1.0 |
| [INFO GPL-0072] 2.0rcK: 0.0 |
| [INFO GPL-0073] 5.0rcK: 0.0 |
| [INFO GPL-0074] FinalRC: 0.7611946 |
| [NesterovSolve] Iter: 460 overflow: 0.149033 HPWL: 333708048 |
| [NesterovSolve] Iter: 470 overflow: 0.1773 HPWL: 332638618 |
| [NesterovSolve] Iter: 480 overflow: 0.192314 HPWL: 325041470 |
| [NesterovSolve] Iter: 490 overflow: 0.243017 HPWL: 321319942 |
| [NesterovSolve] Iter: 500 overflow: 0.16519 HPWL: 313843482 |
| [NesterovSolve] Iter: 510 overflow: 0.155928 HPWL: 310910317 |
| [NesterovSolve] Iter: 520 overflow: 0.160034 HPWL: 305569763 |
| [INFO GPL-0100] worst slack 9.35e-09 |
| [INFO GPL-0103] Weighted 251 nets. |
| [NesterovSolve] Iter: 530 overflow: 0.138557 HPWL: 302090263 |
| [NesterovSolve] Iter: 540 overflow: 0.143123 HPWL: 298623260 |
| [NesterovSolve] Iter: 550 overflow: 0.118805 HPWL: 297635839 |
| [NesterovSolve] Iter: 560 overflow: 0.117546 HPWL: 296666285 |
| [NesterovSolve] Iter: 570 overflow: 0.104817 HPWL: 294842065 |
| [NesterovSolve] Finished with Overflow: 0.098672 |
| ############################################################################### |
| # Created by write_sdc |
| # Fri May 27 13:55:58 2022 |
| ############################################################################### |
| current_design user_project_wrapper |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name wb_clk_i -period 20.0000 [get_ports {wb_clk_i}] |
| set_clock_transition 0.1500 [get_clocks {wb_clk_i}] |
| set_clock_uncertainty 0.2500 wb_clk_i |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[32]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[33]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[34]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[35]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[36]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[37]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[100]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[101]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[102]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[103]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[104]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[105]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[106]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[107]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[108]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[109]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[110]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[111]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[112]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[113]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[114]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[115]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[116]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[117]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[118]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[119]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[120]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[121]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[122]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[123]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[124]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[125]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[126]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[127]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[32]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[33]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[34]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[35]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[36]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[37]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[38]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[39]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[40]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[41]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[42]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[43]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[44]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[45]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[46]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[47]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[48]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[49]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[50]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[51]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[52]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[53]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[54]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[55]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[56]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[57]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[58]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[59]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[60]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[61]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[62]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[63]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[64]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[65]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[66]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[67]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[68]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[69]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[70]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[71]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[72]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[73]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[74]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[75]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[76]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[77]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[78]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[79]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[80]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[81]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[82]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[83]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[84]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[85]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[86]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[87]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[88]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[89]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[90]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[91]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[92]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[93]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[94]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[95]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[96]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[97]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[98]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[99]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[100]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[101]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[102]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[103]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[104]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[105]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[106]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[107]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[108]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[109]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[110]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[111]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[112]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[113]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[114]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[115]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[116]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[117]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[118]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[119]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[120]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[121]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[122]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[123]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[124]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[125]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[126]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[127]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[32]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[33]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[34]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[35]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[36]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[37]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[38]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[39]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[40]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[41]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[42]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[43]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[44]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[45]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[46]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[47]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[48]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[49]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[50]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[51]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[52]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[53]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[54]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[55]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[56]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[57]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[58]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[59]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[60]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[61]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[62]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[63]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[64]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[65]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[66]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[67]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[68]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[69]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[70]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[71]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[72]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[73]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[74]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[75]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[76]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[77]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[78]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[79]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[80]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[81]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[82]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[83]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[84]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[85]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[86]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[87]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[88]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[89]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[90]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[91]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[92]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[93]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[94]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[95]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[96]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[97]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[98]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[99]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {user_clock2}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_rst_i}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_cyc_i}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_stb_i}] |
| set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_we_i}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[32]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[33]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[34]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[35]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[36]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[37]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[32]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[33]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[34]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[35]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[36]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[37]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[100]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[101]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[102]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[103]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[104]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[105]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[106]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[107]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[108]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[109]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[110]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[111]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[112]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[113]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[114]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[115]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[116]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[117]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[118]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[119]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[120]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[121]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[122]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[123]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[124]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[125]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[126]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[127]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[32]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[33]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[34]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[35]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[36]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[37]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[38]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[39]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[40]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[41]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[42]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[43]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[44]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[45]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[46]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[47]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[48]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[49]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[50]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[51]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[52]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[53]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[54]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[55]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[56]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[57]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[58]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[59]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[60]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[61]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[62]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[63]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[64]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[65]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[66]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[67]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[68]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[69]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[70]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[71]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[72]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[73]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[74]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[75]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[76]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[77]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[78]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[79]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[80]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[81]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[82]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[83]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[84]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[85]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[86]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[87]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[88]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[89]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[90]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[91]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[92]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[93]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[94]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[95]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[96]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[97]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[98]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[99]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {user_irq[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {user_irq[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {user_irq[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_ack_o}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}] |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_load -pin_load 0.0334 [get_ports {wbs_ack_o}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[28]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[27]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[26]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[25]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[24]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[23]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[22]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[21]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[20]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[19]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[18]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[17]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[16]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[15]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[14]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[13]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[12]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[11]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[10]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[9]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[8]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[7]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[6]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[5]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[4]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[3]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[2]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[1]}] |
| set_load -pin_load 0.0334 [get_ports {analog_io[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[37]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[36]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[35]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[34]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[33]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[32]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[31]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[30]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[29]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[28]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[27]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[26]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[25]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[24]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[23]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[22]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[21]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[20]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[19]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[18]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[17]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[16]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[15]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[14]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[13]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[12]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[11]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[10]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[9]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[8]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[7]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[6]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[5]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[4]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[37]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[36]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[35]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[34]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[33]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[32]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[31]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[30]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[29]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[28]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[27]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[26]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[25]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[24]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[23]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[22]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[21]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[20]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[19]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[18]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[17]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[16]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[15]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[14]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[13]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[12]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[11]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[10]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[9]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[8]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[7]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[6]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[5]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[4]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[0]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[127]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[126]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[125]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[124]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[123]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[122]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[121]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[120]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[119]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[118]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[117]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[116]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[115]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[114]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[113]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[112]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[111]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[110]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[109]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[108]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[107]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[106]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[105]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[104]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[103]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[102]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[101]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[100]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[99]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[98]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[97]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[96]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[95]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[94]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[93]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[92]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[91]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[90]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[89]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[88]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[87]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[86]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[85]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[84]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[83]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[82]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[81]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[80]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[79]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[78]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[77]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[76]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[75]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[74]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[73]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[72]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[71]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[70]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[69]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[68]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[67]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[66]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[65]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[64]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[63]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[62]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[61]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[60]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[59]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[58]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[57]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[56]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[55]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[54]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[53]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[52]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[51]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[50]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[49]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[48]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[47]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[46]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[45]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[44]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[43]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[42]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[41]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[40]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[39]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[38]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[37]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[36]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[35]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[34]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[33]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[32]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[31]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[30]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[29]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[28]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[27]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[26]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[25]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[24]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[23]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[22]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[21]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[20]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[19]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[18]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[17]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[16]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[15]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[14]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[13]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[12]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[11]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[10]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[9]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[8]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[7]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[6]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[5]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[4]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[3]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[2]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[1]}] |
| set_load -pin_load 0.0334 [get_ports {la_data_out[0]}] |
| set_load -pin_load 0.0334 [get_ports {user_irq[2]}] |
| set_load -pin_load 0.0334 [get_ports {user_irq[1]}] |
| set_load -pin_load 0.0334 [get_ports {user_irq[0]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock2}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_cyc_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_stb_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_we_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[127]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[126]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[125]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[124]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[123]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[122]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[121]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[120]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[119]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[118]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[117]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[116]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[115]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[114]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[113]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[112]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[111]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[110]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[109]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[108]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[107]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[106]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[105]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[104]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[103]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[102]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[101]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[100]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[99]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[98]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[97]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[96]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[95]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[94]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[93]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[92]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[91]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[90]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[89]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[88]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[87]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[86]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[85]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[84]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[83]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[82]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[81]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[80]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[79]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[78]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[77]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[76]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[75]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[74]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[73]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[72]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[71]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[70]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[69]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[68]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[67]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[66]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[65]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[64]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[63]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[62]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[61]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[60]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[59]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[58]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[57]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[56]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[55]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[54]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[53]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[52]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[51]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[50]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[49]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[48]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[47]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[46]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[45]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[44]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[43]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[42]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[41]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[40]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[39]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[38]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[127]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[126]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[125]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[124]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[123]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[122]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[121]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[120]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[119]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[118]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[117]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[116]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[115]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[114]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[113]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[112]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[111]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[110]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[109]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[108]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[107]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[106]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[105]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[104]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[103]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[102]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[101]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[100]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[99]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[98]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[97]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[96]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[95]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[94]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[93]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[92]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[91]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[90]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[89]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[88]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[87]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[86]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[85]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[84]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[83]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[82]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[81]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[80]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[79]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[78]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[77]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[76]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[75]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[74]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[73]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[72]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[71]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[70]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[69]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[68]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[67]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[66]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[65]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[64]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[63]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[62]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[61]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[60]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[59]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[58]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[57]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[56]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[55]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[54]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[53]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[52]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[51]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[50]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[49]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[48]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[47]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[46]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[45]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[44]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[43]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[42]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[41]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[40]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[39]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[38]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[0]}] |
| set_timing_derate -early 0.9500 |
| set_timing_derate -late 1.0500 |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |
| set_max_fanout 5.0000 [current_design] |
| [INFO]: Setting RC values... |
| min_report |
| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: _313_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _313_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _313_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| 0.92 0.85 0.85 ^ _313_/Q (sky130_fd_sc_hd__dfxtp_2) |
| 2 0.03 wbs_ack_o (net) |
| 0.97 0.16 1.01 ^ _151_/A_N (sky130_fd_sc_hd__nand3b_2) |
| 0.84 0.73 1.74 ^ _151_/Y (sky130_fd_sc_hd__nand3b_2) |
| 5 0.17 _010_ (net) |
| 0.88 0.13 1.87 ^ _152_/A (sky130_fd_sc_hd__buf_1) |
| 0.22 0.26 2.14 ^ _152_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.02 _011_ (net) |
| 0.22 0.00 2.14 ^ _312_/A (sky130_fd_sc_hd__nor2_2) |
| 0.06 0.08 2.21 v _312_/Y (sky130_fd_sc_hd__nor2_2) |
| 1 0.01 _008_ (net) |
| 0.06 0.00 2.21 v _313_/D (sky130_fd_sc_hd__dfxtp_2) |
| 2.21 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _313_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| -0.03 0.22 library hold time |
| 0.22 data required time |
| ----------------------------------------------------------------------------- |
| 0.22 data required time |
| -2.21 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.99 slack (MET) |
| |
| |
| Startpoint: _313_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: wbs_ack_o (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _313_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| 0.40 0.54 0.54 v _313_/Q (sky130_fd_sc_hd__dfxtp_2) |
| 2 0.03 wbs_ack_o (net) |
| 0.52 0.15 0.70 v wbs_ack_o (out) |
| 0.70 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| -4.00 -3.75 output external delay |
| -3.75 data required time |
| ----------------------------------------------------------------------------- |
| -3.75 data required time |
| -0.70 data arrival time |
| ----------------------------------------------------------------------------- |
| 4.45 slack (MET) |
| |
| |
| Startpoint: wbs_dat_i[31] (input port clocked by wb_clk_i) |
| Endpoint: la_data_out[63] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 4.00 4.00 v input external delay |
| 0.71 0.55 4.55 v wbs_dat_i[31] (in) |
| 5 0.32 wbs_dat_i[31] (net) |
| 0.77 0.00 4.55 v _508_/A (sky130_fd_sc_hd__buf_4) |
| 0.08 0.41 4.97 v _508_/X (sky130_fd_sc_hd__buf_4) |
| 1 0.03 la_data_out[63] (net) |
| 0.08 0.00 4.97 v la_data_out[63] (out) |
| 4.97 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| -4.00 -3.75 output external delay |
| -3.75 data required time |
| ----------------------------------------------------------------------------- |
| -3.75 data required time |
| -4.97 data arrival time |
| ----------------------------------------------------------------------------- |
| 8.72 slack (MET) |
| |
| |
| Startpoint: wbs_dat_i[30] (input port clocked by wb_clk_i) |
| Endpoint: la_data_out[62] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 4.00 4.00 v input external delay |
| 0.72 0.56 4.56 v wbs_dat_i[30] (in) |
| 5 0.32 wbs_dat_i[30] (net) |
| 0.77 0.00 4.56 v _507_/A (sky130_fd_sc_hd__buf_4) |
| 0.08 0.42 4.97 v _507_/X (sky130_fd_sc_hd__buf_4) |
| 1 0.03 la_data_out[62] (net) |
| 0.08 0.00 4.97 v la_data_out[62] (out) |
| 4.97 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| -4.00 -3.75 output external delay |
| -3.75 data required time |
| ----------------------------------------------------------------------------- |
| -3.75 data required time |
| -4.97 data arrival time |
| ----------------------------------------------------------------------------- |
| 8.72 slack (MET) |
| |
| |
| Startpoint: wbs_dat_i[29] (input port clocked by wb_clk_i) |
| Endpoint: la_data_out[61] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 4.00 4.00 v input external delay |
| 0.72 0.56 4.56 v wbs_dat_i[29] (in) |
| 5 0.33 wbs_dat_i[29] (net) |
| 0.78 0.00 4.56 v _506_/A (sky130_fd_sc_hd__buf_4) |
| 0.08 0.42 4.98 v _506_/X (sky130_fd_sc_hd__buf_4) |
| 1 0.03 la_data_out[61] (net) |
| 0.08 0.00 4.98 v la_data_out[61] (out) |
| 4.98 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| -4.00 -3.75 output external delay |
| -3.75 data required time |
| ----------------------------------------------------------------------------- |
| -3.75 data required time |
| -4.98 data arrival time |
| ----------------------------------------------------------------------------- |
| 8.73 slack (MET) |
| |
| |
| min_report_end |
| max_report |
| |
| =========================================================================== |
| report_checks -path_delay max (Setup) |
| ============================================================================ |
| Startpoint: wbs_adr_i[11] (input port clocked by wb_clk_i) |
| Endpoint: wbs_dat_o[29] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 4.00 4.00 v input external delay |
| 0.32 0.31 4.31 v wbs_adr_i[11] (in) |
| 5 0.15 wbs_adr_i[11] (net) |
| 0.38 0.00 4.31 v _159_/A (sky130_fd_sc_hd__inv_2) |
| 0.09 0.14 4.45 ^ _159_/Y (sky130_fd_sc_hd__inv_2) |
| 2 0.00 _016_ (net) |
| 0.09 0.00 4.45 ^ _160_/A (sky130_fd_sc_hd__buf_1) |
| 0.93 0.73 5.18 ^ _160_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.08 _017_ (net) |
| 0.93 0.02 5.20 ^ _161_/A (sky130_fd_sc_hd__buf_1) |
| 0.91 0.79 5.98 ^ _161_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.08 _018_ (net) |
| 0.91 0.02 6.00 ^ _303_/A1 (sky130_fd_sc_hd__a22o_2) |
| 0.31 0.52 6.52 ^ _303_/X (sky130_fd_sc_hd__a22o_2) |
| 1 0.06 _124_ (net) |
| 0.32 0.02 6.54 ^ _304_/B2 (sky130_fd_sc_hd__o22a_2) |
| 0.59 0.59 7.13 ^ _304_/X (sky130_fd_sc_hd__o22a_2) |
| 2 0.04 la_data_out[29] (net) |
| 0.60 0.07 7.19 ^ _538_/A (sky130_fd_sc_hd__buf_4) |
| 0.21 0.36 7.55 ^ _538_/X (sky130_fd_sc_hd__buf_4) |
| 1 0.03 wbs_dat_o[29] (net) |
| 0.21 0.02 7.58 ^ wbs_dat_o[29] (out) |
| 7.58 data arrival time |
| |
| 0.15 20.00 20.00 clock wb_clk_i (rise edge) |
| 0.00 20.00 clock network delay (ideal) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -7.58 data arrival time |
| ----------------------------------------------------------------------------- |
| 8.17 slack (MET) |
| |
| |
| Startpoint: wbs_adr_i[11] (input port clocked by wb_clk_i) |
| Endpoint: wbs_dat_o[28] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 4.00 4.00 v input external delay |
| 0.32 0.31 4.31 v wbs_adr_i[11] (in) |
| 5 0.15 wbs_adr_i[11] (net) |
| 0.38 0.00 4.31 v _159_/A (sky130_fd_sc_hd__inv_2) |
| 0.09 0.14 4.45 ^ _159_/Y (sky130_fd_sc_hd__inv_2) |
| 2 0.00 _016_ (net) |
| 0.09 0.00 4.45 ^ _160_/A (sky130_fd_sc_hd__buf_1) |
| 0.93 0.73 5.18 ^ _160_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.08 _017_ (net) |
| 0.93 0.02 5.20 ^ _161_/A (sky130_fd_sc_hd__buf_1) |
| 0.91 0.79 5.98 ^ _161_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.08 _018_ (net) |
| 0.91 0.02 6.00 ^ _300_/A1 (sky130_fd_sc_hd__a22o_2) |
| 0.31 0.52 6.52 ^ _300_/X (sky130_fd_sc_hd__a22o_2) |
| 1 0.06 _122_ (net) |
| 0.31 0.02 6.54 ^ _301_/B2 (sky130_fd_sc_hd__o22a_2) |
| 0.59 0.59 7.13 ^ _301_/X (sky130_fd_sc_hd__o22a_2) |
| 2 0.04 la_data_out[28] (net) |
| 0.60 0.07 7.19 ^ _537_/A (sky130_fd_sc_hd__buf_4) |
| 0.21 0.36 7.55 ^ _537_/X (sky130_fd_sc_hd__buf_4) |
| 1 0.03 wbs_dat_o[28] (net) |
| 0.21 0.02 7.58 ^ wbs_dat_o[28] (out) |
| 7.58 data arrival time |
| |
| 0.15 20.00 20.00 clock wb_clk_i (rise edge) |
| 0.00 20.00 clock network delay (ideal) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -7.58 data arrival time |
| ----------------------------------------------------------------------------- |
| 8.17 slack (MET) |
| |
| |
| Startpoint: wbs_adr_i[11] (input port clocked by wb_clk_i) |
| Endpoint: wbs_dat_o[31] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 4.00 4.00 v input external delay |
| 0.32 0.31 4.31 v wbs_adr_i[11] (in) |
| 5 0.15 wbs_adr_i[11] (net) |
| 0.38 0.00 4.31 v _159_/A (sky130_fd_sc_hd__inv_2) |
| 0.09 0.14 4.45 ^ _159_/Y (sky130_fd_sc_hd__inv_2) |
| 2 0.00 _016_ (net) |
| 0.09 0.00 4.45 ^ _160_/A (sky130_fd_sc_hd__buf_1) |
| 0.93 0.73 5.18 ^ _160_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.08 _017_ (net) |
| 0.93 0.02 5.20 ^ _161_/A (sky130_fd_sc_hd__buf_1) |
| 0.91 0.79 5.98 ^ _161_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.08 _018_ (net) |
| 0.91 0.01 5.99 ^ _309_/A1 (sky130_fd_sc_hd__a22o_2) |
| 0.14 0.39 6.38 ^ _309_/X (sky130_fd_sc_hd__a22o_2) |
| 1 0.02 _128_ (net) |
| 0.14 0.00 6.38 ^ _310_/B2 (sky130_fd_sc_hd__o22a_2) |
| 0.65 0.58 6.95 ^ _310_/X (sky130_fd_sc_hd__o22a_2) |
| 2 0.04 la_data_out[31] (net) |
| 0.67 0.08 7.03 ^ _540_/A (sky130_fd_sc_hd__buf_4) |
| 0.18 0.35 7.38 ^ _540_/X (sky130_fd_sc_hd__buf_4) |
| 1 0.03 wbs_dat_o[31] (net) |
| 0.18 0.02 7.40 ^ wbs_dat_o[31] (out) |
| 7.40 data arrival time |
| |
| 0.15 20.00 20.00 clock wb_clk_i (rise edge) |
| 0.00 20.00 clock network delay (ideal) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -7.40 data arrival time |
| ----------------------------------------------------------------------------- |
| 8.35 slack (MET) |
| |
| |
| Startpoint: wbs_adr_i[11] (input port clocked by wb_clk_i) |
| Endpoint: wbs_dat_o[30] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 4.00 4.00 v input external delay |
| 0.32 0.31 4.31 v wbs_adr_i[11] (in) |
| 5 0.15 wbs_adr_i[11] (net) |
| 0.38 0.00 4.31 v _159_/A (sky130_fd_sc_hd__inv_2) |
| 0.09 0.14 4.45 ^ _159_/Y (sky130_fd_sc_hd__inv_2) |
| 2 0.00 _016_ (net) |
| 0.09 0.00 4.45 ^ _160_/A (sky130_fd_sc_hd__buf_1) |
| 0.93 0.73 5.18 ^ _160_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.08 _017_ (net) |
| 0.93 0.02 5.20 ^ _161_/A (sky130_fd_sc_hd__buf_1) |
| 0.91 0.79 5.98 ^ _161_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.08 _018_ (net) |
| 0.91 0.01 5.99 ^ _306_/A1 (sky130_fd_sc_hd__a22o_2) |
| 0.14 0.39 6.38 ^ _306_/X (sky130_fd_sc_hd__a22o_2) |
| 1 0.02 _126_ (net) |
| 0.14 0.00 6.38 ^ _307_/B2 (sky130_fd_sc_hd__o22a_2) |
| 0.64 0.57 6.95 ^ _307_/X (sky130_fd_sc_hd__o22a_2) |
| 2 0.04 la_data_out[30] (net) |
| 0.65 0.08 7.03 ^ _539_/A (sky130_fd_sc_hd__buf_4) |
| 0.18 0.35 7.38 ^ _539_/X (sky130_fd_sc_hd__buf_4) |
| 1 0.03 wbs_dat_o[30] (net) |
| 0.19 0.02 7.40 ^ wbs_dat_o[30] (out) |
| 7.40 data arrival time |
| |
| 0.15 20.00 20.00 clock wb_clk_i (rise edge) |
| 0.00 20.00 clock network delay (ideal) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -7.40 data arrival time |
| ----------------------------------------------------------------------------- |
| 8.35 slack (MET) |
| |
| |
| Startpoint: wbs_adr_i[11] (input port clocked by wb_clk_i) |
| Endpoint: wbs_dat_o[11] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 4.00 4.00 ^ input external delay |
| 0.67 0.56 4.56 ^ wbs_adr_i[11] (in) |
| 5 0.15 wbs_adr_i[11] (net) |
| 0.71 0.00 4.56 ^ _173_/A (sky130_fd_sc_hd__and2_2) |
| 0.08 0.31 4.87 ^ _173_/X (sky130_fd_sc_hd__and2_2) |
| 2 0.01 _026_ (net) |
| 0.08 0.00 4.87 ^ _209_/A (sky130_fd_sc_hd__buf_1) |
| 0.83 0.66 5.53 ^ _209_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.07 _054_ (net) |
| 0.83 0.03 5.56 ^ _230_/A (sky130_fd_sc_hd__buf_1) |
| 0.21 0.28 5.84 ^ _230_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.02 _070_ (net) |
| 0.21 0.00 5.84 ^ _234_/B1 (sky130_fd_sc_hd__a22o_2) |
| 0.32 0.39 6.24 ^ _234_/X (sky130_fd_sc_hd__a22o_2) |
| 1 0.06 _073_ (net) |
| 0.32 0.02 6.26 ^ _235_/B2 (sky130_fd_sc_hd__o22a_2) |
| 0.72 0.66 6.92 ^ _235_/X (sky130_fd_sc_hd__o22a_2) |
| 2 0.04 la_data_out[11] (net) |
| 0.73 0.09 7.01 ^ _520_/A (sky130_fd_sc_hd__buf_4) |
| 0.16 0.34 7.35 ^ _520_/X (sky130_fd_sc_hd__buf_4) |
| 1 0.03 wbs_dat_o[11] (net) |
| 0.16 0.01 7.36 ^ wbs_dat_o[11] (out) |
| 7.36 data arrival time |
| |
| 0.15 20.00 20.00 clock wb_clk_i (rise edge) |
| 0.00 20.00 clock network delay (ideal) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -7.36 data arrival time |
| ----------------------------------------------------------------------------- |
| 8.39 slack (MET) |
| |
| |
| max_report_end |
| check_report |
| |
| =========================================================================== |
| report_checks -unconstrained |
| ============================================================================ |
| Startpoint: wbs_adr_i[11] (input port clocked by wb_clk_i) |
| Endpoint: wbs_dat_o[29] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 4.00 4.00 v input external delay |
| 0.32 0.31 4.31 v wbs_adr_i[11] (in) |
| 5 0.15 wbs_adr_i[11] (net) |
| 0.38 0.00 4.31 v _159_/A (sky130_fd_sc_hd__inv_2) |
| 0.09 0.14 4.45 ^ _159_/Y (sky130_fd_sc_hd__inv_2) |
| 2 0.00 _016_ (net) |
| 0.09 0.00 4.45 ^ _160_/A (sky130_fd_sc_hd__buf_1) |
| 0.93 0.73 5.18 ^ _160_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.08 _017_ (net) |
| 0.93 0.02 5.20 ^ _161_/A (sky130_fd_sc_hd__buf_1) |
| 0.91 0.79 5.98 ^ _161_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.08 _018_ (net) |
| 0.91 0.02 6.00 ^ _303_/A1 (sky130_fd_sc_hd__a22o_2) |
| 0.31 0.52 6.52 ^ _303_/X (sky130_fd_sc_hd__a22o_2) |
| 1 0.06 _124_ (net) |
| 0.32 0.02 6.54 ^ _304_/B2 (sky130_fd_sc_hd__o22a_2) |
| 0.59 0.59 7.13 ^ _304_/X (sky130_fd_sc_hd__o22a_2) |
| 2 0.04 la_data_out[29] (net) |
| 0.60 0.07 7.19 ^ _538_/A (sky130_fd_sc_hd__buf_4) |
| 0.21 0.36 7.55 ^ _538_/X (sky130_fd_sc_hd__buf_4) |
| 1 0.03 wbs_dat_o[29] (net) |
| 0.21 0.02 7.58 ^ wbs_dat_o[29] (out) |
| 7.58 data arrival time |
| |
| 0.15 20.00 20.00 clock wb_clk_i (rise edge) |
| 0.00 20.00 clock network delay (ideal) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -7.58 data arrival time |
| ----------------------------------------------------------------------------- |
| 8.17 slack (MET) |
| |
| |
| |
| =========================================================================== |
| report_checks --slack_max -0.01 |
| ============================================================================ |
| No paths found. |
| check_report_end |
| check_slew |
| |
| =========================================================================== |
| report_check_types -max_slew -max_cap -max_fanout -violators |
| ============================================================================ |
| max slew |
| |
| Pin Limit Slew Slack |
| ------------------------------------------------------------ |
| wbs_adr_i[2] 1.50 2.51 -1.01 (VIOLATED) |
| wbs_adr_i[3] 1.50 2.50 -1.00 (VIOLATED) |
| wbs_adr_i[10] 1.50 2.16 -0.66 (VIOLATED) |
| wbs_adr_i[9] 1.50 2.15 -0.66 (VIOLATED) |
| wbs_adr_i[8] 1.50 2.04 -0.54 (VIOLATED) |
| wbs_adr_i[7] 1.50 2.03 -0.53 (VIOLATED) |
| wbs_adr_i[6] 1.50 2.01 -0.51 (VIOLATED) |
| wbs_adr_i[5] 1.50 2.00 -0.50 (VIOLATED) |
| wbs_adr_i[4] 1.50 1.98 -0.48 (VIOLATED) |
| _477_/A 1.50 1.78 -0.28 (VIOLATED) |
| _178_/X 1.51 1.78 -0.28 (VIOLATED) |
| _478_/A 1.50 1.76 -0.26 (VIOLATED) |
| _479_/A 1.50 1.75 -0.25 (VIOLATED) |
| wbs_dat_i[0] 1.50 1.74 -0.25 (VIOLATED) |
| _480_/A 1.50 1.73 -0.23 (VIOLATED) |
| wbs_dat_i[1] 1.50 1.73 -0.23 (VIOLATED) |
| _481_/A 1.50 1.72 -0.22 (VIOLATED) |
| wbs_dat_i[2] 1.50 1.72 -0.22 (VIOLATED) |
| _482_/A 1.50 1.71 -0.21 (VIOLATED) |
| wbs_dat_i[3] 1.50 1.70 -0.20 (VIOLATED) |
| _483_/A 1.50 1.70 -0.20 (VIOLATED) |
| _484_/A 1.50 1.69 -0.19 (VIOLATED) |
| wbs_dat_i[4] 1.50 1.69 -0.19 (VIOLATED) |
| _485_/A 1.50 1.68 -0.18 (VIOLATED) |
| wbs_dat_i[5] 1.50 1.68 -0.18 (VIOLATED) |
| _486_/A 1.50 1.67 -0.17 (VIOLATED) |
| wbs_dat_i[6] 1.50 1.67 -0.17 (VIOLATED) |
| _487_/A 1.50 1.67 -0.17 (VIOLATED) |
| wbs_dat_i[7] 1.50 1.66 -0.16 (VIOLATED) |
| _488_/A 1.50 1.66 -0.16 (VIOLATED) |
| wbs_dat_i[8] 1.50 1.65 -0.15 (VIOLATED) |
| _489_/A 1.50 1.65 -0.15 (VIOLATED) |
| wbs_dat_i[9] 1.50 1.64 -0.15 (VIOLATED) |
| _490_/A 1.50 1.64 -0.14 (VIOLATED) |
| wbs_dat_i[10] 1.50 1.63 -0.14 (VIOLATED) |
| _491_/A 1.50 1.63 -0.13 (VIOLATED) |
| wbs_dat_i[11] 1.50 1.63 -0.13 (VIOLATED) |
| _492_/A 1.50 1.62 -0.12 (VIOLATED) |
| wbs_dat_i[12] 1.50 1.62 -0.12 (VIOLATED) |
| _493_/A 1.50 1.61 -0.11 (VIOLATED) |
| wbs_dat_i[13] 1.50 1.61 -0.11 (VIOLATED) |
| _494_/A 1.50 1.60 -0.10 (VIOLATED) |
| wbs_dat_i[14] 1.50 1.60 -0.10 (VIOLATED) |
| wbs_dat_i[15] 1.50 1.59 -0.09 (VIOLATED) |
| _495_/A 1.50 1.59 -0.09 (VIOLATED) |
| _496_/A 1.50 1.58 -0.08 (VIOLATED) |
| wbs_dat_i[16] 1.50 1.58 -0.08 (VIOLATED) |
| wbs_dat_i[17] 1.50 1.57 -0.07 (VIOLATED) |
| _497_/A 1.50 1.57 -0.07 (VIOLATED) |
| _498_/A 1.50 1.56 -0.06 (VIOLATED) |
| wbs_dat_i[18] 1.50 1.56 -0.06 (VIOLATED) |
| wbs_dat_i[19] 1.50 1.55 -0.06 (VIOLATED) |
| _499_/A 1.50 1.56 -0.06 (VIOLATED) |
| wbs_dat_i[20] 1.50 1.54 -0.05 (VIOLATED) |
| _500_/A 1.50 1.55 -0.05 (VIOLATED) |
| wbs_dat_i[21] 1.50 1.54 -0.04 (VIOLATED) |
| _501_/A 1.50 1.54 -0.04 (VIOLATED) |
| wbs_dat_i[22] 1.50 1.53 -0.03 (VIOLATED) |
| _502_/A 1.50 1.53 -0.03 (VIOLATED) |
| wbs_dat_i[23] 1.50 1.52 -0.02 (VIOLATED) |
| _503_/A 1.50 1.52 -0.02 (VIOLATED) |
| wbs_dat_i[24] 1.50 1.51 -0.01 (VIOLATED) |
| _504_/A 1.50 1.51 -0.01 (VIOLATED) |
| wbs_dat_i[25] 1.50 1.50 -0.00 (VIOLATED) |
| _505_/A 1.50 1.50 -0.00 (VIOLATED) |
| |
| max fanout |
| |
| Pin Limit Fanout Slack |
| --------------------------------------------------------- |
| wbs_adr_i[10] 5 8 -3 (VIOLATED) |
| wbs_adr_i[2] 5 8 -3 (VIOLATED) |
| wbs_adr_i[3] 5 8 -3 (VIOLATED) |
| wbs_adr_i[4] 5 8 -3 (VIOLATED) |
| wbs_adr_i[5] 5 8 -3 (VIOLATED) |
| wbs_adr_i[6] 5 8 -3 (VIOLATED) |
| wbs_adr_i[7] 5 8 -3 (VIOLATED) |
| wbs_adr_i[8] 5 8 -3 (VIOLATED) |
| wbs_adr_i[9] 5 8 -3 (VIOLATED) |
| |
| max capacitance |
| |
| Pin Limit Cap Slack |
| ------------------------------------------------------------ |
| wbs_adr_i[2] 0.33 0.56 -0.23 (VIOLATED) |
| wbs_adr_i[3] 0.33 0.56 -0.23 (VIOLATED) |
| wbs_adr_i[10] 0.33 0.49 -0.16 (VIOLATED) |
| wbs_adr_i[9] 0.33 0.49 -0.16 (VIOLATED) |
| wbs_adr_i[8] 0.33 0.46 -0.13 (VIOLATED) |
| wbs_adr_i[7] 0.33 0.46 -0.13 (VIOLATED) |
| wbs_adr_i[6] 0.33 0.45 -0.12 (VIOLATED) |
| wbs_adr_i[5] 0.33 0.45 -0.12 (VIOLATED) |
| wbs_adr_i[4] 0.33 0.45 -0.11 (VIOLATED) |
| wbs_dat_i[0] 0.33 0.39 -0.06 (VIOLATED) |
| wbs_dat_i[1] 0.33 0.39 -0.05 (VIOLATED) |
| wbs_dat_i[2] 0.33 0.38 -0.05 (VIOLATED) |
| wbs_dat_i[3] 0.33 0.38 -0.05 (VIOLATED) |
| wbs_dat_i[4] 0.33 0.38 -0.05 (VIOLATED) |
| wbs_dat_i[5] 0.33 0.38 -0.04 (VIOLATED) |
| wbs_dat_i[6] 0.33 0.37 -0.04 (VIOLATED) |
| wbs_dat_i[7] 0.33 0.37 -0.04 (VIOLATED) |
| wbs_dat_i[8] 0.33 0.37 -0.04 (VIOLATED) |
| wbs_dat_i[9] 0.33 0.37 -0.04 (VIOLATED) |
| wbs_dat_i[10] 0.33 0.37 -0.03 (VIOLATED) |
| wbs_dat_i[11] 0.33 0.36 -0.03 (VIOLATED) |
| wbs_dat_i[12] 0.33 0.36 -0.03 (VIOLATED) |
| wbs_dat_i[13] 0.33 0.36 -0.03 (VIOLATED) |
| wbs_dat_i[14] 0.33 0.36 -0.03 (VIOLATED) |
| _178_/X 0.13 0.15 -0.02 (VIOLATED) |
| wbs_dat_i[15] 0.33 0.36 -0.02 (VIOLATED) |
| wbs_dat_i[16] 0.33 0.35 -0.02 (VIOLATED) |
| wbs_dat_i[17] 0.33 0.35 -0.02 (VIOLATED) |
| wbs_dat_i[18] 0.33 0.35 -0.02 (VIOLATED) |
| wbs_dat_i[19] 0.33 0.35 -0.02 (VIOLATED) |
| wbs_dat_i[20] 0.33 0.35 -0.01 (VIOLATED) |
| wbs_dat_i[21] 0.33 0.34 -0.01 (VIOLATED) |
| wbs_dat_i[22] 0.33 0.34 -0.01 (VIOLATED) |
| wbs_dat_i[23] 0.33 0.34 -0.01 (VIOLATED) |
| wbs_dat_i[24] 0.33 0.34 -0.01 (VIOLATED) |
| wbs_dat_i[25] 0.33 0.34 -0.00 (VIOLATED) |
| wbs_dat_i[26] 0.33 0.33 -0.00 (VIOLATED) |
| |
| |
| =========================================================================== |
| max slew violation count 65 |
| max fanout violation count 9 |
| max cap violation count 37 |
| ============================================================================ |
| check_slew_end |
| tns_report |
| |
| =========================================================================== |
| report_tns |
| ============================================================================ |
| tns 0.00 |
| tns_report_end |
| wns_report |
| |
| =========================================================================== |
| report_wns |
| ============================================================================ |
| wns 0.00 |
| wns_report_end |
| worst_slack |
| |
| =========================================================================== |
| report_worst_slack -max (Setup) |
| ============================================================================ |
| worst slack 8.17 |
| |
| =========================================================================== |
| report_worst_slack -min (Hold) |
| ============================================================================ |
| worst slack 1.99 |
| worst_slack_end |
| clock_skew |
| |
| =========================================================================== |
| report_clock_skew |
| ============================================================================ |
| Clock wb_clk_i |
| Latency CRPR Skew |
| _313_/CLK ^ |
| 4.98 |
| _313_/CLK ^ |
| 0.22 0.00 4.76 |
| |
| clock_skew_end |
| power_report |
| |
| =========================================================================== |
| report_power |
| ============================================================================ |
| Group Internal Switching Leakage Total |
| Power Power Power Power (Watts) |
| ---------------------------------------------------------------- |
| Sequential 2.08e-06 1.72e-07 8.44e-12 2.25e-06 1.8% |
| Combinational 3.48e-05 8.63e-05 1.38e-08 1.21e-04 98.2% |
| Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| ---------------------------------------------------------------- |
| Total 3.69e-05 8.65e-05 1.38e-08 1.23e-04 100.0% |
| 29.9% 70.1% 0.0% |
| power_report_end |
| area_report |
| |
| =========================================================================== |
| report_design_area |
| ============================================================================ |
| Design area 1314646 u^2 13% utilization. |
| area_report_end |
