openlane/user_project_wrapper/runs/user_project_wrapper/logs/placement/9-resizer.log

OpenROAD 79a46b62da64bbebc18f06b20c42211046de719a 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.unpadded.nom.lef
[INFO ODB-0223]     Created 13 technology layers
[INFO ODB-0224]     Created 25 technology vias
[INFO ODB-0225]     Created 442 library cells
[INFO ODB-0226] Finished LEF file:  /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.unpadded.nom.lef
[INFO ODB-0127] Reading DEF file: /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/placement/8-global.def
[INFO ODB-0128] Design: user_project_wrapper
[INFO ODB-0094] 		Created 100000 Insts
[INFO ODB-0130]     Created 645 pins.
[INFO ODB-0131]     Created 131684 components and 273438 component-terminals.
[INFO ODB-0132]     Created 8 special nets and 271878 connections.
[INFO ODB-0133]     Created 1044 nets and 1397 connections.
[INFO ODB-0134] Finished DEF file: /home/serdar/Desktop/openram_demo/openram_openmpw/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/placement/8-global.def
###############################################################################
# Created by write_sdc
# Sat May 28 12:17:32 2022
###############################################################################
current_design user_project_wrapper
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# Timing Constraints
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create_clock -name wb_clk_i -period 20.0000 [get_ports {wb_clk_i}]
set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
set_clock_uncertainty 0.2500 wb_clk_i
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[0]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[10]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[11]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[12]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[13]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[14]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[15]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[16]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[17]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[18]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[19]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[1]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[20]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[21]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[22]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[23]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[24]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[25]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[26]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[27]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[28]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[2]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[3]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[4]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[5]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[6]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[7]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[8]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[9]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[0]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[10]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[11]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[12]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[13]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[14]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[15]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[16]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[17]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[18]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[19]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[1]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[20]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[21]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[22]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[23]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[24]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[25]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[26]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[27]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[28]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[29]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[2]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[30]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[31]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[32]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[33]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[34]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[35]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[36]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[37]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[3]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[4]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[5]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[6]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[7]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[8]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[9]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[0]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[100]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[101]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[102]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[103]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[104]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[105]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[106]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[107]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[108]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[109]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[10]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[110]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[111]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[112]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[113]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[114]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[115]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[116]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[117]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[118]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[119]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[11]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[120]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[121]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[122]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[123]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[124]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[125]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[126]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[127]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[12]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[13]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[14]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[15]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[16]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[17]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[18]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[19]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[1]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[20]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[21]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[22]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[23]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[24]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[25]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[26]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[27]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[28]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[29]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[2]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[30]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[31]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[32]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[33]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[34]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[35]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[36]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[37]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[38]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[39]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[3]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[40]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[41]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[42]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[43]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[44]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[45]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[46]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[47]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[48]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[49]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[4]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[50]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[51]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[52]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[53]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[54]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[55]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[56]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[57]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[58]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[59]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[5]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[60]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[61]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[62]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[63]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[64]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[65]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[66]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[67]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[68]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[69]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[6]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[70]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[71]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[72]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[73]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[74]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[75]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[76]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[77]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[78]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[79]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[7]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[80]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[81]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[82]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[83]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[84]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[85]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[86]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[87]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[88]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[89]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[8]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[90]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[91]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[92]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[93]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[94]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[95]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[96]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[97]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[98]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[99]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[9]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[0]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[100]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[101]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[102]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[103]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[104]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[105]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[106]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[107]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[108]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[109]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[10]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[110]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[111]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[112]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[113]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[114]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[115]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[116]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[117]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[118]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[119]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[11]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[120]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[121]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[122]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[123]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[124]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[125]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[126]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[127]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[12]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[13]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[14]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[15]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[16]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[17]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[18]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[19]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[1]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[20]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[21]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[22]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[23]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[24]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[25]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[26]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[27]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[28]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[29]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[2]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[30]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[31]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[32]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[33]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[34]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[35]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[36]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[37]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[38]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[39]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[3]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[40]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[41]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[42]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[43]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[44]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[45]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[46]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[47]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[48]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[49]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[4]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[50]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[51]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[52]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[53]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[54]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[55]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[56]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[57]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[58]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[59]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[5]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[60]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[61]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[62]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[63]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[64]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[65]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[66]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[67]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[68]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[69]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[6]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[70]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[71]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[72]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[73]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[74]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[75]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[76]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[77]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[78]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[79]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[7]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[80]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[81]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[82]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[83]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[84]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[85]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[86]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[87]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[88]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[89]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[8]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[90]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[91]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[92]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[93]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[94]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[95]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[96]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[97]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[98]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[99]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[9]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {user_clock2}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_rst_i}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[0]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[10]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[11]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[12]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[13]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[14]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[15]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[16]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[17]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[18]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[19]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[1]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[20]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[21]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[22]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[23]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[24]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[25]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[26]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[27]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[28]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[29]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[2]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[30]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[31]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[3]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[4]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[5]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[6]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[7]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[8]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[9]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_cyc_i}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[0]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[10]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[11]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[12]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[13]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[14]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[15]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[16]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[17]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[18]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[19]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[1]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[20]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[21]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[22]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[23]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[24]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[25]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[26]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[27]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[28]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[29]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[2]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[30]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[31]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[3]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[4]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[5]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[6]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[7]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[0]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[1]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[2]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[3]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_stb_i}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_we_i}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[0]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[10]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[11]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[12]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[13]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[14]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[15]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[16]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[17]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[18]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[19]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[1]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[20]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[21]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[22]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[23]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[24]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[25]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[26]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[27]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[28]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[2]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[3]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[4]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[5]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[6]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[7]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[8]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {analog_io[9]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[0]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[10]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[11]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[12]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[13]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[14]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[15]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[16]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[17]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[18]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[19]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[1]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[20]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[21]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[22]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[23]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[24]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[25]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[26]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[27]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[28]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[29]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[2]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[30]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[31]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[32]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[33]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[34]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[35]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[36]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[37]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[3]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[4]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[5]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[6]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[7]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[8]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[9]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[0]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[10]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[11]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[12]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[13]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[14]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[15]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[16]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[17]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[18]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[19]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[1]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[20]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[21]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[22]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[23]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[24]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[25]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[26]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[27]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[28]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[29]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[2]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[30]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[31]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[32]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[33]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[34]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[35]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[36]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[37]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[3]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[4]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[5]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[6]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[7]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[8]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[9]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[0]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[100]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[101]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[102]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[103]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[104]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[105]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[106]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[107]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[108]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[109]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[10]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[110]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[111]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[112]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[113]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[114]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[115]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[116]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[117]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[118]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[119]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[11]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[120]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[121]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[122]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[123]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[124]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[125]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[126]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[127]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[12]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[13]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[14]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[15]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[16]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[17]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[18]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[19]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[1]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[20]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[21]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[22]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[23]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[24]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[25]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[26]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[27]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[28]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[29]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[2]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[30]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[31]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[32]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[33]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[34]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[35]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[36]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[37]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[38]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[39]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[3]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[40]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[41]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[42]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[43]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[44]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[45]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[46]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[47]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[48]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[49]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[4]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[50]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[51]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[52]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[53]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[54]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[55]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[56]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[57]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[58]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[59]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[5]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[60]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[61]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[62]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[63]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[64]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[65]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[66]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[67]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[68]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[69]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[6]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[70]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[71]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[72]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[73]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[74]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[75]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[76]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[77]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[78]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[79]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[7]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[80]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[81]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[82]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[83]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[84]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[85]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[86]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[87]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[88]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[89]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[8]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[90]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[91]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[92]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[93]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[94]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[95]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[96]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[97]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[98]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[99]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[9]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {user_irq[0]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {user_irq[1]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {user_irq[2]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_ack_o}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {wbs_ack_o}]
set_load -pin_load 0.0334 [get_ports {analog_io[28]}]
set_load -pin_load 0.0334 [get_ports {analog_io[27]}]
set_load -pin_load 0.0334 [get_ports {analog_io[26]}]
set_load -pin_load 0.0334 [get_ports {analog_io[25]}]
set_load -pin_load 0.0334 [get_ports {analog_io[24]}]
set_load -pin_load 0.0334 [get_ports {analog_io[23]}]
set_load -pin_load 0.0334 [get_ports {analog_io[22]}]
set_load -pin_load 0.0334 [get_ports {analog_io[21]}]
set_load -pin_load 0.0334 [get_ports {analog_io[20]}]
set_load -pin_load 0.0334 [get_ports {analog_io[19]}]
set_load -pin_load 0.0334 [get_ports {analog_io[18]}]
set_load -pin_load 0.0334 [get_ports {analog_io[17]}]
set_load -pin_load 0.0334 [get_ports {analog_io[16]}]
set_load -pin_load 0.0334 [get_ports {analog_io[15]}]
set_load -pin_load 0.0334 [get_ports {analog_io[14]}]
set_load -pin_load 0.0334 [get_ports {analog_io[13]}]
set_load -pin_load 0.0334 [get_ports {analog_io[12]}]
set_load -pin_load 0.0334 [get_ports {analog_io[11]}]
set_load -pin_load 0.0334 [get_ports {analog_io[10]}]
set_load -pin_load 0.0334 [get_ports {analog_io[9]}]
set_load -pin_load 0.0334 [get_ports {analog_io[8]}]
set_load -pin_load 0.0334 [get_ports {analog_io[7]}]
set_load -pin_load 0.0334 [get_ports {analog_io[6]}]
set_load -pin_load 0.0334 [get_ports {analog_io[5]}]
set_load -pin_load 0.0334 [get_ports {analog_io[4]}]
set_load -pin_load 0.0334 [get_ports {analog_io[3]}]
set_load -pin_load 0.0334 [get_ports {analog_io[2]}]
set_load -pin_load 0.0334 [get_ports {analog_io[1]}]
set_load -pin_load 0.0334 [get_ports {analog_io[0]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[37]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[36]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[35]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[34]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[33]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[32]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[31]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[30]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[29]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[28]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[27]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[26]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[25]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[24]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[23]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[22]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[21]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[20]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[19]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[18]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[17]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[16]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[15]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[14]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[13]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[12]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[11]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[10]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[9]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[8]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[7]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[6]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
set_load -pin_load 0.0334 [get_ports {io_out[37]}]
set_load -pin_load 0.0334 [get_ports {io_out[36]}]
set_load -pin_load 0.0334 [get_ports {io_out[35]}]
set_load -pin_load 0.0334 [get_ports {io_out[34]}]
set_load -pin_load 0.0334 [get_ports {io_out[33]}]
set_load -pin_load 0.0334 [get_ports {io_out[32]}]
set_load -pin_load 0.0334 [get_ports {io_out[31]}]
set_load -pin_load 0.0334 [get_ports {io_out[30]}]
set_load -pin_load 0.0334 [get_ports {io_out[29]}]
set_load -pin_load 0.0334 [get_ports {io_out[28]}]
set_load -pin_load 0.0334 [get_ports {io_out[27]}]
set_load -pin_load 0.0334 [get_ports {io_out[26]}]
set_load -pin_load 0.0334 [get_ports {io_out[25]}]
set_load -pin_load 0.0334 [get_ports {io_out[24]}]
set_load -pin_load 0.0334 [get_ports {io_out[23]}]
set_load -pin_load 0.0334 [get_ports {io_out[22]}]
set_load -pin_load 0.0334 [get_ports {io_out[21]}]
set_load -pin_load 0.0334 [get_ports {io_out[20]}]
set_load -pin_load 0.0334 [get_ports {io_out[19]}]
set_load -pin_load 0.0334 [get_ports {io_out[18]}]
set_load -pin_load 0.0334 [get_ports {io_out[17]}]
set_load -pin_load 0.0334 [get_ports {io_out[16]}]
set_load -pin_load 0.0334 [get_ports {io_out[15]}]
set_load -pin_load 0.0334 [get_ports {io_out[14]}]
set_load -pin_load 0.0334 [get_ports {io_out[13]}]
set_load -pin_load 0.0334 [get_ports {io_out[12]}]
set_load -pin_load 0.0334 [get_ports {io_out[11]}]
set_load -pin_load 0.0334 [get_ports {io_out[10]}]
set_load -pin_load 0.0334 [get_ports {io_out[9]}]
set_load -pin_load 0.0334 [get_ports {io_out[8]}]
set_load -pin_load 0.0334 [get_ports {io_out[7]}]
set_load -pin_load 0.0334 [get_ports {io_out[6]}]
set_load -pin_load 0.0334 [get_ports {io_out[5]}]
set_load -pin_load 0.0334 [get_ports {io_out[4]}]
set_load -pin_load 0.0334 [get_ports {io_out[3]}]
set_load -pin_load 0.0334 [get_ports {io_out[2]}]
set_load -pin_load 0.0334 [get_ports {io_out[1]}]
set_load -pin_load 0.0334 [get_ports {io_out[0]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[127]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[126]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[125]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[124]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[123]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[122]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[121]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[120]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[119]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[118]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[117]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[116]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[115]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[114]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[113]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[112]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[111]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[110]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[109]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[108]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[107]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[106]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[105]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[104]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[103]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[102]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[101]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[100]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[99]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[98]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[97]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[96]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[95]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[94]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[93]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[92]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[91]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[90]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[89]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[88]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[87]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[86]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[85]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[84]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[83]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[82]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[81]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[80]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[79]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[78]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[77]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[76]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[75]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[74]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[73]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[72]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[71]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[70]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[69]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[68]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[67]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[66]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[65]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[64]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[63]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[62]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[61]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[60]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[59]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[58]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[57]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[56]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[55]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[54]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[53]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[52]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[51]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[50]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[49]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[48]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[47]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[46]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[45]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[44]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[43]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[42]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[41]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[40]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[39]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[38]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[37]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[36]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[35]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[34]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[33]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[32]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[31]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[30]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[29]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[28]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[27]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[26]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[25]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[24]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[23]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[22]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[21]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[20]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[19]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[18]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[17]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[16]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[15]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[14]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[13]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[12]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[11]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[10]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[9]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[8]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[7]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[6]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[5]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[4]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[3]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[2]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[1]}]
set_load -pin_load 0.0334 [get_ports {la_data_out[0]}]
set_load -pin_load 0.0334 [get_ports {user_irq[2]}]
set_load -pin_load 0.0334 [get_ports {user_irq[1]}]
set_load -pin_load 0.0334 [get_ports {user_irq[0]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}]
set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock2}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_cyc_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_stb_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_we_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[127]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[126]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[125]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[124]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[123]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[122]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[121]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[120]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[119]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[118]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[117]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[116]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[115]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[114]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[113]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[112]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[111]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[110]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[109]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[108]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[107]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[106]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[105]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[104]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[103]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[102]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[101]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[100]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[99]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[98]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[97]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[96]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[95]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[94]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[93]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[92]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[91]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[90]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[89]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[88]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[87]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[86]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[85]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[84]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[83]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[82]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[81]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[80]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[79]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[78]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[77]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[76]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[75]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[74]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[73]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[72]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[71]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[70]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[69]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[68]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[67]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[66]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[65]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[64]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[63]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[62]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[61]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[60]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[59]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[58]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[57]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[56]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[55]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[54]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[53]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[52]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[51]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[50]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[49]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[48]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[47]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[46]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[45]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[44]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[43]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[42]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[41]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[40]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[39]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[38]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[37]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[36]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[35]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[34]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[33]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[32]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[127]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[126]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[125]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[124]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[123]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[122]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[121]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[120]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[119]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[118]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[117]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[116]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[115]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[114]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[113]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[112]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[111]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[110]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[109]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[108]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[107]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[106]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[105]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[104]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[103]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[102]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[101]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[100]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[99]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[98]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[97]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[96]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[95]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[94]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[93]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[92]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[91]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[90]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[89]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[88]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[87]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[86]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[85]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[84]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[83]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[82]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[81]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[80]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[79]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[78]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[77]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[76]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[75]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[74]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[73]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[72]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[71]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[70]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[69]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[68]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[67]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[66]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[65]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[64]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[63]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[62]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[61]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[60]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[59]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[58]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[57]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[56]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[55]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[54]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[53]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[52]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[51]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[50]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[49]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[48]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[47]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[46]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[45]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[44]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[43]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[42]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[41]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[40]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[39]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[38]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[37]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[36]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[35]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[34]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[33]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[32]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 5.0000 [current_design]
[INFO]: Setting RC values...
[INFO RSZ-0027] Inserted 51 input buffers.
[INFO RSZ-0028] Inserted 97 output buffers.
[WARNING RSZ-0065] max wire length less than 3154u increases wire delays.
[INFO RSZ-0035] Found 9 fanout violations.
[INFO RSZ-0037] Found 238 long wires.
[INFO RSZ-0038] Inserted 1701 buffers in 238 nets.
[INFO RSZ-0039] Resized 446 instances.
[INFO RSZ-0042] Inserted 110 tie sky130_fd_sc_hd__conb_1 instances.
[INFO RSZ-0042] Inserted 53 tie sky130_fd_sc_hd__conb_1 instances.
Placement Analysis
---------------------------------
total displacement      61908.7 u
average displacement        0.5 u
max displacement          225.3 u
original HPWL          369317.7 u
legalized HPWL         383720.4 u
delta HPWL                    4 %

[INFO DPL-0020] Mirrored 1097 instances
[INFO DPL-0021] HPWL before          383720.4 u
[INFO DPL-0022] HPWL after           381066.7 u
[INFO DPL-0023] HPWL delta               -0.7 %
min_report

===========================================================================
report_checks -path_delay min (Hold)
============================================================================
Startpoint: _313_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _313_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                  0.15    0.00    0.00 ^ _313_/CLK (sky130_fd_sc_hd__dfxtp_1)
                  0.05    0.33    0.33 ^ _313_/Q (sky130_fd_sc_hd__dfxtp_1)
     1    0.00                           net116 (net)
                  0.05    0.00    0.33 ^ repeater414/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.14    0.15    0.48 ^ repeater414/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.01                           net414 (net)
                  0.14    0.00    0.48 ^ repeater413/A (sky130_fd_sc_hd__clkbuf_4)
                  0.12    0.21    0.69 ^ repeater413/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.04                           net413 (net)
                  0.13    0.01    0.70 ^ repeater412/A (sky130_fd_sc_hd__buf_4)
                  0.05    0.14    0.84 ^ repeater412/X (sky130_fd_sc_hd__buf_4)
     1    0.01                           net412 (net)
                  0.05    0.00    0.84 ^ repeater411/A (sky130_fd_sc_hd__buf_6)
                  0.04    0.09    0.93 ^ repeater411/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net411 (net)
                  0.04    0.00    0.93 ^ repeater410/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.10    1.03 ^ repeater410/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net410 (net)
                  0.05    0.00    1.04 ^ repeater409/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.10    1.14 ^ repeater409/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net409 (net)
                  0.05    0.00    1.14 ^ repeater408/A (sky130_fd_sc_hd__buf_4)
                  0.06    0.12    1.26 ^ repeater408/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net408 (net)
                  0.06    0.00    1.26 ^ repeater407/A (sky130_fd_sc_hd__buf_4)
                  0.06    0.12    1.38 ^ repeater407/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net407 (net)
                  0.06    0.00    1.39 ^ repeater406/A (sky130_fd_sc_hd__buf_4)
                  0.06    0.13    1.51 ^ repeater406/X (sky130_fd_sc_hd__buf_4)
     2    0.02                           net406 (net)
                  0.06    0.00    1.51 ^ _151_/A_N (sky130_fd_sc_hd__nand3b_1)
                  0.12    0.15    1.66 ^ _151_/Y (sky130_fd_sc_hd__nand3b_1)
     1    0.01                           _010_ (net)
                  0.12    0.00    1.67 ^ repeater405/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
                  0.11    0.25    1.92 ^ repeater405/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
     1    0.02                           net405 (net)
                  0.11    0.00    1.92 ^ repeater404/A (sky130_fd_sc_hd__clkbuf_4)
                  0.07    0.17    2.09 ^ repeater404/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.02                           net404 (net)
                  0.07    0.00    2.09 ^ repeater403/A (sky130_fd_sc_hd__buf_4)
                  0.07    0.13    2.22 ^ repeater403/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net403 (net)
                  0.07    0.00    2.22 ^ repeater402/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.11    2.33 ^ repeater402/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net402 (net)
                  0.05    0.00    2.33 ^ repeater401/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.10    2.43 ^ repeater401/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net401 (net)
                  0.05    0.00    2.43 ^ repeater400/A (sky130_fd_sc_hd__buf_4)
                  0.04    0.10    2.54 ^ repeater400/X (sky130_fd_sc_hd__buf_4)
     1    0.01                           net400 (net)
                  0.04    0.00    2.54 ^ repeater399/A (sky130_fd_sc_hd__buf_4)
                  0.11    0.15    2.69 ^ repeater399/X (sky130_fd_sc_hd__buf_4)
     1    0.04                           net399 (net)
                  0.11    0.01    2.69 ^ repeater398/A (sky130_fd_sc_hd__buf_4)
                  0.04    0.13    2.82 ^ repeater398/X (sky130_fd_sc_hd__buf_4)
     1    0.01                           net398 (net)
                  0.04    0.00    2.82 ^ repeater397/A (sky130_fd_sc_hd__buf_4)
                  0.06    0.12    2.94 ^ repeater397/X (sky130_fd_sc_hd__buf_4)
     2    0.02                           net397 (net)
                  0.06    0.00    2.94 ^ repeater396/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.15    0.16    3.10 ^ repeater396/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     4    0.01                           net396 (net)
                  0.15    0.00    3.10 ^ _152_/A (sky130_fd_sc_hd__clkdlybuf4s18_2)
                  0.14    0.29    3.39 ^ _152_/X (sky130_fd_sc_hd__clkdlybuf4s18_2)
     5    0.03                           _011_ (net)
                  0.14    0.00    3.39 ^ _312_/A (sky130_fd_sc_hd__nor2_1)
                  0.02    0.06    3.45 v _312_/Y (sky130_fd_sc_hd__nor2_1)
     1    0.00                           _008_ (net)
                  0.02    0.00    3.45 v repeater225/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.10    0.17    3.62 v repeater225/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.02                           net225 (net)
                  0.10    0.00    3.63 v _313_/D (sky130_fd_sc_hd__dfxtp_1)
                                  3.63   data arrival time

                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                          0.25    0.25   clock uncertainty
                          0.00    0.25   clock reconvergence pessimism
                                  0.25 ^ _313_/CLK (sky130_fd_sc_hd__dfxtp_1)
                         -0.05    0.20   library hold time
                                  0.20   data required time
-----------------------------------------------------------------------------
                                  0.20   data required time
                                 -3.63   data arrival time
-----------------------------------------------------------------------------
                                  3.43   slack (MET)


Startpoint: _313_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: wbs_ack_o (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                  0.15    0.00    0.00 ^ _313_/CLK (sky130_fd_sc_hd__dfxtp_1)
                  0.05    0.33    0.33 ^ _313_/Q (sky130_fd_sc_hd__dfxtp_1)
     1    0.00                           net116 (net)
                  0.05    0.00    0.33 ^ repeater414/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.14    0.15    0.48 ^ repeater414/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.01                           net414 (net)
                  0.14    0.00    0.48 ^ repeater413/A (sky130_fd_sc_hd__clkbuf_4)
                  0.12    0.21    0.69 ^ repeater413/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.04                           net413 (net)
                  0.13    0.01    0.70 ^ repeater412/A (sky130_fd_sc_hd__buf_4)
                  0.05    0.14    0.84 ^ repeater412/X (sky130_fd_sc_hd__buf_4)
     1    0.01                           net412 (net)
                  0.05    0.00    0.84 ^ repeater411/A (sky130_fd_sc_hd__buf_6)
                  0.04    0.09    0.93 ^ repeater411/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net411 (net)
                  0.04    0.00    0.93 ^ repeater410/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.10    1.03 ^ repeater410/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net410 (net)
                  0.05    0.00    1.04 ^ repeater409/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.10    1.14 ^ repeater409/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net409 (net)
                  0.05    0.00    1.14 ^ repeater408/A (sky130_fd_sc_hd__buf_4)
                  0.06    0.12    1.26 ^ repeater408/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net408 (net)
                  0.06    0.00    1.26 ^ repeater407/A (sky130_fd_sc_hd__buf_4)
                  0.06    0.12    1.38 ^ repeater407/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net407 (net)
                  0.06    0.00    1.39 ^ repeater406/A (sky130_fd_sc_hd__buf_4)
                  0.06    0.13    1.51 ^ repeater406/X (sky130_fd_sc_hd__buf_4)
     2    0.02                           net406 (net)
                  0.06    0.00    1.51 ^ output116/A (sky130_fd_sc_hd__clkbuf_4)
                  0.11    0.18    1.70 ^ output116/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.03                           wbs_ack_o (net)
                  0.11    0.00    1.70 ^ wbs_ack_o (out)
                                  1.70   data arrival time

                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                          0.25    0.25   clock uncertainty
                          0.00    0.25   clock reconvergence pessimism
                         -4.00   -3.75   output external delay
                                 -3.75   data required time
-----------------------------------------------------------------------------
                                 -3.75   data required time
                                 -1.70   data arrival time
-----------------------------------------------------------------------------
                                  5.45   slack (MET)


Startpoint: wbs_dat_i[10] (input port clocked by wb_clk_i)
Endpoint: la_data_out[42] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                          4.00    4.00 ^ input external delay
                  0.02    0.01    4.01 ^ wbs_dat_i[10] (in)
     1    0.00                           wbs_dat_i[10] (net)
                  0.02    0.00    4.01 ^ input19/A (sky130_fd_sc_hd__buf_4)
                  0.06    0.11    4.13 ^ input19/X (sky130_fd_sc_hd__buf_4)
     2    0.02                           net19 (net)
                  0.06    0.00    4.13 ^ repeater1178/A (sky130_fd_sc_hd__clkbuf_4)
                  0.07    0.15    4.28 ^ repeater1178/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.02                           net1178 (net)
                  0.07    0.00    4.28 ^ repeater1177/A (sky130_fd_sc_hd__buf_4)
                  0.07    0.13    4.41 ^ repeater1177/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net1177 (net)
                  0.07    0.00    4.42 ^ repeater1176/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.11    4.53 ^ repeater1176/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net1176 (net)
                  0.05    0.00    4.53 ^ repeater1175/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.10    4.63 ^ repeater1175/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net1175 (net)
                  0.05    0.00    4.63 ^ repeater1174/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.10    4.73 ^ repeater1174/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net1174 (net)
                  0.05    0.00    4.74 ^ repeater1173/A (sky130_fd_sc_hd__buf_4)
                  0.07    0.12    4.86 ^ repeater1173/X (sky130_fd_sc_hd__buf_4)
     2    0.02                           net1173 (net)
                  0.07    0.00    4.86 ^ _487_/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.06    0.10    4.96 ^ _487_/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.00                           net88 (net)
                  0.06    0.00    4.96 ^ output88/A (sky130_fd_sc_hd__clkbuf_4)
                  0.11    0.18    5.14 ^ output88/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.03                           la_data_out[42] (net)
                  0.11    0.00    5.14 ^ la_data_out[42] (out)
                                  5.14   data arrival time

                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                          0.25    0.25   clock uncertainty
                          0.00    0.25   clock reconvergence pessimism
                         -4.00   -3.75   output external delay
                                 -3.75   data required time
-----------------------------------------------------------------------------
                                 -3.75   data required time
                                 -5.14   data arrival time
-----------------------------------------------------------------------------
                                  8.89   slack (MET)


Startpoint: wbs_dat_i[26] (input port clocked by wb_clk_i)
Endpoint: la_data_out[58] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                          4.00    4.00 ^ input external delay
                  0.02    0.01    4.01 ^ wbs_dat_i[26] (in)
     1    0.00                           wbs_dat_i[26] (net)
                  0.02    0.00    4.01 ^ input36/A (sky130_fd_sc_hd__buf_4)
                  0.07    0.12    4.13 ^ input36/X (sky130_fd_sc_hd__buf_4)
     2    0.02                           net36 (net)
                  0.07    0.00    4.14 ^ repeater815/A (sky130_fd_sc_hd__clkbuf_4)
                  0.07    0.15    4.29 ^ repeater815/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.02                           net815 (net)
                  0.07    0.00    4.29 ^ repeater814/A (sky130_fd_sc_hd__buf_4)
                  0.07    0.13    4.42 ^ repeater814/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net814 (net)
                  0.07    0.00    4.43 ^ repeater813/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.11    4.54 ^ repeater813/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net813 (net)
                  0.05    0.00    4.54 ^ repeater812/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.10    4.64 ^ repeater812/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net812 (net)
                  0.05    0.00    4.64 ^ repeater811/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.10    4.74 ^ repeater811/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net811 (net)
                  0.05    0.00    4.75 ^ repeater810/A (sky130_fd_sc_hd__buf_4)
                  0.07    0.12    4.87 ^ repeater810/X (sky130_fd_sc_hd__buf_4)
     2    0.02                           net810 (net)
                  0.07    0.00    4.87 ^ _503_/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.06    0.10    4.97 ^ _503_/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.00                           net105 (net)
                  0.06    0.00    4.97 ^ output105/A (sky130_fd_sc_hd__clkbuf_4)
                  0.11    0.18    5.15 ^ output105/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.03                           la_data_out[58] (net)
                  0.11    0.00    5.15 ^ la_data_out[58] (out)
                                  5.15   data arrival time

                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                          0.25    0.25   clock uncertainty
                          0.00    0.25   clock reconvergence pessimism
                         -4.00   -3.75   output external delay
                                 -3.75   data required time
-----------------------------------------------------------------------------
                                 -3.75   data required time
                                 -5.15   data arrival time
-----------------------------------------------------------------------------
                                  8.90   slack (MET)


Startpoint: wbs_dat_i[11] (input port clocked by wb_clk_i)
Endpoint: la_data_out[43] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                          4.00    4.00 ^ input external delay
                  0.02    0.01    4.01 ^ wbs_dat_i[11] (in)
     1    0.00                           wbs_dat_i[11] (net)
                  0.02    0.00    4.01 ^ input20/A (sky130_fd_sc_hd__buf_4)
                  0.06    0.11    4.13 ^ input20/X (sky130_fd_sc_hd__buf_4)
     2    0.02                           net20 (net)
                  0.06    0.00    4.13 ^ repeater1154/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
                  0.11    0.23    4.36 ^ repeater1154/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
     1    0.02                           net1154 (net)
                  0.11    0.00    4.36 ^ repeater1153/A (sky130_fd_sc_hd__buf_4)
                  0.07    0.15    4.51 ^ repeater1153/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net1153 (net)
                  0.07    0.00    4.51 ^ repeater1152/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.11    4.62 ^ repeater1152/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net1152 (net)
                  0.05    0.00    4.62 ^ repeater1151/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.10    4.73 ^ repeater1151/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net1151 (net)
                  0.05    0.00    4.73 ^ repeater1150/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.10    4.83 ^ repeater1150/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net1150 (net)
                  0.05    0.00    4.83 ^ repeater1149/A (sky130_fd_sc_hd__buf_4)
                  0.07    0.12    4.95 ^ repeater1149/X (sky130_fd_sc_hd__buf_4)
     2    0.02                           net1149 (net)
                  0.07    0.00    4.96 ^ _488_/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.05    0.10    5.05 ^ _488_/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.00                           net89 (net)
                  0.05    0.00    5.05 ^ output89/A (sky130_fd_sc_hd__clkbuf_4)
                  0.11    0.18    5.23 ^ output89/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.03                           la_data_out[43] (net)
                  0.11    0.00    5.23 ^ la_data_out[43] (out)
                                  5.23   data arrival time

                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                          0.25    0.25   clock uncertainty
                          0.00    0.25   clock reconvergence pessimism
                         -4.00   -3.75   output external delay
                                 -3.75   data required time
-----------------------------------------------------------------------------
                                 -3.75   data required time
                                 -5.23   data arrival time
-----------------------------------------------------------------------------
                                  8.98   slack (MET)


min_report_end
max_report

===========================================================================
report_checks -path_delay max (Setup)
============================================================================
Startpoint: wbs_adr_i[11] (input port clocked by wb_clk_i)
Endpoint: wbs_dat_o[6] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                          4.00    4.00 v input external delay
                  0.01    0.00    4.00 v wbs_adr_i[11] (in)
     1    0.00                           wbs_adr_i[11] (net)
                  0.01    0.00    4.00 v input7/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.04    0.13    4.13 v input7/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.00                           net7 (net)
                  0.04    0.00    4.13 v repeater476/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.10    0.20    4.33 v repeater476/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.02                           net476 (net)
                  0.10    0.00    4.33 v repeater475/A (sky130_fd_sc_hd__clkbuf_4)
                  0.05    0.19    4.53 v repeater475/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.02                           net475 (net)
                  0.05    0.00    4.53 v repeater474/A (sky130_fd_sc_hd__buf_4)
                  0.04    0.16    4.69 v repeater474/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net474 (net)
                  0.04    0.00    4.69 v repeater473/A (sky130_fd_sc_hd__buf_6)
                  0.03    0.13    4.82 v repeater473/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net473 (net)
                  0.03    0.00    4.83 v repeater472/A (sky130_fd_sc_hd__buf_6)
                  0.03    0.12    4.94 v repeater472/X (sky130_fd_sc_hd__buf_6)
     1    0.01                           net472 (net)
                  0.03    0.00    4.94 v repeater471/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.14    5.08 v repeater471/X (sky130_fd_sc_hd__buf_6)
     1    0.04                           net471 (net)
                  0.05    0.01    5.09 v repeater470/A (sky130_fd_sc_hd__buf_4)
                  0.03    0.15    5.24 v repeater470/X (sky130_fd_sc_hd__buf_4)
     1    0.01                           net470 (net)
                  0.03    0.00    5.24 v repeater469/A (sky130_fd_sc_hd__buf_4)
                  0.04    0.15    5.39 v repeater469/X (sky130_fd_sc_hd__buf_4)
     2    0.02                           net469 (net)
                  0.04    0.00    5.39 v repeater468/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.09    0.19    5.58 v repeater468/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     4    0.02                           net468 (net)
                  0.09    0.00    5.58 v _159_/A (sky130_fd_sc_hd__inv_2)
                  0.04    0.07    5.65 ^ _159_/Y (sky130_fd_sc_hd__inv_2)
     2    0.01                           _016_ (net)
                  0.04    0.00    5.65 ^ _160_/A (sky130_fd_sc_hd__clkbuf_4)
                  0.06    0.15    5.80 ^ _160_/X (sky130_fd_sc_hd__clkbuf_4)
     3    0.01                           _017_ (net)
                  0.06    0.00    5.80 ^ _164_/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.21    0.22    6.02 ^ _164_/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     5    0.02                           _020_ (net)
                  0.21    0.00    6.02 ^ _205_/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.16    0.23    6.25 ^ _205_/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     5    0.01                           _050_ (net)
                  0.16    0.00    6.25 ^ _213_/A1 (sky130_fd_sc_hd__o21a_1)
                  0.08    0.18    6.43 ^ _213_/X (sky130_fd_sc_hd__o21a_1)
     1    0.01                           _057_ (net)
                  0.08    0.00    6.43 ^ repeater389/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
                  0.11    0.27    6.70 ^ repeater389/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
     1    0.02                           net389 (net)
                  0.11    0.00    6.70 ^ _215_/B1 (sky130_fd_sc_hd__o22a_1)
                  0.08    0.18    6.88 ^ _215_/X (sky130_fd_sc_hd__o22a_1)
     1    0.01                           net112 (net)
                  0.08    0.00    6.88 ^ repeater283/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
                  0.22    0.35    7.23 ^ repeater283/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
     1    0.04                           net283 (net)
                  0.22    0.01    7.24 ^ repeater282/A (sky130_fd_sc_hd__clkbuf_4)
                  0.12    0.27    7.50 ^ repeater282/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.04                           net282 (net)
                  0.12    0.01    7.51 ^ repeater281/A (sky130_fd_sc_hd__buf_4)
                  0.06    0.16    7.67 ^ repeater281/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net281 (net)
                  0.06    0.00    7.67 ^ repeater280/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.12    7.79 ^ repeater280/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net280 (net)
                  0.05    0.00    7.79 ^ repeater279/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.11    7.90 ^ repeater279/X (sky130_fd_sc_hd__buf_6)
     2    0.02                           net279 (net)
                  0.05    0.00    7.90 ^ _515_/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.07    0.11    8.02 ^ _515_/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.00                           net145 (net)
                  0.07    0.00    8.02 ^ repeater176/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.20    0.22    8.23 ^ repeater176/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.02                           net176 (net)
                  0.20    0.00    8.23 ^ repeater175/A (sky130_fd_sc_hd__clkbuf_4)
                  0.07    0.22    8.45 ^ repeater175/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.02                           net175 (net)
                  0.07    0.00    8.45 ^ output145/A (sky130_fd_sc_hd__clkbuf_4)
                  0.11    0.21    8.66 ^ output145/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.03                           wbs_dat_o[6] (net)
                  0.11    0.00    8.66 ^ wbs_dat_o[6] (out)
                                  8.66   data arrival time

                  0.15   20.00   20.00   clock wb_clk_i (rise edge)
                          0.00   20.00   clock network delay (ideal)
                         -0.25   19.75   clock uncertainty
                          0.00   19.75   clock reconvergence pessimism
                         -4.00   15.75   output external delay
                                 15.75   data required time
-----------------------------------------------------------------------------
                                 15.75   data required time
                                 -8.66   data arrival time
-----------------------------------------------------------------------------
                                  7.09   slack (MET)


Startpoint: wbs_adr_i[11] (input port clocked by wb_clk_i)
Endpoint: wbs_dat_o[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                          4.00    4.00 v input external delay
                  0.01    0.00    4.00 v wbs_adr_i[11] (in)
     1    0.00                           wbs_adr_i[11] (net)
                  0.01    0.00    4.00 v input7/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.04    0.13    4.13 v input7/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.00                           net7 (net)
                  0.04    0.00    4.13 v repeater476/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.10    0.20    4.33 v repeater476/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.02                           net476 (net)
                  0.10    0.00    4.33 v repeater475/A (sky130_fd_sc_hd__clkbuf_4)
                  0.05    0.19    4.53 v repeater475/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.02                           net475 (net)
                  0.05    0.00    4.53 v repeater474/A (sky130_fd_sc_hd__buf_4)
                  0.04    0.16    4.69 v repeater474/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net474 (net)
                  0.04    0.00    4.69 v repeater473/A (sky130_fd_sc_hd__buf_6)
                  0.03    0.13    4.82 v repeater473/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net473 (net)
                  0.03    0.00    4.83 v repeater472/A (sky130_fd_sc_hd__buf_6)
                  0.03    0.12    4.94 v repeater472/X (sky130_fd_sc_hd__buf_6)
     1    0.01                           net472 (net)
                  0.03    0.00    4.94 v repeater471/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.14    5.08 v repeater471/X (sky130_fd_sc_hd__buf_6)
     1    0.04                           net471 (net)
                  0.05    0.01    5.09 v repeater470/A (sky130_fd_sc_hd__buf_4)
                  0.03    0.15    5.24 v repeater470/X (sky130_fd_sc_hd__buf_4)
     1    0.01                           net470 (net)
                  0.03    0.00    5.24 v repeater469/A (sky130_fd_sc_hd__buf_4)
                  0.04    0.15    5.39 v repeater469/X (sky130_fd_sc_hd__buf_4)
     2    0.02                           net469 (net)
                  0.04    0.00    5.39 v repeater468/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.09    0.19    5.58 v repeater468/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     4    0.02                           net468 (net)
                  0.09    0.00    5.58 v _159_/A (sky130_fd_sc_hd__inv_2)
                  0.04    0.07    5.65 ^ _159_/Y (sky130_fd_sc_hd__inv_2)
     2    0.01                           _016_ (net)
                  0.04    0.00    5.65 ^ _186_/A (sky130_fd_sc_hd__clkbuf_4)
                  0.05    0.14    5.79 ^ _186_/X (sky130_fd_sc_hd__clkbuf_4)
     2    0.01                           _036_ (net)
                  0.05    0.00    5.79 ^ repeater419/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
                  0.12    0.27    6.05 ^ repeater419/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
     3    0.02                           net419 (net)
                  0.12    0.00    6.06 ^ _187_/A (sky130_fd_sc_hd__clkbuf_4)
                  0.06    0.19    6.24 ^ _187_/X (sky130_fd_sc_hd__clkbuf_4)
     3    0.02                           _037_ (net)
                  0.06    0.00    6.24 ^ repeater416/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.20    0.22    6.46 ^ repeater416/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.02                           net416 (net)
                  0.20    0.00    6.46 ^ repeater415/A (sky130_fd_sc_hd__clkbuf_4)
                  0.08    0.23    6.69 ^ repeater415/X (sky130_fd_sc_hd__clkbuf_4)
     3    0.02                           net415 (net)
                  0.08    0.00    6.69 ^ _189_/A1 (sky130_fd_sc_hd__a22o_1)
                  0.16    0.24    6.93 ^ _189_/X (sky130_fd_sc_hd__a22o_1)
     1    0.02                           _039_ (net)
                  0.16    0.00    6.93 ^ _190_/B2 (sky130_fd_sc_hd__o22a_1)
                  0.05    0.16    7.09 ^ _190_/X (sky130_fd_sc_hd__o22a_1)
     1    0.00                           net52 (net)
                  0.05    0.00    7.09 ^ repeater315/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.09    0.13    7.22 ^ repeater315/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.01                           net315 (net)
                  0.09    0.00    7.22 ^ repeater314/A (sky130_fd_sc_hd__clkbuf_4)
                  0.13    0.22    7.44 ^ repeater314/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.04                           net314 (net)
                  0.14    0.01    7.45 ^ repeater313/A (sky130_fd_sc_hd__buf_4)
                  0.09    0.18    7.63 ^ repeater313/X (sky130_fd_sc_hd__buf_4)
     1    0.03                           net313 (net)
                  0.09    0.00    7.64 ^ repeater312/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.13    7.76 ^ repeater312/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net312 (net)
                  0.05    0.00    7.77 ^ repeater311/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.11    7.88 ^ repeater311/X (sky130_fd_sc_hd__buf_6)
     2    0.02                           net311 (net)
                  0.05    0.00    7.88 ^ repeater310/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.20    0.21    8.09 ^ repeater310/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.02                           net310 (net)
                  0.20    0.00    8.10 ^ _509_/A (sky130_fd_sc_hd__buf_4)
                  0.06    0.18    8.28 ^ _509_/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net117 (net)
                  0.06    0.00    8.28 ^ repeater183/A (sky130_fd_sc_hd__clkbuf_4)
                  0.07    0.17    8.45 ^ repeater183/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.02                           net183 (net)
                  0.07    0.00    8.45 ^ output117/A (sky130_fd_sc_hd__clkbuf_4)
                  0.11    0.20    8.65 ^ output117/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.03                           wbs_dat_o[0] (net)
                  0.11    0.00    8.65 ^ wbs_dat_o[0] (out)
                                  8.65   data arrival time

                  0.15   20.00   20.00   clock wb_clk_i (rise edge)
                          0.00   20.00   clock network delay (ideal)
                         -0.25   19.75   clock uncertainty
                          0.00   19.75   clock reconvergence pessimism
                         -4.00   15.75   output external delay
                                 15.75   data required time
-----------------------------------------------------------------------------
                                 15.75   data required time
                                 -8.65   data arrival time
-----------------------------------------------------------------------------
                                  7.10   slack (MET)


Startpoint: wbs_adr_i[11] (input port clocked by wb_clk_i)
Endpoint: wbs_dat_o[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                          4.00    4.00 v input external delay
                  0.01    0.00    4.00 v wbs_adr_i[11] (in)
     1    0.00                           wbs_adr_i[11] (net)
                  0.01    0.00    4.00 v input7/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.04    0.13    4.13 v input7/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.00                           net7 (net)
                  0.04    0.00    4.13 v repeater476/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.10    0.20    4.33 v repeater476/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.02                           net476 (net)
                  0.10    0.00    4.33 v repeater475/A (sky130_fd_sc_hd__clkbuf_4)
                  0.05    0.19    4.53 v repeater475/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.02                           net475 (net)
                  0.05    0.00    4.53 v repeater474/A (sky130_fd_sc_hd__buf_4)
                  0.04    0.16    4.69 v repeater474/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net474 (net)
                  0.04    0.00    4.69 v repeater473/A (sky130_fd_sc_hd__buf_6)
                  0.03    0.13    4.82 v repeater473/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net473 (net)
                  0.03    0.00    4.83 v repeater472/A (sky130_fd_sc_hd__buf_6)
                  0.03    0.12    4.94 v repeater472/X (sky130_fd_sc_hd__buf_6)
     1    0.01                           net472 (net)
                  0.03    0.00    4.94 v repeater471/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.14    5.08 v repeater471/X (sky130_fd_sc_hd__buf_6)
     1    0.04                           net471 (net)
                  0.05    0.01    5.09 v repeater470/A (sky130_fd_sc_hd__buf_4)
                  0.03    0.15    5.24 v repeater470/X (sky130_fd_sc_hd__buf_4)
     1    0.01                           net470 (net)
                  0.03    0.00    5.24 v repeater469/A (sky130_fd_sc_hd__buf_4)
                  0.04    0.15    5.39 v repeater469/X (sky130_fd_sc_hd__buf_4)
     2    0.02                           net469 (net)
                  0.04    0.00    5.39 v repeater468/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.09    0.19    5.58 v repeater468/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     4    0.02                           net468 (net)
                  0.09    0.00    5.58 v _159_/A (sky130_fd_sc_hd__inv_2)
                  0.04    0.07    5.65 ^ _159_/Y (sky130_fd_sc_hd__inv_2)
     2    0.01                           _016_ (net)
                  0.04    0.00    5.65 ^ _186_/A (sky130_fd_sc_hd__clkbuf_4)
                  0.05    0.14    5.79 ^ _186_/X (sky130_fd_sc_hd__clkbuf_4)
     2    0.01                           _036_ (net)
                  0.05    0.00    5.79 ^ repeater419/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
                  0.12    0.27    6.05 ^ repeater419/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
     3    0.02                           net419 (net)
                  0.12    0.00    6.06 ^ _187_/A (sky130_fd_sc_hd__clkbuf_4)
                  0.06    0.19    6.24 ^ _187_/X (sky130_fd_sc_hd__clkbuf_4)
     3    0.02                           _037_ (net)
                  0.06    0.00    6.24 ^ repeater416/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.20    0.22    6.46 ^ repeater416/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.02                           net416 (net)
                  0.20    0.00    6.46 ^ repeater415/A (sky130_fd_sc_hd__clkbuf_4)
                  0.08    0.23    6.69 ^ repeater415/X (sky130_fd_sc_hd__clkbuf_4)
     3    0.02                           net415 (net)
                  0.08    0.00    6.69 ^ _192_/A1 (sky130_fd_sc_hd__a22o_1)
                  0.16    0.24    6.93 ^ _192_/X (sky130_fd_sc_hd__a22o_1)
     1    0.02                           _041_ (net)
                  0.16    0.00    6.93 ^ _193_/B2 (sky130_fd_sc_hd__o22a_1)
                  0.04    0.15    7.08 ^ _193_/X (sky130_fd_sc_hd__o22a_1)
     1    0.00                           net63 (net)
                  0.04    0.00    7.08 ^ repeater309/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.09    0.13    7.21 ^ repeater309/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.01                           net309 (net)
                  0.09    0.00    7.21 ^ repeater308/A (sky130_fd_sc_hd__clkbuf_4)
                  0.13    0.23    7.44 ^ repeater308/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.04                           net308 (net)
                  0.14    0.01    7.45 ^ repeater307/A (sky130_fd_sc_hd__buf_4)
                  0.09    0.19    7.63 ^ repeater307/X (sky130_fd_sc_hd__buf_4)
     1    0.03                           net307 (net)
                  0.09    0.00    7.64 ^ repeater306/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.13    7.77 ^ repeater306/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net306 (net)
                  0.05    0.00    7.77 ^ repeater305/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.11    7.88 ^ repeater305/X (sky130_fd_sc_hd__buf_6)
     2    0.02                           net305 (net)
                  0.05    0.00    7.88 ^ repeater304/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.20    0.21    8.09 ^ repeater304/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.02                           net304 (net)
                  0.20    0.00    8.10 ^ _510_/A (sky130_fd_sc_hd__buf_4)
                  0.06    0.18    8.28 ^ _510_/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net128 (net)
                  0.06    0.00    8.28 ^ repeater182/A (sky130_fd_sc_hd__clkbuf_4)
                  0.07    0.16    8.45 ^ repeater182/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.02                           net182 (net)
                  0.07    0.00    8.45 ^ output128/A (sky130_fd_sc_hd__clkbuf_4)
                  0.11    0.20    8.65 ^ output128/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.03                           wbs_dat_o[1] (net)
                  0.11    0.00    8.65 ^ wbs_dat_o[1] (out)
                                  8.65   data arrival time

                  0.15   20.00   20.00   clock wb_clk_i (rise edge)
                          0.00   20.00   clock network delay (ideal)
                         -0.25   19.75   clock uncertainty
                          0.00   19.75   clock reconvergence pessimism
                         -4.00   15.75   output external delay
                                 15.75   data required time
-----------------------------------------------------------------------------
                                 15.75   data required time
                                 -8.65   data arrival time
-----------------------------------------------------------------------------
                                  7.10   slack (MET)


Startpoint: wbs_adr_i[11] (input port clocked by wb_clk_i)
Endpoint: wbs_dat_o[2] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                          4.00    4.00 v input external delay
                  0.01    0.00    4.00 v wbs_adr_i[11] (in)
     1    0.00                           wbs_adr_i[11] (net)
                  0.01    0.00    4.00 v input7/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.04    0.13    4.13 v input7/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.00                           net7 (net)
                  0.04    0.00    4.13 v repeater476/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.10    0.20    4.33 v repeater476/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.02                           net476 (net)
                  0.10    0.00    4.33 v repeater475/A (sky130_fd_sc_hd__clkbuf_4)
                  0.05    0.19    4.53 v repeater475/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.02                           net475 (net)
                  0.05    0.00    4.53 v repeater474/A (sky130_fd_sc_hd__buf_4)
                  0.04    0.16    4.69 v repeater474/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net474 (net)
                  0.04    0.00    4.69 v repeater473/A (sky130_fd_sc_hd__buf_6)
                  0.03    0.13    4.82 v repeater473/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net473 (net)
                  0.03    0.00    4.83 v repeater472/A (sky130_fd_sc_hd__buf_6)
                  0.03    0.12    4.94 v repeater472/X (sky130_fd_sc_hd__buf_6)
     1    0.01                           net472 (net)
                  0.03    0.00    4.94 v repeater471/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.14    5.08 v repeater471/X (sky130_fd_sc_hd__buf_6)
     1    0.04                           net471 (net)
                  0.05    0.01    5.09 v repeater470/A (sky130_fd_sc_hd__buf_4)
                  0.03    0.15    5.24 v repeater470/X (sky130_fd_sc_hd__buf_4)
     1    0.01                           net470 (net)
                  0.03    0.00    5.24 v repeater469/A (sky130_fd_sc_hd__buf_4)
                  0.04    0.15    5.39 v repeater469/X (sky130_fd_sc_hd__buf_4)
     2    0.02                           net469 (net)
                  0.04    0.00    5.39 v repeater468/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.09    0.19    5.58 v repeater468/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     4    0.02                           net468 (net)
                  0.09    0.00    5.58 v _159_/A (sky130_fd_sc_hd__inv_2)
                  0.04    0.07    5.65 ^ _159_/Y (sky130_fd_sc_hd__inv_2)
     2    0.01                           _016_ (net)
                  0.04    0.00    5.65 ^ _186_/A (sky130_fd_sc_hd__clkbuf_4)
                  0.05    0.14    5.79 ^ _186_/X (sky130_fd_sc_hd__clkbuf_4)
     2    0.01                           _036_ (net)
                  0.05    0.00    5.79 ^ repeater419/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
                  0.12    0.27    6.05 ^ repeater419/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
     3    0.02                           net419 (net)
                  0.12    0.00    6.06 ^ _187_/A (sky130_fd_sc_hd__clkbuf_4)
                  0.06    0.19    6.24 ^ _187_/X (sky130_fd_sc_hd__clkbuf_4)
     3    0.02                           _037_ (net)
                  0.06    0.00    6.24 ^ repeater416/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.20    0.22    6.46 ^ repeater416/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.02                           net416 (net)
                  0.20    0.00    6.46 ^ repeater415/A (sky130_fd_sc_hd__clkbuf_4)
                  0.08    0.23    6.69 ^ repeater415/X (sky130_fd_sc_hd__clkbuf_4)
     3    0.02                           net415 (net)
                  0.08    0.00    6.69 ^ _195_/A1 (sky130_fd_sc_hd__a22o_1)
                  0.16    0.24    6.93 ^ _195_/X (sky130_fd_sc_hd__a22o_1)
     1    0.02                           _043_ (net)
                  0.16    0.00    6.93 ^ _196_/B2 (sky130_fd_sc_hd__o22a_1)
                  0.08    0.18    7.12 ^ _196_/X (sky130_fd_sc_hd__o22a_1)
     1    0.01                           net74 (net)
                  0.08    0.00    7.12 ^ repeater303/A (sky130_fd_sc_hd__clkbuf_4)
                  0.13    0.22    7.34 ^ repeater303/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.04                           net303 (net)
                  0.13    0.01    7.35 ^ repeater302/A (sky130_fd_sc_hd__buf_4)
                  0.09    0.19    7.53 ^ repeater302/X (sky130_fd_sc_hd__buf_4)
     1    0.03                           net302 (net)
                  0.09    0.00    7.54 ^ repeater301/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.13    7.67 ^ repeater301/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net301 (net)
                  0.05    0.00    7.67 ^ repeater300/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.11    7.78 ^ repeater300/X (sky130_fd_sc_hd__buf_6)
     2    0.02                           net300 (net)
                  0.05    0.00    7.78 ^ repeater299/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.20    0.21    8.00 ^ repeater299/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.02                           net299 (net)
                  0.20    0.00    8.00 ^ _511_/A (sky130_fd_sc_hd__buf_4)
                  0.06    0.18    8.18 ^ _511_/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net139 (net)
                  0.06    0.00    8.18 ^ repeater181/A (sky130_fd_sc_hd__clkbuf_4)
                  0.07    0.17    8.35 ^ repeater181/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.02                           net181 (net)
                  0.07    0.00    8.35 ^ output139/A (sky130_fd_sc_hd__clkbuf_4)
                  0.11    0.20    8.55 ^ output139/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.03                           wbs_dat_o[2] (net)
                  0.11    0.00    8.55 ^ wbs_dat_o[2] (out)
                                  8.55   data arrival time

                  0.15   20.00   20.00   clock wb_clk_i (rise edge)
                          0.00   20.00   clock network delay (ideal)
                         -0.25   19.75   clock uncertainty
                          0.00   19.75   clock reconvergence pessimism
                         -4.00   15.75   output external delay
                                 15.75   data required time
-----------------------------------------------------------------------------
                                 15.75   data required time
                                 -8.55   data arrival time
-----------------------------------------------------------------------------
                                  7.20   slack (MET)


Startpoint: wbs_adr_i[11] (input port clocked by wb_clk_i)
Endpoint: wbs_dat_o[5] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                          4.00    4.00 v input external delay
                  0.01    0.00    4.00 v wbs_adr_i[11] (in)
     1    0.00                           wbs_adr_i[11] (net)
                  0.01    0.00    4.00 v input7/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.04    0.13    4.13 v input7/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.00                           net7 (net)
                  0.04    0.00    4.13 v repeater476/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.10    0.20    4.33 v repeater476/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.02                           net476 (net)
                  0.10    0.00    4.33 v repeater475/A (sky130_fd_sc_hd__clkbuf_4)
                  0.05    0.19    4.53 v repeater475/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.02                           net475 (net)
                  0.05    0.00    4.53 v repeater474/A (sky130_fd_sc_hd__buf_4)
                  0.04    0.16    4.69 v repeater474/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net474 (net)
                  0.04    0.00    4.69 v repeater473/A (sky130_fd_sc_hd__buf_6)
                  0.03    0.13    4.82 v repeater473/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net473 (net)
                  0.03    0.00    4.83 v repeater472/A (sky130_fd_sc_hd__buf_6)
                  0.03    0.12    4.94 v repeater472/X (sky130_fd_sc_hd__buf_6)
     1    0.01                           net472 (net)
                  0.03    0.00    4.94 v repeater471/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.14    5.08 v repeater471/X (sky130_fd_sc_hd__buf_6)
     1    0.04                           net471 (net)
                  0.05    0.01    5.09 v repeater470/A (sky130_fd_sc_hd__buf_4)
                  0.03    0.15    5.24 v repeater470/X (sky130_fd_sc_hd__buf_4)
     1    0.01                           net470 (net)
                  0.03    0.00    5.24 v repeater469/A (sky130_fd_sc_hd__buf_4)
                  0.04    0.15    5.39 v repeater469/X (sky130_fd_sc_hd__buf_4)
     2    0.02                           net469 (net)
                  0.04    0.00    5.39 v repeater468/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.09    0.19    5.58 v repeater468/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     4    0.02                           net468 (net)
                  0.09    0.00    5.58 v _159_/A (sky130_fd_sc_hd__inv_2)
                  0.04    0.07    5.65 ^ _159_/Y (sky130_fd_sc_hd__inv_2)
     2    0.01                           _016_ (net)
                  0.04    0.00    5.65 ^ _160_/A (sky130_fd_sc_hd__clkbuf_4)
                  0.06    0.15    5.80 ^ _160_/X (sky130_fd_sc_hd__clkbuf_4)
     3    0.01                           _017_ (net)
                  0.06    0.00    5.80 ^ _164_/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.21    0.22    6.02 ^ _164_/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     5    0.02                           _020_ (net)
                  0.21    0.00    6.02 ^ _205_/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.16    0.23    6.25 ^ _205_/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     5    0.01                           _050_ (net)
                  0.16    0.00    6.25 ^ _208_/A1 (sky130_fd_sc_hd__o21a_1)
                  0.09    0.19    6.43 ^ _208_/X (sky130_fd_sc_hd__o21a_1)
     1    0.01                           _053_ (net)
                  0.09    0.00    6.43 ^ repeater390/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
                  0.11    0.27    6.70 ^ repeater390/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
     1    0.02                           net390 (net)
                  0.11    0.00    6.71 ^ _212_/B1 (sky130_fd_sc_hd__o22a_1)
                  0.08    0.18    6.89 ^ _212_/X (sky130_fd_sc_hd__o22a_1)
     1    0.01                           net107 (net)
                  0.08    0.00    6.89 ^ repeater288/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
                  0.22    0.35    7.24 ^ repeater288/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
     1    0.04                           net288 (net)
                  0.22    0.01    7.25 ^ repeater287/A (sky130_fd_sc_hd__buf_4)
                  0.04    0.16    7.41 ^ repeater287/X (sky130_fd_sc_hd__buf_4)
     1    0.01                           net287 (net)
                  0.04    0.00    7.41 ^ repeater286/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.11    7.52 ^ repeater286/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net286 (net)
                  0.05    0.00    7.52 ^ repeater285/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.11    7.63 ^ repeater285/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net285 (net)
                  0.05    0.00    7.63 ^ repeater284/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.11    7.75 ^ repeater284/X (sky130_fd_sc_hd__buf_6)
     2    0.02                           net284 (net)
                  0.05    0.00    7.75 ^ _514_/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.06    0.10    7.85 ^ _514_/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.00                           net144 (net)
                  0.06    0.00    7.85 ^ repeater178/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.20    0.21    8.07 ^ repeater178/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.02                           net178 (net)
                  0.20    0.00    8.07 ^ repeater177/A (sky130_fd_sc_hd__clkbuf_4)
                  0.07    0.22    8.29 ^ repeater177/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.02                           net177 (net)
                  0.07    0.00    8.29 ^ output144/A (sky130_fd_sc_hd__clkbuf_4)
                  0.11    0.21    8.49 ^ output144/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.03                           wbs_dat_o[5] (net)
                  0.11    0.00    8.49 ^ wbs_dat_o[5] (out)
                                  8.49   data arrival time

                  0.15   20.00   20.00   clock wb_clk_i (rise edge)
                          0.00   20.00   clock network delay (ideal)
                         -0.25   19.75   clock uncertainty
                          0.00   19.75   clock reconvergence pessimism
                         -4.00   15.75   output external delay
                                 15.75   data required time
-----------------------------------------------------------------------------
                                 15.75   data required time
                                 -8.49   data arrival time
-----------------------------------------------------------------------------
                                  7.26   slack (MET)


max_report_end
check_report

===========================================================================
report_checks -unconstrained
============================================================================
Startpoint: wbs_adr_i[11] (input port clocked by wb_clk_i)
Endpoint: wbs_dat_o[6] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                          4.00    4.00 v input external delay
                  0.01    0.00    4.00 v wbs_adr_i[11] (in)
     1    0.00                           wbs_adr_i[11] (net)
                  0.01    0.00    4.00 v input7/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.04    0.13    4.13 v input7/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.00                           net7 (net)
                  0.04    0.00    4.13 v repeater476/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.10    0.20    4.33 v repeater476/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.02                           net476 (net)
                  0.10    0.00    4.33 v repeater475/A (sky130_fd_sc_hd__clkbuf_4)
                  0.05    0.19    4.53 v repeater475/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.02                           net475 (net)
                  0.05    0.00    4.53 v repeater474/A (sky130_fd_sc_hd__buf_4)
                  0.04    0.16    4.69 v repeater474/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net474 (net)
                  0.04    0.00    4.69 v repeater473/A (sky130_fd_sc_hd__buf_6)
                  0.03    0.13    4.82 v repeater473/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net473 (net)
                  0.03    0.00    4.83 v repeater472/A (sky130_fd_sc_hd__buf_6)
                  0.03    0.12    4.94 v repeater472/X (sky130_fd_sc_hd__buf_6)
     1    0.01                           net472 (net)
                  0.03    0.00    4.94 v repeater471/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.14    5.08 v repeater471/X (sky130_fd_sc_hd__buf_6)
     1    0.04                           net471 (net)
                  0.05    0.01    5.09 v repeater470/A (sky130_fd_sc_hd__buf_4)
                  0.03    0.15    5.24 v repeater470/X (sky130_fd_sc_hd__buf_4)
     1    0.01                           net470 (net)
                  0.03    0.00    5.24 v repeater469/A (sky130_fd_sc_hd__buf_4)
                  0.04    0.15    5.39 v repeater469/X (sky130_fd_sc_hd__buf_4)
     2    0.02                           net469 (net)
                  0.04    0.00    5.39 v repeater468/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.09    0.19    5.58 v repeater468/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     4    0.02                           net468 (net)
                  0.09    0.00    5.58 v _159_/A (sky130_fd_sc_hd__inv_2)
                  0.04    0.07    5.65 ^ _159_/Y (sky130_fd_sc_hd__inv_2)
     2    0.01                           _016_ (net)
                  0.04    0.00    5.65 ^ _160_/A (sky130_fd_sc_hd__clkbuf_4)
                  0.06    0.15    5.80 ^ _160_/X (sky130_fd_sc_hd__clkbuf_4)
     3    0.01                           _017_ (net)
                  0.06    0.00    5.80 ^ _164_/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.21    0.22    6.02 ^ _164_/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     5    0.02                           _020_ (net)
                  0.21    0.00    6.02 ^ _205_/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.16    0.23    6.25 ^ _205_/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     5    0.01                           _050_ (net)
                  0.16    0.00    6.25 ^ _213_/A1 (sky130_fd_sc_hd__o21a_1)
                  0.08    0.18    6.43 ^ _213_/X (sky130_fd_sc_hd__o21a_1)
     1    0.01                           _057_ (net)
                  0.08    0.00    6.43 ^ repeater389/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
                  0.11    0.27    6.70 ^ repeater389/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
     1    0.02                           net389 (net)
                  0.11    0.00    6.70 ^ _215_/B1 (sky130_fd_sc_hd__o22a_1)
                  0.08    0.18    6.88 ^ _215_/X (sky130_fd_sc_hd__o22a_1)
     1    0.01                           net112 (net)
                  0.08    0.00    6.88 ^ repeater283/A (sky130_fd_sc_hd__clkdlybuf4s15_2)
                  0.22    0.35    7.23 ^ repeater283/X (sky130_fd_sc_hd__clkdlybuf4s15_2)
     1    0.04                           net283 (net)
                  0.22    0.01    7.24 ^ repeater282/A (sky130_fd_sc_hd__clkbuf_4)
                  0.12    0.27    7.50 ^ repeater282/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.04                           net282 (net)
                  0.12    0.01    7.51 ^ repeater281/A (sky130_fd_sc_hd__buf_4)
                  0.06    0.16    7.67 ^ repeater281/X (sky130_fd_sc_hd__buf_4)
     1    0.02                           net281 (net)
                  0.06    0.00    7.67 ^ repeater280/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.12    7.79 ^ repeater280/X (sky130_fd_sc_hd__buf_6)
     1    0.02                           net280 (net)
                  0.05    0.00    7.79 ^ repeater279/A (sky130_fd_sc_hd__buf_6)
                  0.05    0.11    7.90 ^ repeater279/X (sky130_fd_sc_hd__buf_6)
     2    0.02                           net279 (net)
                  0.05    0.00    7.90 ^ _515_/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.07    0.11    8.02 ^ _515_/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.00                           net145 (net)
                  0.07    0.00    8.02 ^ repeater176/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.20    0.22    8.23 ^ repeater176/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     1    0.02                           net176 (net)
                  0.20    0.00    8.23 ^ repeater175/A (sky130_fd_sc_hd__clkbuf_4)
                  0.07    0.22    8.45 ^ repeater175/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.02                           net175 (net)
                  0.07    0.00    8.45 ^ output145/A (sky130_fd_sc_hd__clkbuf_4)
                  0.11    0.21    8.66 ^ output145/X (sky130_fd_sc_hd__clkbuf_4)
     1    0.03                           wbs_dat_o[6] (net)
                  0.11    0.00    8.66 ^ wbs_dat_o[6] (out)
                                  8.66   data arrival time

                  0.15   20.00   20.00   clock wb_clk_i (rise edge)
                          0.00   20.00   clock network delay (ideal)
                         -0.25   19.75   clock uncertainty
                          0.00   19.75   clock reconvergence pessimism
                         -4.00   15.75   output external delay
                                 15.75   data required time
-----------------------------------------------------------------------------
                                 15.75   data required time
                                 -8.66   data arrival time
-----------------------------------------------------------------------------
                                  7.09   slack (MET)



===========================================================================
report_checks --slack_max -0.01
============================================================================
No paths found.
check_report_end
check_slew

===========================================================================
 report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================

===========================================================================
max slew violation count 0
max fanout violation count 0
max cap violation count 0
============================================================================
check_slew_end
tns_report

===========================================================================
 report_tns
============================================================================
tns 0.00
tns_report_end
wns_report

===========================================================================
 report_wns
============================================================================
wns 0.00
wns_report_end
worst_slack

===========================================================================
 report_worst_slack -max (Setup)
============================================================================
worst slack 7.09

===========================================================================
 report_worst_slack -min (Hold)
============================================================================
worst slack 3.43
worst_slack_end
clock_skew

===========================================================================
 report_clock_skew
============================================================================
Clock wb_clk_i
Latency      CRPR       Skew
_313_/CLK ^
   5.93
_313_/CLK ^
   0.22      0.00       5.71

clock_skew_end
power_report

===========================================================================
 report_power
============================================================================
Group                  Internal  Switching    Leakage      Total
                          Power      Power      Power      Power (Watts)
----------------------------------------------------------------
Sequential             2.07e-06   2.11e-08   8.44e-12   2.09e-06   0.3%
Combinational          2.76e-04   3.28e-04   2.47e-08   6.04e-04  99.7%
Macro                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
----------------------------------------------------------------
Total                  2.78e-04   3.28e-04   2.47e-08   6.06e-04 100.0%
                          45.9%      54.1%       0.0%
power_report_end
area_report

===========================================================================
 report_design_area
============================================================================
Design area 1332002 u^2 13% utilization.
area_report_end