verilog/includes/includes.rtl.caravel_user_project

# Caravel user project includes
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
-v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
-v $(USER_PROJECT_VERILOG)/rtl/wishbone_1mst_to_8slv.v
-v $(USER_PROJECT_VERILOG)/rtl/prescaler.v
-v $(USER_PROJECT_VERILOG)/rtl/simple_fifo.v
-v $(USER_PROJECT_VERILOG)/rtl/nec_ir_receiver.v
-v $(USER_PROJECT_VERILOG)/rtl/pseudorandom.v
-v $(USER_PROJECT_VERILOG)/rtl/step_motor_controller.v
-v $(USER_PROJECT_VERILOG)/beh/ir_behavioral_driver.v