Add missed file paths

openlane/user_proj_example/config.tcl

diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 04390c2..a536cb8 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -23,8 +23,10 @@
 set ::env(VERILOG_FILES) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
 	$script_dir/../../verilog/rtl/user_proj_example.v \
+	$script_dir/../../verilog/rtl/wishbone_1mst_to_8slv.v \
 	$script_dir/../../verilog/rtl/simple_fifo.v \
-	$script_dir/../../verilog/rtl/nec_ir_receiver.v"
+	$script_dir/../../verilog/rtl/nec_ir_receiver.v \
+	$script_dir/../../verilog/rtl/pseudorandom.v"
 
 set ::env(DESIGN_IS_CORE) 0