Update testbenchs to avoid X propagation that trigger GL simulations fail

verilog/dv/nec_ir_receiver/nec_ir_receiver_tb.v

diff --git a/verilog/dv/nec_ir_receiver/nec_ir_receiver_tb.v b/verilog/dv/nec_ir_receiver/nec_ir_receiver_tb.v
index 385d30f..45ae55c 100644
--- a/verilog/dv/nec_ir_receiver/nec_ir_receiver_tb.v
+++ b/verilog/dv/nec_ir_receiver/nec_ir_receiver_tb.v
@@ -26,7 +26,6 @@
 
   wire gpio;
   wire [37:0] mprj_io;
-  wire [7:0] mprj_io_0;
   wire [15:0] checkbits;
   wire [7:0] addrbits;
   wire [7:0] databits;
@@ -37,6 +36,8 @@
   assign checkbits = mprj_io[31:16];
   assign addrbits  = mprj_io[15:8];
   assign databits  = mprj_io[7:0];
+  
+  assign (pull1,pull0)  mprj_io[37:0] = 38'b11111111111111111111111111111111111111;
 
   // External clock is used by default.  Make this artificially fast for the
   // simulation.  Normally this would be a slow clock and the digital PLL
@@ -117,8 +118,6 @@
 
   wire VDD3V3 = power1;
   wire VDD1V8 = power2;
-  wire USER_VDD3V3 = power3;
-  wire USER_VDD1V8 = power4;
   wire VSS = 1'b0;
   
   ir_behavioral_driver ir_drv(

verilog/dv/pseudorandom/pseudorandom_tb.v

diff --git a/verilog/dv/pseudorandom/pseudorandom_tb.v b/verilog/dv/pseudorandom/pseudorandom_tb.v
index c32c9b8..83a580a 100644
--- a/verilog/dv/pseudorandom/pseudorandom_tb.v
+++ b/verilog/dv/pseudorandom/pseudorandom_tb.v
@@ -26,7 +26,6 @@
 
   wire gpio;
   wire [37:0] mprj_io;
-  wire [7:0] mprj_io_0;
   wire [15:0] checkbits;
   wire [15:0] errorbits;
   
@@ -35,6 +34,8 @@
 
   assign checkbits = mprj_io[31:16];
   assign errorbits = mprj_io[15:0];
+  
+  assign (pull1,pull0)  mprj_io[37:0] = 38'b11111111111111111111111111111111111111;
 
   // External clock is used by default.  Make this artificially fast for the
   // simulation.  Normally this would be a slow clock and the digital PLL
@@ -111,8 +112,6 @@
 
   wire VDD3V3 = power1;
   wire VDD1V8 = power2;
-  wire USER_VDD3V3 = power3;
-  wire USER_VDD1V8 = power4;
   wire VSS = 1'b0;
 
   caravel uut (