commit	bd31973431fca2cb722789001c86c69e2f3eb946	[log] [tgz]
author	BYCakar <bycakar98@gmail.com>	Tue Jun 07 18:09:43 2022 +0300
committer	BYCakar <bycakar98@gmail.com>	Tue Jun 07 18:09:43 2022 +0300
tree	0f2c076c97bcdab5b2d6cf5f58077bad5bd36d9a
parent	a11292b5ad1ffdb085a7884807f9d9569dce13f5 [diff]

Added modbus_test and yonga_modbus_controller

Makefile[diff]
README.md[diff]
def/user_project_wrapper.def[diff]
gds/Modbus_w_RegSpace_Controller.gds[Added - diff]
gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds[Added - diff]
gds/user_project_wrapper.gds[diff]
lef/Modbus_w_RegSpace_Controller.lef[Added - diff]
lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef[Added - diff]
lef/user_project_wrapper.lef[diff]
mag/user_project_wrapper.mag[diff]
maglef/user_project_wrapper.mag[diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
sdc/user_project_wrapper.sdc[Added - diff]
sdf/user_project_wrapper.sdf[Added - diff]
signoff/user_project_wrapper/PDK_SOURCES[diff]
signoff/user_project_wrapper/final_summary_report.csv[diff]
spef/user_project_wrapper.spef[Added - diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/dv/Makefile[diff]
verilog/dv/modbus_test/Makefile[Added - diff]
verilog/dv/modbus_test/modbus_test.c[Added - diff]
verilog/dv/modbus_test/modbus_test_tb.v[Added - diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/includes/includes.rtl.caravel_user_project[diff]
verilog/rtl/Modbus_CRC16.v[Added - diff]
verilog/rtl/Modbus_Top.v[Added - diff]
verilog/rtl/Modbus_UART_Controller.v[Added - diff]
verilog/rtl/Modbus_w_RegSpace_Controller.v[Added - diff]
verilog/rtl/fifo.v[Added - diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v[Added - diff]
verilog/rtl/uart_rx.v[Added - diff]
verilog/rtl/uart_tx.v[Added - diff]
verilog/rtl/user_project_wrapper.v[diff]

34 files changed

tree: 0f2c076c97bcdab5b2d6cf5f58077bad5bd36d9a

README.md

Yonga-Modbus Controller

:exclamation: Important Note

This is a Modbus Controller with a read(03h) and a write(10h) function. Register space has read-write (0x00-0x7F) and read-only (0x80-0xFF) areas. Can also be accessed from PicoRV. PicoRV can write read-only space too.