updated top-level schematic
1 file changed
tree: fa05aa322e118bf2b2fd79df2da44092a4f8b2d8
  1. docs/
  2. gds/
  3. mag/
  4. netgen/
  5. openlane/
  6. verilog/
  7. xschem/
  8. .gitignore
  9. LICENSE
  10. Makefile
  11. README.md
README.md

10 bit SAR-ADC + Analog Circuits

This submission features:

  • 10b SAR-ADC on powered from external supply.
  • 10b SAR-ADC powered from internal regulators.
  • Trimable bandgap reference.
  • Testbuffer with multiplexer input.
  • Clock generator
  • 2 linear regulators, 1.2V and 1.5V.
  • Bias current/voltage generator.