commit: 13e5ec5e1967fd31a7854342a255cd81670c561c
[log] [tgz]
author: chrische <christoph-weiser@gmx.de>
Mon May 02 22:40:59 2022 +0200
committer: chrische <christoph-weiser@gmx.de>
Mon May 02 22:40:59 2022 +0200
tree: d93d3a2446aed8368d2f79831b97d3e7871f9cf1

init commit

.github/scripts/build/run-set-id.sh[Added - diff]
.github/scripts/build/run-truck.sh[Added - diff]
.github/scripts/build/run-xor.sh[Added - diff]
.github/scripts/dv/pdkBuild.sh[Added - diff]
.github/scripts/dv/run-dv-wrapper.sh[Added - diff]
.github/scripts/dv/run-dv.sh[Added - diff]
.github/scripts/precheck/precheckBuild.sh[Added - diff]
.github/scripts/precheck/run-precheck-drc.sh[Added - diff]
.github/scripts/precheck/run-precheck.sh[Added - diff]
.github/workflows/caravan_build.yml[Added - diff]
.github/workflows/user_project_ci.yml[Added - diff]
.gitignore[Added - diff]
Makefile[Added - diff]
README.md[Added - diff]
docs/Makefile[Added - diff]
docs/environment.yml[Added - diff]
docs/requirements.txt[Added - diff]
docs/source/conf.py[Added - diff]
docs/source/index.rst[Added - diff]
gds/user_analog_project_wrapper.gds[Added - diff]
mag/example_por.mag[Added - diff]
mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag[Added - diff]
mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag[Added - diff]
mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag[Added - diff]
mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag[Added - diff]
mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag[Added - diff]
mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag[Added - diff]
mag/user_analog_proj_example.mag[Added - diff]
mag/user_analog_project_wrapper.mag[Added - diff]
mag/user_analog_project_wrapper_empty.mag[Added - diff]
netgen/comp.out[Added - diff]
netgen/example_por.spice[Added - diff]
netgen/run_lvs_por.sh[Added - diff]
netgen/run_lvs_wrapper_verilog.sh[Added - diff]
netgen/run_lvs_wrapper_xschem.sh[Added - diff]
netgen/user_analog_project_wrapper.spice[Added - diff]
openlane/.gitignore[Added - diff]
openlane/Makefile[Added - diff]
verilog/dv/Makefile[Added - diff]
verilog/dv/README.md[Added - diff]
verilog/dv/mprj_por/Makefile[Added - diff]
verilog/dv/mprj_por/mprj_por.c[Added - diff]
verilog/dv/mprj_por/mprj_por_tb.v[Added - diff]
verilog/rtl/example_por.v[Added - diff]
verilog/rtl/uprj_analog_netlists.v[Added - diff]
verilog/rtl/user_analog_proj_example.v[Added - diff]
verilog/rtl/user_analog_project_wrapper.v[Added - diff]
xschem/.spiceinit[Added - diff]
xschem/analog_wrapper_tb.sch[Added - diff]
xschem/analog_wrapper_tb.spice[Added - diff]
xschem/current_test.spice[Added - diff]
xschem/example_por.sch[Added - diff]
xschem/example_por.sym[Added - diff]
xschem/example_por_tb.sch[Added - diff]
xschem/example_por_tb.spice[Added - diff]
xschem/example_por_tb.spice.orig[Added - diff]
xschem/test.data[Added - diff]
xschem/threshold_test_tb.spice[Added - diff]
xschem/user_analog_project_wrapper.sch[Added - diff]
xschem/user_analog_project_wrapper.spice[Added - diff]
xschem/user_analog_project_wrapper.sym[Added - diff]
xschem/xschemrc[Added - diff]

67 files changed

tree: d93d3a2446aed8368d2f79831b97d3e7871f9cf1

README.md

10 bit SAR-ADC with autocalibration + Analog Circuits

This submission features:

10b SAR-ADC on powered from standalone supply.
8b SAR-ADC powered from internal regulators.
trimable bandgap reference
Testbuffer with 8 inputs
1MHz ringoscillator
2 linear regulators, 1.2V and 1.4V
bias current generator