| /root/asicle-ro/Makefile |
| /root/asicle-ro/docs/Makefile |
| /root/asicle-ro/docs/environment.yml |
| /root/asicle-ro/docs/source/conf.py |
| /root/asicle-ro/docs/source/index.rst |
| /root/asicle-ro/docs/source/quickstart.rst |
| /root/asicle-ro/openlane/user_project/config.json |
| /root/asicle-ro/openlane/user_project/config.tcl |
| /root/asicle-ro/openlane/user_project_wrapper/config.json |
| /root/asicle-ro/openlane/user_project_wrapper/config.tcl |
| /root/asicle-ro/verilog/dv/Makefile |
| /root/asicle-ro/verilog/dv/io_ports/Makefile |
| /root/asicle-ro/verilog/dv/io_ports/io_ports.c |
| /root/asicle-ro/verilog/dv/io_ports/io_ports_tb.v |
| /root/asicle-ro/verilog/dv/la_test1/Makefile |
| /root/asicle-ro/verilog/dv/la_test1/la_test1.c |
| /root/asicle-ro/verilog/dv/la_test1/la_test1_tb.v |
| /root/asicle-ro/verilog/dv/la_test2/Makefile |
| /root/asicle-ro/verilog/dv/la_test2/la_test2.c |
| /root/asicle-ro/verilog/dv/la_test2/la_test2_tb.v |
| /root/asicle-ro/verilog/dv/mprj_stimulus/Makefile |
| /root/asicle-ro/verilog/dv/mprj_stimulus/mprj_stimulus.c |
| /root/asicle-ro/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v |
| /root/asicle-ro/verilog/dv/wb_port/Makefile |
| /root/asicle-ro/verilog/dv/wb_port/wb_port.c |
| /root/asicle-ro/verilog/dv/wb_port/wb_port_tb.v |
| /root/asicle-ro/verilog/includes/includes.gl+sdf.caravel_user_project |
| /root/asicle-ro/verilog/includes/includes.gl.caravel_user_project |
| /root/asicle-ro/verilog/includes/includes.rtl.caravel_user_project |
| /root/asicle-ro/verilog/rtl/control.v |
| /root/asicle-ro/verilog/rtl/debounce.v |
| /root/asicle-ro/verilog/rtl/display.v |
| /root/asicle-ro/verilog/rtl/eval.v |
| /root/asicle-ro/verilog/rtl/font.mem |
| /root/asicle-ro/verilog/rtl/frame.v |
| /root/asicle-ro/verilog/rtl/picks.mem |
| /root/asicle-ro/verilog/rtl/square.v |
| /root/asicle-ro/verilog/rtl/top.v |
| /root/asicle-ro/verilog/rtl/uprj_netlists.v |
| /root/asicle-ro/verilog/rtl/user_defines.v |
| /root/asicle-ro/verilog/rtl/user_project.v |
| /root/asicle-ro/verilog/rtl/user_project_wrapper.v |
| /root/asicle-ro/verilog/rtl/vga.v |
| /root/asicle-ro/verilog/rtl/wordlist.mem |
| /root/asicle-ro/verilog/rtl/wordlist.v |
