| # ISA 16-bit microprocessor | |
| This is the next version of the SOC. 1KB of memory has been added. | |
| The memory can be loadded via logic analyzer bus from management core. | |
| Then the program and data can be used from memory. | |
| The clock can be chosen from wishbone clock or user_clock2 or external. | |
| The reset can be chosen from wishbone reset or external pin. | |
| A soc configuration block has been aceated to control memory and cpu. |