Timing clean up and dcache bug fix
diff --git a/openlane/mbist/base.sdc b/openlane/mbist/base.sdc index eb845a0..26a1fe6 100644 --- a/openlane/mbist/base.sdc +++ b/openlane/mbist/base.sdc
@@ -11,7 +11,7 @@ create_generated_clock -name bist_mem_clk_a -add -source [get_ports {wb_clk2_i}] -master_clock [get_clocks wb_clk2_i] -divide_by 1 -comment {Mem Clock A} [get_ports mem_clk_a] create_generated_clock -name bist_mem_clk_b -add -source [get_ports {wb_clk2_i}] -master_clock [get_clocks wb_clk2_i] -divide_by 1 -comment {Mem Clock B} [get_ports mem_clk_b] -set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks {wb_clk_i wb_clk2_i bist_mem_clk_a bist_mem_clk_b}] +set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks {bist_mem_clk_a bist_mem_clk_b}] -group [get_clocks {wb_clk_i }] -group [get_clocks {wb_clk2_i}] set_clock_transition 0.1500 [all_clocks] set_clock_uncertainty -setup 0.2500 [all_clocks]
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index d45af45..ac93699 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,6 +1,6 @@ -u_qspi_master 2250 700 N -u_uart_i2c_usb_spi 2250 1400 N -u_pinmux 2250 2300 N +u_qspi_master 2225 700 N +u_uart_i2c_usb_spi 2225 1400 N +u_pinmux 2225 2300 N u_sram2_2kb 150 3000 N u_sram3_2kb 950 3000 N
diff --git a/openlane/wb_host/base.sdc b/openlane/wb_host/base.sdc index c332df0..ee8410c 100644 --- a/openlane/wb_host/base.sdc +++ b/openlane/wb_host/base.sdc
@@ -78,12 +78,12 @@ set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}] set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}] -set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[*]}] -set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}] -set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[*]}] -set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[*]}] -set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}] -set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}] +set_output_delay -min -1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[*]}] +set_output_delay -min -1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}] +set_output_delay -min -1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[*]}] +set_output_delay -min -1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[*]}] +set_output_delay -min -1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}] +set_output_delay -min -1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}] ############################################################################### # Environment
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl index eec3264..85fe0e5 100755 --- a/openlane/wb_interconnect/config.tcl +++ b/openlane/wb_interconnect/config.tcl
@@ -96,7 +96,7 @@ ## Placement set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1 -set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1 +set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0 set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 2 set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2
diff --git a/openlane/yifive/base.sdc b/openlane/yifive/base.sdc index 626a527..375538d 100644 --- a/openlane/yifive/base.sdc +++ b/openlane/yifive/base.sdc
@@ -5,10 +5,21 @@ create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}] create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}] +create_generated_clock -name sram0_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {tcm sram clock0} [get_ports sram0_clk0] +create_generated_clock -name sram0_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {tcm sram clock1} [get_ports sram0_clk1] + +create_generated_clock -name icache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {icache clock0} [get_ports icache_mem_clk0] +create_generated_clock -name icache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {icache clock1} [get_ports icache_mem_clk1] + +create_generated_clock -name dcache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache clock0} [get_ports dcache_mem_clk0] +create_generated_clock -name dcache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache clock1} [get_ports dcache_mem_clk1] + set_clock_transition 0.1500 [all_clocks] set_clock_uncertainty -setup 0.2500 [all_clocks] set_clock_uncertainty -hold 0.2500 [all_clocks] +set_propagated_clock [all_clocks] + set ::env(SYNTH_TIMING_DERATE) 0.05 puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %" @@ -16,7 +27,7 @@ set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] set_clock_groups -name async_clock -asynchronous \ - -group [get_clocks {core_clk}]\ + -group [get_clocks {core_clk sram0_clk0 sram0_clk1 icache_mem_clk0 icache_mem_clk1 dcache_mem_clk0 dcache_mem_clk1} ]\ -group [get_clocks {rtc_clk}]\ -group [get_clocks {wb_clk}] -comment {Async Clock group} @@ -31,63 +42,152 @@ set_max_delay 2 -to [get_ports {wbd_clk_riscv}] set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_riscv -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[*]}] -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[*]}] +#TCM Memory +set_input_delay -max 6.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_dout0[*]}] +set_input_delay -min 3.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_dout0[*]}] -set_input_delay -min 3.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[*]}] -set_input_delay -min 3.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[*]}] +set_input_delay -max 6.0000 -clock [get_clocks {sram0_clk1}] -add_delay [get_ports {sram0_dout1[*]}] +set_input_delay -min 3.0000 -clock [get_clocks {sram0_clk1}] -add_delay [get_ports {sram0_dout1[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_csb0}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_csb1}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_web0}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_wmask0[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk1}] -add_delay [get_ports {sram0_addr1[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk1}] -add_delay [get_ports {sram0_csb1}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_csb0}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_csb1}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_web0}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_wmask0[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk1}] -add_delay [get_ports {sram0_addr1[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk1}] -add_delay [get_ports {sram0_csb1}] +set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_addr0[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_csb0}] +set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_din0[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_web0}] +set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_wmask0[*]}] + +set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_addr0[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_csb0}] +set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_din0[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_web0}] +set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_wmask0[*]}] + +#icache memory +set_input_delay -max 6.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_dout1[*]}] +set_input_delay -min 3.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_dout1[*]}] + +set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_addr1[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_csb1}] + +set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_addr1[*]}] +set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_csb1}] + +set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_addr0[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_csb0}] +set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_din0[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_web0}] +set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_wmask0[*]}] + +set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_addr0[*]}] +set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_csb0}] +set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_din0[*]}] +set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_web0}] +set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_wmask0[*]}] + +#dcache memory +set_input_delay -max 6.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_dout0[*]}] +set_input_delay -min 3.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_dout0[*]}] + +set_input_delay -max 6.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_dout1[*]}] +set_input_delay -min 3.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_dout1[*]}] + +set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_addr1[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_csb1}] + +set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_addr1[*]}] +set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_csb1}] + +set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_addr0[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_csb0}] +set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_din0[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_web0}] +set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_wmask0[*]}] + +set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_addr0[*]}] +set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_csb0}] +set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_din0[*]}] +set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_web0}] +set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_wmask0[*]}] set_input_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_rst_n}] + +#Wishbone DMEM set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_ack_i}] set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[*]}] set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_err_i}] -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_ack_i}] -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[*]}] -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_err_i}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_ack_i}] set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[*]}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_ack_i}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[*]}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_err_i}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[*]}] set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[*]}] set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[*]}] set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[*]}] set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_stb_o}] set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_we_o}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_stb_o}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_we_o}] set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[*]}] set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[*]}] set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[*]}] set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_stb_o}] set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_we_o}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_stb_o}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_we_o}] + +#Wishbone icache +set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_lack_i}] +set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_ack_i}] +set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_dat_i[*]}] +set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_err_i}] + +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_lack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_ack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_dat_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_dat_i[*]}] + +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_adr_o[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_sel_o[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_bl_o[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_bry_o}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_stb_o}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_we_o}] + +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_adr_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_sel_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_bl_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_bry_o}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_stb_o}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_we_o}] + +#Wishbone dcache +set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_lack_i}] +set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_ack_i}] +set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_dat_i[*]}] +set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_err_i}] + +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_lack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_ack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_dat_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_dat_i[*]}] + +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_adr_o[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_dat_o[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_sel_o[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_bl_o[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_bry_o}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_stb_o}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_we_o}] + +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_adr_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_dat_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_sel_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_bl_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_bry_o}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_stb_o}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_we_o}] set_false_path\ -from [get_ports {soft_irq}]
diff --git a/openlane/yifive/config.tcl b/openlane/yifive/config.tcl index 219ef26..435a8f9 100755 --- a/openlane/yifive/config.tcl +++ b/openlane/yifive/config.tcl
@@ -106,7 +106,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) [list 0.0 0.0 750.0 1450.0] +set ::env(DIE_AREA) [list 0.0 0.0 725.0 1425.0] # If you're going to use multiple power domains, then keep this disabled. @@ -116,7 +116,7 @@ set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) "0.40" +set ::env(PL_TARGET_DENSITY) "0.36" set ::env(FP_CORE_UTIL) "50" # helps in anteena fix
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index 393d72c..ffcbae2 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h7m7s,-1,2.724159402241594,10.2784,1.362079701120797,-1,536.8,14,0,0,0,0,0,0,-1,0,0,-1,-1,1487509,10317,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,64380.99,4.37,5.42,1.03,0.72,-1,313,2877,313,2877,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,100,90,0.55,0.0,sky130_fd_sc_hd,4,0 +0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h50m22s,-1,2.724159402241594,10.2784,1.362079701120797,-1,536.41,14,0,0,0,0,0,0,-1,0,0,-1,-1,1382277,9457,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,64380.99,4.47,4.45,0.78,0.67,-1,313,2877,313,2877,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,100,90,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv index fae4e84..8afeccf 100644 --- a/signoff/wb_host/final_summary_report.csv +++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h9m8s,-1,41500.0,0.2,20750.0,27.14,656.0,4150,0,0,0,0,0,0,0,2,0,0,-1,339728,47338,0.0,-0.73,-1,-0.52,-1,0.0,-124.0,-1,-1.44,-1,276222913.0,0.16,54.59,17.5,16.78,0.0,-1,3443,6114,1023,3550,0,0,0,3745,0,0,0,0,0,0,0,4,1231,1200,17,166,2592,0,2758,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.33,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h9m5s,-1,41570.0,0.2,20785.0,27.16,665.55,4157,0,0,0,0,0,0,0,7,0,0,-1,342762,47421,0.0,-0.39,-1,-0.15,-1,0.0,-47.54,-1,-0.52,-1,279734014.0,2.28,55.55,17.8,16.11,0.01,-1,3490,6163,1024,3553,0,0,0,3793,0,0,0,0,0,0,0,4,1233,1205,17,166,2592,0,2758,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.33,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv index af52d28..5f2f6ea 100644 --- a/signoff/wb_interconnect/final_summary_report.csv +++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow_completed,0h17m1s,-1,19817.391304347824,0.46,9908.695652173912,9.26,733.2,4558,0,-1,-1,-1,-1,0,0,1,0,-1,-1,845641,51327,-1.0,-9.35,-1,-0.57,-1,-120.98,-2527.7,-1,-31.1,-1,738740222.0,0.0,15.77,51.42,2.18,44.71,0.0,1769,5285,252,3767,0,0,0,2675,0,0,0,0,0,0,0,4,1191,1078,18,1674,5873,0,7547,90.9090909090909,11,10,AREA 0,2,50,1,153.6,153.18,0.3,0,sky130_fd_sc_hd,4,4 +0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow_completed,0h18m24s,-1,19852.173913043476,0.46,9926.086956521738,9.27,726.88,4566,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,848196,51567,-0.9,-9.3,-1,-1.34,-1,-99.69,-2508.48,-1,-173.72,-1,745063608.0,0.0,15.97,52.54,2.07,42.24,0.0,1776,5292,252,3767,0,0,0,2682,0,0,0,0,0,0,0,4,1192,1079,18,1674,5873,0,7547,90.9090909090909,11,10,AREA 0,2,50,1,153.6,153.18,0.3,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/yifive/final_summary_report.csv b/signoff/yifive/final_summary_report.csv index 25aa043..cedb7e9 100644 --- a/signoff/yifive/final_summary_report.csv +++ b/signoff/yifive/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/yifive,ycr1_top_wb,yifive,flow_completed,1h36m1s,-1,58992.183908045976,1.0875,29496.091954022988,33.75,1525.48,32077,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,2442216,371640,-27.11,-54.85,-1,-9.94,-1,-72257.27,-140592.75,-1,-4304.53,-1,1669037052.0,11.0,44.4,52.11,9.29,10.28,-1,26877,46216,1728,20697,0,0,0,32103,0,0,0,0,0,0,0,4,7879,8416,55,1050,15019,0,16069,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/yifive,ycr1_top_wb,yifive,flow_completed,1h10m32s,-1,62420.32667876588,1.033125,31210.16333938294,35.63,1498.7,32244,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,2409836,367161,-15.33,-49.98,-1,-0.01,-1,-31946.93,-11474.41,-1,-0.01,-1,1780383901.0,5.46,44.53,58.67,5.38,10.76,0.0,26922,45935,1722,20366,0,0,0,32127,0,0,0,0,0,0,0,4,7920,8456,48,1030,14217,0,15247,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.36,0.0,sky130_fd_sc_hd,4,4
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl index d872e0b..f78d21e 100644 --- a/sta/scripts/caravel_timing.tcl +++ b/sta/scripts/caravel_timing.tcl
@@ -49,7 +49,7 @@ read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v - read_verilog $::env(USER_ROOT)/verilog/gl/mbist.v + read_verilog $::env(USER_ROOT)/verilog/gl/mbist_wrapper.v read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v @@ -144,7 +144,7 @@ read_spef -path gpio_defaults_block_37 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef ## User Project Spef - read_spef -path mprj/u_mbist $::env(USER_ROOT)/spef/mbist_top.spef + read_spef -path mprj/u_mbist $::env(USER_ROOT)/spef/mbist_wrapper.spef read_spef -path mprj/u_riscv_top $::env(USER_ROOT)/spef/ycr1_top_wb.spef read_spef -path mprj/u_pinmux $::env(USER_ROOT)/spef/pinmux.spef
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc index 9ec6823..711014a 100644 --- a/sta/sdc/caravel.sdc +++ b/sta/sdc/caravel.sdc
@@ -22,15 +22,15 @@ create_clock -name uarts_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart_core.u_lineclk_buf.u_mux/X}] create_clock -name uartm_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.u_mux/X}] -create_generated_clock -name mem_clk0 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/mem_no[0].u_mem_sel.u_mem_clk_sel.u_mux/X] -create_generated_clock -name mem_clk1 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/mem_no[1].u_mem_sel.u_mem_clk_sel.u_mux/X] -create_generated_clock -name mem_clk2 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/mem_no[2].u_mem_sel.u_mem_clk_sel.u_mux/X] -create_generated_clock -name mem_clk3 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/mem_no[3].u_mem_sel.u_mem_clk_sel.u_mux/X] +create_generated_clock -name mem_clk0 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/u_mbist.mem_no[0].u_mem_sel.u_mem_clk_sel.u_mux/X] +create_generated_clock -name mem_clk1 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/u_mbist.mem_no[1].u_mem_sel.u_mem_clk_sel.u_mux/X] +create_generated_clock -name mem_clk2 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/u_mbist.mem_no[2].u_mem_sel.u_mem_clk_sel.u_mux/X] +create_generated_clock -name mem_clk3 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/u_mbist.mem_no[3].u_mem_sel.u_mem_clk_sel.u_mux/X] ## Case analysis set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[0]}] -set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}] +set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}] set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}] set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[3]}] @@ -44,17 +44,17 @@ set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}] set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}] -set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}] -set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}] -set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}] -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}] +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}] +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}] +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}] +set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}] set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[0]}] set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[1]}] set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[2]}] set_case_analysis 1 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[3]}] -set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}] +set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}] set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}] set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}] set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}]
diff --git a/verilog/dv/firmware/link.ld b/verilog/dv/firmware/link.ld index 0496122..222363d 100644 --- a/verilog/dv/firmware/link.ld +++ b/verilog/dv/firmware/link.ld
@@ -26,7 +26,7 @@ MEMORY { ROM (rxx) : ORIGIN = 0x0, LENGTH = 64K - RAM (rwx) : ORIGIN = 0x08000000, LENGTH = 8K + RAM (rwx) : ORIGIN = 0x08000000, LENGTH = 64K TCM (rwx) : ORIGIN = 0x0C480000, LENGTH = 2K }
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile index 1703420..0461ba3 100644 --- a/verilog/dv/riscv_regress/Makefile +++ b/verilog/dv/riscv_regress/Makefile
@@ -189,13 +189,13 @@ TARGETS += isr_sample # Comment this target if you don't want to run the coremark -#TARGETS += coremark +TARGETS += coremark # Comment this target if you don't want to run the dhrystone -#TARGETS += dhrystone21 +TARGETS += dhrystone21 # Comment this target if you don't want to run the hello test -#TARGETS += hello +TARGETS += hello # Targets
diff --git a/verilog/dv/riscv_regress/riscv_runtests.sv b/verilog/dv/riscv_regress/riscv_runtests.sv index 0396ed2..25c14a5 100644 --- a/verilog/dv/riscv_regress/riscv_runtests.sv +++ b/verilog/dv/riscv_regress/riscv_runtests.sv
@@ -106,6 +106,7 @@ force u_top.u_riscv_top.u_intf.u_dcache.cfg_force_flush = 1'b1; wait(u_top.u_riscv_top.u_intf.u_dcache.force_flush_done == 1'b1); release u_top.u_riscv_top.u_intf.u_dcache.cfg_force_flush; + repeat (2000) @(posedge clock); // wait data to flush in pipe $display("STATUS: Checking Complaince Test Status .... "); test_running <= 1'b0; test_pass = 1; @@ -156,7 +157,8 @@ `endif fd = $fopen(tmpstr, "w"); while ((start != stop)) begin - test_data = u_top.u_sram0_2kb.mem[(start & 32'h1FFF)]; + //test_data = u_top.u_sram0_2kb.mem[(start & 32'h1FFF)]; + test_data = {u_sram.memory[start+3], u_sram.memory[start+2], u_sram.memory[start+1], u_sram.memory[start]}; $fwrite(fd, "%x", test_data); $fwrite(fd, "%s", "\n"); start += 4; @@ -180,7 +182,8 @@ // other-wise need to switch bank // -------------------------------------------------- //$writememh("sram0_out.hex",u_top.u_tsram0_2kb.mem,0,511); - test_data = u_top.u_sram0_2kb.mem[((start >> 2) & 32'h1FFF)]; + //test_data = u_top.u_sram0_2kb.mem[((start >> 2) & 32'h1FFF)]; + test_data = {u_sram.memory[start+3], u_sram.memory[start+2], u_sram.memory[start+1], u_sram.memory[start]}; //$display("Compare Addr: %x ref_data : %x, test_data: %x",start,ref_data,test_data); test_pass &= (ref_data == test_data); if(ref_data != test_data)
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v index 0636940..ca9ee0a 100644 --- a/verilog/dv/riscv_regress/user_risc_regress_tb.v +++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -76,12 +76,28 @@ `include "s25fl256s.sv" `include "uprj_netlists.v" `include "mt48lc8m8a2.v" +`include "spiram.v" localparam [31:0] YCR1_SIM_EXIT_ADDR = 32'h0000_00F8; localparam [31:0] YCR1_SIM_PRINT_ADDR = 32'hF000_0000; localparam [31:0] YCR1_SIM_EXT_IRQ_ADDR = 32'hF000_0100; localparam [31:0] YCR1_SIM_SOFT_IRQ_ADDR = 32'hF000_0200; + `define QSPIM_GLBL_CTRL 32'h10000000 + `define QSPIM_DMEM_G0_RD_CTRL 32'h10000004 + `define QSPIM_DMEM_G0_WR_CTRL 32'h10000008 + `define QSPIM_DMEM_G1_RD_CTRL 32'h1000000C + `define QSPIM_DMEM_G1_WR_CTRL 32'h10000010 + + `define QSPIM_DMEM_CS_AMAP 32'h10000014 + `define QSPIM_DMEM_CA_AMASK 32'h10000018 + + `define QSPIM_IMEM_CTRL1 32'h1000001C + `define QSPIM_IMEM_CTRL2 32'h10000020 + `define QSPIM_IMEM_ADDR 32'h10000024 + `define QSPIM_IMEM_WDATA 32'h10000028 + `define QSPIM_IMEM_RDATA 32'h1000002C + `define QSPIM_SPI_STATUS 32'h10000030 module user_risc_regress_tb; reg clock; @@ -143,6 +159,31 @@ logic [31:0] mem_data; +parameter P_FSM_C = 4'b0000; // Command Phase Only +parameter P_FSM_CW = 4'b0001; // Command + Write DATA Phase Only +parameter P_FSM_CA = 4'b0010; // Command -> Address Phase Only + +parameter P_FSM_CAR = 4'b0011; // Command -> Address -> Read Data +parameter P_FSM_CADR = 4'b0100; // Command -> Address -> Dummy -> Read Data +parameter P_FSM_CAMR = 4'b0101; // Command -> Address -> Mode -> Read Data +parameter P_FSM_CAMDR = 4'b0110; // Command -> Address -> Mode -> Dummy -> Read Data + +parameter P_FSM_CAW = 4'b0111; // Command -> Address ->Write Data +parameter P_FSM_CADW = 4'b1000; // Command -> Address -> DUMMY + Write Data +parameter P_FSM_CAMW = 4'b1001; // Command -> Address -> MODE + Write Data + +parameter P_FSM_CDR = 4'b1010; // COMMAND -> DUMMY -> READ +parameter P_FSM_CDW = 4'b1011; // COMMAND -> DUMMY -> WRITE +parameter P_FSM_CR = 4'b1100; // COMMAND -> READ + +parameter P_MODE_SWITCH_IDLE = 2'b00; +parameter P_MODE_SWITCH_AT_ADDR = 2'b01; +parameter P_MODE_SWITCH_AT_DATA = 2'b10; + +parameter P_SINGLE = 2'b00; +parameter P_DOUBLE = 2'b01; +parameter P_QUAD = 2'b10; +parameter P_QDDR = 2'b11; //----------------------------------------------------------------- // Since this is regression, reset will be applied multiple time // Reset logic @@ -209,6 +250,9 @@ // some of the RISCV test need SRAM area for specific // instruction execution like fence $sformat(test_ram_file, "%s.ram",test_file); + $readmemh(test_ram_file,u_sram.memory); + + /*** // Split the Temp memory content to two sram file $readmemh(test_ram_file,tem_mem); // Load the SRAM0/SRAM1 with 2KB data @@ -224,6 +268,7 @@ //$display("Filling Mem Location : %x with data : %x",i, mem_data); u_top.u_sram1_2kb.mem[(2048-i)/4] = mem_data; end + ***/ //for(i =32'h00; i < 32'h100; i = i+1) // $display("Location: %x, Data: %x", i, u_top.u_tsram0_2kb.mem[i]); @@ -243,8 +288,18 @@ repeat (2) @(posedge clock); #1; + // Remove WB and SPI Reset, Keep SDARM and CORE under Reset + wb_user_core_write('h3080_0000,'h5); + + // CS#2 Switch to QSPI Mode + wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 + wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); + wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38}); + wb_user_core_write(`QSPIM_IMEM_WDATA,32'h0); + // Enable the DCACHE Remap to SRAM region - wb_user_core_write('h3080_000C,{4'b0000,4'b1111, 24'h0}); + //wb_user_core_write('h3080_000C,{4'b0000,4'b1111, 24'h0}); + // // Remove all the reset wb_user_core_write('h3080_0000,'h8F); @@ -361,6 +416,19 @@ ); + wire spiram_csb = io_out[26]; + + spiram #(.mem_file_name("none")) + u_sram ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb), + .io2 (flash_io2), + .io3 (flash_io3) + );
diff --git a/verilog/rtl/lib/sync_wbb.sv b/verilog/rtl/lib/sync_wbb.sv index a8c8209..e2cc794 100644 --- a/verilog/rtl/lib/sync_wbb.sv +++ b/verilog/rtl/lib/sync_wbb.sv
@@ -159,11 +159,13 @@ case(m_state) IDLE: begin // Read DATA - if(wbm_stb_i && !wbm_we_i && wbm_bry_i && !m_cmd_wr_full && !wbm_lack_o) begin + // Make sure that FIFO is not overflow and there is no previous + // pending write + fifo is about to full + if(wbm_stb_i && !wbm_we_i && wbm_bry_i && !m_cmd_wr_full && !(m_cmd_wr_afull && m_cmd_wr_en) && !wbm_lack_o) begin m_bl_cnt <= wbm_bl_i; m_cmd_wr_en <= 'b1; m_state <= READ_DATA; - end else if(wbm_stb_i && wbm_we_i && wbm_bry_i && !m_cmd_wr_full && !wbm_lack_o) begin + end else if(wbm_stb_i && wbm_we_i && wbm_bry_i && !m_cmd_wr_full && !(m_cmd_wr_afull && m_cmd_wr_en) && !wbm_lack_o) begin wbm_ack_o <= 'b1; m_cmd_wr_en <= 'b1; m_bl_cnt <= wbm_bl_i-1; @@ -184,7 +186,7 @@ // Write next Transaction WRITE_DATA: begin - if(m_cmd_wr_full != 1 && wbm_bry_i) begin + if(m_cmd_wr_full != 1 && !(m_cmd_wr_afull && m_cmd_wr_en) && wbm_bry_i) begin wbm_ack_o <= 'b1; m_cmd_wr_en <= 'b1; if(m_bl_cnt == 1) begin
diff --git a/verilog/rtl/yifive/ycr1c b/verilog/rtl/yifive/ycr1c index 08852b6..384c470 160000 --- a/verilog/rtl/yifive/ycr1c +++ b/verilog/rtl/yifive/ycr1c
@@ -1 +1 @@ -Subproject commit 08852b63dac383caf5161340680e28ce834065a4 +Subproject commit 384c470fc7ed3bbc0a9056549afddfde8112afdc