i2c related clean-up
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl
index 57819dc..0be5bbd 100755
--- a/openlane/pinmux_top/config.tcl
+++ b/openlane/pinmux_top/config.tcl
@@ -55,11 +55,15 @@
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/timer_reg.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/timer.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/semaphore_reg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/ws281x_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/ws281x_driver.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/ws281x_reg.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type1.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type2.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \
$::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/sync_fifo.sv \
"
@@ -80,7 +84,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 500 400"
+set ::env(DIE_AREA) "0 0 500 750"
# If you're going to use multiple power domains, then keep this disabled.
@@ -92,13 +96,15 @@
set ::env(PL_TIME_DRIVEN) 1
set ::env(PL_TARGET_DENSITY) "0.40"
set ::env(CELL_PAD) "4"
+set ::env(GRT_ADJUSTMENT) {0.2}
+
set ::env(FP_IO_VEXTEND) {6}
set ::env(FP_IO_HEXTEND) {6}
# helps in anteena fix
-set ::env(USE_ARC_ANTENNA_CHECK) "0"
+set ::env(USE_ARC_ANTENNA_CHECK) "1"
set ::env(FP_IO_VEXTEND) 4
set ::env(FP_IO_HEXTEND) 4
diff --git a/openlane/pinmux_top/pin_order.cfg b/openlane/pinmux_top/pin_order.cfg
index 6dc053a..bbb7284 100644
--- a/openlane/pinmux_top/pin_order.cfg
+++ b/openlane/pinmux_top/pin_order.cfg
@@ -100,6 +100,22 @@
#W
soft_irq
+irq_lines\[31\]
+irq_lines\[30\]
+irq_lines\[29\]
+irq_lines\[28\]
+irq_lines\[27\]
+irq_lines\[26\]
+irq_lines\[25\]
+irq_lines\[24\]
+irq_lines\[23\]
+irq_lines\[22\]
+irq_lines\[21\]
+irq_lines\[20\]
+irq_lines\[19\]
+irq_lines\[18\]
+irq_lines\[17\]
+irq_lines\[16\]
irq_lines\[15\]
irq_lines\[14\]
irq_lines\[13\]
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index c58574a..b82a6da 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -51,7 +51,7 @@
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=4\
- CH_DATA_WD=37 \
+ CH_DATA_WD=53 \
"
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index 2d8237e..4bf2c2b 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -147,7 +147,23 @@
#W
-ch_data_out\[36\] 000 0 2
+ch_data_out\[52\] 000 0 2
+ch_data_out\[51\]
+ch_data_out\[50\]
+ch_data_out\[49\]
+ch_data_out\[48\]
+ch_data_out\[47\]
+ch_data_out\[46\]
+ch_data_out\[45\]
+ch_data_out\[44\]
+ch_data_out\[43\]
+ch_data_out\[42\]
+ch_data_out\[41\]
+ch_data_out\[40\]
+ch_data_out\[39\]
+ch_data_out\[38\]
+ch_data_out\[37\]
+ch_data_out\[36\]
ch_data_out\[35\]
ch_data_out\[34\]
ch_data_out\[33\]
@@ -705,7 +721,23 @@
s1_wbd_ack_i
s1_wbd_cyc_o
-ch_data_in\[36\] 1500 0 2
+ch_data_in\[52\] 1500 0 2
+ch_data_in\[51\]
+ch_data_in\[50\]
+ch_data_in\[49\]
+ch_data_in\[48\]
+ch_data_in\[47\]
+ch_data_in\[46\]
+ch_data_in\[45\]
+ch_data_in\[44\]
+ch_data_in\[43\]
+ch_data_in\[42\]
+ch_data_in\[41\]
+ch_data_in\[40\]
+ch_data_in\[39\]
+ch_data_in\[38\]
+ch_data_in\[37\]
+ch_data_in\[36\]
ch_data_in\[35\]
ch_data_in\[34\]
ch_data_in\[33\]
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl
index ea5b60a..faaab7a 100644
--- a/openlane/ycr_core_top/config.tcl
+++ b/openlane/ycr_core_top/config.tcl
@@ -74,9 +74,9 @@
## Floorplan
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 540 950 "
+set ::env(DIE_AREA) "0 0 550 950 "
-set ::env(PL_TARGET_DENSITY) 0.43
+set ::env(PL_TARGET_DENSITY) 0.50
set ::env(CELL_PAD) "4"
## Routing
diff --git a/openlane/ycr_core_top/pin_order.cfg b/openlane/ycr_core_top/pin_order.cfg
index 79b2c6f..8fc1648 100644
--- a/openlane/ycr_core_top/pin_order.cfg
+++ b/openlane/ycr_core_top/pin_order.cfg
@@ -296,6 +296,22 @@
core_mtimer_val_i\[1\]
core_mtimer_val_i\[0\]
+core_irq_lines_i\[31\]
+core_irq_lines_i\[30\]
+core_irq_lines_i\[29\]
+core_irq_lines_i\[28\]
+core_irq_lines_i\[27\]
+core_irq_lines_i\[26\]
+core_irq_lines_i\[25\]
+core_irq_lines_i\[24\]
+core_irq_lines_i\[23\]
+core_irq_lines_i\[22\]
+core_irq_lines_i\[21\]
+core_irq_lines_i\[20\]
+core_irq_lines_i\[19\]
+core_irq_lines_i\[18\]
+core_irq_lines_i\[17\]
+core_irq_lines_i\[16\]
core_irq_lines_i\[15\]
core_irq_lines_i\[14\]
core_irq_lines_i\[13\]
diff --git a/openlane/ycr_iconnect/pin_order.cfg b/openlane/ycr_iconnect/pin_order.cfg
index 0a02c62..2ecb2b2 100644
--- a/openlane/ycr_iconnect/pin_order.cfg
+++ b/openlane/ycr_iconnect/pin_order.cfg
@@ -423,6 +423,22 @@
core0_timer_val\[1\]
core0_timer_val\[0\]
+core0_irq_lines\[31\]
+core0_irq_lines\[30\]
+core0_irq_lines\[29\]
+core0_irq_lines\[28\]
+core0_irq_lines\[27\]
+core0_irq_lines\[26\]
+core0_irq_lines\[25\]
+core0_irq_lines\[24\]
+core0_irq_lines\[23\]
+core0_irq_lines\[22\]
+core0_irq_lines\[21\]
+core0_irq_lines\[20\]
+core0_irq_lines\[19\]
+core0_irq_lines\[18\]
+core0_irq_lines\[17\]
+core0_irq_lines\[16\]
core0_irq_lines\[15\]
core0_irq_lines\[14\]
core0_irq_lines\[13\]
@@ -800,6 +816,23 @@
riscv_debug\[1\]
riscv_debug\[0\]
+#N
+core_irq_lines_i\[31\]
+core_irq_lines_i\[30\]
+core_irq_lines_i\[29\]
+core_irq_lines_i\[28\]
+core_irq_lines_i\[27\]
+core_irq_lines_i\[26\]
+core_irq_lines_i\[25\]
+core_irq_lines_i\[24\]
+core_irq_lines_i\[23\]
+core_irq_lines_i\[22\]
+core_irq_lines_i\[21\]
+core_irq_lines_i\[20\]
+core_irq_lines_i\[19\]
+core_irq_lines_i\[18\]
+core_irq_lines_i\[17\]
+core_irq_lines_i\[16\]
core_irq_lines_i\[15\]
core_irq_lines_i\[14\]
core_irq_lines_i\[13\]
diff --git a/verilog/dv/arduino_i2c_scaner/Makefile b/verilog/dv/arduino_i2c_scaner/Makefile
index e6d5947..7688c67 100644
--- a/verilog/dv/arduino_i2c_scaner/Makefile
+++ b/verilog/dv/arduino_i2c_scaner/Makefile
@@ -52,9 +52,8 @@
vvp: ${PATTERN:=.vvp}
%.vvp: %_tb.v
- ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/Wire ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
- ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/Wire -I${RISCDUINO_BOARD}/libraries/Wire/utility ${RISCDUINO_BOARD}/libraries/Wire/Wire.cpp -o Wire.cpp.o
- ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/Wire -I${RISCDUINO_BOARD}/libraries/Wire/utility ${RISCDUINO_BOARD}/libraries/Wire/utility/twi.c -o twi.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/Wire/src ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/Wire/src -I${RISCDUINO_BOARD}/libraries/Wire/src/utility ${RISCDUINO_BOARD}/libraries/Wire/src/Wire.cpp -o Wire.cpp.o
${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
@@ -99,7 +98,7 @@
${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o
${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o
- ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o Wire.cpp.o twi.c.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+ ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o Wire.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump
diff --git a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino.cpp b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino.cpp
index dc656cb..1900e1f 100644
--- a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino.cpp
+++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino.cpp
@@ -45,7 +45,7 @@
Serial.println("Scanning...");
- for (byte address = 1; address < 127; ++address) {
+ for (byte address = 1; address < 32; ++address) {
// The i2c_scanner uses the return value of
// the Wire.endTransmission to see if
// a device did acknowledge to the address.
@@ -67,6 +67,13 @@
Serial.print("0");
}
Serial.println(address, HEX);
+ } else {
+ Serial.print("No I2C device found at address 0x");
+ if (address < 16) {
+ Serial.print("0");
+ }
+ Serial.println(address, HEX);
+
}
}
if (nDevices == 0) {
diff --git a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
index 1ed24fc..71a8371 100644
--- a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
+++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
@@ -151,6 +151,7 @@
$dumpvars(0, arduino_i2c_scaner_tb.u_top.u_riscv_top.u_intf);
$dumpvars(0, arduino_i2c_scaner_tb.u_top.u_uart_i2c_usb_spi.u_uart0_core);
$dumpvars(0, arduino_i2c_scaner_tb.u_top.u_uart_i2c_usb_spi.u_i2cm);
+ $dumpvars(0, arduino_i2c_scaner_tb.u_top.u_pinmux);
end
`endif
@@ -208,16 +209,16 @@
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
end else if(d_risc_id == 2) begin
$display("STATUS: Working with Risc core 2");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
end else if(d_risc_id == 3) begin
$display("STATUS: Working with Risc core 3");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
end
repeat (100) @(posedge clock); // wait for Processor Get Ready
@@ -227,6 +228,12 @@
tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
uart_stick_parity, uart_timeout, uart_divisor);
+ u_i2c_slave_0.debug = 0; // disable i2c bfm debug message
+ u_i2c_slave_1.debug = 0; // disable i2c bfm debug message
+ u_i2c_slave_2.debug = 0; // disable i2c bfm debug message
+ u_i2c_slave_3.debug = 0; // disable i2c bfm debug message
+ u_i2c_slave_4.debug = 0; // disable i2c bfm debug message
+
repeat (45000) @(posedge clock); // wait for Processor Get Ready
flag = 0;
check_sum = 0;
@@ -244,7 +251,7 @@
end
end
begin
- repeat (200000) @(posedge clock); // wait for Processor Get Ready
+ repeat (800000) @(posedge clock); // wait for Processor Get Ready
end
join_any
@@ -255,25 +262,24 @@
$display("Total Rx Char: %d Check Sum : %x ",uart_rx_nu, check_sum);
// Check
- // if all the 102 byte received
+ // if all the byte received
// if no error
- if(uart_rx_nu != 102) test_fail = 1;
- if(check_sum != 32'h1fab) test_fail = 1;
- if(tb_uart.err_cnt != 0) test_fail = 1;
+ if(uart_rx_nu != 1181) test_fail = 1;
+ if(check_sum != 32'h000170c9) test_fail = 1;
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone String (GL) Passed");
+ $display("Monitor: Standalone i2c scanner (GL) Passed");
`else
- $display("Monitor: Standalone String (RTL) Passed");
+ $display("Monitor: Standalone i2c scanner (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone String (GL) Failed");
+ $display("Monitor: Standalone i2c scanner (GL) Failed");
`else
- $display("Monitor: Standalone String (RTL) Failed");
+ $display("Monitor: Standalone i2c scanner (RTL) Failed");
`endif
end
$display("###################################################");
@@ -340,7 +346,27 @@
pullup p2(sda); // pullup sda line
-i2c_slave_model #(.I2C_ADR(7'h4)) u_i2c_slave (
+i2c_slave_model #(.I2C_ADR(7'h4)) u_i2c_slave_0 (
+ .scl (scl),
+ .sda (sda)
+ );
+
+i2c_slave_model #(.I2C_ADR(7'h8)) u_i2c_slave_1 (
+ .scl (scl),
+ .sda (sda)
+ );
+
+i2c_slave_model #(.I2C_ADR(7'h10)) u_i2c_slave_2 (
+ .scl (scl),
+ .sda (sda)
+ );
+
+i2c_slave_model #(.I2C_ADR(7'h11)) u_i2c_slave_3 (
+ .scl (scl),
+ .sda (sda)
+ );
+
+i2c_slave_model #(.I2C_ADR(7'h13)) u_i2c_slave_4 (
.scl (scl),
.sda (sda)
);
diff --git a/verilog/dv/arduino_i2c_wr_rd/Makefile b/verilog/dv/arduino_i2c_wr_rd/Makefile
new file mode 100644
index 0000000..8c362aa
--- /dev/null
+++ b/verilog/dv/arduino_i2c_wr_rd/Makefile
@@ -0,0 +1,141 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = arduino_i2c_wr_rd
+
+all: ${PATTERN:=.vcd}
+
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/Wire/src ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/Wire/src -I${RISCDUINO_BOARD}/libraries/Wire/src/utility ${RISCDUINO_BOARD}/libraries/Wire/src/Wire.cpp -o Wire.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o
+ ${GCC_PREFIX}-ar rcs core.a Print.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a UARTClass.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WInterrupts.c.o
+ ${GCC_PREFIX}-ar rcs core.a WMath.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WString.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a abi.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a fe300prci_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a plic_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a entry.S.o
+ ${GCC_PREFIX}-ar rcs core.a hooks.c.o
+ ${GCC_PREFIX}-ar rcs core.a init.S.o
+ ${GCC_PREFIX}-ar rcs core.a itoa.c.o
+ ${GCC_PREFIX}-ar rcs core.a main.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a malloc.c.o
+ ${GCC_PREFIX}-ar rcs core.a new.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a sbrk.c.o
+ ${GCC_PREFIX}-ar rcs core.a start.S.o
+ ${GCC_PREFIX}-ar rcs core.a wiring.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_analog.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o
+ ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o Wire.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
+ ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump
+ rm *.o *.a
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ endif
+else
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd.ino b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd.ino
new file mode 100644
index 0000000..158e3f1
--- /dev/null
+++ b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd.ino
@@ -0,0 +1,50 @@
+// --------------------------------------
+// I2C Write and Reading to Memory
+// https://microchipdeveloper.com/i2c:sequential-read
+// --------------------------------------
+
+#include <Wire.h>
+
+void setup() {
+ Wire.begin();
+
+ Serial.begin(9600);
+ while (!Serial); // Leonardo: wait for Serial Monitor
+ Serial.println("\nI2C Write Read");
+}
+
+void loop() {
+
+ // step 1: instruct sensor to read echoes
+ Wire.beginTransmission(0x4); // transmit to device #4 (0x0x4)
+ Wire.write(byte(0x02)); // sets memory pointer (0x02)
+ Wire.write(byte(0x11)); // Write Location-0: 0x11
+ Wire.write(byte(0x22)); // Write Location-0: 0x22
+ Wire.write(byte(0x33)); // Write Location-0: 0x33
+ Wire.write(byte(0x44)); // Write Location-0: 0x44
+ Wire.write(byte(0x55)); // Write Location-0: 0x55
+ Wire.write(byte(0x66)); // Write Location-0: 0x66
+ Wire.write(byte(0x77)); // Write Location-0: 0x77
+ Wire.write(byte(0x88)); // Write Location-0: 0x88
+ Wire.endTransmission(); // stop transmitting
+
+ // step 2: Reset the the memory pointer
+ Wire.beginTransmission(0x4); // transmit to device #4 (0x4)
+ Wire.write(byte(0x02)); // sets memory pointer (0x02)
+ Wire.endTransmission(); // stop transmitting
+
+ // step 3: request reading from sensor
+ Wire.requestFrom(0x4, 8); // request 8 bytes from slave device #4
+
+ // step 4: receive reading from sensor
+
+ Serial.println("\nRead Back Data:");
+ while(Wire.available()) // slave may send less than requested
+ {
+ char c = Wire.read(); // receive a byte as character
+ Serial.println(c,HEX); // print the character
+ }
+
+
+ delay(5000); // Wait 5 seconds for next scan
+}
diff --git a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd.ino.cpp b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd.ino.cpp
new file mode 100644
index 0000000..92e1de1
--- /dev/null
+++ b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd.ino.cpp
@@ -0,0 +1,94 @@
+// --------------------------------------
+// I2C Write and Reading to Memory
+// https://microchipdeveloper.com/i2c:sequential-read
+// --------------------------------------
+#include <Arduino.h>
+
+#include <Wire.h>
+
+void setup();
+void loop();
+void setup() {
+ Wire.begin();
+
+ Serial.begin(1152000);
+ while (!Serial); // Leonardo: wait for Serial Monitor
+ Serial.println("\nI2C Write Read");
+}
+
+void loop() {
+
+ //-----------------------------
+ // Write & Read to Device #4
+ //------------------------------
+ // step 1: instruct sensor to read echoes
+ Wire.beginTransmission(0x4); // transmit to device #4 (0x0x4)
+ Wire.write(byte(0x02)); // sets memory pointer (0x02)
+ Wire.write(byte(0x11)); // Write Location-0: 0x11
+ Wire.write(byte(0x22)); // Write Location-0: 0x22
+ Wire.write(byte(0x33)); // Write Location-0: 0x33
+ Wire.write(byte(0x44)); // Write Location-0: 0x44
+ Wire.write(byte(0x55)); // Write Location-0: 0x55
+ Wire.write(byte(0x66)); // Write Location-0: 0x66
+ Wire.write(byte(0x77)); // Write Location-0: 0x77
+ Wire.write(byte(0x88)); // Write Location-0: 0x88
+ Wire.endTransmission(); // stop transmitting
+
+ // step 2: Reset the the memory pointer
+ Wire.beginTransmission(0x4); // transmit to device #4 (0x4)
+ Wire.write(byte(0x02)); // sets memory pointer (0x02)
+ Wire.endTransmission(); // stop transmitting
+
+ // step 3: request reading from sensor
+ Wire.requestFrom(0x4, 8); // request 8 bytes from slave device #4
+ Wire.available();
+
+ // step 4: receive reading from sensor
+
+ Serial.println("Read Back Data from Port-0x04:");
+ while(Wire.available()) // slave may send less than requested
+ {
+ uint8_t c = Wire.read(); // receive a byte as character
+ Serial.println(c,HEX); // print the character
+ }
+ Wire.endTransmission(); // stop transmitting
+
+ //-----------------------------
+ // Write & Read to Device #4
+ //------------------------------
+ // step 1: instruct sensor to read echoes
+ Wire.beginTransmission(0x10); // transmit to device #10 (0x10)
+ Wire.write(byte(0x20)); // sets memory pointer (0x20)
+ Wire.write(byte(0x01)); // Write Location-0: 0x11
+ Wire.write(byte(0x02)); // Write Location-0: 0x22
+ Wire.write(byte(0x03)); // Write Location-0: 0x33
+ Wire.write(byte(0x04)); // Write Location-0: 0x44
+ Wire.write(byte(0x05)); // Write Location-0: 0x55
+ Wire.write(byte(0x06)); // Write Location-0: 0x66
+ Wire.write(byte(0x07)); // Write Location-0: 0x77
+ Wire.write(byte(0x08)); // Write Location-0: 0x88
+ Wire.endTransmission(); // stop transmitting
+
+
+ // step 2: Reset the the memory pointer
+ Wire.beginTransmission(0x10); // transmit to device #10 (0x10)
+ Wire.write(byte(0x20)); // sets memory pointer (0x10)
+ Wire.endTransmission(); // stop transmitting
+
+ // step 3: request reading from sensor
+ Wire.requestFrom(0x10, 8); // request 8 bytes from slave device #4
+ Wire.available();
+
+ // step 4: receive reading from sensor
+
+ Serial.println("\nRead Back Data from Port-0x10:");
+ while(Wire.available()) // slave may send less than requested
+ {
+ uint8_t c = Wire.read(); // receive a byte as character
+ Serial.println(c,HEX); // print the character
+ }
+ Wire.endTransmission(); // stop transmitting
+
+ delay(5000); // Wait 5 seconds for next scan
+}
+
diff --git a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
new file mode 100644
index 0000000..8d3965e
--- /dev/null
+++ b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
@@ -0,0 +1,551 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Standalone User validation Test bench ////
+//// ////
+//// This file is part of the riscdunio cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
+//// ////
+//// Description ////
+//// This is a standalone test bench to validate the ////
+//// Digital core. ////
+//// This test bench to valid Arduino example: ////
+//// <example><Wire><i2c_scanner> ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
+//// ////
+//// Revision : ////
+//// 0.1 - 29th July 2022, Dinesh A ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+`include "uart_agent.v"
+`include "i2c_slave_model.v"
+
+`define TB_HEX "arduino_i2c_wr_rd.ino.hex"
+`define TB_TOP arduino_i2c_wr_rd_tb
+module `TB_TOP;
+ reg clock;
+ reg wb_rst_i;
+ reg power1, power2;
+ reg power3, power4;
+
+ reg wbd_ext_cyc_i; // strobe/request
+ reg wbd_ext_stb_i; // strobe/request
+ reg [31:0] wbd_ext_adr_i; // address
+ reg wbd_ext_we_i; // write
+ reg [31:0] wbd_ext_dat_i; // data output
+ reg [3:0] wbd_ext_sel_i; // byte enable
+
+ wire [31:0] wbd_ext_dat_o; // data input
+ wire wbd_ext_ack_o; // acknowlegement
+ wire wbd_ext_err_o; // error
+
+ // User I/O
+ wire [37:0] io_oeb;
+ wire [37:0] io_out;
+ wire [37:0] io_in;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+ wire [7:0] mprj_io_0;
+ reg test_fail;
+ reg [31:0] read_data;
+ //----------------------------------
+ // Uart Configuration
+ // ---------------------------------
+ reg [1:0] uart_data_bit ;
+ reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit;
+ reg uart_stick_parity ; // 1: force even parity
+ reg uart_parity_en ; // parity enable
+ reg uart_even_odd_parity ; // 0: odd parity; 1: even parity
+
+ reg [7:0] uart_data ;
+ reg [15:0] uart_divisor ; // divided by n * 16
+ reg [15:0] uart_timeout ;// wait time limit
+
+ reg [15:0] uart_rx_nu ;
+ reg [15:0] uart_tx_nu ;
+ reg [7:0] uart_write_data [0:39];
+ reg uart_fifo_enable ; // fifo mode disable
+ reg flag ;
+ reg compare_start ; // User Need to make sure that compare start match with RiscV core completing initial booting
+
+ reg [31:0] check_sum ;
+
+ integer d_risc_id;
+
+ integer i,j;
+
+
+
+
+ // 50Mhz CLock
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ flag = 0;
+ compare_start = 0;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ end
+
+ `ifdef WFDUMP
+ initial begin
+ $dumpfile("simx.vcd");
+ $dumpvars(3, `TB_TOP);
+ $dumpvars(0, `TB_TOP.u_top.u_riscv_top.i_core_top_0);
+ $dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_connect);
+ $dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_intf);
+ $dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_uart0_core);
+ $dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_i2cm);
+ $dumpvars(0, `TB_TOP.u_top.u_pinmux);
+ end
+ `endif
+
+ /*************************************************************************
+ * This is Baud Rate to clock divider conversion for Test Bench
+ * Note: DUT uses 16x baud clock, where are test bench uses directly
+ * baud clock, Due to 16x Baud clock requirement at RTL, there will be
+ * some resolution loss, we expect at lower baud rate this resolution
+ * loss will be less. For Quick simulation perpose higher baud rate used
+ * *************************************************************************/
+ task tb_set_uart_baud;
+ input [31:0] ref_clk;
+ input [31:0] baud_rate;
+ output [31:0] baud_div;
+ reg [31:0] baud_div;
+ begin
+ // for 230400 Baud = (50Mhz/230400) = 216.7
+ baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
+ // Baud 16x = 216/16 = 13
+ baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
+ // Test bench baud clock , 16x of above value
+ // 13 * 16 = 208,
+ // (Note if you see original value was 216, now it's 208 )
+ baud_div = baud_div * 16;
+ // Test bench half cycle counter to toggle it
+ // 208/2 = 104
+ baud_div = baud_div/2;
+ //As counter run's from 0 , substract from 1
+ baud_div = baud_div-1;
+ end
+ endtask
+
+
+ initial begin
+ uart_data_bit = 2'b11;
+ uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
+ uart_stick_parity = 0; // 1: force even parity
+ uart_parity_en = 0; // parity enable
+ uart_even_odd_parity = 1; // 0: odd parity; 1: even parity
+ tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
+ uart_timeout = 20000;// wait time limit
+ uart_fifo_enable = 0; // fifo mode disable
+
+ $value$plusargs("risc_core_id=%d", d_risc_id);
+
+ #200; // Wait for reset removal
+ repeat (10) @(posedge clock);
+ $display("Monitor: Standalone User Risc Boot Test Started");
+
+ // Remove Wb Reset
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+ repeat (2) @(posedge clock);
+ #1;
+ // Remove all the reset
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ end else if(d_risc_id == 1) begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+ end else if(d_risc_id == 2) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+ end else if(d_risc_id == 3) begin
+ $display("STATUS: Working with Risc core 3");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+ end
+
+ repeat (100) @(posedge clock); // wait for Processor Get Ready
+
+ tb_uart.debug_mode = 0; // disable debug display
+ tb_uart.uart_init;
+ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
+ uart_stick_parity, uart_timeout, uart_divisor);
+
+ u_i2c_slave_0.debug = 1; // disable i2c bfm debug message
+ u_i2c_slave_1.debug = 1; // disable i2c bfm debug message
+
+ repeat (45000) @(posedge clock); // wait for Processor Get Ready
+ flag = 0;
+ check_sum = 0;
+ compare_start = 1;
+
+ fork
+ begin
+ while(flag == 0)
+ begin
+ tb_uart.read_char(read_data,flag);
+ if(flag == 0) begin
+ $write ("%c",read_data);
+ check_sum = check_sum+read_data;
+ end
+ end
+ end
+ begin
+ repeat (250000) @(posedge clock); // wait for Processor Get Ready
+ end
+ join_any
+
+ #100
+ tb_uart.report_status(uart_rx_nu, uart_tx_nu);
+
+ test_fail = 0;
+
+ $display("Total Rx Char: %d Check Sum : %x ",uart_rx_nu, check_sum);
+ // Check
+ // if all the byte received
+ // if no error
+ if(uart_rx_nu != 138) test_fail = 1;
+ if(check_sum != 32'h00001e9d) test_fail = 1;
+
+
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: Standalone i2c scanner (GL) Passed");
+ `else
+ $display("Monitor: Standalone i2c scanner (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: Standalone i2c scanner (GL) Failed");
+ `else
+ $display("Monitor: Standalone i2c scanner (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ $finish;
+ end
+
+ initial begin
+ wb_rst_i <= 1'b1;
+ #100;
+ wb_rst_i <= 1'b0; // Release reset
+ end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+ .vccd1(USER_VDD1V8), // User area 1 1.8V supply
+ .vssd1(VSS), // User area 1 digital ground
+`endif
+ .wb_clk_i (clock), // System clock
+ .user_clock2 (1'b1), // Real-time clock
+ .wb_rst_i (wb_rst_i), // Regular Reset signal
+
+ .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
+ .wbs_stb_i (wbd_ext_stb_i), // strobe/request
+ .wbs_adr_i (wbd_ext_adr_i), // address
+ .wbs_we_i (wbd_ext_we_i), // write
+ .wbs_dat_i (wbd_ext_dat_i), // data output
+ .wbs_sel_i (wbd_ext_sel_i), // byte enable
+
+ .wbs_dat_o (wbd_ext_dat_o), // data input
+ .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
+
+
+ // Logic Analyzer Signals
+ .la_data_in ('1) ,
+ .la_data_out (),
+ .la_oenb ('0),
+
+
+ // IOs
+ .io_in (io_in) ,
+ .io_out (io_out) ,
+ .io_oeb (io_oeb) ,
+
+ .user_irq ()
+
+);
+// SSPI Slave I/F
+assign io_in[0] = 1'b1; // RESET
+assign io_in[16] = 1'b0 ; // SPIS SCK
+
+//---------------------------
+// I2C
+// --------------------------
+tri scl,sda;
+
+assign sda = (io_oeb[22] == 1'b0) ? io_out[22] : 1'bz;
+assign scl = (io_oeb[23] == 1'b0) ? io_out[23]: 1'bz;
+assign io_in[22] = sda;
+assign io_in[23] = scl;
+
+pullup p1(scl); // pullup scl line
+pullup p2(sda); // pullup sda line
+
+
+i2c_slave_model #(.I2C_ADR(7'h4)) u_i2c_slave_0 (
+ .scl (scl),
+ .sda (sda)
+ );
+
+i2c_slave_model #(.I2C_ADR(7'h10)) u_i2c_slave_1 (
+ .scl (scl),
+ .sda (sda)
+ );
+
+`ifndef GL // Drive Power for Hold Fix Buf
+ // All standard cell need power hook-up for functionality work
+ initial begin
+
+ end
+`endif
+
+//------------------------------------------------------
+// Integrate the Serial flash with qurd support to
+// user core using the gpio pads
+// ----------------------------------------------------
+
+ wire flash_clk = io_out[24];
+ wire flash_csb = io_out[25];
+ // Creating Pad Delay
+ wire #1 io_oeb_29 = io_oeb[29];
+ wire #1 io_oeb_30 = io_oeb[30];
+ wire #1 io_oeb_31 = io_oeb[31];
+ wire #1 io_oeb_32 = io_oeb[32];
+ tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
+
+ assign io_in[29] = flash_io0;
+ assign io_in[30] = flash_io1;
+ assign io_in[31] = flash_io2;
+ assign io_in[32] = flash_io3;
+
+ // Quard flash
+ s25fl256s #(.mem_file_name(`TB_HEX),
+ .otp_file_name("none"),
+ .TimingModel("S25FL512SAGMFI010_F_30pF"))
+ u_spi_flash_256mb (
+ // Data Inputs/Outputs
+ .SI (flash_io0),
+ .SO (flash_io1),
+ // Controls
+ .SCK (flash_clk),
+ .CSNeg (flash_csb),
+ .WPNeg (flash_io2),
+ .HOLDNeg (flash_io3),
+ .RSTNeg (!wb_rst_i)
+
+ );
+
+
+//---------------------------
+// UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd = io_out[2];
+assign io_in[1] = uart_rxd ;
+
+uart_agent tb_uart(
+ .mclk (clock ),
+ .txd (uart_rxd ),
+ .rxd (uart_txd )
+ );
+
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h1; // write
+ wbd_ext_dat_i =data; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ if(data !== cmp_data) begin
+ $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+ test_fail = 1;
+ end else begin
+ $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
+ end
+ repeat (2) @(posedge clock);
+end
+endtask
+
+`ifdef GL
+
+wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
+
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+ if(`RISC_CORE.wbd_imem_ack_i)
+ $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+ if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+ if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+endmodule
+`include "s25fl256s.sv"
+`default_nettype wire
diff --git a/verilog/dv/arduino_ws281x/Makefile b/verilog/dv/arduino_ws281x/Makefile
new file mode 100644
index 0000000..8d88be5
--- /dev/null
+++ b/verilog/dv/arduino_ws281x/Makefile
@@ -0,0 +1,148 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = arduino_ws281x
+
+all: ${PATTERN:=.vcd}
+
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${PATTERN}.ino.cpp -I${RISCDUINO_BOARD}/libraries/WS281X/src -o ${PATTERN}.ino.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o
+
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/TIMERClass.cpp -o TIMERClass.cpp.o
+
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/WS281X/src ${RISCDUINO_BOARD}/libraries/WS281X/src/WS281X.cpp -o WS281X.cpp.o
+
+
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o
+ ${GCC_PREFIX}-ar rcs core.a Print.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a UARTClass.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a TIMERClass.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WS281X.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WInterrupts.c.o
+ ${GCC_PREFIX}-ar rcs core.a WMath.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WString.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a abi.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a fe300prci_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a plic_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a entry.S.o
+ ${GCC_PREFIX}-ar rcs core.a hooks.c.o
+ ${GCC_PREFIX}-ar rcs core.a init.S.o
+ ${GCC_PREFIX}-ar rcs core.a itoa.c.o
+ ${GCC_PREFIX}-ar rcs core.a main.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a malloc.c.o
+ ${GCC_PREFIX}-ar rcs core.a new.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a sbrk.c.o
+ ${GCC_PREFIX}-ar rcs core.a start.S.o
+ ${GCC_PREFIX}-ar rcs core.a wiring.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_analog.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o
+ ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
+ ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump
+ rm *.o *.a
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ endif
+else
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/arduino_ws281x/arduino_ws281x.ino b/verilog/dv/arduino_ws281x/arduino_ws281x.ino
new file mode 100644
index 0000000..20517d7
--- /dev/null
+++ b/verilog/dv/arduino_ws281x/arduino_ws281x.ino
@@ -0,0 +1,60 @@
+
+/*
+
+ Analog input, analog output, serial output
+
+ Reads an analog input pin, maps the result to a range from 0 to 255 and uses
+
+ the result to set the pulse width modulation (PWM) of an output pin.
+
+ Also prints the results to the Serial Monitor.
+
+ The circuit:
+
+ - potentiometer connected to analog pin 0.
+
+ Center pin of the potentiometer goes to the analog pin.
+
+ side pins of the potentiometer go to +5V and ground
+
+ - LED connected from digital pin 9 to ground
+
+ created 29 Dec. 2008
+
+ modified 9 Apr 2012
+
+ by Tom Igoe
+
+ This example code is in the public domain.
+
+ http://www.arduino.cc/en/Tutorial/AnalogInOutSerial
+
+*/
+
+#include"Arduino.h"
+// These constants won't change. They're used to give names to the pins used:
+
+
+int but1=2;
+int but2=3;
+
+
+void setup() {
+
+ ws281x.begin(WS2811_LOW_SPEED);
+ ws281x.enable(2);
+}
+
+void loop() {
+
+ ws281x.write(2, 0x112233);
+ ws281x.write(2, 0x223344);
+ ws281x.write(2, 0x334455);
+ ws281x.write(2, 0x445566);
+ ws281x.write(2, 0x556677);
+ ws281x.write(2, 0x667788);
+ ws281x.write(2, 0x778899);
+ delay(1);
+}
+
+
diff --git a/verilog/dv/arduino_ws281x/arduino_ws281x.ino.cpp b/verilog/dv/arduino_ws281x/arduino_ws281x.ino.cpp
new file mode 100644
index 0000000..db5dc4a
--- /dev/null
+++ b/verilog/dv/arduino_ws281x/arduino_ws281x.ino.cpp
@@ -0,0 +1,135 @@
+#line 1 "/home/dinesha/Arduino/ws281x_example1/ws281x_example1.ino"
+
+/*
+
+ Analog input, analog output, serial output
+
+ Reads an analog input pin, maps the result to a range from 0 to 255 and uses
+
+ the result to set the pulse width modulation (PWM) of an output pin.
+
+ Also prints the results to the Serial Monitor.
+
+ The circuit:
+
+ - potentiometer connected to analog pin 0.
+
+ Center pin of the potentiometer goes to the analog pin.
+
+ side pins of the potentiometer go to +5V and ground
+
+ - LED connected from digital pin 9 to ground
+
+ created 29 Dec. 2008
+
+ modified 9 Apr 2012
+
+ by Tom Igoe
+
+ This example code is in the public domain.
+
+ http://www.arduino.cc/en/Tutorial/AnalogInOutSerial
+
+*/
+
+#include"Arduino.h"
+#include"WS281X.h"
+// These constants won't change. They're used to give names to the pins used:
+
+
+int port0 = 2;
+int port1 = 3;
+int port2 = 5;
+int port3 = 9;
+
+
+void setup();
+void loop();
+void setup() {
+
+ ws281x.begin(WS2811_HIGH_SPEED);
+
+ // Enable WS_281X PORT-0
+ ws281x.enable(port0);
+ ws281x.write(port0, 0x112233);
+ ws281x.write(port0, 0x223344);
+ ws281x.write(port0, 0x334455);
+ ws281x.write(port0, 0x445566);
+ ws281x.write(port0, 0x556677);
+ ws281x.write(port0, 0x667788);
+ ws281x.write(port0, 0x778899);
+ ws281x.write(port0, 0x8899AA);
+ ws281x.write(port0, 0x99AABB);
+ ws281x.write(port0, 0xAABBCC);
+ ws281x.write(port0, 0xBBCCDD);
+ ws281x.write(port0, 0xCCDDEE);
+ ws281x.write(port0, 0xDDEEFF);
+ ws281x.write(port0, 0xEEFF00);
+ ws281x.write(port0, 0xFF0011);
+ ws281x.write(port0, 0x001122);
+
+// Enable WS_281X PORT-1
+ ws281x.enable(port1);
+ ws281x.write(port1, 0x010203);
+ ws281x.write(port1, 0x020304);
+ ws281x.write(port1, 0x030405);
+ ws281x.write(port1, 0x040506);
+ ws281x.write(port1, 0x050607);
+ ws281x.write(port1, 0x060708);
+ ws281x.write(port1, 0x070809);
+ ws281x.write(port1, 0x08090A);
+ ws281x.write(port1, 0x090A0B);
+ ws281x.write(port1, 0x0A0B0C);
+ ws281x.write(port1, 0x0B0C0D);
+ ws281x.write(port1, 0x0C0D0E);
+ ws281x.write(port1, 0x0D0E0F);
+ ws281x.write(port1, 0x0E0F00);
+ ws281x.write(port1, 0x0F0001);
+ ws281x.write(port1, 0x000102);
+
+// Enable WS_281X PORT-2
+ ws281x.enable(port2);
+ ws281x.write(port2, 0x102030);
+ ws281x.write(port2, 0x203040);
+ ws281x.write(port2, 0x304050);
+ ws281x.write(port2, 0x405060);
+ ws281x.write(port2, 0x506070);
+ ws281x.write(port2, 0x607080);
+ ws281x.write(port2, 0x708090);
+ ws281x.write(port2, 0x8090A0);
+ ws281x.write(port2, 0x90A0B0);
+ ws281x.write(port2, 0xA0B0C0);
+ ws281x.write(port2, 0xB0C0D0);
+ ws281x.write(port2, 0xC0D0E0);
+ ws281x.write(port2, 0xD0E0F0);
+ ws281x.write(port2, 0xE0F000);
+ ws281x.write(port2, 0xF00010);
+ ws281x.write(port2, 0x001020);
+
+// Enable WS_281X PORT-3
+ ws281x.enable(port3);
+ ws281x.write(port3, 0x012345);
+ ws281x.write(port3, 0x123456);
+ ws281x.write(port3, 0x234567);
+ ws281x.write(port3, 0x345678);
+ ws281x.write(port3, 0x456789);
+ ws281x.write(port3, 0x56789A);
+ ws281x.write(port3, 0x6789AB);
+ ws281x.write(port3, 0x789ABC);
+ ws281x.write(port3, 0x89ABCD);
+ ws281x.write(port3, 0x9ABCDE);
+ ws281x.write(port3, 0xABCDEF);
+ ws281x.write(port3, 0xBCDEF0);
+ ws281x.write(port3, 0xCDEF01);
+ ws281x.write(port3, 0xDEF012);
+ ws281x.write(port3, 0xEF0123);
+ ws281x.write(port3, 0xF01234);
+}
+
+void loop() {
+
+ delay(1);
+}
+
+
+
diff --git a/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v b/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v
new file mode 100644
index 0000000..2746a60
--- /dev/null
+++ b/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v
@@ -0,0 +1,558 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Standalone User validation Test bench ////
+//// ////
+//// This file is part of the riscdunio cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
+//// ////
+//// Description ////
+//// This is a standalone test bench to validate the ////
+//// Digital core. ////
+//// This test bench to validate ws281x driver ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
+//// ////
+//// Revision : ////
+//// 0.1 - 29th July 2022, Dinesh A ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+`include "uart_agent.v"
+`include "bfm_ws281x.sv"
+
+`define TB_HEX "arduino_ws281x.ino.hex"
+`define TB_TOP arduino_ws281x_tb
+
+module `TB_TOP;
+ reg clock;
+ reg wb_rst_i;
+ reg power1, power2;
+ reg power3, power4;
+
+ reg wbd_ext_cyc_i; // strobe/request
+ reg wbd_ext_stb_i; // strobe/request
+ reg [31:0] wbd_ext_adr_i; // address
+ reg wbd_ext_we_i; // write
+ reg [31:0] wbd_ext_dat_i; // data output
+ reg [3:0] wbd_ext_sel_i; // byte enable
+
+ wire [31:0] wbd_ext_dat_o; // data input
+ wire wbd_ext_ack_o; // acknowlegement
+ wire wbd_ext_err_o; // error
+
+ // User I/O
+ wire [37:0] io_oeb;
+ wire [37:0] io_out;
+ wire [37:0] io_in;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+ wire [7:0] mprj_io_0;
+ reg test_fail;
+ reg [31:0] read_data;
+ reg flag ;
+ reg compare_start ; // User Need to make sure that compare start match with RiscV core completing initial booting
+
+ reg [31:0] rx_wcnt ;
+ reg [31:0] check_sum ;
+
+ integer d_risc_id;
+
+ integer i,j;
+
+//-----------------------------------------------
+// WS281X BFM integration
+//----------------------------------------------
+parameter WS2811_LS = 0;
+parameter WS2811_HS = 1;
+parameter WS2812_HS = 2;
+parameter WS2812S_HS = 3;
+parameter WS2812B_HS = 4;
+
+wire [3:0] ws281x_port ;
+reg ws281x_enb ;
+
+
+
+ // 50Mhz CLock
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ flag = 0;
+ compare_start = 0;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ end
+
+ `ifdef WFDUMP
+ initial begin
+ $dumpfile("simx.vcd");
+ $dumpvars(3, `TB_TOP);
+ $dumpvars(0, `TB_TOP.u_top.u_riscv_top);
+ $dumpvars(0, `TB_TOP.u_top.u_pinmux);
+ $dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi);
+ end
+ `endif
+
+
+
+
+/**********************************************************************
+ Arduino Digital PinMapping
+* Pin Mapping Arduino ATMGE CONFIG
+* ATMEGA328 Port caravel Pin Mapping
+* Pin-1 22 PC6/WS[0]/RESET* digital_io[0]
+* Pin-2 0 PD0/WS[0]/RXD[0] digital_io[1]
+* Pin-3 1 PD1/WS[0]/TXD[0] digital_io[2]
+* Pin-4 2 PD2/WS[0]/RXD[1]/INT0 digital_io[3]
+* Pin-5 3 PD3/WS[1]INT1/OC2B(PWM0) digital_io[4]
+* Pin-6 4 PD4/WS[1]TXD[1] digital_io[5]
+* Pin-7 VCC -
+* Pin-8 GND -
+* Pin-9 20 PB6/WS[1]/XTAL1/TOSC1 digital_io[6]
+* Pin-10 21 PB7/WS[1]/XTAL2/TOSC2 digital_io[7]
+* Pin-11 5 PD5/WS[2]/SS[3]/OC0B(PWM1)/T1 digital_io[8]
+* Pin-12 6 PD6/WS[2]/SS[2]/OC0A(PWM2)/AIN0 digital_io[9]/analog_io[2]
+* Pin-13 7 PD7/WS[2]/A1N1 digital_io[10]/analog_io[3]
+* Pin-14 8 PB0/WS[2]/CLKO/ICP1 digital_io[11]
+* Pin-15 9 PB1/WS[3]/SS[1]OC1A(PWM3) digital_io[12]
+* Pin-16 10 PB2/WS[3]/SS[0]/OC1B(PWM4) digital_io[13]
+* Pin-17 11 PB3/WS[3]/MOSI/OC2A(PWM5) digital_io[14]
+* Pin-18 12 PB4/WS[3]/MISO digital_io[15]
+* Pin-19 13 PB5/SCK digital_io[16]
+* Pin-20 AVCC -
+* Pin-21 AREF analog_io[10]
+* Pin-22 GND -
+* Pin-23 14 PC0/ADC0 digital_io[18]/analog_io[11]
+* Pin-24 15 PC1/ADC1 digital_io[19]/analog_io[12]
+* Pin-25 16 PC2/ADC2 digital_io[20]/analog_io[13]
+* Pin-26 17 PC3/ADC3 digital_io[21]/analog_io[14]
+* Pin-27 18 PC4/ADC4/SDA digital_io[22]/analog_io[15]
+* Pin-28 19 PC5/ADC5/SCL digital_io[23]/analog_io[16]
+*****************************************************************************/
+
+
+ initial begin
+
+ ws281x_enb = 0;
+
+ $value$plusargs("risc_core_id=%d", d_risc_id);
+
+ #200; // Wait for reset removal
+ repeat (10) @(posedge clock);
+ $display("Monitor: Standalone User Risc Boot Test Started");
+
+ // Remove Wb Reset
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+ repeat (2) @(posedge clock);
+ #1;
+ // Remove all the reset
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ end else if(d_risc_id == 1) begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+ end else if(d_risc_id == 2) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+ end else if(d_risc_id == 3) begin
+ $display("STATUS: Working with Risc core 3");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+ end
+
+ repeat (100) @(posedge clock); // wait for Processor Get Ready
+
+
+ repeat (40000) @(posedge clock); // wait for Processor Get Ready
+ ws281x_enb = 1;
+ flag = 0;
+ check_sum = 0;
+ compare_start = 1;
+
+ fork
+ begin
+ wait(u_ws281x_port0.rx_wcnt == 16);
+ wait(u_ws281x_port1.rx_wcnt == 16);
+ wait(u_ws281x_port2.rx_wcnt == 16);
+ wait(u_ws281x_port3.rx_wcnt == 16);
+ end
+ begin
+ repeat (300000) @(posedge clock); // wait for Processor Get Ready
+ end
+ join_any
+
+ #1000
+
+ test_fail = 0;
+ rx_wcnt = u_ws281x_port0.rx_wcnt + u_ws281x_port1.rx_wcnt + u_ws281x_port2.rx_wcnt + u_ws281x_port3.rx_wcnt;
+ check_sum = u_ws281x_port0.check_sum + u_ws281x_port1.check_sum + u_ws281x_port2.check_sum + u_ws281x_port3.check_sum;
+
+ $display("Total Rx Cnt: %d Check Sum : %x ",rx_wcnt, check_sum);
+ // Check
+ // if all the 102 byte received
+ // if no error
+ if(rx_wcnt != 64) test_fail = 1;
+ if(check_sum != 32'h2ffe8) test_fail = 1;
+
+
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: Standalone String (GL) Passed");
+ `else
+ $display("Monitor: Standalone String (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: Standalone String (GL) Failed");
+ `else
+ $display("Monitor: Standalone String (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ $finish;
+ end
+
+ initial begin
+ wb_rst_i <= 1'b1;
+ #100;
+ wb_rst_i <= 1'b0; // Release reset
+ end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+ .vccd1(USER_VDD1V8), // User area 1 1.8V supply
+ .vssd1(VSS), // User area 1 digital ground
+`endif
+ .wb_clk_i (clock), // System clock
+ .user_clock2 (1'b1), // Real-time clock
+ .wb_rst_i (wb_rst_i), // Regular Reset signal
+
+ .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
+ .wbs_stb_i (wbd_ext_stb_i), // strobe/request
+ .wbs_adr_i (wbd_ext_adr_i), // address
+ .wbs_we_i (wbd_ext_we_i), // write
+ .wbs_dat_i (wbd_ext_dat_i), // data output
+ .wbs_sel_i (wbd_ext_sel_i), // byte enable
+
+ .wbs_dat_o (wbd_ext_dat_o), // data input
+ .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
+
+
+ // Logic Analyzer Signals
+ .la_data_in ('1) ,
+ .la_data_out (),
+ .la_oenb ('0),
+
+
+ // IOs
+ .io_in (io_in) ,
+ .io_out (io_out) ,
+ .io_oeb (io_oeb) ,
+
+ .user_irq ()
+
+);
+// SSPI Slave I/F
+assign io_in[0] = 1'b1; // RESET
+//assign io_in[16] = 1'b0 ; // SPIS SCK
+
+`ifndef GL // Drive Power for Hold Fix Buf
+ // All standard cell need power hook-up for functionality work
+ initial begin
+
+ end
+`endif
+
+//------------------------------------------------------
+// Integrate the Serial flash with qurd support to
+// user core using the gpio pads
+// ----------------------------------------------------
+
+ wire flash_clk = io_out[24];
+ wire flash_csb = io_out[25];
+ // Creating Pad Delay
+ wire #1 io_oeb_29 = io_oeb[29];
+ wire #1 io_oeb_30 = io_oeb[30];
+ wire #1 io_oeb_31 = io_oeb[31];
+ wire #1 io_oeb_32 = io_oeb[32];
+ tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
+
+ assign io_in[29] = flash_io0;
+ assign io_in[30] = flash_io1;
+ assign io_in[31] = flash_io2;
+ assign io_in[32] = flash_io3;
+
+ // Quard flash
+ s25fl256s #(.mem_file_name(`TB_HEX),
+ .otp_file_name("none"),
+ .TimingModel("S25FL512SAGMFI010_F_30pF"))
+ u_spi_flash_256mb (
+ // Data Inputs/Outputs
+ .SI (flash_io0),
+ .SO (flash_io1),
+ // Controls
+ .SCK (flash_clk),
+ .CSNeg (flash_csb),
+ .WPNeg (flash_io2),
+ .HOLDNeg (flash_io3),
+ .RSTNeg (!wb_rst_i)
+
+ );
+
+
+//-----------------------------------------------
+// WS281X BFM integration
+//----------------------------------------------
+assign ws281x_port[0] = io_out[3];
+
+bfm_ws281x #(
+ .PORT_ID(0),
+ .MODE(WS2811_HS)) u_ws281x_port0(
+ .reset_n (!wb_rst_i ),
+ .clk (clock ),
+ .enb (ws281x_enb ),
+ .rxd (ws281x_port[0])
+ );
+
+//-----------------------------------------------
+// WS281X BFM integration
+//----------------------------------------------
+assign ws281x_port[1] = io_out[4];
+
+bfm_ws281x #(
+ .PORT_ID(1),
+ .MODE(WS2811_HS)) u_ws281x_port1(
+ .reset_n (!wb_rst_i ),
+ .clk (clock ),
+ .enb (ws281x_enb ),
+ .rxd (ws281x_port[1])
+ );
+
+//-----------------------------------------------
+// WS281X BFM integration
+//----------------------------------------------
+assign ws281x_port[2] = io_out[8];
+
+bfm_ws281x #(
+ .PORT_ID(2),
+ .MODE(WS2811_HS)) u_ws281x_port2(
+ .reset_n (!wb_rst_i ),
+ .clk (clock ),
+ .enb (ws281x_enb ),
+ .rxd (ws281x_port[2])
+ );
+
+//-----------------------------------------------
+// WS281X BFM integration
+//----------------------------------------------
+assign ws281x_port[3] = io_out[12];
+
+bfm_ws281x #(
+ .PORT_ID(3),
+ .MODE(WS2811_HS)) u_ws281x_port3(
+ .reset_n (!wb_rst_i ),
+ .clk (clock ),
+ .enb (ws281x_enb ),
+ .rxd (ws281x_port[3])
+ );
+//----------------------------
+// All the task are defined here
+//----------------------------
+
+
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h1; // write
+ wbd_ext_dat_i =data; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ if(data !== cmp_data) begin
+ $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+ test_fail = 1;
+ end else begin
+ $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
+ end
+ repeat (2) @(posedge clock);
+end
+endtask
+
+`ifdef GL
+
+wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
+
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+ if(`RISC_CORE.wbd_imem_ack_i)
+ $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+ if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+ if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+endmodule
+`include "s25fl256s.sv"
+`default_nettype wire
diff --git a/verilog/dv/bfm/bfm_ws281x.sv b/verilog/dv/bfm/bfm_ws281x.sv
new file mode 100644
index 0000000..6caa57c
--- /dev/null
+++ b/verilog/dv/bfm/bfm_ws281x.sv
@@ -0,0 +1,225 @@
+
+`timescale 1 ns / 1 ns
+
+module bfm_ws281x #(
+ parameter PORT_ID = 0,
+ parameter MODE = 0) (
+ input logic reset_n,
+ input logic clk,
+ input logic enb,
+ input logic rxd
+ );
+
+//---------------------------------------------------
+// Parameter decleration
+//---------------------------------------------------
+parameter WS2811_LS = 0;
+parameter WS2811_HS = 1;
+parameter WS2812_HS = 2;
+parameter WS2812S_HS = 3;
+parameter WS2812B_HS = 4;
+
+
+parameter WS281X_LS_PERIOD = 2500 ; // 400Khz - 2.5us
+parameter WS281X_HS_PERIOD = 1250 ; // 800Khz - 1.25us
+
+parameter WS2811_LS_TOH = 500 ;// 0.5us - 500ns
+parameter WS2811_LS_T1H = 1200 ;// 1.2us - 1200ns
+
+parameter WS2811_HS_TOH = 250 ;// 0.25us - 250ns
+parameter WS2811_HS_T1H = 600 ;// 0.6us - 600ns
+
+parameter WS2812_HS_TOH = 350 ;// 0.35us - 350ns
+parameter WS2812_HS_T1H = 700 ;// 0.7us - 700ns
+
+parameter WS2812S_HS_TOH = 350 ;// 0.35us - 350ns
+parameter WS2812S_HS_T1H = 700 ;// 0.7us - 700ns
+
+parameter WS2812B_HS_TOH = 350 ;// 0.35us - 350ns
+parameter WS2812B_HS_T1H = 900 ;// 0.9us - 900ns
+
+parameter WS281X_TOLERENCE = 150 ; // 150ns
+
+parameter WS281X_RST = 50000 ;// 50us - 50000ns
+
+parameter WS281X_PERIOD = (MODE == WS2811_LS) ? WS281X_LS_PERIOD :
+ (MODE == WS2811_HS) ? WS281X_HS_PERIOD :
+ (MODE == WS2812_HS) ? WS281X_HS_PERIOD :
+ (MODE == WS2812S_HS) ? WS281X_HS_PERIOD :
+ (MODE == WS2812B_HS) ? WS281X_HS_PERIOD : WS281X_LS_PERIOD;
+
+parameter WS281X_TOH = (MODE == WS2811_LS) ? WS2811_LS_TOH :
+ (MODE == WS2811_HS) ? WS2811_HS_TOH :
+ (MODE == WS2812_HS) ? WS2812S_HS_TOH :
+ (MODE == WS2812S_HS) ? WS2812S_HS_TOH :
+ (MODE == WS2812B_HS) ? WS2812B_HS_TOH : WS2811_LS_TOH;
+
+parameter WS281X_T1H = (MODE == WS2811_LS) ? WS2811_LS_T1H :
+ (MODE == WS2811_HS) ? WS2811_HS_T1H :
+ (MODE == WS2812_HS) ? WS2812S_HS_T1H :
+ (MODE == WS2812S_HS) ? WS2812S_HS_T1H :
+ (MODE == WS2812B_HS) ? WS2812B_HS_T1H : WS2811_LS_T1H;
+
+
+//---------------------------------------------------------
+// FSM State
+//---------------------------------------------------------
+parameter STATE_RESET = 3'b000;
+parameter STATE_WAIT_POS_EDGE = 3'b001;
+parameter STATE_WAIT_NEG_EDGE = 3'b010;
+parameter STATE_DATA0_LOW = 3'b011;
+parameter STATE_DATA1_LOW = 3'b100;
+
+//---------------------------------------------------
+// Variable decleration
+//---------------------------------------------------
+logic [15:0] rx_wcnt ;
+logic [15:0] clk_cnt ;
+logic [7:0] bit_cnt ;
+logic [15:0] check_sum ;
+logic [23:0] led_data ;
+time neg_edge_time ;
+time pos_edge_time ;
+time time_ref ;
+logic [2:0] state ;
+
+
+always @(negedge rxd) begin
+ neg_edge_time = $time;
+end
+
+always @(posedge rxd) begin
+ pos_edge_time = $time;
+end
+
+
+always @ (posedge clk) begin
+ if(reset_n == 0) begin
+ rx_wcnt = 0; // rx word count
+ bit_cnt = 0; // bit count
+ clk_cnt = 0; // clock edge count
+ check_sum = 0;
+ state = STATE_RESET;
+ time_ref = $time;
+ led_data = 0;
+ end else begin
+ if(enb == 0) begin
+ state = STATE_RESET;
+ end else begin
+ case(state)
+ STATE_RESET: begin
+ if(rxd == 0) begin
+ if(($time - time_ref) > WS281X_RST) begin
+ $display("STATUS-WS281X-%0d: RESET PHASE DETECTED",PORT_ID);
+ state = STATE_WAIT_POS_EDGE;
+ end
+ end else begin
+ time_ref = $time;
+ $display("ERROR-WS281X-%0d: Out of Spec Positive Pulse Width Detected at Reset Phase : %t",PORT_ID,$time);
+ #1000;
+ $stop;
+ end
+ end
+ STATE_WAIT_POS_EDGE: begin
+ if(rxd == 1) begin
+ state = STATE_WAIT_NEG_EDGE;
+ end
+ end
+ STATE_WAIT_NEG_EDGE: begin
+ if(rxd == 0) begin
+ if(((neg_edge_time-pos_edge_time) > (WS281X_TOH-WS281X_TOLERENCE)) &&
+ ((neg_edge_time-pos_edge_time) < (WS281X_TOH+WS281X_TOLERENCE))) begin
+ // Check of the Width Match with Data-0: High Pulse width
+ state = STATE_DATA0_LOW;
+ end else if(((neg_edge_time-pos_edge_time) > (WS281X_T1H-WS281X_TOLERENCE)) &&
+ (neg_edge_time-pos_edge_time) < (WS281X_T1H+WS281X_TOLERENCE)) begin
+ // Check of the Width Match with Data-1: High Pulse width
+ state = STATE_DATA1_LOW;
+ end else begin
+ $display("ERROR-WS281X-%0d: Out of Spec Positive Pulse Width Detected : %t",PORT_ID,neg_edge_time-pos_edge_time);
+ #1000;
+ $stop;
+ end
+ end else if(($time-pos_edge_time) > (WS281X_T1H+WS281X_TOLERENCE)) begin
+ $display("ERROR-WS281X-%0d: Out of Spec Positive Pulse Width Detected : %t",PORT_ID,$time);
+ #1000;
+ $stop;
+ end
+ end
+
+ // Check Data low period for DATA-0
+ STATE_DATA0_LOW: begin
+ if(rxd == 1) begin
+ if(((pos_edge_time-neg_edge_time) > (WS281X_PERIOD-WS281X_TOH-WS281X_TOLERENCE)) &&
+ ((pos_edge_time-neg_edge_time) < (WS281X_PERIOD-WS281X_TOH+WS281X_TOLERENCE))) begin
+ // Check of the Width Match with Data-0: Neg Pulse width
+ led_data = led_data << 1; // Data is zero
+ bit_cnt = bit_cnt+1;
+ if(bit_cnt == 24) begin
+ bit_cnt = 0;
+ rx_wcnt = rx_wcnt+1;
+ $display("STATUS-WS281X-%0d: Word Cnt: %d Green: %x Red: %x Blue: %x",PORT_ID,rx_wcnt,led_data[23:16],led_data[15:8],led_data[7:0]);
+ check_sum = check_sum+{led_data[23:16],led_data[15:8],led_data[7:0]};
+ end
+ state = STATE_WAIT_POS_EDGE;
+ end else begin
+ $display("ERROR-WS281X-%0d: Data-0 => Out of Spec Negative Pulse Width Detected : %t",PORT_ID,pos_edge_time-neg_edge_time);
+ #1000;
+ $stop;
+ end
+ end else begin
+ if((($time-neg_edge_time) > (WS281X_PERIOD-WS281X_TOH+WS281X_TOLERENCE))) begin
+ led_data = led_data << 1; // Data is zero
+ bit_cnt = bit_cnt+1;
+ if(bit_cnt != 24) begin
+ $display("ERROR-WS281X-%0d: Partial Data Detected , Rx Count: %d Bit count: %d",PORT_ID,rx_wcnt,bit_cnt);
+ #1000;
+ $stop;
+ end
+ rx_wcnt = rx_wcnt+1;
+ $display("STATUS-WS281X-%0d: Word Cnt: %d Green: %x Red: %x Blue: %x",PORT_ID,rx_wcnt,led_data[23:16],led_data[15:8],led_data[7:0]);
+ check_sum = check_sum+{led_data[23:16],led_data[15:8],led_data[7:0]};
+ time_ref = $time;
+ state = STATE_RESET;
+ end
+ end
+ end
+ // Check Data low period for DATA-1
+ STATE_DATA1_LOW: begin
+ if(rxd == 1) begin
+ if(((pos_edge_time-neg_edge_time) > (WS281X_PERIOD-WS281X_T1H-WS281X_TOLERENCE)) &&
+ ((pos_edge_time-neg_edge_time) < (WS281X_PERIOD-WS281X_T1H+WS281X_TOLERENCE))) begin
+ // Check of the Width Match with Data-0: Neg Pulse width
+ led_data = (led_data << 1) | 1'b1; // Data is high
+ bit_cnt = bit_cnt+1;
+ if(bit_cnt == 24) begin
+ bit_cnt = 0;
+ rx_wcnt = rx_wcnt+1;
+ $display("STATUS-WS281X-%0d: Word Cnt: %d Green: %x Red: %x Blue: %x",PORT_ID,rx_wcnt,led_data[23:16],led_data[15:8],led_data[7:0]);
+ check_sum = check_sum+{led_data[23:16],led_data[15:8],led_data[7:0]};
+ end
+ state = STATE_WAIT_POS_EDGE;
+ end else begin
+ if((($time-neg_edge_time) > (WS281X_PERIOD-WS281X_T1H+WS281X_TOLERENCE))) begin
+ led_data = (led_data << 1) | 1'b1; // Data is Hih
+ bit_cnt = bit_cnt+1;
+ if(bit_cnt != 24) begin
+ $display("ERROR-WS281X-%0d: Partial Data Detected , Rx Count: %d Bit count: %d",PORT_ID,rx_wcnt,bit_cnt);
+ #1000;
+ $stop;
+ end
+ rx_wcnt = rx_wcnt+1;
+ $display("STATUS-WS281X-%0d: Word Cnt: %d Green: %x Red: %x Blue: %x",PORT_ID,rx_wcnt,led_data[23:16],led_data[15:8],led_data[7:0]);
+ check_sum = check_sum+{led_data[23:16],led_data[15:8],led_data[7:0]};
+ time_ref = $time;
+ state = STATE_RESET;
+ end
+ end
+ end
+ end
+ endcase
+ end
+ end
+end
+
+endmodule
diff --git a/verilog/dv/common/riscduino_board b/verilog/dv/common/riscduino_board
index 30c5dc9..5b5dd05 160000
--- a/verilog/dv/common/riscduino_board
+++ b/verilog/dv/common/riscduino_board
@@ -1 +1 @@
-Subproject commit 30c5dc912352049877661b3571064e314aaffcde
+Subproject commit 5b5dd057677b00948b02288291ad2141f0543108
diff --git a/verilog/dv/model/i2c_slave_model.v b/verilog/dv/model/i2c_slave_model.v
index 83b8f8b..7151c3c 100755
--- a/verilog/dv/model/i2c_slave_model.v
+++ b/verilog/dv/model/i2c_slave_model.v
@@ -100,7 +100,7 @@
//
// Variable declaration
//
- wire debug = 1'b1;
+ reg debug = 1'b1;
reg [7:0] mem [255:0]; // initiate memory
reg [7:0] mem_adr; // memory address
@@ -130,6 +130,7 @@
parameter data_ack = 3'b101;
reg [2:0] state; // synopsys enum_state
+ reg block;
//
// module body
@@ -174,14 +175,14 @@
if(scl)
begin
sta <= #1 1'b1;
- d_sta <= #1 1'b0;
- sto <= #1 1'b0;
+ d_sta <= #1 1'b0;
+ sto <= #1 1'b0;
if(debug)
- $display("DEBUG i2c_slave; start condition detected at %t", $time);
+ $display("DEBUG i2c_slave-%0d: start condition detected at %t",I2C_ADR, $time);
end
else
- sta <= #1 1'b0;
+ sta <= #1 1'b0;
always @(posedge scl)
d_sta <= #1 sta;
@@ -194,7 +195,7 @@
sto <= #1 1'b1;
if(debug)
- $display("DEBUG i2c_slave; stop condition detected at %t", $time);
+ $display("DEBUG i2c_slave-%0d: stop condition detected at %t",I2C_ADR, $time);
end
else
sto <= #1 1'b0;
@@ -206,6 +207,7 @@
always @(negedge scl or posedge sto)
if (sto || (sta && !d_sta) )
begin
+ block <= 0;
state <= #1 idle; // reset statemachine
sda_o <= #1 1'b1;
@@ -219,7 +221,7 @@
case(state) // synopsys full_case parallel_case
idle: // idle state
- if (acc_done && my_adr)
+ if (acc_done && my_adr && !block)
begin
state <= #1 slave_ack;
rw <= #1 sr[0];
@@ -227,9 +229,9 @@
#2;
if(debug && rw)
- $display("DEBUG i2c_slave; command byte received (read) at %t", $time);
+ $display("DEBUG i2c_slave-%0d: command byte received (read) at %t",I2C_ADR, $time);
if(debug && !rw)
- $display("DEBUG i2c_slave; command byte received (write) at %t", $time);
+ $display("DEBUG i2c_slave-%0d: command byte received (write) at %t",I2C_ADR, $time);
if(rw)
begin
@@ -237,11 +239,13 @@
if(debug)
begin
- #2 $display("DEBUG i2c_slave; data block read %x from address %x (1)", mem_do, mem_adr);
- #2 $display("DEBUG i2c_slave; memcheck [%x]=%x", mem_adr, mem[mem_adr]);
+ #2 $display("DEBUG i2c_slave-%0d: data block read %x from address %x (1)",I2C_ADR, mem_do, mem_adr);
+ //#2 $display("DEBUG i2c_slave-%0d: memcheck [%x]=%x",I2C_ADR, mem_adr, mem[mem_adr]);
end
end
- end
+ end else if (acc_done) begin // Wait for Next Start or Stop
+ block <= 1;
+ end
slave_ack:
begin
@@ -264,7 +268,7 @@
sda_o <= #1 !(sr <= 255); // generate i2c_ack, for valid address
if(debug)
- #1 $display("DEBUG i2c_slave; address received. adr=%x, ack=%b", sr, sda_o);
+ #1 $display("DEBUG i2c_slave-%0d; address received. adr=%x, ack=%b",I2C_ADR, sr, sda_o);
end
gma_ack:
@@ -289,7 +293,7 @@
#3 mem_do <= mem[mem_adr];
if(debug)
- #5 $display("DEBUG i2c_slave; data block read %x from address %x (2)", mem_do, mem_adr);
+ #5 $display("DEBUG i2c_slave-%0d: data block read %x from address %x (2)",I2C_ADR, mem_do, mem_adr);
end
if(!rw)
@@ -297,7 +301,7 @@
mem[ mem_adr ] <= #1 sr; // store data in memory
if(debug)
- #2 $display("DEBUG i2c_slave; data block write %x to address %x", sr, mem_adr);
+ #2 $display("DEBUG i2c_slave-%0d: data block write %x to address %x",I2C_ADR, sr, mem_adr);
end
end
end
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 5f1c60b..3a0b083 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -280,8 +280,8 @@
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h8273_8343);
- wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h1508_2022);
- wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h0005_0000);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h2408_2022);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h0005_1000);
end
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 92122c1..d58f2aa 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -20,6 +20,9 @@
-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer_reg.sv
-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer.sv
-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/semaphore_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/ws281x_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/ws281x_driver.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/ws281x_reg.sv
-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv
-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv
-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_top.sv
diff --git a/verilog/rtl/pinmux/src/glbl_reg.sv b/verilog/rtl/pinmux/src/glbl_reg.sv
index bc3de29..125bc29 100644
--- a/verilog/rtl/pinmux/src/glbl_reg.sv
+++ b/verilog/rtl/pinmux/src/glbl_reg.sv
@@ -312,7 +312,7 @@
//-----------------------------------------
// Software Reg-1, Release date: <DAY><MONTH><YEAR>
// ----------------------------------------
-gen_32b_reg #(32'h1508_2022) u_reg_7 (
+gen_32b_reg #(32'h2408_2022) u_reg_7 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
@@ -325,9 +325,9 @@
);
//-----------------------------------------
-// Software Reg-2: Poject Revison 5.0 = 0005000
+// Software Reg-2: Poject Revison 5.1 = 0005100
// ----------------------------------------
-gen_32b_reg #(32'h0005_0000) u_reg_8 (
+gen_32b_reg #(32'h0005_1000) u_reg_8 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
diff --git a/verilog/rtl/pinmux/src/gpio_reg.sv b/verilog/rtl/pinmux/src/gpio_reg.sv
index c911cdc..10b90bd 100644
--- a/verilog/rtl/pinmux/src/gpio_reg.sv
+++ b/verilog/rtl/pinmux/src/gpio_reg.sv
@@ -58,7 +58,7 @@
input logic [31:0] gpio_int_event ,
output logic [31:0] cfg_gpio_out_data ,// GPIO statuc O/P data from config reg
output logic [31:0] cfg_gpio_dir_sel ,// decides on GPIO pin is I/P or O/P at pad level, 0 -> Input, 1 -> Output
- output logic [31:0] cfg_gpio_out_type ,// GPIO Type, Unused
+ output logic [31:0] cfg_gpio_out_type ,// GPIO Type, 1 - WS_281X port
output logic [31:0] cfg_multi_func_sel ,// GPIO Multi function type
output logic [31:0] cfg_gpio_posedge_int_sel ,// select posedge interrupt
output logic [31:0] cfg_gpio_negedge_int_sel ,// select negedge interrupt
diff --git a/verilog/rtl/pinmux/src/gpio_top.sv b/verilog/rtl/pinmux/src/gpio_top.sv
index b5d747d..097623f 100644
--- a/verilog/rtl/pinmux/src/gpio_top.sv
+++ b/verilog/rtl/pinmux/src/gpio_top.sv
@@ -52,7 +52,8 @@
// Outputs
output logic [31:0] reg_rdata,
output logic reg_ack,
-
+
+ output logic [31:0] cfg_gpio_out_type ,// GPIO Type, 1 - ws281x
output logic [31:0] cfg_gpio_dir_sel,
input logic [31:0] pad_gpio_in,
output logic [31:0] pad_gpio_out,
@@ -64,7 +65,6 @@
logic [31:0] gpio_prev_indata ;// previously captured GPIO I/P pins data
logic [31:0] cfg_gpio_out_data ;// GPIO statuc O/P data from config reg
-logic [31:0] cfg_gpio_out_type ;// GPIO Type, Unused
logic [31:0] cfg_multi_func_sel ;// GPIO Multi function type
logic [31:0] cfg_gpio_posedge_int_sel ;// select posedge interrupt
logic [31:0] cfg_gpio_negedge_int_sel ;// select negedge interrupt
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index 5c43778..caed827 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -38,36 +38,36 @@
//// uart_master disable option added ////
//////////////////////////////////////////////////////////////////////
/************************************************
-* Pin Mapping ATMGE CONFIG
-* ATMEGA328 caravel Pin Mapping
-* Pin-1 PC6/RESET* digital_io[0]
-* Pin-2 PD0/RXD[0] digital_io[1]
-* Pin-3 PD1/TXD[0] digital_io[2]
-* Pin-4 PD2/RXD[1]/INT0 digital_io[3]
-* Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4]
-* Pin-6 PD4/TXD[1] digital_io[5]
-* Pin-7 VCC -
-* Pin-8 GND -
-* Pin-9 PB6/XTAL1/TOSC1 digital_io[6]
-* Pin-10 PB7/XTAL2/TOSC2 digital_io[7]
-* Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8]
-* Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9]/analog_io[2]
-* Pin-13 PD7/A1N1 digital_io[10]/analog_io[3]
-* Pin-14 PB0/CLKO/ICP1 digital_io[11]
-* Pin-15 PB1/SS[1]OC1A(PWM3) digital_io[12]
-* Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[13]
-* Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14]
-* Pin-18 PB4/MISO digital_io[15]
-* Pin-19 PB5/SCK digital_io[16]
-* Pin-20 AVCC -
-* Pin-21 AREF analog_io[10]
-* Pin-22 GND -
-* Pin-23 PC0/ADC0 digital_io[18]/analog_io[11]
-* Pin-24 PC1/ADC1 digital_io[19]/analog_io[12]
-* Pin-25 PC2/ADC2 digital_io[20]/analog_io[13]
-* Pin-26 PC3/ADC3 digital_io[21]/analog_io[14]
-* Pin-27 PC4/ADC4/SDA digital_io[22]/analog_io[15]
-* Pin-28 PC5/ADC5/SCL digital_io[23]/analog_io[16]
+* Pin Mapping Arduino ATMGE CONFIG
+* ATMEGA328 Port caravel Pin Mapping
+* Pin-1 22 PC6/WS[0]/RESET* digital_io[0]
+* Pin-2 0 PD0/WS[0]/RXD[0] digital_io[1]
+* Pin-3 1 PD1/WS[0]/TXD[0] digital_io[2]
+* Pin-4 2 PD2/WS[0]/RXD[1]/INT0 digital_io[3]
+* Pin-5 3 PD3/WS[1]INT1/OC2B(PWM0) digital_io[4]
+* Pin-6 4 PD4/WS[1]TXD[1] digital_io[5]
+* Pin-7 VCC -
+* Pin-8 GND -
+* Pin-9 20 PB6/WS[1]/XTAL1/TOSC1 digital_io[6]
+* Pin-10 21 PB7/WS[1]/XTAL2/TOSC2 digital_io[7]
+* Pin-11 5 PD5/WS[2]/SS[3]/OC0B(PWM1)/T1 digital_io[8]
+* Pin-12 6 PD6/WS[2]/SS[2]/OC0A(PWM2)/AIN0 digital_io[9]/analog_io[2]
+* Pin-13 7 PD7/WS[2]/A1N1 digital_io[10]/analog_io[3]
+* Pin-14 8 PB0/WS[2]/CLKO/ICP1 digital_io[11]
+* Pin-15 9 PB1/WS[3]/SS[1]OC1A(PWM3) digital_io[12]
+* Pin-16 10 PB2/WS[3]/SS[0]/OC1B(PWM4) digital_io[13]
+* Pin-17 11 PB3/WS[3]/MOSI/OC2A(PWM5) digital_io[14]
+* Pin-18 12 PB4/WS[3]/MISO digital_io[15]
+* Pin-19 13 PB5/SCK digital_io[16]
+* Pin-20 AVCC -
+* Pin-21 AREF analog_io[10]
+* Pin-22 GND -
+* Pin-23 14 PC0/ADC0 digital_io[18]/analog_io[11]
+* Pin-24 15 PC1/ADC1 digital_io[19]/analog_io[12]
+* Pin-25 16 PC2/ADC2 digital_io[20]/analog_io[13]
+* Pin-26 17 PC3/ADC3 digital_io[21]/analog_io[14]
+* Pin-27 18 PC4/ADC4/SDA digital_io[22]/analog_io[15]
+* Pin-28 19 PC5/ADC5/SCL digital_io[23]/analog_io[16]
*
* Additional Pad used for Externam ROM/RAM
* sflash_sck digital_io[24]
@@ -95,6 +95,7 @@
input logic [37:0] digital_io_in ,
// Config
+ input logic [31:0] cfg_gpio_out_type ,// GPIO Type, 1 - WS_281X port
input logic [31:0] cfg_gpio_dir_sel ,
input logic [31:0] cfg_multi_func_sel ,
@@ -153,6 +154,9 @@
output logic uartm_rxd ,
input logic uartm_txd ,
+ // WS_281X TXD Port
+ input logic [3:0] ws_txd,
+
input logic dbg_clk_mon
);
@@ -194,6 +198,10 @@
wire [7:0] cfg_port_c_dir_sel = cfg_gpio_dir_sel[23:16];
wire [7:0] cfg_port_d_dir_sel = cfg_gpio_dir_sel[31:24];
+wire [7:0] cfg_port_a_port_type = cfg_gpio_out_type[7:0];
+wire [7:0] cfg_port_b_port_type = cfg_gpio_out_type[15:8];
+wire [7:0] cfg_port_c_port_type = cfg_gpio_out_type[23:16];
+wire [7:0] cfg_port_d_port_type = cfg_gpio_out_type[31:24];
// This logic to create spi slave interface
logic pin_resetn,spis_boot;
@@ -310,69 +318,85 @@
// dataout selection
always_comb begin
digital_io_out = 'h0;
- //Pin-1 PC6/RESET* digital_io[0]
- if(cfg_port_c_dir_sel[6]) digital_io_out[0] = port_c_out[6];
+ //Pin-1 PC6/WS[0]/RESET* digital_io[0]
+ if(cfg_port_c_port_type[6]) digital_io_out[0] = ws_txd[0];
+ else if(cfg_port_c_dir_sel[6]) digital_io_out[0] = port_c_out[6];
- //Pin-2 PD0/RXD[0] digital_io[1]
- if(cfg_port_d_dir_sel[0]) digital_io_out[1] = port_d_out[0];
+ //Pin-2 PD0/WS[0]/RXD[0] digital_io[1]
+ if(cfg_port_d_port_type[0]) digital_io_out[1] = ws_txd[0];
+ else if(cfg_port_d_dir_sel[0]) digital_io_out[1] = port_d_out[0];
- //Pin-3 PD1/TXD[0] digital_io[2]
- if (cfg_uart_enb[0]) digital_io_out[2] = uart_txd[0];
- else if(cfg_port_d_dir_sel[1]) digital_io_out[2] = port_d_out[1];
+ //Pin-3 PD1/WS[0]/TXD[0] digital_io[2]
+ if (cfg_uart_enb[0]) digital_io_out[2] = uart_txd[0];
+ else if(cfg_port_d_port_type[1]) digital_io_out[2] = ws_txd[0];
+ else if(cfg_port_d_dir_sel[1]) digital_io_out[2] = port_d_out[1];
- //Pin-4 PD2/RXD[1]/INT0 digital_io[3]
- if(cfg_port_d_dir_sel[2]) digital_io_out[3] = port_d_out[2];
+ //Pin-4 PD2/WS[0]/RXD[1]/INT0 digital_io[3]
+ if(cfg_port_d_port_type[2]) digital_io_out[3] = ws_txd[0];
+ else if(cfg_port_d_dir_sel[2]) digital_io_out[3] = port_d_out[2];
- //Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4]
+ //Pin-5 PD3/WS[1]INT1/OC2B(PWM0) digital_io[4]
if(cfg_pwm_enb[0]) digital_io_out[4] = pwm_wfm[0];
+ else if(cfg_port_d_port_type[3])digital_io_out[4] = ws_txd[1];
else if(cfg_port_d_dir_sel[3]) digital_io_out[4] = port_d_out[3];
- //Pin-6 PD4/TXD[1] digital_io[5]
+ //Pin-6 PD4/WS[1]/TXD[1] digital_io[5]
if (cfg_uart_enb[1]) digital_io_out[5] = uart_txd[1];
+ else if(cfg_port_d_port_type[4]) digital_io_out[5] = ws_txd[1];
else if(cfg_port_d_dir_sel[4]) digital_io_out[5] = port_d_out[4];
- //Pin-9 PB6/XTAL1/TOSC1 digital_io[6]
- if(cfg_port_b_dir_sel[6]) digital_io_out[6] = port_b_out[6];
+ //Pin-9 PB6/XTAL1/WS[1]/TOSC1 digital_io[6]
+ if(cfg_port_b_port_type[6]) digital_io_out[6] = ws_txd[1];
+ else if(cfg_port_b_dir_sel[6]) digital_io_out[6] = port_b_out[6];
- // Pin-10 PB7/XTAL2/TOSC2 digital_io[7]
- if(cfg_port_b_dir_sel[7]) digital_io_out[7] = port_b_out[7];
+ // Pin-10 PB7/XTAL2/WS[1]/TOSC2 digital_io[7]
+ if(cfg_port_b_port_type[7]) digital_io_out[7] = ws_txd[1];
+ else if(cfg_port_b_dir_sel[7]) digital_io_out[7] = port_b_out[7];
- //Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8]
+ //Pin-11 PD5/SS[3]/WS[2]/OC0B(PWM1)/T1 digital_io[8]
if(cfg_pwm_enb[1]) digital_io_out[8] = pwm_wfm[1];
else if(cfg_spim_cs_enb[3]) digital_io_out[8] = spim_ssn[3];
+ else if(cfg_port_d_port_type[5])digital_io_out[8] = ws_txd[2];
else if(cfg_port_d_dir_sel[5]) digital_io_out[8] = port_d_out[5];
- //Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2]
+ //Pin-12 PD6/SS[2]/WS[2]/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2]
if(cfg_pwm_enb[2]) digital_io_out[9] = pwm_wfm[2];
else if(cfg_spim_cs_enb[2]) digital_io_out[9] = spim_ssn[2];
+ else if(cfg_port_d_port_type[6])digital_io_out[9] = ws_txd[2];
else if(cfg_port_d_dir_sel[6]) digital_io_out[9] = port_d_out[6];
- //Pin-13 PD7/A1N1 digital_io[10]/analog_io[3]
- if(cfg_port_d_dir_sel[7]) digital_io_out[10] = port_d_out[7];
+ //Pin-13 PD7/A1N1/WS[2] digital_io[10]/analog_io[3]
+ if(cfg_port_d_port_type[7]) digital_io_out[10] = ws_txd[2];
+ else if(cfg_port_d_dir_sel[7]) digital_io_out[10] = port_d_out[7];
- //Pin-14 PB0/CLKO/ICP1 digital_io[11]
- if(cfg_port_b_dir_sel[0]) digital_io_out[11] = port_b_out[0];
+ //Pin-14 PB0/CLKO/WS[2]/ICP1 digital_io[11]
+ if(cfg_port_b_port_type[0]) digital_io_out[11] = ws_txd[2];
+ else if(cfg_port_b_dir_sel[0]) digital_io_out[11] = port_b_out[0];
- //Pin-15 PB1/SS[1]/OC1A(PWM3) digital_io[12]
- if(cfg_pwm_enb[3]) digital_io_out[12] = pwm_wfm[3];
- else if(cfg_spim_cs_enb[1]) digital_io_out[12] = spim_ssn[1];
- else if(cfg_port_b_dir_sel[1]) digital_io_out[12] = port_b_out[1];
+ //Pin-15 PB1/SS[1]/WS[3]/OC1A(PWM3) digital_io[12]
+ if(cfg_pwm_enb[3]) digital_io_out[12] = pwm_wfm[3];
+ else if(cfg_spim_cs_enb[1]) digital_io_out[12] = spim_ssn[1];
+ else if(cfg_port_b_port_type[1])digital_io_out[12] = ws_txd[3];
+ else if(cfg_port_b_dir_sel[1]) digital_io_out[12] = port_b_out[1];
- //Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[13]
+ //Pin-16 PB2/SS[0]/WS[3]/OC1B(PWM4) digital_io[13]
if(cfg_pwm_enb[4]) digital_io_out[13] = pwm_wfm[4];
else if(cfg_spim_cs_enb[0]) digital_io_out[13] = spim_ssn[0];
+ else if(cfg_port_b_port_type[2])digital_io_out[13] = ws_txd[3];
else if(cfg_port_b_dir_sel[2]) digital_io_out[13] = port_b_out[2];
- //Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14]
+ //Pin-17 PB3/MOSI/WS[3]/OC2A(PWM5) digital_io[14]
if(cfg_pwm_enb[5]) digital_io_out[14] = pwm_wfm[5];
+ else if(cfg_port_b_port_type[3]) digital_io_out[14] = ws_txd[3];
else if(cfg_port_b_dir_sel[3]) digital_io_out[14] = port_b_out[3];
else if(spis_boot) digital_io_out[14] = spis_miso; // SPIM MOSI (Input) = SPIS MISO (Output)
- //Pin-18 PB4/MISO digital_io[15]
+ //Pin-18 PB4/WS[3]/MISO digital_io[15]
if(cfg_spim_enb) digital_io_out[15] = spim_miso; // SPIM MISO (Output) = SPIS MOSI (Input)
+ else if(cfg_port_b_port_type[4])digital_io_out[15] = ws_txd[3];
else if(cfg_port_b_dir_sel[4]) digital_io_out[15] = port_b_out[4];
//Pin-19 PB5/SCK digital_io[16]
@@ -425,71 +449,87 @@
// dataoen selection
always_comb begin
digital_io_oen = 38'h3F_FFFF_FFFF;
- //Pin-1 PC6/RESET* digital_io[0]
- if(cfg_port_c_dir_sel[6]) digital_io_oen[0] = 1'b0;
+ //Pin-1 PC6/WS[0]/RESET* digital_io[0]
+ if(cfg_port_c_port_type[6]) digital_io_oen[0] = 1'b1;
+ else if(cfg_port_c_dir_sel[6]) digital_io_oen[0] = 1'b0;
- //Pin-2 PD0/RXD[0] digital_io[1]
+ //Pin-2 PD0/WS[0]/RXD[0] digital_io[1]
if (cfg_uart_enb[0]) digital_io_oen[1] = 1'b1;
+ else if(cfg_port_d_port_type[0])digital_io_oen[1] = 1'b1;
else if(cfg_port_d_dir_sel[0]) digital_io_oen[1] = 1'b0;
- //Pin-3 PD1/TXD[0] digital_io[2]
+ //Pin-3 PD1/WS[0]/TXD[0] digital_io[2]
if (cfg_uart_enb[0]) digital_io_oen[2] = 1'b0;
+ else if(cfg_port_d_port_type[1])digital_io_oen[2] = 1'b1;
else if(cfg_port_d_dir_sel[1]) digital_io_oen[2] = 1'b0;
- //Pin-4 PD2/RXD[1]/INT0 digital_io[3]
+ //Pin-4 PD2/WS[0]/RXD[1]/INT0 digital_io[3]
if (cfg_uart_enb[1]) digital_io_oen[3] = 1'b1;
else if(cfg_int_enb[0]) digital_io_oen[3] = 1'b1;
+ else if(cfg_port_d_port_type[2])digital_io_oen[3] = 1'b1;
else if(cfg_port_d_dir_sel[2]) digital_io_oen[3] = 1'b0;
- //Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4]
+ //Pin-5 PD3/WS[1]/INT1/OC2B(PWM0) digital_io[4]
if(cfg_pwm_enb[0]) digital_io_oen[4] = 1'b0;
else if(cfg_int_enb[1]) digital_io_oen[4] = 1'b1;
+ else if(cfg_port_d_port_type[3])digital_io_oen[4] = 1'b1;
else if(cfg_port_d_dir_sel[3]) digital_io_oen[4] = 1'b0;
- //Pin-6 PD4/TXD[1] digital_io[5]
+ //Pin-6 PD4/WS[1]/TXD[1] digital_io[5]
if (cfg_uart_enb[1]) digital_io_oen[5] = 1'b0;
+ else if(cfg_port_d_port_type[4])digital_io_oen[5] = 1'b1;
else if(cfg_port_d_dir_sel[4]) digital_io_oen[5] = 1'b0;
- //Pin-9 PB6/XTAL1/TOSC1 digital_io[6]
- if(cfg_port_b_dir_sel[6]) digital_io_oen[6] = 1'b0;
+ //Pin-9 PB6/WS[1]/XTAL1/TOSC1 digital_io[6]
+ if(cfg_port_b_port_type[6]) digital_io_oen[6] = 1'b1;
+ else if(cfg_port_b_dir_sel[6]) digital_io_oen[6] = 1'b0;
- // Pin-10 PB7/XTAL2/TOSC2 digital_io[7]
- if(cfg_port_b_dir_sel[7]) digital_io_oen[7] = 1'b0;
+ // Pin-10 PB7/WS[1]/XTAL2/TOSC2 digital_io[7]
+ if(cfg_port_b_port_type[7]) digital_io_oen[7] = 1'b1;
+ else if(cfg_port_b_dir_sel[7]) digital_io_oen[7] = 1'b0;
- //Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8]
+ //Pin-11 PD5/WS[2]/SS[3]/OC0B(PWM1)/T1 digital_io[8]
if(cfg_pwm_enb[1]) digital_io_oen[8] = 1'b0;
else if(cfg_spim_cs_enb[3]) digital_io_oen[8] = 1'b0;
+ else if(cfg_port_d_port_type[5])digital_io_oen[8] = 1'b1;
else if(cfg_port_d_dir_sel[5]) digital_io_oen[8] = 1'b0;
//Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2]
if(cfg_pwm_enb[2]) digital_io_oen[9] = 1'b0;
else if(cfg_spim_cs_enb[2]) digital_io_oen[9] = 1'b0;
+ else if(cfg_port_d_port_type[6])digital_io_oen[9] = 1'b1;
else if(cfg_port_d_dir_sel[6]) digital_io_oen[9] = 1'b0;
- //Pin-13 PD7/A1N1 digital_io[10]/analog_io[3]
- if(cfg_port_d_dir_sel[7]) digital_io_oen[10] = 1'b0;
+ //Pin-13 PD7/WS[2]/A1N1 digital_io[10]/analog_io[3]
+ if(cfg_port_d_port_type[7]) digital_io_oen[10] = 1'b1;
+ else if(cfg_port_d_dir_sel[7]) digital_io_oen[10] = 1'b0;
- //Pin-14 PB0/CLKO/ICP1 digital_io[11]
- if(cfg_port_b_dir_sel[0]) digital_io_oen[11] = 1'b0;
+ //Pin-14 PB0/WS[2]/CLKO/ICP1 digital_io[11]
+ if(cfg_port_b_port_type[0]) digital_io_oen[11] = 1'b1;
+ else if(cfg_port_b_dir_sel[0]) digital_io_oen[11] = 1'b0;
- //Pin-15 PB1/SS[1]/OC1A(PWM3) digital_io[12]
+ //Pin-15 PB1/WS[3]/SS[1]/OC1A(PWM3) digital_io[12]
if(cfg_pwm_enb[3]) digital_io_oen[12] = 1'b0;
else if(cfg_spim_cs_enb[1]) digital_io_oen[12] = 1'b0;
+ else if(cfg_port_b_port_type[1])digital_io_oen[12] = 1'b1;
else if(cfg_port_b_dir_sel[1]) digital_io_oen[12] = 1'b0;
- //Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[13]
+ //Pin-16 PB2/WS[3]/SS[0]/OC1B(PWM4) digital_io[13]
if(cfg_pwm_enb[4]) digital_io_oen[13] = 1'b0;
else if(cfg_spim_cs_enb[0]) digital_io_oen[13] = 1'b0;
+ else if(cfg_port_b_port_type[2])digital_io_oen[13] = 1'b1;
else if(cfg_port_b_dir_sel[2]) digital_io_oen[13] = 1'b0;
- //Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14]
+ //Pin-17 PB3/WS[3]/MOSI/OC2A(PWM5) digital_io[14]
if(cfg_spim_enb) digital_io_oen[14] = 1'b1; // SPIM MOSI (Input)
else if(cfg_pwm_enb[5]) digital_io_oen[14] = 1'b0;
+ else if(cfg_port_b_port_type[3])digital_io_oen[14] = 1'b1;
else if(cfg_port_b_dir_sel[3]) digital_io_oen[14] = 1'b0;
else if(spis_boot) digital_io_oen[14] = 1'b0; // SPIS MISO (Output)
- //Pin-18 PB4/MISO digital_io[15]
+ //Pin-18 PB4/WS[3]/MISO digital_io[15]
if(cfg_spim_enb) digital_io_oen[15] = 1'b0; // SPIM MISO (Output)
+ else if(cfg_port_b_port_type[4])digital_io_oen[15] = 1'b1;
else if(cfg_port_b_dir_sel[4]) digital_io_oen[15] = 1'b0;
else if(spis_boot) digital_io_oen[15] = 1'b1; // SPIS MOSI (Input)
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv
index 22dce38..7638688 100755
--- a/verilog/rtl/pinmux/src/pinmux_top.sv
+++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -45,8 +45,19 @@
//// 0.4 - 20 July 2022, Dinesh A ////
//// On Power On, If RESET* = 0, then system will enter ////
//// in to SPIS slave mode to support boot ////
-//// 0.5 - 21 Aug 2022, Dinesh A ////
-//// uart_master disable option added ////
+//// 0.5 Aug 5 2022, Dinesh A ////
+//// changes in sspim ////
+//// A. SPI Mode 0 to 3 support added, ////
+//// B. SPI Duplex mode TX-RX Mode added ////
+//// 0.6 Aug 15 2022, Dinesh A ////
+//// A. 15 Hardware Semahore added ////
+//// 0.7 - 24 Aug 2022, Dinesh A ////
+//// A. GPIO interrupt generation changed from 1 to 32 ////
+//// B. uart_master disable option added ////
+//// C. Timer interrupt related clean-up ////
+//// D. 4x ws281x driver logic added ////
+//// E. 4x ws281x driver are mux with 16x gpio ////
+//// F. gpio type select the normal gpio vs ws281x ////
//////////////////////////////////////////////////////////////////////
module pinmux_top (
@@ -195,17 +206,19 @@
wire [31:0] gpio_int_event; // GPIO Interrupt indication
reg [1:0] ext_intr_in; // External PAD level interrupt
+logic [3:0] ws_txd ; // ws281x txd port
assign pinmux_debug = '0; // Todo: Need to fix
//------------------------------------------------------
// Register Map Decoding
-`define SEL_GLBL 3'b000 // GLOBAL REGISTER
-`define SEL_GPIO 3'b001 // GPIO REGISTER
-`define SEL_PWM 3'b010 // PWM REGISTER
-`define SEL_TIMER 3'b011 // TIMER REGISTER
-`define SEL_SEMA 3'b100 // SEMAPHORE REGISTER
+`define SEL_GLBL 3'b000 // GLOBAL REGISTER
+`define SEL_GPIO 3'b001 // GPIO REGISTER
+`define SEL_PWM 3'b010 // PWM REGISTER
+`define SEL_TIMER 3'b011 // TIMER REGISTER
+`define SEL_SEMA 3'b100 // SEMAPHORE REGISTER
+`define SEL_WS 3'b101 // WS281x REGISTER
//----------------------------------------
@@ -226,24 +239,29 @@
logic [15:0] reg_sema_rdata;
logic reg_sema_ack;
+logic [31:0] reg_ws_rdata;
+logic reg_ws_ack;
assign reg_rdata = (reg_addr[8:6] == `SEL_GLBL) ? {reg_glbl_rdata} :
(reg_addr[8:6] == `SEL_GPIO) ? {reg_gpio_rdata} :
(reg_addr[8:6] == `SEL_PWM) ? {reg_pwm_rdata} :
(reg_addr[8:6] == `SEL_TIMER) ? reg_timer_rdata :
- (reg_addr[8:6] == `SEL_SEMA) ? {16'h0,reg_sema_rdata} : 'h0;
+ (reg_addr[8:6] == `SEL_SEMA) ? {16'h0,reg_sema_rdata} :
+ (reg_addr[8:6] == `SEL_WS) ? reg_ws_rdata : 'h0;
assign reg_ack = (reg_addr[8:6] == `SEL_GLBL) ? reg_glbl_ack :
(reg_addr[8:6] == `SEL_GPIO) ? reg_gpio_ack :
(reg_addr[8:6] == `SEL_PWM) ? reg_pwm_ack :
(reg_addr[8:6] == `SEL_TIMER) ? reg_timer_ack :
- (reg_addr[8:6] == `SEL_SEMA) ? reg_sema_ack : 1'b0;
+ (reg_addr[8:6] == `SEL_SEMA) ? reg_sema_ack :
+ (reg_addr[8:6] == `SEL_WS) ? reg_ws_ack : 1'b0;
wire reg_glbl_cs = (reg_addr[8:6] == `SEL_GLBL) ? reg_cs : 1'b0;
wire reg_gpio_cs = (reg_addr[8:6] == `SEL_GPIO) ? reg_cs : 1'b0;
wire reg_pwm_cs = (reg_addr[8:6] == `SEL_PWM) ? reg_cs : 1'b0;
wire reg_timer_cs = (reg_addr[8:6] == `SEL_TIMER)? reg_cs : 1'b0;
wire reg_sema_cs = (reg_addr[8:6] == `SEL_SEMA) ? reg_cs : 1'b0;
+wire reg_ws_cs = (reg_addr[8:6] == `SEL_WS) ? reg_cs : 1'b0;
//---------------------------------------------------------------------
@@ -268,9 +286,9 @@
reset_sync u_rst_sync (
.scan_mode (1'b0 ),
- .dclk (mclk ), // Destination clock domain
+ .dclk (mclk ), // Destination clock domain
.arst_n (h_reset_n ), // active low async reset
- .srst_n (sreset_n )
+ .srst_n (sreset_n )
);
//------------------------------------------------------------------
@@ -341,6 +359,7 @@
.reg_ack (reg_gpio_ack ),
+ .cfg_gpio_out_type (cfg_gpio_out_type ),
.cfg_gpio_dir_sel (cfg_gpio_dir_sel ),
.pad_gpio_in (pad_gpio_in ),
.pad_gpio_out (pad_gpio_out ),
@@ -420,6 +439,32 @@
.reg_ack (reg_sema_ack )
);
+//-----------------------------------------------------------------------
+// 4 Port ws281x driver
+//----------------------------------------------------------------------
+
+ws281x_top u_ws281x(
+ .mclk (mclk ),
+ .h_reset_n (h_reset_n ),
+
+ .reg_cs (reg_ws_cs ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr[5:2] ),
+ .reg_wdata (reg_wdata ),
+ .reg_be (reg_be ),
+
+ .reg_rdata (reg_ws_rdata ),
+ .reg_ack (reg_ws_ack ),
+
+ .txd (ws_txd )
+
+ );
+
+
+
+//----------------------------------------------------------------------
+// Pinmux
+//----------------------------------------------------------------------
pinmux u_pinmux (
// Digital IO
@@ -428,6 +473,7 @@
.digital_io_in (digital_io_in ),
// Config
+ .cfg_gpio_out_type (cfg_gpio_out_type ),
.cfg_gpio_dir_sel (cfg_gpio_dir_sel ),
.cfg_multi_func_sel (cfg_multi_func_sel ),
@@ -477,7 +523,9 @@
// UART MASTER I/F
.uartm_rxd (uartm_rxd ),
- .uartm_txd (uartm_txd ),
+ .uartm_txd (uartm_txd ),
+
+ .ws_txd (ws_txd ),
.dbg_clk_mon (dbg_clk_mon )
diff --git a/verilog/rtl/pinmux/src/ws281x_driver.sv b/verilog/rtl/pinmux/src/ws281x_driver.sv
new file mode 100644
index 0000000..9974a83
--- /dev/null
+++ b/verilog/rtl/pinmux/src/ws281x_driver.sv
@@ -0,0 +1,110 @@
+
+// 24 bit ws281x led driver
+
+module ws281x_driver (
+ input logic clk , // Clock input.
+ input logic reset_n , // Resets the internal state of the driver
+
+ input logic[15:0] cfg_reset_period , // Reset period interm of clk
+ input logic [9:0] cfg_clk_period , // Total bit clock period
+ input logic [9:0] cfg_th0_period , // bit-0 drive low period
+ input logic [9:0] cfg_th1_period , // bit-1 drive low period
+
+ input logic port_enb ,
+ input logic data_available ,
+ input logic [7:0] green_in , // 8-bit green data
+ input logic [7:0] red_in , // 8-bit red data
+ input logic [7:0] blue_in , // 8-bit blue data
+ output logic data_rd , // data read
+
+ output logic txd // Signal to send to WS2811 chain.
+ );
+
+
+ parameter STATE_RESET = 1'd0;
+ parameter STATE_TRANSMIT = 1'd1;
+ /////////////////////////////////////////////////////////////
+ // Timing parameters for the WS2811 //
+ // The LEDs are reset by driving D0 low for at least 50us. //
+ // Data is transmitted using a 800kHz signal. //
+ // A '1' is 50% duty cycle, a '0' is 20% duty cycle. //
+ /////////////////////////////////////////////////////////////
+
+ reg [15:0] clk_cnt ; // Clock divider for a cycle
+ reg state ; // FSM state
+ reg [23:0] led_data ; // Current byte to send
+ reg [4:0] bit_cnt ; // Current bit index to send
+
+
+
+
+ always @ (posedge clk or negedge reset_n) begin
+ if (reset_n == 1'b0) begin
+ state <= STATE_RESET;
+ txd <= 0;
+ data_rd <= 0;
+ bit_cnt <= 23;
+ clk_cnt <= 0;
+ led_data <= 0;
+ end
+ else begin
+ case (state)
+ STATE_RESET: begin
+ if(port_enb) begin
+ if (clk_cnt == cfg_reset_period) begin
+ if(data_available) begin
+ led_data <= {green_in,red_in,blue_in};
+ bit_cnt <= 23;
+ clk_cnt <= 0;
+ txd <= 1;
+ data_rd <= 1;
+ state <= STATE_TRANSMIT;
+ end
+ end
+ else begin
+ // De-assert txd , and wait for 75 us.
+ txd <= 0;
+ clk_cnt <= clk_cnt + 1;
+ end
+ end else begin
+ txd <= 0;
+ clk_cnt <= 0;
+ end
+ end // case: STATE_RESET
+ STATE_TRANSMIT: begin
+ // Advance cycle counter
+ if (clk_cnt == cfg_clk_period) begin
+ txd <= 1;
+ clk_cnt <= 'h0;
+ if (bit_cnt != 0) begin
+ bit_cnt <= bit_cnt -1;
+ // Start sending next bit of data
+ led_data <= {led_data [22:0], 1'b0};
+ end else begin
+ if(data_available) begin // if new data available
+ led_data <= {green_in,red_in,blue_in};
+ bit_cnt <= 23;
+ data_rd <= 1;
+ end else begin
+ state <= STATE_RESET;
+ end
+
+ end
+ end else begin
+ data_rd <= 0;
+ // De-assert txd after a certain amount of time, depending on if you're transmitting a 1 or 0.
+ if (led_data[23] == 0 && clk_cnt >= cfg_th0_period) begin
+ txd <= 0;
+ end
+ else if (led_data[23] == 1 && clk_cnt >= cfg_th1_period) begin
+ txd <= 0;
+ end
+ clk_cnt <= clk_cnt + 1;
+ end
+ end
+ endcase
+ end
+ end
+
+endmodule
+
diff --git a/verilog/rtl/pinmux/src/ws281x_reg.sv b/verilog/rtl/pinmux/src/ws281x_reg.sv
new file mode 100644
index 0000000..2b43097
--- /dev/null
+++ b/verilog/rtl/pinmux/src/ws281x_reg.sv
@@ -0,0 +1,280 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// ws281x Register ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// Manages the 4x ws281x driver register ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 23rd Aug 2022, Dinesh A ////
+//// initial version ////
+//////////////////////////////////////////////////////////////////////
+
+
+module ws281x_reg #( parameter NP = 4, // Number of PORT
+ parameter DW = 32, // DATA WIDTH
+ parameter AW = 4, // ADDRESS WIDTH
+ parameter BW = 4 // BYTE WIDTH
+ ) (
+ // System Signals
+ // Inputs
+ input logic mclk ,
+ input logic h_reset_n ,
+
+ // Reg Bus Interface Signal
+ input logic reg_cs ,
+ input logic reg_wr ,
+ input logic [AW-1:0] reg_addr ,
+ input logic [DW-1:0] reg_wdata ,
+ input logic [BW-1:0] reg_be ,
+
+ // Outputs
+ output logic [DW-1:0] reg_rdata ,
+ output logic reg_ack ,
+
+ output logic[15:0] cfg_reset_period , // Reset period interm of clk
+ output logic [9:0] cfg_clk_period , // Total bit clock period
+ output logic [9:0] cfg_th0_period , // bit-0 drive low period
+ output logic [9:0] cfg_th1_period , // bit-1 drive low period
+
+ // wd281x port-0 data
+ input logic port0_enb ,
+ input logic port0_rd ,
+ output logic [23:0] port0_data ,
+ output logic port0_dval ,
+
+ // wd281x port-1 data
+ input logic port1_enb ,
+ input logic port1_rd ,
+ output logic [23:0] port1_data ,
+ output logic port1_dval ,
+
+ // wd281x port-2 data
+ input logic port2_enb ,
+ input logic port2_rd ,
+ output logic [23:0] port2_data ,
+ output logic port2_dval ,
+
+ // wd281x port-3 data
+ input logic port3_enb ,
+ input logic port3_rd ,
+ output logic [23:0] port3_data ,
+ output logic port3_dval
+
+
+ );
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+logic sw_rd_en ;
+logic sw_wr_en ;
+logic [AW-1:0] sw_addr ;
+logic [DW-1:0] sw_reg_wdata ;
+logic [BW-1:0] sw_be ;
+
+logic [DW-1:0] reg_out ;
+logic [DW-1:0] reg_0 ;
+logic [DW-1:0] reg_1 ;
+logic [DW-1:0] reg_2 ;
+logic [DW-1:0] reg_3 ;
+
+logic [NP-1:0] fifo_full ;
+logic [NP-1:0] fifo_empty ;
+logic [NP-1:0] fifo_wr ;
+logic [NP-1:0] fifo_rd ;
+logic [23:0] fifo_rdata[0:NP-1] ;
+logic [NP-1:0] port_op_done ;
+
+assign sw_addr = reg_addr;
+assign sw_be = reg_be;
+assign sw_rd_en = reg_cs & !reg_wr;
+assign sw_wr_en = reg_cs & reg_wr;
+assign sw_reg_wdata = reg_wdata;
+
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+wire sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0);
+wire sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1);
+wire sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2);
+wire sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3);
+wire sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4) & !fifo_full[0]; // Write only if fifo is not full
+wire sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5) & !fifo_full[1]; // Write only if fifo is not full
+wire sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6) & !fifo_full[2]; // Write only if fifo is not full
+wire sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7) & !fifo_full[3]; // Write only if fifo is not full
+
+
+// Generated seperate write enable case to block the reg ack duration when fifo is full
+wire sw_wr_en_t = sw_wr_en_0 | sw_wr_en_1 | sw_wr_en_2 | sw_wr_en_3 | sw_wr_en_4 | sw_wr_en_5 | sw_wr_en_6 | sw_wr_en_7;
+
+
+always @ (posedge mclk or negedge h_reset_n)
+begin : preg_out_Seq
+ if (h_reset_n == 1'b0) begin
+ reg_rdata <= 'h0;
+ reg_ack <= 1'b0;
+ end else if (reg_cs && !reg_ack && sw_rd_en) begin
+ reg_rdata <= reg_out[DW-1:0] ;
+ reg_ack <= 1'b1;
+ end else if (reg_cs && !reg_ack && sw_wr_en_t) begin // Block Ack generation when FIFO is full
+ reg_ack <= 1'b1;
+ end else begin
+ reg_ack <= 1'b0;
+ end
+end
+
+//----------------------------------------
+// Hardware Command Register
+// Assumption: Maximum 32 port assumed
+//----------------------------------------
+
+assign port0_enb = reg_0[0];
+assign port1_enb = reg_0[1];
+assign port2_enb = reg_0[2];
+assign port3_enb = reg_0[3];
+
+ generic_register #(.WD(4)) u_reg_0(
+ //List of Inputs
+ .we ({8{sw_wr_en_0 &
+ sw_be[0] }}),
+ .data_in (sw_reg_wdata[3:0]),
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_0[3:0] )
+ );
+
+// CONFIG-0
+assign cfg_reset_period = reg_1[15:0];
+gen_16b_reg #(32'h0) u_reg_1 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_1 ),
+ .we (sw_be[1:0] ),
+ .data_in (sw_reg_wdata[15:0] ),
+
+ //List of Outs
+ .data_out (reg_1[15:0] )
+ );
+
+// CONFIG-1
+
+assign cfg_th1_period = reg_2[29:20]; // High Exit Period for Data-1
+assign cfg_th0_period = reg_2[19:10]; // High Exit period for Data-0
+assign cfg_clk_period = reg_2[9:0];
+
+gen_32b_reg #(32'h0) u_reg_2 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_2 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_2 )
+ );
+
+
+
+assign port0_dval =!fifo_empty[0];
+assign port1_dval =!fifo_empty[1];
+assign port2_dval =!fifo_empty[2];
+assign port3_dval =!fifo_empty[3];
+
+assign reg_3 = {2'b00,fifo_empty[3],fifo_full[3],
+ 2'b00,fifo_empty[2],fifo_full[2],
+ 2'b00,fifo_empty[1],fifo_full[1],
+ 2'b00,fifo_empty[0],fifo_full[0]};
+
+
+//----------------------------------------------------
+// DATA FIFO
+//----------------------------------------------------
+
+assign fifo_wr[0] = sw_wr_en_4 & reg_ack;
+assign fifo_wr[1] = sw_wr_en_5 & reg_ack;
+assign fifo_wr[2] = sw_wr_en_6 & reg_ack;
+assign fifo_wr[3] = sw_wr_en_7 & reg_ack;
+
+assign fifo_rd[0] = port0_rd;
+assign fifo_rd[1] = port1_rd;
+assign fifo_rd[2] = port2_rd;
+assign fifo_rd[3] = port3_rd;
+
+assign port0_data = fifo_rdata[0];
+assign port1_data = fifo_rdata[1];
+assign port2_data = fifo_rdata[2];
+assign port3_data = fifo_rdata[3];
+
+genvar port;
+generate
+for (port = 0; $unsigned(port) < NP; port=port+1) begin : gfifo
+
+sync_fifo #(.W(24), .D(8)) u_fifo
+ (
+ .clk (mclk ),
+ .reset_n (h_reset_n ),
+ .wr_en (fifo_wr[port] ),
+ .wr_data (sw_reg_wdata[23:0] ),
+ .full (fifo_full[port] ),
+ .empty (fifo_empty[port] ),
+ .rd_en (fifo_rd[port] ),
+ .rd_data (fifo_rdata[port] )
+ );
+
+end
+endgenerate // gfifo
+
+
+//-----------------------------------------------------------------------
+// Register Read Path Multiplexer instantiation
+//-----------------------------------------------------------------------
+
+always_comb
+begin
+ reg_out [31:0] = 32'h0;
+
+ case (sw_addr [3:0])
+ 4'b0000 : reg_out [31:0] = reg_0 [31:0];
+ 4'b0001 : reg_out [31:0] = reg_1 [31:0];
+ 4'b0010 : reg_out [31:0] = reg_2 [31:0];
+ 4'b0011 : reg_out [31:0] = reg_3 [31:0];
+ 4'b0100 : reg_out [31:0] = port0_data;
+ 4'b0101 : reg_out [31:0] = port1_data;
+ 4'b0110 : reg_out [31:0] = port2_data;
+ 4'b0111 : reg_out [31:0] = port3_data;
+ default : reg_out [31:0] = 32'h0;
+ endcase
+end
+endmodule
diff --git a/verilog/rtl/pinmux/src/ws281x_top.sv b/verilog/rtl/pinmux/src/ws281x_top.sv
new file mode 100644
index 0000000..a048967
--- /dev/null
+++ b/verilog/rtl/pinmux/src/ws281x_top.sv
@@ -0,0 +1,189 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// ws281x Top ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 23rd Aug 2022, Dinesh A ////
+//// initial version ////
+//////////////////////////////////////////////////////////////////////
+
+module ws281x_top (
+ // System Signals
+ // Inputs
+ input logic mclk,
+ input logic h_reset_n,
+
+ // Reg Bus Interface Signal
+ input logic reg_cs,
+ input logic reg_wr,
+ input logic [3:0] reg_addr,
+ input logic [31:0] reg_wdata,
+ input logic [3:0] reg_be,
+
+ // Outputs
+ output logic [31:0] reg_rdata,
+ output logic reg_ack,
+
+ output logic [3:0] txd
+
+ );
+
+logic[15:0] cfg_reset_period ; // Reset period interm of clk
+logic [9:0] cfg_clk_period ; // Total bit clock period
+logic [9:0] cfg_th0_period ; // bit-0 drive low period
+logic [9:0] cfg_th1_period ; // bit-1 drive low period
+
+logic [23:0] port0_data ;
+logic [23:0] port1_data ;
+logic [23:0] port2_data ;
+logic [23:0] port3_data ;
+
+ws281x_reg u_reg (
+ .mclk ( mclk ),
+ .h_reset_n ( h_reset_n ),
+
+ .reg_cs ( reg_cs ),
+ .reg_wr ( reg_wr ),
+ .reg_addr ( reg_addr ),
+ .reg_wdata ( reg_wdata ),
+ .reg_be ( reg_be ),
+
+ .reg_rdata ( reg_rdata ),
+ .reg_ack ( reg_ack ),
+
+ .cfg_reset_period ( cfg_reset_period ), // Reset period interm of clk
+ .cfg_clk_period ( cfg_clk_period ), // Total bit clock period
+ .cfg_th0_period ( cfg_th0_period ), // bit-0 drive low period
+ .cfg_th1_period ( cfg_th1_period ), // bit-1 drive low period
+
+ .port0_enb ( port0_enb ),
+ .port0_rd ( port0_rd ),
+ .port0_data ( port0_data ),
+ .port0_dval ( port0_dval ),
+
+ .port1_enb ( port1_enb ),
+ .port1_rd ( port1_rd ),
+ .port1_data ( port1_data ),
+ .port1_dval ( port1_dval ),
+
+ .port2_enb ( port2_enb ),
+ .port2_rd ( port2_rd ),
+ .port2_data ( port2_data ),
+ .port2_dval ( port2_dval ),
+
+ .port3_enb ( port3_enb ),
+ .port3_rd ( port3_rd ),
+ .port3_data ( port3_data ),
+ .port3_dval ( port3_dval )
+
+ );
+
+
+//wx281x port-0
+ws281x_driver u_txd_0(
+ .clk (mclk ), // Clock input.
+ .reset_n (h_reset_n ), // Resets the internal state of the driver
+
+ .cfg_reset_period (cfg_reset_period ), // Reset period interm of clk
+ .cfg_clk_period (cfg_clk_period ), // Total bit clock period
+ .cfg_th0_period (cfg_th0_period ), // bit-0 drive low period
+ .cfg_th1_period (cfg_th1_period ), // bit-1 drive low period
+
+ .port_enb (port0_enb ),
+ .data_available (port0_dval ),
+ .green_in (port0_data[23:16]), // 8-bit green data
+ .red_in (port0_data[15:8] ), // 8-bit red data
+ .blue_in (port0_data[7:0] ), // 8-bit blue data
+ .data_rd (port0_rd ), // data read
+
+ .txd (txd[0] ) // Signal to send to WS2811 chain.
+ );
+
+//wx281x port-1
+ws281x_driver u_txd_1(
+ .clk (mclk ), // Clock input.
+ .reset_n (h_reset_n ), // Resets the internal state of the driver
+
+ .cfg_reset_period (cfg_reset_period ), // Reset period interm of clk
+ .cfg_clk_period (cfg_clk_period ), // Total bit clock period
+ .cfg_th0_period (cfg_th0_period ), // bit-0 drive low period
+ .cfg_th1_period (cfg_th1_period ), // bit-1 drive low period
+
+ .port_enb (port1_enb ),
+ .data_available (port1_dval ),
+ .green_in (port1_data[23:16]), // 8-bit green data
+ .red_in (port1_data[15:8] ), // 8-bit red data
+ .blue_in (port1_data[7:0] ), // 8-bit blue data
+ .data_rd (port1_rd ), // data read
+
+ .txd (txd[1] ) // Signal to send to WS2811 chain.
+ );
+
+//wx281x port-2
+ws281x_driver u_txd_2(
+ .clk (mclk ), // Clock input.
+ .reset_n (h_reset_n ), // Resets the internal state of the driver
+
+ .cfg_reset_period (cfg_reset_period ), // Reset period interm of clk
+ .cfg_clk_period (cfg_clk_period ), // Total bit clock period
+ .cfg_th0_period (cfg_th0_period ), // bit-0 drive low period
+ .cfg_th1_period (cfg_th1_period ), // bit-1 drive low period
+
+ .port_enb (port2_enb ),
+ .data_available (port2_dval ),
+ .green_in (port2_data[23:16]), // 8-bit green data
+ .red_in (port2_data[15:8] ), // 8-bit red data
+ .blue_in (port2_data[7:0] ), // 8-bit blue data
+ .data_rd (port2_rd ), // data read
+
+ .txd (txd[2] ) // Signal to send to WS2811 chain.
+ );
+
+//wx281x port-3
+ws281x_driver u_txd_3(
+ .clk (mclk ), // Clock input.
+ .reset_n (h_reset_n ), // Resets the internal state of the driver
+
+ .cfg_reset_period (cfg_reset_period ), // Reset period interm of clk
+ .cfg_clk_period (cfg_clk_period ), // Total bit clock period
+ .cfg_th0_period (cfg_th0_period ), // bit-0 drive low period
+ .cfg_th1_period (cfg_th1_period ), // bit-1 drive low period
+
+ .port_enb (port3_enb ),
+ .data_available (port3_dval ),
+ .green_in (port3_data[23:16]), // 8-bit green data
+ .red_in (port3_data[15:8] ), // 8-bit red data
+ .blue_in (port3_data[7:0] ), // 8-bit blue data
+ .data_rd (port3_rd ), // data read
+
+ .txd (txd[3] ) // Signal to send to WS2811 chain.
+ );
+endmodule
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index e54e37a..882d9ba 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -25,17 +25,21 @@
//// Description ////
//// This is digital core and integrate all the main block ////
//// here. Following block are integrated here ////
-//// 1. Risc V Core ////
-//// 2. Quad SPI Master ////
-//// 3. Wishbone Cross Bar ////
-//// 4. UART ////
-//// 5, USB 1.1 ////
-//// 6. SPI Master (Single) ////
-//// 7. TCM SRAM 2KB ////
-//// 8. 2KB icache and 2KB dcache ////
-//// 8. 6 Channel ADC ////
-//// 9. Pinmux with GPIO and 6 PWM ////
-////
+//// 1. 32 bit Risc V Core ////
+//// 2. Quad SPI Master(SPI Flash/SRAM) ////
+//// 3. Wishbone Cross Bar ////
+//// 4. 2 x UART ////
+//// 5, USB 1.1 Host ////
+//// 6. SPI Master (Single) ////
+//// 7. TCM SRAM 2KB ////
+//// 8. 2KB icache and 2KB dcache ////
+//// 9. 6 Channel ADC (Pending) ////
+//// 10. Pinmux with GPIO and 6 PWM ////
+//// 11. 15 x hardware Semaphore ////
+//// 12. 4 x ws281x driver ////
+//// 13. 3 x Hardware Timer ////
+//// 14. UART Master ////
+//// 15. SPI Slave (As Arduino ISP) ////
//// ////
//// To Do: ////
//// nothing ////
@@ -183,7 +187,7 @@
//// wishbone slave clock generation config increase from ////
//// 3 to 4 bit support clock source selection ////
//// B. Changed Module: qspim ////
-////// 1. Bug fix in spi rise and fall pulse relation w.r.t ////
+//// 1. Bug fix in spi rise and fall pulse relation w.r.t ////
//// spi_clk. Note: Previous version work only with ////
//// spi clock config = 0x2 ////
//// 2. spi_oen generation fix for different spi mode ////
@@ -235,11 +239,14 @@
//// `define ADDR_SPACE_PWM 32'h1002_0080 ////
//// `define ADDR_SPACE_TIMER 32'h1002_00C0 ////
//// `define ADDR_SPACE_SEMA 32'h1002_0100 ////
-//// 5.1 Aug 21 2022, Dinesh A ////
+//// 5.1 Aug 24 2022, Dinesh A ////
//// A. GPIO interrupt generation changed from 1 to 32 ////
//// B. Total interrupt to Riscv changed from 16 to 32 ////
//// C. uart_master disable option added at pinmux ////
//// D. Timer interrupt related clean-up ////
+//// E. 4x ws281x driver logic added ////
+//// F. 4x ws281x driver are mux with 16x gpio ////
+//// G. gpio type select the normal gpio vs ws281x ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -294,6 +301,50 @@
0x3000_0000 to 0x307F_FFFF - Indirect Address
{Bank_Sel[15:3],WB ADDR[18:0]}
***********************************************************************/
+/***********************************************************************
+ * Caravel I/O mapping
+ *
+ * mprj_io[37] io_in/out/oeb/in_3v3[26] --- ---
+ * mprj_io[36] io_in/out/oeb/in_3v3[25] --- ---
+ * mprj_io[35] io_in/out/oeb/in_3v3[24] gpio_analog/noesd[17] ---
+ * mprj_io[34] io_in/out/oeb/in_3v3[23] gpio_analog/noesd[16] ---
+ * mprj_io[33] io_in/out/oeb/in_3v3[22] gpio_analog/noesd[15] ---
+ * mprj_io[32] io_in/out/oeb/in_3v3[21] gpio_analog/noesd[14] ---
+ * mprj_io[31] io_in/out/oeb/in_3v3[20] gpio_analog/noesd[13] ---
+ * mprj_io[30] io_in/out/oeb/in_3v3[19] gpio_analog/noesd[12] ---
+ * mprj_io[29] io_in/out/oeb/in_3v3[18] gpio_analog/noesd[11] ---
+ * mprj_io[28] io_in/out/oeb/in_3v3[17] gpio_analog/noesd[10] ---
+ * mprj_io[27] io_in/out/oeb/in_3v3[16] gpio_analog/noesd[9] ---
+ * mprj_io[26] io_in/out/oeb/in_3v3[15] gpio_analog/noesd[8] ---
+ * mprj_io[25] io_in/out/oeb/in_3v3[14] gpio_analog/noesd[7] ---
+ * mprj_io[24] --- --- user_analog[10]
+ * mprj_io[23] --- --- user_analog[9]
+ * mprj_io[22] --- --- user_analog[8]
+ * mprj_io[21] --- --- user_analog[7]
+ * mprj_io[20] --- --- user_analog[6] clamp[2]
+ * mprj_io[19] --- --- user_analog[5] clamp[1]
+ * mprj_io[18] --- --- user_analog[4] clamp[0]
+ * mprj_io[17] --- --- user_analog[3]
+ * mprj_io[16] --- --- user_analog[2]
+ * mprj_io[15] --- --- user_analog[1]
+ * mprj_io[14] --- --- user_analog[0]
+ * mprj_io[13] io_in/out/oeb/in_3v3[13] gpio_analog/noesd[6] ---
+ * mprj_io[12] io_in/out/oeb/in_3v3[12] gpio_analog/noesd[5] ---
+ * mprj_io[11] io_in/out/oeb/in_3v3[11] gpio_analog/noesd[4] ---
+ * mprj_io[10] io_in/out/oeb/in_3v3[10] gpio_analog/noesd[3] ---
+ * mprj_io[9] io_in/out/oeb/in_3v3[9] gpio_analog/noesd[2] ---
+ * mprj_io[8] io_in/out/oeb/in_3v3[8] gpio_analog/noesd[1] ---
+ * mprj_io[7] io_in/out/oeb/in_3v3[7] gpio_analog/noesd[0] ---
+ * mprj_io[6] io_in/out/oeb/in_3v3[6] --- ---
+ * mprj_io[5] io_in/out/oeb/in_3v3[5] --- ---
+ * mprj_io[4] io_in/out/oeb/in_3v3[4] --- ---
+ * mprj_io[3] io_in/out/oeb/in_3v3[3] --- ---
+ * mprj_io[2] io_in/out/oeb/in_3v3[2] --- ---
+ * mprj_io[1] io_in/out/oeb/in_3v3[1] --- ---
+ * mprj_io[0] io_in/out/oeb/in_3v3[0] --- ---
+
+
+************************************************************************/
module user_project_wrapper (
`ifdef USE_POWER_PINS
diff --git a/verilog/rtl/yifive/ycr1c b/verilog/rtl/yifive/ycr1c
index 1a3afdf..564632d 160000
--- a/verilog/rtl/yifive/ycr1c
+++ b/verilog/rtl/yifive/ycr1c
@@ -1 +1 @@
-Subproject commit 1a3afdf0887e7a222c08751b8eeab0533cf6694e
+Subproject commit 564632db2e360384f3af7d61b7d87f6ec03b9b3c
