| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/syntacore,scr1_top_wb,syntacore,flow_completed,0h52m58s,0h28m47s,21958.333333333336,1.92,10979.166666666668,12.31,1583.24,21080,0,0,0,0,0,0,0,1,0,-1,-1,1482754,216223,-15.03,-29.73,-8.21,-15.82,-12.04,-19585.69,-41361.04,-498.79,-8887.44,-3636.06,1131946386.0,4.15,20.68,14.17,4.52,0.33,-1,18285,29630,984,12222,0,0,0,21719,0,0,0,0,0,0,0,4,5144,5849,49,866,26752,0,27618,45.37205081669692,22.04,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4 |
