Basic Verification and Physical design cleanup
diff --git a/openlane/Makefile b/openlane/Makefile
index a368605..62637fe 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -18,8 +18,8 @@
CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
-OPENLANE_TAG ?= rc7
-OPENLANE_IMAGE_NAME ?= dineshannayya/openlane:$(OPENLANE_TAG)
+OPENLANE_TAG ?= 2021.09.19_20.25.16
+OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
@@ -34,47 +34,32 @@
@echo "Please export OPENLANE_ROOT"
@exit 1
endif
-#ifeq ($(PDK_ROOT),)
-# @echo "Please export PDK_ROOT"
-# @exit 1
-#endif
- @echo "############ Running Command #####################"
+ifeq ($(PDK_ROOT),)
+ @echo "Please export PDK_ROOT"
+ @exit 1
+endif
+ @echo "###############################################"
@sleep 1
-#if PDK root is not defines, then use the PDK ROOT inside docker /opt/pdk
-ifneq ($(PDK_ROOT), 1)
- @if [ -f ./$*/interactive.tcl ]; then\
- docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
- -v $(PWD)/..:/project \
- -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
- $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
- else\
- docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
- -v $(PWD)/..:/project \
- -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
- $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\
- fi
-endif
-
-#if PDK_ROOT define, then pick the local path
-ifeq ($(PDK_ROOT), 1)
@if [ -f ./$*/interactive.tcl ]; then\
docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
-v $(PDK_ROOT):$(PDK_ROOT) \
-v $(PWD)/..:/project \
+ -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
-e PDK_ROOT=$(PDK_ROOT) \
+ -e CARAVEL_ROOT=$(CARAVEL_ROOT) \
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
else\
docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
-v $(PDK_ROOT):$(PDK_ROOT) \
-v $(PWD)/..:/project \
+ -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
-e PDK_ROOT=$(PDK_ROOT) \
+ -e CARAVEL_ROOT=$(CARAVEL_ROOT) \
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\
- fi
-endif
-
+ fi
mkdir -p ../signoff/$*/
cp $*/runs/$*/OPENLANE_VERSION ../signoff/$*/
cp $*/runs/$*/PDK_SOURCES ../signoff/$*/
@@ -86,8 +71,9 @@
@echo "Please export OPENLANE_ROOT"
@exit 1
endif
- git clone https://github.com/dineshannayya/openlane.git --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
+ git clone https://github.com/The-OpenROAD-Project/OpenLane --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
cd $(OPENLANE_ROOT) && \
+ export IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
make openlane
FORCE:
diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl
index 93cc2de..9e226cd 100755
--- a/openlane/pinmux/config.tcl
+++ b/openlane/pinmux/config.tcl
@@ -86,9 +86,9 @@
set ::env(FP_PDN_VWIDTH) 5
set ::env(FP_PDN_HWIDTH) 5
-set ::env(GLB_RT_MAXLAYER) 4
+set ::env(GLB_RT_MAXLAYER) 5
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-set ::env(DIODE_INSERTION_STRATEGY) 5
+set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg
index a701001..c502b5a 100644
--- a/openlane/pinmux/pin_order.cfg
+++ b/openlane/pinmux/pin_order.cfg
@@ -91,6 +91,9 @@
spim_mosi
pulse1m_mclk
+i2cm_intr
+usb_intr
+
reg_cs 200 0
reg_wr
diff --git a/openlane/qspim/base.sdc b/openlane/qspim/base.sdc
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/openlane/qspim/base.sdc
diff --git a/openlane/qspim/config.tcl b/openlane/qspim/config.tcl
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/openlane/qspim/config.tcl
diff --git a/openlane/qspim/pdn.tcl b/openlane/qspim/pdn.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/openlane/qspim/pdn.tcl
diff --git a/openlane/qspim/pin_order.cfg b/openlane/qspim/pin_order.cfg
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/openlane/qspim/pin_order.cfg
diff --git a/openlane/qspim/sta.tcl b/openlane/qspim/sta.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/openlane/qspim/sta.tcl
diff --git a/openlane/spi_master/base.sdc b/openlane/spi_master/base.sdc
deleted file mode 100644
index e151002..0000000
--- a/openlane/spi_master/base.sdc
+++ /dev/null
@@ -1,94 +0,0 @@
-# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-
-set_units -time ns
-set ::env(WB_CLOCK_PERIOD) "10"
-set ::env(WB_CLOCK_PORT) "mclk"
-
-set ::env(SPI_CLOCK_PORT) "spiclk"
-set ::env(SPI_CLOCK_PERIOD) "20"
-
-######################################
-# WB Clock domain input output
-######################################
-create_clock [get_ports $::env(WB_CLOCK_PORT)] -name $::env(WB_CLOCK_PORT) -period $::env(WB_CLOCK_PERIOD)
-
-create_generated_clock -name $::env(SPI_CLOCK_PORT) -source [get_ports $::env(WB_CLOCK_PORT)] -master_clock $::env(WB_CLOCK_PORT) -divide_by 2 -add -comment "SPI Clock Out" [get_port spi_clk]
-
-set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
-set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
-puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
-puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
-
-
-set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {rst_n}
-
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_stb_i*]
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_adr_i*]
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_we_i*]
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_dat_i*]
-set_input_delay $wb_input_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_sel_i*]
-
-
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_dat_o*]
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_ack_o*]
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_err_o*]
-set_output_delay $wb_output_delay_value -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_debug*]
-
-### SPI I/F constaints
-set spi_input_delay_value [expr $::env(SPI_CLOCK_PERIOD) * 0.6]
-set spi_output_delay_value [expr $::env(SPI_CLOCK_PERIOD) * 0.6]
-
-set_input_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[3]]
-set_input_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[2]]
-set_input_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[1]]
-set_input_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[0]]
-
-set_input_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[3]]
-set_input_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[2]]
-set_input_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[1]]
-set_input_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[0]]
-
-#io_out[0] is spiclcok
-#set_output_delay $wb_output_delay_value -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[0]]
-set_output_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_csn0]
-set_output_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[3]]
-set_output_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[2]]
-set_output_delay 6 -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[1]]
-
-
-set_output_delay -0.5 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_csn0]
-set_output_delay -0.5 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[3]]
-set_output_delay -0.5 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[2]]
-set_output_delay -0.5 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[1]]
-set_output_delay -0.5 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[0]]
-
-# Chip select asserted multiple cycle eariler than spi clock
-set_output_delay 0 -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_csn0]
-
-
-set_clock_uncertainty -from $::env(SPI_CLOCK_PORT) -to $::env(SPI_CLOCK_PORT) -setup 0.800
-set_clock_uncertainty -from $::env(WB_CLOCK_PORT) -to $::env(WB_CLOCK_PORT) -setup 0.800
-set_clock_uncertainty -from $::env(SPI_CLOCK_PORT) -to $::env(SPI_CLOCK_PORT) -hold 0.050
-set_clock_uncertainty -from $::env(WB_CLOCK_PORT) -to $::env(WB_CLOCK_PORT) -hold 0.050
-
-# TODO set this as parameter
-set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
-puts "\[INFO\]: Setting load to: $cap_load"
-set_load $cap_load [all_outputs]
-
diff --git a/openlane/spi_master/config.tcl b/openlane/spi_master/config.tcl
deleted file mode 100755
index 5a11a92..0000000
--- a/openlane/spi_master/config.tcl
+++ /dev/null
@@ -1,92 +0,0 @@
-# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-# Global
-# ------
-
-set script_dir [file dirname [file normalize [info script]]]
-# Name
-
-set ::env(DESIGN_NAME) spim_top
-
-set ::env(DESIGN_IS_CORE) "0"
-set ::env(FP_PDN_CORE_RING) "0"
-
-# Timing configuration
-set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "mclk"
-
-set ::env(SYNTH_MAX_FANOUT) 4
-
-# Sources
-# -------
-
-# Local sources + no2usb sources
-set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/spi_master/src/spim_top.sv \
- $script_dir/../../verilog/rtl/spi_master/src/spim_if.sv \
- $script_dir/../../verilog/rtl/spi_master/src/spim_regs.sv \
- $script_dir/../../verilog/rtl/spi_master/src/spim_fifo.sv \
- $script_dir/../../verilog/rtl/spi_master/src/spim_clkgen.sv \
- $script_dir/../../verilog/rtl/spi_master/src/spim_ctrl.sv \
- $script_dir/../../verilog/rtl/spi_master/src/spim_rx.sv \
- $script_dir/../../verilog/rtl/spi_master/src/spim_tx.sv "
-
-set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
-
-set ::env(LEC_ENABLE) 0
-
-set ::env(VDD_PIN) [list {vccd1}]
-set ::env(GND_PIN) [list {vssd1}]
-
-
-# Floorplanning
-# -------------
-
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 400 650"
-
-set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.45"
-
-
-# If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 0
-
-#set ::env(PDN_CFG) $script_dir/pdn.tcl
-
-
-set ::env(PL_ROUTABILITY_DRIVEN) 1
-
-# helps in anteena fix
-set ::env(USE_ARC_ANTENNA_CHECK) "0"
-
-set ::env(FP_IO_VEXTEND) 4
-set ::env(FP_IO_HEXTEND) 4
-
-set ::env(FP_PDN_VPITCH) 100
-set ::env(FP_PDN_HPITCH) 100
-set ::env(FP_PDN_VWIDTH) 5
-set ::env(FP_PDN_HWIDTH) 5
-
-set ::env(GLB_RT_MAXLAYER) 4
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-set ::env(DIODE_INSERTION_STRATEGY) 5
-
diff --git a/openlane/spi_master/pin_order.cfg b/openlane/spi_master/pin_order.cfg
deleted file mode 100644
index 5f537e0..0000000
--- a/openlane/spi_master/pin_order.cfg
+++ /dev/null
@@ -1,162 +0,0 @@
-#BUS_SORT
-#MANUAL_PLACE
-
-#W
-mclk 0000 0
-rst_n
-
-#E
-spi_debug\[0\] 0000 0
-spi_debug\[1\]
-spi_debug\[2\]
-spi_debug\[3\]
-spi_debug\[4\]
-spi_debug\[5\]
-spi_debug\[6\]
-spi_debug\[7\]
-spi_debug\[8\]
-spi_debug\[9\]
-spi_debug\[10\]
-spi_debug\[11\]
-spi_debug\[12\]
-spi_debug\[13\]
-spi_debug\[14\]
-spi_debug\[15\]
-spi_debug\[16\]
-spi_debug\[17\]
-spi_debug\[18\]
-spi_debug\[19\]
-spi_debug\[20\]
-spi_debug\[21\]
-spi_debug\[22\]
-spi_debug\[23\]
-spi_debug\[24\]
-spi_debug\[25\]
-spi_debug\[26\]
-spi_debug\[27\]
-spi_debug\[28\]
-spi_debug\[29\]
-spi_debug\[30\]
-spi_debug\[31\]
-
-spi_sdi\[3\] 0200 0
-spi_sdi\[2\]
-spi_sdi\[1\]
-spi_sdi\[0\]
-spi_sdo\[3\]
-spi_sdo\[2\]
-spi_sdo\[1\]
-spi_sdo\[0\]
-spi_clk
-spi_csn0
-spi_oen\[3\]
-spi_oen\[2\]
-spi_oen\[1\]
-spi_oen\[0\]
-
-#S
-wbd_stb_i 0000 0
-wbd_we_i 0000 1
-wbd_adr_i\[31\] 0000 2
-wbd_adr_i\[30\] 0000 3
-wbd_adr_i\[29\] 0000 4
-wbd_adr_i\[28\] 0000 5
-wbd_adr_i\[27\] 0000 6
-wbd_adr_i\[26\] 0000 7
-wbd_adr_i\[25\] 0000 8
-wbd_adr_i\[24\] 0000 9
-wbd_adr_i\[23\] 0000 10
-wbd_adr_i\[22\] 0000 11
-wbd_adr_i\[21\] 0000 12
-wbd_adr_i\[20\] 0000 13
-wbd_adr_i\[19\] 0000 14
-wbd_adr_i\[18\] 0000 15
-wbd_adr_i\[17\] 0000 16
-wbd_adr_i\[16\] 0000 17
-wbd_adr_i\[15\] 0000 18
-wbd_adr_i\[14\] 0000 19
-wbd_adr_i\[13\] 0000 20
-wbd_adr_i\[12\] 0000 21
-wbd_adr_i\[11\] 0000 22
-wbd_adr_i\[10\] 0000 23
-wbd_adr_i\[9\] 0000 24
-wbd_adr_i\[8\] 0000 25
-wbd_adr_i\[7\] 0000 26
-wbd_adr_i\[6\] 0000 27
-wbd_adr_i\[5\] 0000 28
-wbd_adr_i\[4\] 0000 29
-wbd_adr_i\[3\] 0000 30
-wbd_adr_i\[2\] 0000 31
-wbd_adr_i\[1\] 0000 32
-wbd_adr_i\[0\] 0000 33
-wbd_sel_i\[3\] 0000 34
-wbd_sel_i\[2\] 0000 35
-wbd_sel_i\[1\] 0000 36
-wbd_sel_i\[0\] 0000 37
-wbd_dat_i\[31\] 0000 38
-wbd_dat_i\[30\] 0000 39
-wbd_dat_i\[29\] 0000 40
-wbd_dat_i\[28\] 0000 41
-wbd_dat_i\[27\] 0000 42
-wbd_dat_i\[26\] 0000 43
-wbd_dat_i\[25\] 0000 44
-wbd_dat_i\[24\] 0000 45
-wbd_dat_i\[23\] 0000 46
-wbd_dat_i\[22\] 0000 47
-wbd_dat_i\[21\] 0000 48
-wbd_dat_i\[20\] 0000 49
-wbd_dat_i\[19\] 0000 50
-wbd_dat_i\[18\] 0000 51
-wbd_dat_i\[17\] 0000 52
-wbd_dat_i\[16\] 0000 53
-wbd_dat_i\[15\] 0000 54
-wbd_dat_i\[14\] 0000 55
-wbd_dat_i\[13\] 0000 56
-wbd_dat_i\[12\] 0000 57
-wbd_dat_i\[11\] 0000 58
-wbd_dat_i\[10\] 0000 59
-wbd_dat_i\[9\] 0000 60
-wbd_dat_i\[8\] 0000 61
-wbd_dat_i\[7\] 0000 62
-wbd_dat_i\[6\] 0000 63
-wbd_dat_i\[5\] 0000 64
-wbd_dat_i\[4\] 0000 65
-wbd_dat_i\[3\] 0000 66
-wbd_dat_i\[2\] 0000 67
-wbd_dat_i\[1\] 0000 68
-wbd_dat_i\[0\] 0000 69
-wbd_dat_o\[31\] 0000 70
-wbd_dat_o\[30\] 0000 71
-wbd_dat_o\[29\] 0000 72
-wbd_dat_o\[28\] 0000 73
-wbd_dat_o\[27\] 0000 74
-wbd_dat_o\[26\] 0000 75
-wbd_dat_o\[25\] 0000 76
-wbd_dat_o\[24\] 0000 77
-wbd_dat_o\[23\] 0000 78
-wbd_dat_o\[22\] 0000 79
-wbd_dat_o\[21\] 0000 80
-wbd_dat_o\[20\] 0000 81
-wbd_dat_o\[19\] 0000 82
-wbd_dat_o\[18\] 0000 83
-wbd_dat_o\[17\] 0000 84
-wbd_dat_o\[16\] 0000 85
-wbd_dat_o\[15\] 0000 86
-wbd_dat_o\[14\] 0000 87
-wbd_dat_o\[13\] 0000 88
-wbd_dat_o\[12\] 0000 89
-wbd_dat_o\[11\] 0000 90
-wbd_dat_o\[10\] 0000 91
-wbd_dat_o\[9\] 0000 92
-wbd_dat_o\[8\] 0000 93
-wbd_dat_o\[7\] 0000 94
-wbd_dat_o\[6\] 0000 95
-wbd_dat_o\[5\] 0000 96
-wbd_dat_o\[4\] 0000 97
-wbd_dat_o\[3\] 0000 98
-wbd_dat_o\[2\] 0000 99
-wbd_dat_o\[1\] 0000 100
-wbd_dat_o\[0\] 0000 101
-wbd_ack_o 0000 102
-wbd_err_o 0000 103
-
diff --git a/openlane/spi_master/sta.tcl b/openlane/spi_master/sta.tcl
deleted file mode 100644
index af91726..0000000
--- a/openlane/spi_master/sta.tcl
+++ /dev/null
@@ -1,88 +0,0 @@
-# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-
-set ::env(LIB_FASTEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
-set ::env(LIB_SLOWEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
-set ::env(CURRENT_NETLIST) /project/openlane/spi_master/runs/spi_master/results/lvs/spim_top.lvs.powered.v
-set ::env(DESIGN_NAME) "spim_top"
-set ::env(CURRENT_SPEF) /project/openlane/spi_master/runs/spi_master/results/routing/spim_top.spef
-set ::env(BASE_SDC_FILE) "/project/openlane/spi_master/base.sdc"
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
-set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
-set ::env(SYNTH_CAP_LOAD) "17.65"
-set ::env(WIRE_RC_LAYER) "met1"
-
-
-set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
-read_liberty -min $::env(LIB_FASTEST)
-read_liberty -max $::env(LIB_SLOWEST)
-read_verilog $::env(CURRENT_NETLIST)
-link_design $::env(DESIGN_NAME)
-
-read_spef $::env(CURRENT_SPEF)
-
-read_sdc -echo $::env(BASE_SDC_FILE)
-
-# check for missing constraints
-check_setup -verbose > unconstraints.rpt
-
-set_operating_conditions -analysis_type single
-# Propgate the clock
-set_propagated_clock [all_clocks]
-
-report_tns
-report_wns
-report_power
-report_checks -unique -slack_max -0.0 -group_count 100
-report_checks -unique -slack_min -0.0 -group_count 100
-report_checks -path_delay min_max
-report_checks -group_count 100 -slack_max -0.01 > timing.rpt
-
-report_checks -group_count 100 -slack_min -0.01 >> timing.rpt
-
-
-report_checks -to [get_port io_out[5]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[4]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[3]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[2]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_out[1]] -path_delay min >> timing.rpt
-
-report_checks -to [get_port io_out[5]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[4]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[3]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[2]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_out[1]] -path_delay max >> timing.rpt
-
-report_checks -to [get_port io_oeb[5]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_oeb[4]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_oeb[3]] -path_delay min >> timing.rpt
-report_checks -to [get_port io_oeb[2]] -path_delay min >> timing.rpt
-
-report_checks -to [get_port io_oeb[5]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_oeb[4]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_oeb[3]] -path_delay max >> timing.rpt
-report_checks -to [get_port io_oeb[2]] -path_delay max >> timing.rpt
-
-report_checks -from [get_port io_in[5]] -path_delay min >> timing.rpt
-report_checks -from [get_port io_in[4]] -path_delay min >> timing.rpt
-report_checks -from [get_port io_in[3]] -path_delay min >> timing.rpt
-report_checks -from [get_port io_in[2]] -path_delay min >> timing.rpt
-
-report_checks -from [get_port io_in[5]] -path_delay max >> timing.rpt
-report_checks -from [get_port io_in[4]] -path_delay max >> timing.rpt
-report_checks -from [get_port io_in[3]] -path_delay max >> timing.rpt
-report_checks -from [get_port io_in[2]] -path_delay max >> timing.rpt
diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl
index e939e83..de826a4 100755
--- a/openlane/syntacore/config.tcl
+++ b/openlane/syntacore/config.tcl
@@ -109,7 +109,7 @@
set ::env(GLB_RT_MAXLAYER) 5
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-set ::env(DIODE_INSERTION_STRATEGY) 5
+set ::env(DIODE_INSERTION_STRATEGY) 4
set ::env(FP_PDN_VPITCH) 100
set ::env(FP_PDN_HPITCH) 100
diff --git a/openlane/syntacore/pin_order.cfg b/openlane/syntacore/pin_order.cfg
index 90d5c0e..2fe39f5 100644
--- a/openlane/syntacore/pin_order.cfg
+++ b/openlane/syntacore/pin_order.cfg
@@ -57,54 +57,7 @@
fuse_mhartid\[1\]
fuse_mhartid\[0\]
-sram_csb0 600 0 4
-sram_web0
-sram_addr0\[8\]
-sram_addr0\[7\]
-sram_addr0\[6\]
-sram_addr0\[5\]
-sram_addr0\[4\]
-sram_addr0\[3\]
-sram_addr0\[2\]
-sram_addr0\[1\]
-sram_addr0\[0\]
-sram_wmask0\[3\]
-sram_wmask0\[2\]
-sram_wmask0\[1\]
-sram_wmask0\[0\]
-sram_din0\[31\]
-sram_din0\[30\]
-sram_din0\[29\]
-sram_din0\[28\]
-sram_din0\[27\]
-sram_din0\[26\]
-sram_din0\[25\]
-sram_din0\[24\]
-sram_din0\[23\]
-sram_din0\[22\]
-sram_din0\[21\]
-sram_din0\[20\]
-sram_din0\[19\]
-sram_din0\[18\]
-sram_din0\[17\]
-sram_din0\[16\]
-sram_din0\[15\]
-sram_din0\[14\]
-sram_din0\[13\]
-sram_din0\[12\]
-sram_din0\[11\]
-sram_din0\[10\]
-sram_din0\[9\]
-sram_din0\[8\]
-sram_din0\[7\]
-sram_din0\[6\]
-sram_din0\[5\]
-sram_din0\[4\]
-sram_din0\[3\]
-sram_din0\[2\]
-sram_din0\[1\]
-sram_din0\[0\]
-sram_dout0\[31\]
+sram_dout0\[31\] 200 0 4
sram_dout0\[30\]
sram_dout0\[29\]
sram_dout0\[28\]
@@ -137,7 +90,55 @@
sram_dout0\[1\]
sram_dout0\[0\]
-sram_csb1
+sram_din0\[31\] 300 0 4
+sram_din0\[30\]
+sram_din0\[29\]
+sram_din0\[28\]
+sram_din0\[27\]
+sram_din0\[26\]
+sram_din0\[25\]
+sram_din0\[24\]
+sram_din0\[23\]
+sram_din0\[22\]
+sram_din0\[21\]
+sram_din0\[20\]
+sram_din0\[19\]
+sram_din0\[18\]
+sram_din0\[17\]
+sram_din0\[16\]
+sram_din0\[15\]
+sram_din0\[14\]
+sram_din0\[13\]
+sram_din0\[12\]
+sram_din0\[11\]
+sram_din0\[10\]
+sram_din0\[9\]
+sram_din0\[8\]
+sram_din0\[7\]
+sram_din0\[6\]
+sram_din0\[5\]
+sram_din0\[4\]
+sram_din0\[3\]
+sram_din0\[2\]
+sram_din0\[1\]
+sram_din0\[0\]
+sram_wmask0\[3\]
+sram_wmask0\[2\]
+sram_wmask0\[1\]
+sram_wmask0\[0\]
+sram_web0
+sram_csb0
+sram_addr0\[8\]
+sram_addr0\[7\]
+sram_addr0\[6\]
+sram_addr0\[5\]
+sram_addr0\[4\]
+sram_addr0\[3\]
+sram_addr0\[2\]
+sram_addr0\[1\]
+sram_addr0\[0\]
+
+sram_csb1 0800 0 4
sram_addr1\[8\]
sram_addr1\[7\]
sram_addr1\[6\]
diff --git a/openlane/uart_i2cm_usb_spi/base.sdc b/openlane/uart_i2cm_usb_spi/base.sdc
new file mode 100644
index 0000000..3d3a783
--- /dev/null
+++ b/openlane/uart_i2cm_usb_spi/base.sdc
@@ -0,0 +1,82 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
+set_units -time ns
+set ::env(CORE_CLOCK_PERIOD) "10"
+set ::env(CORE_CLOCK_PORT) "app_clk"
+set ::env(CORE_CLOCK_NAME) "app_clk"
+
+set ::env(LINE_CLOCK_PERIOD) "100"
+set ::env(LINE_CLOCK_PORT) "u_uart_core.u_lineclk_buf/X"
+set ::env(LINE_CLOCK_NAME) "line_clk"
+
+set ::env(USB_CLOCK_PERIOD) "100"
+set ::env(USB_CLOCK_PORT) "usb_clk"
+set ::env(USB_CLOCK_NAME) "usb_clk"
+
+######################################
+# WB Clock domain input output
+######################################
+create_clock [get_ports $::env(CORE_CLOCK_PORT)] -name $::env(CORE_CLOCK_NAME) -period $::env(CORE_CLOCK_PERIOD)
+create_clock [get_pins $::env(LINE_CLOCK_PORT)] -name $::env(LINE_CLOCK_NAME) -period $::env(LINE_CLOCK_PERIOD)
+create_clock [get_ports $::env(USB_CLOCK_PORT)] -name $::env(USB_CLOCK_NAME) -period $::env(USB_CLOCK_PERIOD)
+
+set core_input_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
+set core_output_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
+
+set line_input_delay_value [expr $::env(LINE_CLOCK_PERIOD) * 0.6]
+set line_output_delay_value [expr $::env(LINE_CLOCK_PERIOD) * 0.6]
+
+set usb_input_delay_value [expr $::env(USB_CLOCK_PERIOD) * 0.6]
+set usb_output_delay_value [expr $::env(USB_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting wb output delay to:$core_output_delay_value"
+puts "\[INFO\]: Setting wb input delay to: $core_input_delay_value"
+
+
+set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {uart_rstn}
+set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {i2c_rstn}
+set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {usb_rstn}
+
+set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_cs*]
+set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_addr*]
+set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_wr*]
+set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_be*]
+set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_wdata*]
+
+
+set_output_delay $core_output_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_rdata*]
+set_output_delay $core_output_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_ack*]
+
+set_input_delay $line_input_delay_value -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_in*]
+set_output_delay $line_input_delay_value -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_oeb*]
+set_output_delay $line_output_delay_value -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_out*]
+
+
+set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(CORE_CLOCK_NAME)] -group [get_clocks $::env(LINE_CLOCK_NAME)]
+
+set_clock_uncertainty -from $::env(CORE_CLOCK_NAME) -to $::env(CORE_CLOCK_NAME) -setup 0.400
+set_clock_uncertainty -from $::env(LINE_CLOCK_NAME) -to $::env(LINE_CLOCK_NAME) -setup 0.400
+
+set_clock_uncertainty -from $::env(CORE_CLOCK_NAME) -to $::env(CORE_CLOCK_NAME) -hold 0.050
+set_clock_uncertainty -from $::env(LINE_CLOCK_NAME) -to $::env(LINE_CLOCK_NAME) -hold 0.050
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
diff --git a/openlane/uart_i2cm_usb_spi/config.tcl b/openlane/uart_i2cm_usb_spi/config.tcl
new file mode 100644
index 0000000..b0a8c3a
--- /dev/null
+++ b/openlane/uart_i2cm_usb_spi/config.tcl
@@ -0,0 +1,112 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+set ::env(DESIGN_NAME) uart_i2c_usb_spi_top
+
+
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "app_clk usb_clk"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/uart/src/uart_core.sv \
+ $script_dir/../../verilog/rtl/uart/src/uart_cfg.sv \
+ $script_dir/../../verilog/rtl/uart/src/uart_rxfsm.sv \
+ $script_dir/../../verilog/rtl/uart/src/uart_txfsm.sv \
+ $script_dir/../../verilog/rtl/lib/async_wb.sv \
+ $script_dir/../../verilog/rtl/lib/async_fifo.sv \
+ $script_dir/../../verilog/rtl/lib/async_fifo_th.sv \
+ $script_dir/../../verilog/rtl/lib/reset_sync.sv \
+ $script_dir/../../verilog/rtl/lib/double_sync_low.v \
+ $script_dir/../../verilog/rtl/lib/clk_ctl.v \
+ $script_dir/../../verilog/rtl/lib/registers.v \
+ $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_bit_ctrl.v \
+ $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v \
+ $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_top.v \
+ $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_core.sv \
+ $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_crc16.sv \
+ $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_crc5.sv \
+ $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_fifo.sv \
+ $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_sie.sv \
+ $script_dir/../../verilog/rtl/usb1_host/src/phy/usb_fs_phy.v \
+ $script_dir/../../verilog/rtl/usb1_host/src/phy/usb_transceiver.v\
+ $script_dir/../../verilog/rtl/usb1_host/src/top/usb1_host.sv \
+ $script_dir/../../verilog/rtl/sspim/src/sspim_top.sv \
+ $script_dir/../../verilog/rtl/sspim/src/sspim_ctl.sv \
+ $script_dir/../../verilog/rtl/sspim/src/sspim_if.sv \
+ $script_dir/../../verilog/rtl/sspim/src/sspim_cfg.sv \
+ $script_dir/../../verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv\
+ "
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/i2cm/src/includes $script_dir/../../verilog/rtl/usb1_host/src/includes ]
+
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+set ::env(FP_SIZING) "absolute"
+set ::env(DIE_AREA) [list 0.0 0.0 600.0 700.0]
+
+set ::env(PL_TARGET_DENSITY) "0.45"
+
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+
+set ::env(PL_ROUTABILITY_DRIVEN) 1
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "0"
+
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+
+
+set ::env(GLB_RT_MAXLAYER) 5
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 5
+set ::env(FP_PDN_HWIDTH) 5
diff --git a/openlane/spi_master/pdn.tcl b/openlane/uart_i2cm_usb_spi/pdn.tcl
similarity index 100%
rename from openlane/spi_master/pdn.tcl
rename to openlane/uart_i2cm_usb_spi/pdn.tcl
diff --git a/openlane/uart_i2cm_usb_spi/pin_order.cfg b/openlane/uart_i2cm_usb_spi/pin_order.cfg
new file mode 100644
index 0000000..6f6eea7
--- /dev/null
+++ b/openlane/uart_i2cm_usb_spi/pin_order.cfg
@@ -0,0 +1,115 @@
+#BUS_SORT
+#MANUAL_PLACE
+
+#S
+app_clk 0000 0
+usb_clk
+
+reg_cs
+reg_wr
+reg_addr\[7\]
+reg_addr\[6\]
+reg_addr\[5\]
+reg_addr\[4\]
+reg_addr\[3\]
+reg_addr\[2\]
+reg_addr\[1\]
+reg_addr\[0\]
+reg_be
+reg_wdata\[31\]
+reg_wdata\[30\]
+reg_wdata\[29\]
+reg_wdata\[28\]
+reg_wdata\[27\]
+reg_wdata\[26\]
+reg_wdata\[25\]
+reg_wdata\[24\]
+reg_wdata\[23\]
+reg_wdata\[22\]
+reg_wdata\[21\]
+reg_wdata\[20\]
+reg_wdata\[19\]
+reg_wdata\[18\]
+reg_wdata\[17\]
+reg_wdata\[16\]
+reg_wdata\[15\]
+reg_wdata\[14\]
+reg_wdata\[13\]
+reg_wdata\[12\]
+reg_wdata\[11\]
+reg_wdata\[10\]
+reg_wdata\[9\]
+reg_wdata\[8\]
+reg_wdata\[7\]
+reg_wdata\[6\]
+reg_wdata\[5\]
+reg_wdata\[4\]
+reg_wdata\[3\]
+reg_wdata\[2\]
+reg_wdata\[1\]
+reg_wdata\[0\]
+
+reg_rdata\[31\]
+reg_rdata\[30\]
+reg_rdata\[29\]
+reg_rdata\[28\]
+reg_rdata\[27\]
+reg_rdata\[26\]
+reg_rdata\[25\]
+reg_rdata\[24\]
+reg_rdata\[23\]
+reg_rdata\[22\]
+reg_rdata\[21\]
+reg_rdata\[20\]
+reg_rdata\[19\]
+reg_rdata\[18\]
+reg_rdata\[17\]
+reg_rdata\[16\]
+reg_rdata\[15\]
+reg_rdata\[14\]
+reg_rdata\[13\]
+reg_rdata\[12\]
+reg_rdata\[11\]
+reg_rdata\[10\]
+reg_rdata\[9\]
+reg_rdata\[8\]
+reg_rdata\[7\]
+reg_rdata\[6\]
+reg_rdata\[5\]
+reg_rdata\[4\]
+reg_rdata\[3\]
+reg_rdata\[2\]
+reg_rdata\[1\]
+reg_rdata\[0\]
+reg_ack
+
+
+uart_rstn
+i2c_rstn
+usb_rstn
+scl_pad_i
+scl_pad_o
+scl_pad_oen_o
+sda_pad_i
+sda_pad_o
+sda_padoen_o
+uart_rxd
+uart_txd
+usb_in_dp
+usb_in_dn
+usb_out_dp
+usb_out_dn
+usb_out_tx_oen
+
+i2cm_intr_o
+usb_intr_o
+
+spi_rstn
+sspim_sck
+sspim_si
+sspim_so
+sspim_ssn
+
+
+
+
diff --git a/openlane/uart_i2cm_usb_spi/sta.tcl b/openlane/uart_i2cm_usb_spi/sta.tcl
new file mode 100644
index 0000000..ef1ab52
--- /dev/null
+++ b/openlane/uart_i2cm_usb_spi/sta.tcl
@@ -0,0 +1,56 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+set ::env(LIB_FASTEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_SLOWEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(CURRENT_NETLIST) /project/openlane/uart_i2cm/runs/uart_i2cm/results/lvs/uart_i2c_top.lvs.powered.v
+set ::env(DESIGN_NAME) "uart_i2c_top"
+set ::env(CURRENT_SPEF) /project/openlane/uart_i2cm/runs/uart_i2cm/results/routing/uart_i2c_top.spef
+set ::env(BASE_SDC_FILE) "/project/openlane/uart_i2cm/base.sdc"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(WIRE_RC_LAYER) "met1"
+
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+read_liberty -min $::env(LIB_FASTEST)
+read_liberty -max $::env(LIB_SLOWEST)
+read_verilog $::env(CURRENT_NETLIST)
+link_design $::env(DESIGN_NAME)
+
+read_spef $::env(CURRENT_SPEF)
+
+read_sdc -echo $::env(BASE_SDC_FILE)
+
+# check for missing constraints
+#check_setup -verbose > unconstraints.rpt
+
+set_operating_conditions -analysis_type bc_wc
+# Propgate the clock
+set_propagated_clock [all_clocks]
+
+report_tns
+report_wns
+report_power
+report_checks -unique -slack_max -0.0 -group_count 100
+report_checks -unique -slack_min -0.0 -group_count 100
+report_checks -path_delay min_max
+report_checks -group_count 100 -slack_max -0.01
+
+
+
+
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index b89efe6..ef01dc5 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -15,11 +15,16 @@
# Base Configurations. Don't Touch
# section begin
+
+# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS
+source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl
+
+# YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL
+source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/default_wrapper_cfgs.tcl
+
set script_dir [file dirname [file normalize [info script]]]
set proj_dir [file dirname [file normalize [info script]]]
-source $script_dir/../../caravel/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl
-
set ::env(DESIGN_NAME) user_project_wrapper
set verilog_root $proj_dir/../../verilog/
set lef_root $proj_dir/../../lef/
@@ -57,11 +62,11 @@
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
- $proj_dir/../../verilog/gl/spi_master.v \
+ $proj_dir/../../verilog/gl/qspim.v \
$proj_dir/../../verilog/gl/wb_interconnect.v \
$proj_dir/../../verilog/gl/pinmux.v \
$proj_dir/../../verilog/gl/sar_adc.v \
- $proj_dir/../../verilog/gl/uart_i2cm_usb.v \
+ $proj_dir/../../verilog/gl/uart_i2cm_usb_spi.v \
$proj_dir/../../verilog/rtl/sar_adc/DAC_8BIT.v \
$proj_dir/../../verilog/gl/wb_host.v \
$proj_dir/../../verilog/gl/syntacore.v \
@@ -69,10 +74,10 @@
"
set ::env(EXTRA_LEFS) "\
- $lef_root/spi_master.lef \
+ $lef_root/qspim.lef \
$lef_root/pinmux.lef \
$lef_root/wb_interconnect.lef \
- $lef_root/uart_i2cm_usb.lef \
+ $lef_root/uart_i2cm_usb_spi.lef \
$lef_root/wb_host.lef \
$lef_root/sar_adc.lef \
$lef_root/DAC_8BIT.lef \
@@ -81,10 +86,10 @@
"
set ::env(EXTRA_GDS_FILES) "\
- $gds_root/spi_master.gds \
+ $gds_root/qspim.gds \
$gds_root/pinmux.gds \
$gds_root/wb_interconnect.gds \
- $gds_root/uart_i2cm_usb.gds \
+ $gds_root/uart_i2cm_usb_spi.gds \
$gds_root/wb_host.gds \
$gds_root/sar_adc.gds \
$gds_root/DAC_8BIT.gds \
@@ -101,12 +106,15 @@
set ::env(RUN_KLAYOUT_DRC) 0
-set ::env(VDD_PIN) [list {vdda1 vdda2 vccd1 vccd2}]
-set ::env(GND_PIN) [list {vssa1 vssa2 vssd1 vssd2}]
+## Internal Macros
+### Macro PDN Connections
+set ::env(FP_PDN_ENABLE_MACROS_GRID) "0"
+set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1"
-set ::env(VDD_NETS) [list {vdda1 vdda2 vccd1 vccd2}]
-set ::env(GND_NETS) [list {vssa1 vssa2 vssd1 vssd2}]
+set ::env(VDD_NETS) "vccd1 vccd2 vdda1 vdda2"
+set ::env(GND_NETS) "vssd1 vssd2 vssa1 vssa2"
+set ::env(FP_PDN_ENABLE_RAILS) 0
# The following is because there are no std cells in the example wrapper project.
@@ -124,7 +132,7 @@
set ::env(CLOCK_TREE_SYNTH) 0
#set ::env(MAGIC_EXT_USE_GDS) "1"
-
+set ::env(QUIT_ON_LVS_ERROR) "1"
set ::env(PL_DIAMOND_SEARCH_HEIGHT) "250"
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
index f93818b..baf999e 100644
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -16,126 +16,109 @@
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
-
package require openlane;
-proc run_floorplan_yifive {args} {
- puts_info "Running Floorplanning for yifive..."
- # |----------------------------------------------------|
- # |---------------- 2. FLOORPLAN ------------------|
- # |----------------------------------------------------|
- #
- set script_dir [file dirname [file normalize [info script]]]
- # intial fp
- init_floorplan
+proc run_placement_step {args} {
+ # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
+ # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
+ # set_def $pdndef
+ if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+ set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+ }
- # place io
- if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
- place_io_ol
- } else {
- if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
- place_io
- global_placement_or
- place_contextualized_io \
- -lef $::env(FP_CONTEXT_LEF) \
- -def $::env(FP_CONTEXT_DEF)
- } else {
- place_io
- }
- }
-
- apply_def_template
-
- if { [info exist ::env(EXTRA_LEFS)] } {
- if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
- file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(TMP_DIR)/macro_placement.cfg
- manual_macro_placement f
- } else {
- global_placement_or
- basic_macro_placement
- }
- }
-
- # tapcell
- tap_decap_or
- scrot_klayout -layout $::env(CURRENT_DEF)
- puts_info "Running pdn_gen for yifive..."
- # power grid generation
- #run_power_grid_generation
- set ::env(SAVE_DEF) [index_file $::env(pdn_tmp_file_tag).def]
- try_catch openroad -exit $script_dir/gen_pdn.tcl \
- |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(pdn_log_file_tag).log 0]
-
- set_def $::env(SAVE_DEF)
+ run_placement
}
-proc run_power_grid_generation {args} {
- if { [info exists ::env(VDD_NETS)] || [info exists ::env(GND_NETS)] } {
- # they both must exist and be equal in length
- # current assumption: they cannot have a common ground
- if { ! [info exists ::env(VDD_NETS)] || ! [info exists ::env(GND_NETS)] } {
- puts_err "VDD_NETS and GND_NETS must *both* either be defined or undefined"
- return -code error
- }
- } elseif { [info exists ::env(SYNTH_USE_PG_PINS_DEFINES)] } {
- set ::env(VDD_NETS) [list]
- set ::env(GND_NETS) [list]
- # get the pins that are in $yosys_tmp_file_tag.pg_define.v
- # that are not in $yosys_result_file_tag.v
- #
- set full_pins {*}[extract_pins_from_yosys_netlist $::env(yosys_tmp_file_tag).pg_define.v]
- puts_info $full_pins
+proc run_cts_step {args} {
+ # set_def $::env(opendp_result_file_tag).def
+ if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+ set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+ }
- set non_pg_pins {*}[extract_pins_from_yosys_netlist $::env(yosys_result_file_tag).v]
- puts_info $non_pg_pins
+ run_cts
+ run_resizer_timing
+}
- # assumes the pins are ordered correctly (e.g., vdd1, vss1, vcc1, vss1, ...)
- foreach {vdd gnd} $full_pins {
- if { $vdd ne "" && $vdd ni $non_pg_pins } {
- lappend ::env(VDD_NETS) $vdd
- }
- if { $gnd ne "" && $gnd ni $non_pg_pins } {
- lappend ::env(GND_NETS) $gnd
- }
- }
- } else {
- set ::env(VDD_NETS) $::env(VDD_PIN)
- set ::env(GND_NETS) $::env(GND_PIN)
+proc run_routing_step {args} {
+ # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
+ # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
+ # set_def $resizerdef
+ if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+ set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+ }
+ run_routing
+}
+
+proc run_diode_insertion_2_5_step {args} {
+ # set_def $::env(tritonRoute_result_file_tag).def
+ if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+ set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+ }
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+ run_antenna_check
+ heal_antenna_violators; # modifies the routed DEF
}
- puts_info "Power planning the following nets"
- puts_info "Power: $::env(VDD_NETS)"
- puts_info "Ground: $::env(GND_NETS)"
+}
- if { [llength $::env(VDD_NETS)] != [llength $::env(GND_NETS)] } {
- puts_err "VDD_NETS and GND_NETS must be of equal lengths"
- return -code error
+proc run_power_pins_insertion_step {args} {
+ # set_def $::env(tritonRoute_result_file_tag).def
+ if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
+ set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
+ }
+ if { $::env(LVS_INSERT_POWER_PINS) } {
+ write_powered_verilog
+ set_netlist $::env(lvs_result_file_tag).powered.v
+ }
+
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+ # set_def $::env(tritonRoute_result_file_tag).def
+ if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+ set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+ }
+ if { $lvs_enabled } {
+ run_magic_spice_export
+ run_lvs; # requires run_magic_spice_export
}
- # generate multiple power grids per pair of (VDD,GND)
- # offseted by WIDTH + SPACING
- foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
- set ::env(VDD_NET) $vdd
- set ::env(GND_NET) $gnd
+}
- gen_pdn
-
- set ::env(FP_PDN_ENABLE_RAILS) 0
-
- # allow failure until open_pdks is up to date...
- catch {set ::env(FP_PDN_VOFFSET) [expr $::env(FP_PDN_VOFFSET)+$::env(FP_PDN_VWIDTH)+$::env(FP_PDN_VSPACING)]}
- catch {set ::env(FP_PDN_HOFFSET) [expr $::env(FP_PDN_HOFFSET)+$::env(FP_PDN_HWIDTH)+$::env(FP_PDN_HSPACING)]}
-
- catch {set ::env(FP_PDN_CORE_RING_VOFFSET) \
- [expr $::env(FP_PDN_CORE_RING_VOFFSET)\
- +2*($::env(FP_PDN_CORE_RING_VWIDTH)\
- +max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
- catch {set ::env(FP_PDN_CORE_RING_HOFFSET) [expr $::env(FP_PDN_CORE_RING_HOFFSET)\
- +2*($::env(FP_PDN_CORE_RING_HWIDTH)+\
- max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
+proc run_drc_step {{ drc_enabled 1 }} {
+ if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+ set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+ }
+ if { $drc_enabled } {
+ run_magic_drc
+ run_klayout_drc
}
- set ::env(FP_PDN_ENABLE_RAILS) 1
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+ if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+ set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+ }
+ if { $antenna_check_enabled } {
+ run_antenna_check
+ }
}
proc run_flow {args} {
@@ -153,31 +136,58 @@
prep {*}$args
- run_synthesis
- run_floorplan_yifive
- run_placement
- run_cts
- run_routing
+ set LVS_ENABLED 0
+ set DRC_ENABLED 0
+ set ANTENNACHECK_ENABLED 0
- if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
- run_antenna_check
- heal_antenna_violators; # modifies the routed DEF
- }
+ set steps [dict create "synthesis" {run_synthesis "" } \
+ "floorplan" {run_floorplan ""} \
+ "placement" {run_placement_step ""} \
+ "cts" {run_cts_step ""} \
+ "routing" {run_routing_step ""}\
+ "diode_insertion" {run_diode_insertion_2_5_step ""} \
+ "power_pins_insertion" {run_power_pins_insertion_step ""} \
+ "gds_magic" {run_magic ""} \
+ "gds_drc_klayout" {run_klayout ""} \
+ "gds_xor_klayout" {run_klayout_gds_xor ""} \
+ "lvs" "run_lvs_step $LVS_ENABLED" \
+ "drc" "run_drc_step $DRC_ENABLED" \
+ "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
+ "cvc" {run_lef_cvc}
+ ]
- if { $::env(LVS_INSERT_POWER_PINS) } {
- write_powered_verilog
- set_netlist $::env(lvs_result_file_tag).powered.v
- }
+ set_if_unset arg_values(-to) "cvc";
- run_magic
+ if { [info exists ::env(CURRENT_STEP) ] } {
+ puts "\[INFO\]:Picking up where last execution left off"
+ puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
+ } else {
+ set ::env(CURRENT_STEP) "synthesis";
+ }
+ set_if_unset arg_values(-from) $::env(CURRENT_STEP);
+ set exe 0;
+ dict for {step_name step_exe} $steps {
+ if { [ string equal $arg_values(-from) $step_name ] } {
+ set exe 1;
+ }
- run_klayout
+ if { $exe } {
+ # For when it fails
+ set ::env(CURRENT_STEP) $step_name
+ [lindex $step_exe 0] [lindex $step_exe 1] ;
+ }
- run_klayout_gds_xor
+ if { [ string equal $arg_values(-to) $step_name ] } {
+ set exe 0:
+ break;
+ }
- if { ! [info exists flags_map(-no_lvs)] } {
- run_magic_spice_export
- }
+ }
+
+ # for when it resumes
+ set steps_as_list [dict keys $steps]
+ set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+ set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
if { [info exists flags_map(-save) ] } {
if { ! [info exists arg_values(-save_path)] } {
@@ -195,23 +205,9 @@
-tag $::env(RUN_TAG)
}
- # Physical verification
- if { ! [info exists flags_map(-no_lvs)] } {
- run_lvs; # requires run_magic_spice_export
- }
-
- if { ! [info exists flags_map(-no_drc)] } {
- run_magic_drc
- run_klayout_drc
- }
-
- if { ! [info exists flags_map(-no_antennacheck) ] } {
- run_antenna_check
- }
-
- run_lef_cvc
calc_total_runtime
+ save_state
generate_final_summary_report
puts_success "Flow Completed Without Fatal Errors."
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 79dcb94..b628ffc 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,8 +1,7 @@
-u_spi_master 300 2700 N
-u_uart_i2c_usb 1000 2700 N
-u_adc 2000 2700 N
-u_dac 2000 3100 N
-u_riscv_top 500 800 N
+u_qspi_master 300 2700 N
+u_uart_i2c_usb_spi 1000 2700 N
+u_adc 2000 2600 N
+u_riscv_top 300 800 N
u_sram_2kb 2200 1200 N
u_pinmux 2200 300 N
u_intercon 300 2300 N
diff --git a/openlane/user_project_wrapper/pdn.tcl b/openlane/user_project_wrapper/pdn.tcl
index 212085c..3982b7f 100644
--- a/openlane/user_project_wrapper/pdn.tcl
+++ b/openlane/user_project_wrapper/pdn.tcl
@@ -1,55 +1,88 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
# Power nets
-set ::power_nets $::env(_VDD_NET_NAME)
-set ::ground_nets $::env(_GND_NET_NAME)
-set stdcell {
- name grid
- core_ring {
- met5 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_H_OFFSET)}
- met4 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_V_OFFSET)}
- }
- rails {
- }
- connect {{met4 met5}}
+if { ! [info exists ::env(VDD_NET)] } {
+ set ::env(VDD_NET) $::env(VDD_PIN)
}
-if { $::env(_WITH_STRAPS) } {
- dict append stdcell straps {
- met4 {width $::env(_WIDTH) pitch $::env(_V_PITCH) offset $::env(_V_PDN_OFFSET)}
- met5 {width $::env(_WIDTH) pitch $::env(_H_PITCH) offset $::env(_H_PDN_OFFSET)}
+if { ! [info exists ::env(GND_NET)] } {
+ set ::env(GND_NET) $::env(GND_PIN)
+}
+
+set ::power_nets $::env(VDD_NET)
+set ::ground_nets $::env(GND_NET)
+
+if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } {
+ if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } {
+ add_global_connection -net $::env(VDD_NET) -inst_pattern .* -pin_pattern {VPWR} -power
+ add_global_connection -net $::env(VDD_NET) -inst_pattern .* -pin_pattern {VPB} -power
+ add_global_connection -net $::env(GND_NET) -inst_pattern .* -pin_pattern {VGND} -ground
+ add_global_connection -net $::env(GND_NET) -inst_pattern .* -pin_pattern {VNB} -ground
}
}
-pdngen::specify_grid stdcell $stdcell
+set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET)
-set macro {
- orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
- power_pins "vccd1"
- ground_pins "vssd1"
- blockages "li1 met1 met2 met3 met4"
- straps {
- }
- connect {{met4_PIN_ver met5}}
+# Assesses whether the deisgn is the core of the chip or not based on the
+# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
+if { $::env(DESIGN_IS_CORE) == 1 } {
+ # Used if the design is the core of the chip
+ define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
+ add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER
+ add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_UPPER_LAYER) -width $::env(FP_PDN_HWIDTH) -pitch $::env(FP_PDN_HPITCH) -offset $::env(FP_PDN_HOFFSET) -starts_with POWER
+ add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
+} else {
+ # Used if the design is a macro in the core
+ define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins $::env(FP_PDN_LOWER_LAYER)
+ add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER
}
-pdngen::specify_grid macro [subst $macro]
+# Adds the standard cell rails if enabled.
+if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
+ add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_RAILS_LAYER) -width $::env(FP_PDN_RAIL_WIDTH) -followpins -starts_with POWER
+ add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)}]
+}
-set ::halo 10
+
+# Adds the core ring if enabled.
+if { $::env(FP_PDN_CORE_RING) == 1 } {
+ add_pdn_ring -grid stdcell_grid -layer [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}] \
+ -widths [subst {$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)}] \
+ -spacings [subst {$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)}] \
+ -core_offset [subst {$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)}]
+}
+
+# A general macro that follows the premise of the set heirarchy. You may want to modify this or add other macro configs
+# The macro power pin names are assumed to match the VDD and GND net names
+# TODO: parameterize the power pin names
+set macro {
+ orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
+ power_pins $::env(VDD_NET)
+ ground_pins $::env(GND_NET)
+ blockages "li1 met1 met2 met3 met4"
+ straps {
+ }
+ connect {{$::env(FP_PDN_LOWER_LAYER)_PIN_ver $::env(FP_PDN_UPPER_LAYER)}}
+}
+
+if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1} {
+ if { [llength $::env(FP_PDN_MACROS)] > 0 } {
+ # generate automatically per instance:
+ foreach macro_instance $::env(FP_PDN_MACROS) {
+ set macro_instance_grid [subst $macro]
+ dict append $macro_instance_grid instance $macro_instance
+ pdngen::specify_grid macro [subst $macro_instance_grid]
+ set ::halo [list $::env(FP_HORIZONTAL_HALO) $::env(FP_VERTICAL_HALO)]
+ }
+ } else {
+ pdngen::specify_grid macro [subst $macro]
+ set ::halo [list $::env(FP_HORIZONTAL_HALO) $::env(FP_VERTICAL_HALO)]
+ }
+ # CAN NOT ENABLE THE TCL COMMAND BECAUSE THERE IS NO ARGUMENT FOR SPECIFYING THE POWER AND GROUND PIN NAMES ON THE MACRO
+ # define_pdn_grid -macro -orient {R0 R180 MX MY R90 R270 MXR90 MYR90} -grid_over_pg_pins -starts_with POWER -pin_direction vertical -halo [subst {$::env(FP_HORIZONTAL_HALO) $::env(FP_VERTICAL_HALO)}]
+ # add_pdn_connect -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
+} else {
+ define_pdn_grid -macro -orient {R0 R180 MX MY R90 R270 MXR90 MYR90} -grid_over_pg_pins -starts_with POWER -halo [subst {$::env(FP_HORIZONTAL_HALO) $::env(FP_VERTICAL_HALO)}]
+}
# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
set ::rails_start_with "POWER" ;
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index d2c8819..47808f2 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -23,7 +23,6 @@
set ::env(DESIGN_NAME) wb_host
set ::env(DESIGN_IS_CORE) "0"
-set ::env(FP_PDN_CORE_RING) "0"
# Timing configuration
set ::env(CLOCK_PERIOD) "10"
@@ -62,15 +61,14 @@
# If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 0
+set ::env(RUN_CVC) 1
#set ::env(PDN_CFG) $script_dir/pdn.tcl
set ::env(PL_ROUTABILITY_DRIVEN) 1
-# helps in anteena fix
-set ::env(USE_ARC_ANTENNA_CHECK) "0"
+
set ::env(FP_IO_VEXTEND) 4
set ::env(FP_IO_HEXTEND) 4
@@ -80,9 +78,9 @@
set ::env(FP_PDN_VWIDTH) 5
set ::env(FP_PDN_HWIDTH) 5
-set ::env(GLB_RT_MAXLAYER) 4
+set ::env(GLB_RT_MAXLAYER) 5
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-set ::env(DIODE_INSERTION_STRATEGY) 5
+set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 4b8ace2..1b79571 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -5,9 +5,9 @@
#W
sdram_clk 0000 0 4
-sdram_rst_n
+sspim_rst_n
cpu_rst_n
-spi_rst_n
+qspim_rst_n
cfg_clk_ctrl1\[15\]
cfg_clk_ctrl1\[14\]
cfg_clk_ctrl1\[13\]
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index 24f4b45..26b93c7 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -85,5 +85,5 @@
set ::env(GLB_RT_MAXLAYER) 4
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-set ::env(DIODE_INSERTION_STRATEGY) 5
+set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/signoff/pinmux/OPENLANE_VERSION b/signoff/pinmux/OPENLANE_VERSION
index bab6e84..ba96224 100644
--- a/signoff/pinmux/OPENLANE_VERSION
+++ b/signoff/pinmux/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-9-g94fe743
+openlane 2021.09.19_20.25.16
diff --git a/signoff/pinmux/PDK_SOURCES b/signoff/pinmux/PDK_SOURCES
index 8b58bd5..4c20ce4 100644
--- a/signoff/pinmux/PDK_SOURCES
+++ b/signoff/pinmux/PDK_SOURCES
@@ -1,6 +1,6 @@
-ne openlane
-a68c95289612a361870acedb7f6478fcfae32e49
+27752ec11a12afa3214f64401662683f081e2644
-ne skywater-pdk
-f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
+c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-ne open_pdks
-522a373441a865fee9d6e3783015b4445f11afe6
+6c05bc48dc88784f9d98b89d6791cdfd91526676
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv
index dd08286..f7bae69 100644
--- a/signoff/pinmux/final_summary_report.csv
+++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/pinmux,pinmux,pinmux,Flow_completed,0h16m58s,0h8m8s,43688.0,0.25,21844.0,38,639.73,5461,0,0,0,0,0,0,0,0,0,-1,0,401103,52059,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,325104227,0.0,40.27,35.86,2.11,-1,-1,5298,5578,1003,1283,0,0,0,5461,131,0,36,66,784,107,11,1148,1014,964,12,350,3009,0,3359,100.0,10.0,10,AREA 0,4,50,1,100,100,0.35,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h13m20s,0h10m28s,41992.0,0.25,20996.0,24.54,687.7,5249,0,0,0,0,0,0,0,1,0,-1,-1,356411,53685,-1.51,-2.91,0.0,-2.58,-1.51,-707.01,-1833.63,0.0,-128.81,-376.98,280858451.0,6.67,34.96,29.98,5.61,0.5,-1,3127,7858,443,5174,0,0,0,3793,0,0,0,0,0,0,0,4,1147,1169,11,350,3274,0,3624,86.88097306689835,11.51,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/qspim/OPENLANE_VERSION b/signoff/qspim/OPENLANE_VERSION
new file mode 100644
index 0000000..326b88d
--- /dev/null
+++ b/signoff/qspim/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane v0.21-10-gb10884a
diff --git a/signoff/qspim/PDK_SOURCES b/signoff/qspim/PDK_SOURCES
new file mode 100644
index 0000000..8b58bd5
--- /dev/null
+++ b/signoff/qspim/PDK_SOURCES
@@ -0,0 +1,6 @@
+-ne openlane
+a68c95289612a361870acedb7f6478fcfae32e49
+-ne skywater-pdk
+f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
+-ne open_pdks
+522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/qspim/final_summary_report.csv b/signoff/qspim/final_summary_report.csv
new file mode 100644
index 0000000..69addab
--- /dev/null
+++ b/signoff/qspim/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/qspim,qspim_top,qspim,Flow_completed,0h18m21s,0h9m9s,58438.46153846153,0.26,29219.230769230766,47,661.77,7597,0,0,0,0,0,0,0,0,3,-1,0,384228,67124,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,294776771,0.0,31.33,39.79,0.04,-1,-1,7537,7673,1268,1404,0,0,0,7597,245,0,169,100,1051,210,32,2443,1353,1292,24,460,3132,0,3592,100.0,10.0,10,AREA 0,4,50,1,100,100,0.45,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/syntacore/OPENLANE_VERSION b/signoff/syntacore/OPENLANE_VERSION
index bab6e84..ba96224 100644
--- a/signoff/syntacore/OPENLANE_VERSION
+++ b/signoff/syntacore/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-9-g94fe743
+openlane 2021.09.19_20.25.16
diff --git a/signoff/syntacore/PDK_SOURCES b/signoff/syntacore/PDK_SOURCES
index 8b58bd5..4c20ce4 100644
--- a/signoff/syntacore/PDK_SOURCES
+++ b/signoff/syntacore/PDK_SOURCES
@@ -1,6 +1,6 @@
-ne openlane
-a68c95289612a361870acedb7f6478fcfae32e49
+27752ec11a12afa3214f64401662683f081e2644
-ne skywater-pdk
-f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
+c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-ne open_pdks
-522a373441a865fee9d6e3783015b4445f11afe6
+6c05bc48dc88784f9d98b89d6791cdfd91526676
diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index da99116..efd54e7 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,1h31m39s,0h24m23s,28040.625,1.92,14020.3125,21,1253.29,26919,0,0,0,0,0,0,0,0,2,-1,0,1880737,263792,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1499814362,0.0,26.25,17.0,6.81,0.41,-1,26694,27107,3332,3745,0,0,0,26919,705,68,683,599,2928,1044,290,8055,3258,3238,73,866,24574,0,25440,100.0,10.0,10,AREA 0,4,50,1,100,100,0.4,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,flow_completed,0h52m58s,0h28m47s,21958.333333333336,1.92,10979.166666666668,12.31,1583.24,21080,0,0,0,0,0,0,0,1,0,-1,-1,1482754,216223,-15.03,-29.73,-8.21,-15.82,-12.04,-19585.69,-41361.04,-498.79,-8887.44,-3636.06,1131946386.0,4.15,20.68,14.17,4.52,0.33,-1,18285,29630,984,12222,0,0,0,21719,0,0,0,0,0,0,0,4,5144,5849,49,866,26752,0,27618,45.37205081669692,22.04,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm_usb_spi/OPENLANE_VERSION b/signoff/uart_i2cm_usb_spi/OPENLANE_VERSION
new file mode 100644
index 0000000..ba96224
--- /dev/null
+++ b/signoff/uart_i2cm_usb_spi/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane 2021.09.19_20.25.16
diff --git a/signoff/uart_i2cm_usb_spi/PDK_SOURCES b/signoff/uart_i2cm_usb_spi/PDK_SOURCES
new file mode 100644
index 0000000..4c20ce4
--- /dev/null
+++ b/signoff/uart_i2cm_usb_spi/PDK_SOURCES
@@ -0,0 +1,6 @@
+-ne openlane
+27752ec11a12afa3214f64401662683f081e2644
+-ne skywater-pdk
+c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+-ne open_pdks
+6c05bc48dc88784f9d98b89d6791cdfd91526676
diff --git a/signoff/uart_i2cm_usb_spi/final_summary_report.csv b/signoff/uart_i2cm_usb_spi/final_summary_report.csv
new file mode 100644
index 0000000..424576b
--- /dev/null
+++ b/signoff/uart_i2cm_usb_spi/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/uart_i2cm_usb_spi,uart_i2c_usb_spi_top,uart_i2cm_usb_spi,flow_completed,0h18m54s,0h13m36s,52214.285714285725,0.42,26107.142857142862,29.25,869.61,10965,0,0,0,0,0,0,0,1,0,-1,-1,453057,94827,-6.6,-7.12,-6.33,-8.81,-11.23,-694.83,-825.18,-485.91,-1894.31,-4979.38,307076382.0,0.55,25.76,25.22,1.89,0.63,-1,8086,12517,1449,5823,0,0,0,9108,0,0,0,0,0,0,0,4,2535,2532,26,498,5647,0,6145,47.103155911446066,21.23,10,AREA 0,4,50,1,100,100,0.45,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/OPENLANE_VERSION b/signoff/user_project_wrapper/OPENLANE_VERSION
index bab6e84..ba96224 100644
--- a/signoff/user_project_wrapper/OPENLANE_VERSION
+++ b/signoff/user_project_wrapper/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-9-g94fe743
+openlane 2021.09.19_20.25.16
diff --git a/signoff/user_project_wrapper/PDK_SOURCES b/signoff/user_project_wrapper/PDK_SOURCES
index 8b58bd5..4c20ce4 100644
--- a/signoff/user_project_wrapper/PDK_SOURCES
+++ b/signoff/user_project_wrapper/PDK_SOURCES
@@ -1,6 +1,6 @@
-ne openlane
-a68c95289612a361870acedb7f6478fcfae32e49
+27752ec11a12afa3214f64401662683f081e2644
-ne skywater-pdk
-f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
+c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-ne open_pdks
-522a373441a865fee9d6e3783015b4445f11afe6
+6c05bc48dc88784f9d98b89d6791cdfd91526676
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index bc98a12..f8f2aae 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h45m28s,0h6m19s,1.5566625155666252,10.2784,0.7783312577833126,0,530.74,8,0,0,0,0,0,0,0,0,3,-1,-1,1147543,4266,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.2,4.73,0.78,1.3,-1,870,1488,867,1485,0,0,0,8,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,120,120,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h15m50s,0h3m45s,1.5566625155666252,10.2784,0.7783312577833126,-1,520.01,8,0,0,0,0,0,0,-1,-1,-1,-1,-1,1369644,5587,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,53026.4,1.9,5.04,1.02,2.11,-1,152,1776,151,1773,0,0,0,8,0,0,0,0,0,0,0,4,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,120,120,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/OPENLANE_VERSION b/signoff/wb_host/OPENLANE_VERSION
index bab6e84..ba96224 100644
--- a/signoff/wb_host/OPENLANE_VERSION
+++ b/signoff/wb_host/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-9-g94fe743
+openlane 2021.09.19_20.25.16
diff --git a/signoff/wb_host/PDK_SOURCES b/signoff/wb_host/PDK_SOURCES
index 8b58bd5..4c20ce4 100644
--- a/signoff/wb_host/PDK_SOURCES
+++ b/signoff/wb_host/PDK_SOURCES
@@ -1,6 +1,6 @@
-ne openlane
-a68c95289612a361870acedb7f6478fcfae32e49
+27752ec11a12afa3214f64401662683f081e2644
-ne skywater-pdk
-f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
+c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-ne open_pdks
-522a373441a865fee9d6e3783015b4445f11afe6
+6c05bc48dc88784f9d98b89d6791cdfd91526676
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index 66c490c..fd1628d 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h9m58s,0h5m3s,61440.0,0.1,30720.0,49,583.21,3072,0,0,0,0,0,0,0,0,0,-1,0,170202,26317,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,138126985,0.0,48.13,23.41,16.33,-1,-1,2927,3182,554,809,0,0,0,3072,77,0,3,11,49,27,10,797,605,773,14,130,1139,0,1269,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h14m35s,0h13m13s,42500.0,0.1,21250.0,29.07,662.71,2125,0,0,0,0,0,0,0,41,0,0,-1,215024,28645,-1.52,-2.66,-1.41,-3.67,-4.33,-13.89,-136.29,-231.55,-927.15,-1231.73,108251432.0,0.0,47.2,37.88,24.92,1.26,-1,1166,2758,638,2228,0,0,0,1210,0,0,0,0,0,0,0,4,706,785,13,130,1239,0,1369,69.78367062107466,14.33,10,AREA 0,4,50,1,100,100,0.55,0.0,sky130_fd_sc_hd,4,4
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index bd7c2e7..c52a974 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile
@@ -44,6 +44,7 @@
## Simulation mode: RTL/GL
SIM?=RTL
+DUMP?=OFF
.SUFFIXES:
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile
index c1654ac..39da3b4 100644
--- a/verilog/dv/user_i2cm/Makefile
+++ b/verilog/dv/user_i2cm/Makefile
@@ -45,6 +45,7 @@
## Simulation mode: RTL/GL
SIM?=RTL
+DUMP?=OFF
.SUFFIXES:
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile
index 3a03931..fa32693 100644
--- a/verilog/dv/user_risc_boot/Makefile
+++ b/verilog/dv/user_risc_boot/Makefile
@@ -45,6 +45,7 @@
## Simulation mode: RTL/GL
SIM?=RTL
+DUMP?=OFF
.SUFFIXES:
diff --git a/verilog/dv/user_spi/Makefile b/verilog/dv/user_spi/Makefile
index 96527bf..054ec11 100644
--- a/verilog/dv/user_spi/Makefile
+++ b/verilog/dv/user_spi/Makefile
@@ -45,6 +45,7 @@
## Simulation mode: RTL/GL
SIM?=RTL
+DUMP?=OFF
.SUFFIXES:
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile
index 7ef5e6d..fa0a9cf 100644
--- a/verilog/dv/user_uart/Makefile
+++ b/verilog/dv/user_uart/Makefile
@@ -45,6 +45,7 @@
## Simulation mode: RTL/GL
SIM?=RTL
+DUMP?=OFF
.SUFFIXES:
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index e0d9f40..6e77702 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -169,63 +169,63 @@
`ifndef GL // Drive Power for Hold Fix Buf
// All standard cell need power hook-up for functionality work
initial begin
- force uut.mprj.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_delay1_sdio0.VPB =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_delay1_sdio0.VGND =VSS;
- force uut.mprj.u_spi_master.u_delay1_sdio0.VNB = VSS;
- force uut.mprj.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_delay2_sdio0.VPB =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_delay2_sdio0.VGND =VSS;
- force uut.mprj.u_spi_master.u_delay2_sdio0.VNB = VSS;
- force uut.mprj.u_spi_master.u_buf_sdio0.VPWR =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_buf_sdio0.VPB =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_buf_sdio0.VGND =VSS;
- force uut.mprj.u_spi_master.u_buf_sdio0.VNB =VSS;
+ force uut.mprj.u_qspi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_delay1_sdio0.VPB =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_delay1_sdio0.VGND =VSS;
+ force uut.mprj.u_qspi_master.u_delay1_sdio0.VNB = VSS;
+ force uut.mprj.u_qspi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_delay2_sdio0.VPB =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_delay2_sdio0.VGND =VSS;
+ force uut.mprj.u_qspi_master.u_delay2_sdio0.VNB = VSS;
+ force uut.mprj.u_qspi_master.u_buf_sdio0.VPWR =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_buf_sdio0.VPB =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_buf_sdio0.VGND =VSS;
+ force uut.mprj.u_qspi_master.u_buf_sdio0.VNB =VSS;
- force uut.mprj.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_delay1_sdio1.VPB =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_delay1_sdio1.VGND =VSS;
- force uut.mprj.u_spi_master.u_delay1_sdio1.VNB = VSS;
- force uut.mprj.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_delay2_sdio1.VPB =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_delay2_sdio1.VGND =VSS;
- force uut.mprj.u_spi_master.u_delay2_sdio1.VNB = VSS;
- force uut.mprj.u_spi_master.u_buf_sdio1.VPWR =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_buf_sdio1.VPB =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_buf_sdio1.VGND =VSS;
- force uut.mprj.u_spi_master.u_buf_sdio1.VNB =VSS;
+ force uut.mprj.u_qspi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_delay1_sdio1.VPB =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_delay1_sdio1.VGND =VSS;
+ force uut.mprj.u_qspi_master.u_delay1_sdio1.VNB = VSS;
+ force uut.mprj.u_qspi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_delay2_sdio1.VPB =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_delay2_sdio1.VGND =VSS;
+ force uut.mprj.u_qspi_master.u_delay2_sdio1.VNB = VSS;
+ force uut.mprj.u_qspi_master.u_buf_sdio1.VPWR =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_buf_sdio1.VPB =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_buf_sdio1.VGND =VSS;
+ force uut.mprj.u_qspi_master.u_buf_sdio1.VNB =VSS;
- force uut.mprj.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_delay1_sdio2.VPB =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_delay1_sdio2.VGND =VSS;
- force uut.mprj.u_spi_master.u_delay1_sdio2.VNB = VSS;
- force uut.mprj.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_delay2_sdio2.VPB =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_delay2_sdio2.VGND =VSS;
- force uut.mprj.u_spi_master.u_delay2_sdio2.VNB = VSS;
- force uut.mprj.u_spi_master.u_buf_sdio2.VPWR =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_buf_sdio2.VPB =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_buf_sdio2.VGND =VSS;
- force uut.mprj.u_spi_master.u_buf_sdio2.VNB =VSS;
+ force uut.mprj.u_qspi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_delay1_sdio2.VPB =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_delay1_sdio2.VGND =VSS;
+ force uut.mprj.u_qspi_master.u_delay1_sdio2.VNB = VSS;
+ force uut.mprj.u_qspi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_delay2_sdio2.VPB =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_delay2_sdio2.VGND =VSS;
+ force uut.mprj.u_qspi_master.u_delay2_sdio2.VNB = VSS;
+ force uut.mprj.u_qspi_master.u_buf_sdio2.VPWR =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_buf_sdio2.VPB =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_buf_sdio2.VGND =VSS;
+ force uut.mprj.u_qspi_master.u_buf_sdio2.VNB =VSS;
- force uut.mprj.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_delay1_sdio3.VPB =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_delay1_sdio3.VGND =VSS;
- force uut.mprj.u_spi_master.u_delay1_sdio3.VNB = VSS;
- force uut.mprj.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_delay2_sdio3.VPB =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_delay2_sdio3.VGND =VSS;
- force uut.mprj.u_spi_master.u_delay2_sdio3.VNB = VSS;
- force uut.mprj.u_spi_master.u_buf_sdio3.VPWR =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_buf_sdio3.VPB =USER_VDD1V8;
- force uut.mprj.u_spi_master.u_buf_sdio3.VGND =VSS;
- force uut.mprj.u_spi_master.u_buf_sdio3.VNB =VSS;
+ force uut.mprj.u_qspi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_delay1_sdio3.VPB =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_delay1_sdio3.VGND =VSS;
+ force uut.mprj.u_qspi_master.u_delay1_sdio3.VNB = VSS;
+ force uut.mprj.u_qspi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_delay2_sdio3.VPB =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_delay2_sdio3.VGND =VSS;
+ force uut.mprj.u_qspi_master.u_delay2_sdio3.VNB = VSS;
+ force uut.mprj.u_qspi_master.u_buf_sdio3.VPWR =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_buf_sdio3.VPB =USER_VDD1V8;
+ force uut.mprj.u_qspi_master.u_buf_sdio3.VGND =VSS;
+ force uut.mprj.u_qspi_master.u_buf_sdio3.VNB =VSS;
- force uut.mprj.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
- force uut.mprj.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPB =USER_VDD1V8;
- force uut.mprj.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VGND =VSS;
- force uut.mprj.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VNB = VSS;
+ force uut.mprj.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
+ force uut.mprj.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPB =USER_VDD1V8;
+ force uut.mprj.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VGND =VSS;
+ force uut.mprj.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VNB = VSS;
force uut.mprj.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
force uut.mprj.u_wb_host.u_buf_wb_rst.VPB =USER_VDD1V8;
@@ -237,15 +237,15 @@
force uut.mprj.u_wb_host.u_buf_cpu_rst.VGND =VSS;
force uut.mprj.u_wb_host.u_buf_cpu_rst.VNB = VSS;
- force uut.mprj.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_spi_rst.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_spi_rst.VGND =VSS;
- force uut.mprj.u_wb_host.u_buf_spi_rst.VNB = VSS;
+ force uut.mprj.u_wb_host.u_buf_qspim_rst.VPWR =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_qspim_rst.VPB =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_qspim_rst.VGND =VSS;
+ force uut.mprj.u_wb_host.u_buf_qspim_rst.VNB = VSS;
- force uut.mprj.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_sdram_rst.VPB =USER_VDD1V8;
- force uut.mprj.u_wb_host.u_buf_sdram_rst.VGND =VSS;
- force uut.mprj.u_wb_host.u_buf_sdram_rst.VNB = VSS;
+ force uut.mprj.u_wb_host.u_buf_sspim_rst.VPWR =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_sspim_rst.VPB =USER_VDD1V8;
+ force uut.mprj.u_wb_host.u_buf_sspim_rst.VGND =VSS;
+ force uut.mprj.u_wb_host.u_buf_sspim_rst.VNB = VSS;
force uut.mprj.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
force uut.mprj.u_wb_host.u_buf_uart_rst.VPB =USER_VDD1V8;
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index 031f1c8..09832ee 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -20,6 +20,8 @@
output logic [15:0] irq_lines,
output logic soft_irq,
output logic [2:0] user_irq,
+ input logic usb_intr,
+ input logic i2cm_intr,
// Digital IO
output logic [37:0] digital_io_out,
@@ -209,6 +211,8 @@
.irq_lines (irq_lines ),
.soft_irq (soft_irq ),
.user_irq (user_irq ),
+ .usb_intr (usb_intr ),
+ .i2cm_intr (i2cm_intr ),
.cfg_pulse_1us (cfg_pulse_1us ),
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index aea729f..23e5fe2 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -23,6 +23,8 @@
output logic [15:0] irq_lines,
output logic soft_irq,
output logic [2:0] user_irq,
+ input logic usb_intr,
+ input logic i2cm_intr,
output logic [9:0] cfg_pulse_1us,
@@ -300,9 +302,9 @@
//-----------------------------------------------------------------------
// reg-6
//-----------------------------------------------------------------
-assign irq_lines = reg_6[15:0];
-assign soft_irq = reg_6[16];
-assign user_irq = {gpio_intr,ext_intr_in};
+assign irq_lines = {gpio_intr,ext_intr_in[1:0],usb_intr,i2cm_intr,reg_6[10:0]};
+assign soft_irq = reg_6[11];
+assign user_irq = reg_6[14:12];
generic_register #(8,0 ) u_reg6_be0 (
.we ({8{sw_wr_en_6 &
@@ -315,18 +317,18 @@
.data_out (reg_6[7:0] )
);
-generic_register #(8,0 ) u_reg6_be1 (
- .we ({8{sw_wr_en_6 &
+generic_register #(7,0 ) u_reg6_be1 (
+ .we ({7{sw_wr_en_6 &
wr_be[1] }} ),
- .data_in (sw_reg_wdata[15:8]),
+ .data_in (sw_reg_wdata[14:8]),
.reset_n (h_reset_n ),
.clk (mclk ),
//List of Outs
- .data_out (reg_6[15:8] )
+ .data_out (reg_6[14:8] )
);
-assign reg_6[31:16] = '0;
+assign reg_6[31:15] = '0;
// Register-7
gen_32b_reg #(32'h0) u_reg_7 (
diff --git a/verilog/rtl/qspim/src/filelist.f b/verilog/rtl/qspim/src/filelist.f
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/verilog/rtl/qspim/src/filelist.f
diff --git a/verilog/rtl/qspim/src/qspim_clkgen.sv b/verilog/rtl/qspim/src/qspim_clkgen.sv
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/verilog/rtl/qspim/src/qspim_clkgen.sv
diff --git a/verilog/rtl/qspim/src/qspim_ctrl.sv b/verilog/rtl/qspim/src/qspim_ctrl.sv
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/verilog/rtl/qspim/src/qspim_ctrl.sv
diff --git a/verilog/rtl/qspim/src/qspim_fifo.sv b/verilog/rtl/qspim/src/qspim_fifo.sv
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/verilog/rtl/qspim/src/qspim_fifo.sv
diff --git a/verilog/rtl/qspim/src/qspim_if.sv b/verilog/rtl/qspim/src/qspim_if.sv
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/verilog/rtl/qspim/src/qspim_if.sv
diff --git a/verilog/rtl/qspim/src/qspim_regs.sv b/verilog/rtl/qspim/src/qspim_regs.sv
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/verilog/rtl/qspim/src/qspim_regs.sv
diff --git a/verilog/rtl/qspim/src/qspim_rx.sv b/verilog/rtl/qspim/src/qspim_rx.sv
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/verilog/rtl/qspim/src/qspim_rx.sv
diff --git a/verilog/rtl/qspim/src/qspim_top.sv b/verilog/rtl/qspim/src/qspim_top.sv
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/verilog/rtl/qspim/src/qspim_top.sv
diff --git a/verilog/rtl/qspim/src/qspim_tx.sv b/verilog/rtl/qspim/src/qspim_tx.sv
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/verilog/rtl/qspim/src/qspim_tx.sv
diff --git a/verilog/rtl/qspim/synth/Makefile b/verilog/rtl/qspim/synth/Makefile
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/verilog/rtl/qspim/synth/Makefile
diff --git a/verilog/rtl/qspim/synth/synth.tcl b/verilog/rtl/qspim/synth/synth.tcl
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/verilog/rtl/qspim/synth/synth.tcl
diff --git a/verilog/rtl/spi_master/src/filelist.f b/verilog/rtl/spi_master/src/filelist.f
deleted file mode 100644
index ff10568..0000000
--- a/verilog/rtl/spi_master/src/filelist.f
+++ /dev/null
@@ -1,24 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021, Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
-// //////////////////////////////////////////////////////////////////////////
-
-spim_top.sv
-spim_regs.sv
-spim_clkgen.sv
-spim_ctrl.sv
-spim_rx.sv
-spim_tx.sv
diff --git a/verilog/rtl/spi_master/src/spim_clkgen.sv b/verilog/rtl/spi_master/src/spim_clkgen.sv
deleted file mode 100644
index bc3d9fb..0000000
--- a/verilog/rtl/spi_master/src/spim_clkgen.sv
+++ /dev/null
@@ -1,146 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// SPI Clkgen Module ////
-//// ////
-//// This file is part of the YIFive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
-//// ////
-//// Description ////
-//// This is SPI Master Clock Generation control logic. ////
-//// This logic also generate spi clock rise and fall pulse ////
-//// Basis assumption is master clock is 2x time spi clock ////
-//// 1. spi fall pulse is used to transmit spi data ////
-//// 2. spi rise pulse is used to received spi data ////
-//// SPI Master Top module ////
-//// ////
-//// To Do: ////
-//// nothing ////
-//// ////
-//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
-//// ////
-//// Revision: ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
-//// Initial version ////
-//// 0.2 - 24th Mar 2021, Dinesh A ////
-//// 1. Comments are added ////
-//// 2. RTL clean-up done and the output are registred ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-
-module spim_clkgen
-(
- input logic clk,
- input logic rstn,
- input logic en,
- input logic [5:0] cfg_sck_period,
- output logic spi_clk,
- output logic spi_fall,
- output logic spi_rise
-);
-
- logic [5:0] sck_half_period;
- logic [5:0] clk_cnt;
-
- assign sck_half_period = {1'b0, cfg_sck_period[5:1]};
-
- // The first transition on the sck_toggle happens one SCK period
- // after en is asserted
- always @(posedge clk or negedge rstn) begin
- if(!rstn) begin
- spi_clk <= 1'b1;
- end // if (!reset_n)
- else
- begin
- if(en)
- begin
- if(clk_cnt == sck_half_period)
- begin
- spi_clk <= 1'b0;
- end // if (clk_cnt == sck_half_period)
- else if(clk_cnt == cfg_sck_period) begin
- spi_clk <= 1'b1;
- end
- end else begin
- spi_clk <= 1'b1;
- end // else: !if(en)
- end // else: !if(!reset_n)
- end // always @ (posedge clk or negedge reset_n)
-
- // Generate Free runnng spi_fall and rise pulse
- // after en is asserted
- always @(posedge clk or negedge rstn) begin
- if(!rstn) begin
- clk_cnt <= 'h1;
- spi_fall <= 1'b0;
- spi_rise <= 1'b0;
- end // if (!reset_n)
- else
- begin
- if(clk_cnt == sck_half_period)
- begin
- spi_fall <= 1'b0;
- spi_rise <= 1'b1;
- clk_cnt <= clk_cnt + 1'b1;
- end // if (clk_cnt == sck_half_period)
- else begin
- if(clk_cnt == cfg_sck_period)
- begin
- spi_fall <= 1'b1;
- spi_rise <= 1'b0;
- clk_cnt <= 'h1;
- end // if (clk_cnt == cfg_sck_period)
- else
- begin
- clk_cnt <= clk_cnt + 1'b1;
- spi_fall <= 1'b0;
- spi_rise <= 1'b0;
- end // else: !if(clk_cnt == cfg_sck_period)
- end // else: !if(clk_cnt == sck_half_period)
- end // else: !if(!reset_n)
- end // always @ (posedge clk or negedge reset_n)
-
-endmodule
diff --git a/verilog/rtl/spi_master/src/spim_ctrl.sv b/verilog/rtl/spi_master/src/spim_ctrl.sv
deleted file mode 100644
index e8aa2e4..0000000
--- a/verilog/rtl/spi_master/src/spim_ctrl.sv
+++ /dev/null
@@ -1,721 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// SPI CTRL I/F Module ////
-//// ////
-//// This file is part of the YIFive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
-//// ////
-//// Description ////
-//// ////
-//// To Do: ////
-//// nothing ////
-//// ////
-//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
-//// ////
-//// Revision : ////
-//// V.0 - June 8, 2021 ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-module spim_ctrl #(
- parameter ENDIEAN = 0 // 0 - Little, 1 - Big endian, since RISV is Little indian default set 0
- )
-
-(
- input logic clk,
- input logic rstn,
-
- input logic [7:0] spi_clk_div,
- output logic [8:0] spi_status,
-
- // Master 0 Configuration
- input logic [3:0] cfg_m0_cs_reg , // Chip select
- input logic [1:0] cfg_m0_spi_mode , // Final SPI Mode
- input logic [1:0] cfg_m0_spi_switch, // SPI Mode Switching Place
-
- input logic [3:0] cfg_m1_cs_reg , // Chip select
- input logic [1:0] cfg_m1_spi_mode , // Final SPI Mode
- input logic [1:0] cfg_m1_spi_switch, // SPI Mode Switching Place
-
- input logic [1:0] cfg_cs_early , // Amount of cycle early CS asserted
- input logic [1:0] cfg_cs_late , // Amount of cycle late CS de-asserted
-
- // Master 0 Command FIFO Interface
- input logic m0_cmd_fifo_empty,
- output logic m0_cmd_fifo_rd,
- input logic [33:0] m0_cmd_fifo_rdata,
-
- // Master 0 response FIFO Interface
- output logic m0_res_fifo_flush,
- input logic m0_res_fifo_empty,
- input logic m0_res_fifo_full,
- output logic m0_res_fifo_wr,
- output logic [31:0] m0_res_fifo_wdata,
-
- // Master 1 Command FIFO Interface
- output logic m1_res_fifo_flush,
- input logic m1_cmd_fifo_empty,
- output logic m1_cmd_fifo_rd,
- input logic [33:0] m1_cmd_fifo_rdata,
-
- // Master 1 response FIFO Interface
- input logic m1_res_fifo_empty,
- input logic m1_res_fifo_full,
- output logic m1_res_fifo_wr,
- output logic [31:0] m1_res_fifo_wdata,
-
- output logic [3:0] ctrl_state,
-
- output logic spi_clk,
- output logic spi_csn0,
- output logic spi_csn1,
- output logic spi_csn2,
- output logic spi_csn3,
- output logic [1:0] spi_mode,
- output logic spi_sdo0,
- output logic spi_sdo1,
- output logic spi_sdo2,
- output logic spi_sdo3,
- input logic spi_sdi0,
- input logic spi_sdi1,
- input logic spi_sdi2,
- input logic spi_sdi3,
- output logic spi_en_tx_out // Spi Direction control
-);
-
-//--------------------------------------
-// Parameter
-// --------------------------------------
-parameter P_SINGLE = 2'b00;
-parameter P_DOUBLE = 2'b01;
-parameter P_QUAD = 2'b10;
-parameter P_QDDR = 2'b11;
-
-
-/*************************************************************
-* SPI FSM State Control
-*
-* OPERATION COMMAND SEQUENCE
-*
-* ERASE P4E(0x20) -> COMMAND + ADDRESS
-* ERASE P8E(0x40) -> COMMAND + ADDRESS
-* ERASE SE(0xD8) -> COMMAND + ADDRESS
-* ERASE BE(0x60) -> COMMAND + ADDRESS
-* ERASE BE(0xC7) -> COMMAND
-* PROGRAM PP(0x02) -> COMMAND + ADDRESS + Write DATA
-* PROGRAM QPP(0x32) -> COMMAND + ADDRESS + Write DATA
-* READ READ(0x3) -> COMMAND + ADDRESS + READ DATA
-* READ FAST_READ(0xB) -> COMMAND + ADDRESS + DUMMY + READ DATA
-* READ DOR (0x3B) -> COMMAND + ADDRESS + DUMMY + READ DATA
-* READ QOR (0x6B) -> COMMAND + ADDRESS + DUMMY + READ DATA
-* READ DIOR (0xBB) -> COMMAND + ADDRESS + MODE + READ DATA
-* READ QIOR (0xEB) -> COMMAND + ADDRESS + MODE + DUMMY + READ DATA
-* READ RDID (0x9F) -> COMMAND + READ DATA
-* READ READ_ID (0x90) -> COMMAND + ADDRESS + READ DATA
-* WRITE WREN(0x6) -> COMMAND
-* WRITE WRDI -> COMMAND
-* STATUS RDSR(0x05) -> COMMAND + READ DATA
-* STATUS RCR(0x35) -> COMMAND + READ DATA
-* CONFIG WRR(0x01) -> COMMAND + WRITE DATA
-* CONFIG CLSR(0x30) -> COMMAND
-* Power Saving DP(0xB9) -> COMMAND
-* Power Saving RES(0xAB) -> COMMAND + READ DATA
-* OTP OTPP(0x42) -> COMMAND + ADDR+ WRITE DATA
-* OTP OTPR(0x4B) -> COMMAND + ADDR + DUMMY + READ DATA
-* ********************************************************************/
-parameter P_FSM_C = 4'b0000; // Command Phase Only
-parameter P_FSM_CW = 4'b0001; // Command + Write DATA Phase Only
-parameter P_FSM_CA = 4'b0010; // Command -> Address Phase Only
-
-parameter P_FSM_CAR = 4'b0011; // Command -> Address -> Read Data
-parameter P_FSM_CADR = 4'b0100; // Command -> Address -> Dummy -> Read Data
-parameter P_FSM_CAMR = 4'b0101; // Command -> Address -> Mode -> Read Data
-parameter P_FSM_CAMDR = 4'b0110; // Command -> Address -> Mode -> Dummy -> Read Data
-
-parameter P_FSM_CAW = 4'b0111; // Command -> Address ->Write Data
-parameter P_FSM_CADW = 4'b1000; // Command -> Address -> DUMMY + Write Data
-
-parameter P_FSM_CDR = 4'b1001; // COMMAND -> DUMMY -> READ
-parameter P_FSM_CDW = 4'b1010; // COMMAND -> DUMMY -> WRITE
-parameter P_FSM_CR = 4'b1011; // COMMAND -> READ
-
-//---------------------
- parameter P_8BIT = 2'b00;
- parameter P_16BIT = 2'b01;
- parameter P_24BIT = 2'b10;
- parameter P_32BIT = 2'b11;
-
-//---- Phase where to switch the SPI Mode
-//---- This need to decided based on command
- parameter P_MODE_SWITCH_IDLE = 2'b00;
- parameter P_MODE_SWITCH_AT_ADDR = 2'b01;
- parameter P_MODE_SWITCH_AT_DATA = 2'b10;
-//----------------------------------------
-// Local Variable
-// ---------------------------------------
- logic spi_rise;
- logic spi_fall;
-
- logic spi_clock_en;
-
- logic spi_en_rx;
- logic spi_en_tx;
-
-
- logic [15:0] counter_tx;
- logic counter_tx_valid;
- logic [15:0] counter_rx;
- logic counter_rx_valid;
-
- logic dummy_phase;
- logic [31:0] data_to_tx;
- logic data_to_tx_valid;
- logic data_to_tx_ready;
- logic tx_data_ready;
-
-
- logic tx_done;
- logic rx_done;
-
- logic [1:0] s_spi_mode;
-
- logic ctrl_data_valid;
-
- logic spi_cs;
-
- logic tx_clk_en;
- logic rx_clk_en;
- logic [1:0] cnt; // counter for cs assertion and de-assertion
- logic [1:0] nxt_cnt;
- logic [1:0] gnt;
-
- logic [7:0] cfg_data_cnt ;
- logic [1:0] cfg_dummy_cnt ;
- logic [1:0] cfg_addr_cnt ;
- logic [3:0] cfg_spi_seq ;
- logic [7:0] spi_mode_cmd ;
-
-
- enum logic [2:0] {DATA_NULL,DATA_EMPTY,DATA_CMD,DATA_ADDR,DATA_MODE,DATA_FIFO} ctrl_data_mux;
-
- enum logic [4:0] {FSM_IDLE,FSM_CS_ASSERT,FSM_CMD_PHASE,FSM_ADR_PHASE,FSM_DUMMY_PHASE,FSM_MODE_PHASE,FSM_WRITE_CMD,FSM_WRITE_PHASE,
- FSM_READ_WAIT,FSM_READ_PHASE,FSM_TX_DONE,FSM_FLUSH,FSM_CS_DEASEERT} state,next_state;
-
-
- assign ctrl_state = state[3:0];
-
- assign spi_mode = s_spi_mode;
-
- //----------------------------
- // Configuration
- //----------------------------
- logic [3:0] cfg_cs_reg ; // Chip select
- logic [1:0] cfg_spi_mode ; // Final SPI Mode
- logic [1:0] cfg_spi_switch; // SPI Mode Switching Place
-
-
- assign cfg_cs_reg = (gnt == 2'b01) ? cfg_m0_cs_reg : cfg_m1_cs_reg;
- assign cfg_spi_mode = (gnt == 2'b01) ? cfg_m0_spi_mode : cfg_m1_spi_mode; // Final SPI Mode
- assign cfg_spi_switch = (gnt == 2'b01) ? cfg_m0_spi_switch: cfg_m1_spi_switch; // SPI Mode Switching Place
-
- //----------------------------
- // Command FIFO
- //----------------------------
- logic cmd_fifo_empty;
- logic cmd_fifo_rd;
- logic [33:0] cmd_fifo_rdata;
-
- assign cmd_fifo_empty = (gnt == 2'b01) ? m0_cmd_fifo_empty : m1_cmd_fifo_empty;
- assign cmd_fifo_rdata = (gnt == 2'b01) ? m0_cmd_fifo_rdata : m1_cmd_fifo_rdata;
-
- assign m0_cmd_fifo_rd = (gnt == 2'b01) ? cmd_fifo_rd : 1'b0;
- assign m1_cmd_fifo_rd = (gnt == 2'b10) ? cmd_fifo_rd : 1'b0;
-
- //----------------------------
- // Response FIFO
- //----------------------------
- logic res_fifo_empty;
- logic res_fifo_full;
- logic res_fifo_wr;
- logic [31:0] res_fifo_wdata;
-
- assign res_fifo_empty = (gnt == 2'b01) ? m0_res_fifo_empty : m1_res_fifo_empty;
- assign res_fifo_full = (gnt == 2'b01) ? m0_res_fifo_full : m1_res_fifo_full;
-
- assign m0_res_fifo_wr = (gnt == 2'b01) ? res_fifo_wr : 1'b0;
- assign m1_res_fifo_wr = (gnt == 2'b10) ? res_fifo_wr : 1'b0;
-
- assign m0_res_fifo_wdata = (gnt == 2'b01) ? res_fifo_wdata : 1'b0;
- assign m1_res_fifo_wdata = (gnt == 2'b10) ? res_fifo_wdata : 1'b0;
-
- //---------------------------------------------------------------------------
- // To take care of partial/stall data in response fifo
- // we are flushing the content
- //
- // WARNING: This will work well for burst size 4,
- // If User given 6 Word Burst and Read only one location
- // Read Path will hang waiting for Response FIFO to empty, User need to take
- // care of partial reading case.
- //---------------------------------------------------------------------------
-
- logic fsm_flush;
- logic spi_dummy;
- assign m0_res_fifo_flush = (gnt == 2'b01) ? fsm_flush : 1'b0;
- assign m1_res_fifo_flush = (gnt == 2'b10) ? fsm_flush : 1'b0;
-
- assign spi_clock_en = tx_clk_en | rx_clk_en;
-
- assign spi_en_tx_out = (spi_en_tx) && (spi_dummy ==0); // Don't Drive Tx On Dummy Phase
-
- spim_clkgen u_clkgen
- (
- .clk ( clk ),
- .rstn ( rstn ),
- .en ( spi_clock_en ),
- .cfg_sck_period ( spi_clk_div [5:0] ),
- .spi_clk ( spi_clk ),
- .spi_fall ( spi_fall ),
- .spi_rise ( spi_rise )
- );
- spim_tx u_txreg
- (
- .clk ( clk ),
- .rstn ( rstn ),
- .flush ( fsm_flush ),
- .en ( spi_en_tx ),
- .tx_edge ( spi_fall ),
- .tx_done ( tx_done ),
- .sdo0 ( spi_sdo0 ),
- .sdo1 ( spi_sdo1 ),
- .sdo2 ( spi_sdo2 ),
- .sdo3 ( spi_sdo3 ),
- .s_spi_mode ( s_spi_mode ),
- .counter_in ( counter_tx ),
- .counter_in_upd ( counter_tx_valid ),
- .dummy_phase ( dummy_phase ),
- .txdata ( data_to_tx ),
- .data_valid ( data_to_tx_valid ),
- .data_ready ( tx_data_ready ),
- .spi_dummy ( spi_dummy ),
- .clk_en_o ( tx_clk_en )
- );
- spim_rx #(.ENDIEAN(ENDIEAN)) u_rxreg
- (
- .clk ( clk ),
- .rstn ( rstn ),
- .flush ( fsm_flush ),
- .en ( spi_en_rx ),
- .rx_edge ( spi_rise ),
- .rx_done ( rx_done ),
- .sdi0 ( spi_sdi0 ),
- .sdi1 ( spi_sdi1 ),
- .sdi2 ( spi_sdi2 ),
- .sdi3 ( spi_sdi3 ),
- .s_spi_mode ( s_spi_mode ),
- .counter_in ( counter_rx ),
- .counter_in_upd ( counter_rx_valid ),
- .data ( res_fifo_wdata ),
- .data_valid ( res_fifo_wr ),
- .data_ready ( !res_fifo_full ),
- .clk_en_o ( rx_clk_en )
- );
-
- always_comb
- begin
- data_to_tx = 'h0;
- data_to_tx_valid = 1'b0;
- dummy_phase = 1'b0;
-
- case(ctrl_data_mux)
- DATA_NULL:
- begin
- data_to_tx = '0;
- data_to_tx_valid = 1'b0;
- end
-
- DATA_EMPTY:
- begin
- dummy_phase = 1'b1;
- data_to_tx = '0;
- data_to_tx_valid = 1'b1;
- end
-
- DATA_CMD:
- begin
- data_to_tx = {cmd_fifo_rdata[7:0],24'h0};
- data_to_tx_valid = ctrl_data_valid;
- end
- DATA_MODE:
- begin
- data_to_tx = {spi_mode_cmd,24'h0};
- data_to_tx_valid = ctrl_data_valid;
- end
-
- DATA_ADDR:
- begin
- data_to_tx = (cfg_addr_cnt == P_8BIT) ? {cmd_fifo_rdata[7:0],24'h0} :
- (cfg_addr_cnt == P_16BIT) ? {cmd_fifo_rdata[15:0],16'h0} :
- (cfg_addr_cnt == P_24BIT) ? {cmd_fifo_rdata[23:0],8'h0} : {cmd_fifo_rdata[31:0]};
- data_to_tx_valid = ctrl_data_valid;
- end
-
- // RISV is little endian, so data is converted to little endian format
- DATA_FIFO: begin
- data_to_tx = (ENDIEAN) ? cmd_fifo_rdata[31:0] :
- {cmd_fifo_rdata[7:0],cmd_fifo_rdata[15:8],cmd_fifo_rdata[23:16],cmd_fifo_rdata[31:24]};
- data_to_tx_valid = !cmd_fifo_empty;
- end
- endcase
- end
-
- always_comb
- begin
- fsm_flush = 0;
- counter_tx = '0;
- counter_tx_valid = 1'b0;
- counter_rx = '0;
- counter_rx_valid = 1'b0;
- next_state = state;
- ctrl_data_mux = DATA_NULL;
- ctrl_data_valid = 1'b0;
- spi_en_rx = 1'b0;
- spi_en_tx = 1'b0;
- spi_status = '0;
- cmd_fifo_rd = 1'b0;
- nxt_cnt = cnt;
- case(state)
- FSM_IDLE:
- begin
- spi_status[0] = 1'b1;
- nxt_cnt = 0;
- if(!m0_cmd_fifo_empty || !m1_cmd_fifo_empty ) begin
- next_state = FSM_CS_ASSERT;
- end
- end
-
- // Asserted CS# low
- FSM_CS_ASSERT: begin
- fsm_flush=1; // Flush stale data in response fifo
- if(cfg_cs_early == cnt) begin
- next_state = FSM_CMD_PHASE;
- end else begin
- nxt_cnt = nxt_cnt+1;
- end
- end
-
- // WAIT for COMMAND Phase Completed
- FSM_CMD_PHASE: begin
- counter_tx = 8'h8;
- ctrl_data_mux = DATA_CMD;
- ctrl_data_valid = 1'b1;
- counter_tx = 'd8;
- counter_tx_valid = 1'b1;
- spi_en_tx = 1'b1;
- if (tx_data_ready) begin
- cmd_fifo_rd = 1'b1;
- case(cfg_spi_seq)
- P_FSM_C: next_state = FSM_TX_DONE;
- P_FSM_CW: next_state = FSM_WRITE_CMD;
- P_FSM_CA: next_state = FSM_ADR_PHASE;
- P_FSM_CAR: next_state = FSM_ADR_PHASE;
- P_FSM_CADR: next_state = FSM_ADR_PHASE;
- P_FSM_CAMR: next_state = FSM_ADR_PHASE;
- P_FSM_CAMDR: next_state = FSM_ADR_PHASE;
- P_FSM_CAW: next_state = FSM_ADR_PHASE;
- P_FSM_CADW: next_state = FSM_ADR_PHASE;
- P_FSM_CDR: next_state = FSM_DUMMY_PHASE;
- P_FSM_CDW: next_state = FSM_DUMMY_PHASE;
- P_FSM_CR: next_state = FSM_READ_WAIT;
- default : next_state = FSM_TX_DONE;
- endcase
- end
- end
-
- // WAIT for ADDR Command Accepted
- FSM_ADR_PHASE: begin
- nxt_cnt = 0;
- ctrl_data_mux = DATA_ADDR;
- ctrl_data_valid = 1'b1;
- counter_tx = (cfg_addr_cnt == P_8BIT) ? 'd8 :
- (cfg_addr_cnt == P_16BIT) ? 'd16 :
- (cfg_addr_cnt == P_24BIT) ? 'd24 : 'd32;
- counter_tx_valid = 1'b1;
- spi_en_tx = 1'b1;
- if (tx_data_ready) begin
- ctrl_data_valid = 1'b0;
- cmd_fifo_rd = 1'b1;
- case(cfg_spi_seq)
- P_FSM_CA: next_state = FSM_TX_DONE;
- P_FSM_CAR: next_state = FSM_READ_WAIT;
- P_FSM_CADR: next_state = FSM_DUMMY_PHASE;
- P_FSM_CAMR: next_state = FSM_MODE_PHASE;
- P_FSM_CAMDR: next_state = FSM_MODE_PHASE;
- P_FSM_CAW: next_state = FSM_WRITE_CMD;
- P_FSM_CADW: next_state = FSM_DUMMY_PHASE;
- default : next_state = FSM_TX_DONE;
- endcase
- end
- end
-
- // WAIT for DUMMY command Accepted
- FSM_DUMMY_PHASE: begin
- nxt_cnt = 0;
- ctrl_data_mux = DATA_EMPTY;
- ctrl_data_valid = 1'b1;
- counter_tx_valid = 1'b1;
- if(s_spi_mode == P_QDDR ) begin
- // QDDR Mode, change the Dummy cycle values to 32,40,48,56
- counter_tx = (cfg_dummy_cnt == 2'b00) ? 'd32 :
- (cfg_dummy_cnt == 2'b01) ? 'd40 :
- (cfg_dummy_cnt == 2'b10) ? 'd48 : 'd56;
- end else begin
- counter_tx = (cfg_dummy_cnt == P_8BIT) ? 'd8 :
- (cfg_dummy_cnt == P_16BIT) ? 'd16 :
- (cfg_dummy_cnt == P_24BIT) ? 'd24 : 'd32;
- end
- spi_en_tx = 1'b1;
- if (tx_data_ready) begin
- ctrl_data_valid = 1'b0;
- case(cfg_spi_seq)
- P_FSM_CADR: next_state = FSM_READ_WAIT;
- P_FSM_CAMDR: next_state = FSM_READ_WAIT;
- P_FSM_CADW: next_state = FSM_WRITE_CMD;
- P_FSM_CDR: next_state = FSM_READ_WAIT;
- P_FSM_CDW: next_state = FSM_WRITE_CMD;
- default : next_state = FSM_CS_DEASEERT;
- endcase
- end
- end
- // WAIT for MODE command accepted
- FSM_MODE_PHASE: begin
- nxt_cnt = 0;
- ctrl_data_mux = DATA_MODE;
- ctrl_data_valid = 1'b1;
- counter_tx_valid = 1'b1;
- counter_tx = 'd8;
- spi_en_tx = 1'b1;
- if (tx_data_ready) begin
- case(cfg_spi_seq)
- P_FSM_CAMR: next_state = FSM_READ_WAIT;
- P_FSM_CAMDR: next_state = FSM_DUMMY_PHASE;
- default : next_state = FSM_CS_DEASEERT;
- endcase
- end
- end
-
- // Wait for WRITE COMMAND ACCEPTED
- FSM_WRITE_CMD: begin
- nxt_cnt = 0;
- ctrl_data_mux = DATA_FIFO;
- ctrl_data_valid = 1'b1;
- counter_tx_valid = 1'b1;
- counter_tx = {5'b0,cfg_data_cnt[7:0],3'b000}; // Convert Byte to Bit Count
- spi_en_tx = 1'b1;
- if (tx_data_ready) begin
- cmd_fifo_rd = 1'b1;
- next_state = FSM_WRITE_PHASE;
- end
- end
-
- // Wait for ALL WRITE DATA ACCEPTED
- FSM_WRITE_PHASE: begin
- nxt_cnt = 0;
- ctrl_data_mux = DATA_FIFO;
- ctrl_data_valid = 1'b1;
- spi_en_tx = 1'b1;
- if (tx_done) begin
- next_state = FSM_CS_DEASEERT;
- end else if(tx_data_ready && cmd_fifo_empty == 0) begin
- // Once Current Data is accepted by TX FSM, check FIFO not empty
- // and read next location
- cmd_fifo_rd = 1'b1;
- end
- end
-
- // Wait for Previous TX Completeion
- FSM_READ_WAIT: begin
- spi_en_tx = 1'b1;
- if (tx_done) begin
- next_state = FSM_READ_PHASE;
- end
- end
-
- FSM_READ_PHASE: begin
- nxt_cnt = 0;
- counter_rx_valid = 1'b1;
- counter_rx = {5'b0,cfg_data_cnt[7:0],3'b000}; // Convert Byte to Bit Count
- spi_en_rx = 1'b1;
- if(!cmd_fifo_empty) begin
- // If you see new command request, then abort the current request
- next_state = FSM_FLUSH;
- end else begin
- if (rx_done) begin
- next_state = FSM_CS_DEASEERT;
- end
- end
- end
-
- FSM_FLUSH: begin
- fsm_flush = 1;
- // Wait for safe SPI-clock de-assertion phase
- if(spi_clock_en ==0) begin
- next_state = FSM_CS_DEASEERT;
- end
- end
- // Wait for TX Done
- FSM_TX_DONE: begin
- spi_en_tx = 1'b1;
- if(tx_done) next_state = FSM_CS_DEASEERT;
- end
-
- // De-assert CS#
- FSM_CS_DEASEERT: begin
- if(cfg_cs_late == cnt) begin
- next_state = FSM_IDLE;
- end else begin
- nxt_cnt = nxt_cnt+1;
- end
- end
- endcase
-end
-
-
-
-
- always @(posedge clk or negedge rstn) begin
- if (rstn == 1'b0) begin
- state <= FSM_IDLE;
- cnt <= 'h0;
- end else begin
- state <= next_state;
- cnt <= nxt_cnt;
- end
- end
-
- //---------------------------------------------------------------------
- // Grant Generation Based on FIFO empty, priority given to Master 0
- // Grant switch happens only at FSM IDLE State
- // ---------------------------------------------------------------------
-
- always @(posedge clk or negedge rstn) begin
- if (rstn == 1'b0) begin
- gnt <= 0;
- spi_mode_cmd <= 'h0;
- cfg_spi_seq <= 'h0;
- cfg_addr_cnt <= 'h0;
- cfg_dummy_cnt <= 'h0;
- cfg_data_cnt <= 'h0;
- end else begin
- if(state == FSM_IDLE) begin
- if(!m0_cmd_fifo_empty) begin
- cfg_data_cnt <= m0_cmd_fifo_rdata[31:24];
- cfg_dummy_cnt <= m0_cmd_fifo_rdata[23:22];
- cfg_addr_cnt <= m0_cmd_fifo_rdata[21:20];
- cfg_spi_seq <= m0_cmd_fifo_rdata[19:16];
- spi_mode_cmd <= m0_cmd_fifo_rdata[15:8];
- gnt <= 2'b01;
- end
- else if(!m1_cmd_fifo_empty ) begin
- cfg_data_cnt <= m1_cmd_fifo_rdata[31:24];
- cfg_dummy_cnt <= m1_cmd_fifo_rdata[23:22];
- cfg_addr_cnt <= m1_cmd_fifo_rdata[21:20];
- cfg_spi_seq <= m1_cmd_fifo_rdata[19:16];
- spi_mode_cmd <= m1_cmd_fifo_rdata[15:8];
- gnt <= 2'b10;
- end
- end
- end
- end
-
-
- //-----------------------------------------------------------------------
- // SPI Mode Switch Control Logic
- // Note: SPI Protocl Start with SPI_STD Mode (Sigle Bit Mode) Base on the
- // Command, Type it Switch the mode at ADDRESS/DUMMY/DATA Phase
- // QIOR(0xEB) -> Mode switch at Address Phase
- // DIOR(0xBB) -> Mode Switch at Address Phase
- // QOR (0x6B) -> Mode Switch at Data Phase
- // DOR (0x3B) -> Mode Switch at Data Phase
- // QPP (0x32) -> Mode Switch at Data Phase
- // ----------------------------------------------------------------------
- always @(posedge clk or negedge rstn) begin
- if (rstn == 1'b0) begin
- s_spi_mode <= P_SINGLE;
- end else begin
- if(state == FSM_IDLE) begin // Reset the Mode at IDLE State
- s_spi_mode <= P_SINGLE;
- end else if(state == FSM_ADR_PHASE && cfg_spi_switch == P_MODE_SWITCH_AT_ADDR) begin
- s_spi_mode <= cfg_spi_mode;
- end else if(((state == FSM_READ_PHASE) || state == FSM_WRITE_CMD ) && cfg_spi_switch == P_MODE_SWITCH_AT_DATA) begin
- s_spi_mode <= cfg_spi_mode;
- end
- end
- end
-
- // SPI Chip Select Logic
- always @(posedge clk or negedge rstn) begin
- if (rstn == 1'b0) begin
- spi_csn0 <= 1'b1;
- spi_csn1 <= 1'b1;
- spi_csn2 <= 1'b1;
- spi_csn3 <= 1'b1;
- end else begin
- if(state != FSM_IDLE) begin
- spi_csn0 <= ~cfg_cs_reg[0];
- spi_csn1 <= ~cfg_cs_reg[1];
- spi_csn2 <= ~cfg_cs_reg[2];
- spi_csn3 <= ~cfg_cs_reg[3];
- end else begin
- spi_csn0 <= 1'b1;
- spi_csn1 <= 1'b1;
- spi_csn2 <= 1'b1;
- spi_csn3 <= 1'b1;
- end
- end
- end
-
-endmodule
-
diff --git a/verilog/rtl/spi_master/src/spim_fifo.sv b/verilog/rtl/spi_master/src/spim_fifo.sv
deleted file mode 100644
index b16a1b3..0000000
--- a/verilog/rtl/spi_master/src/spim_fifo.sv
+++ /dev/null
@@ -1,227 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-/*********************************************************************
-
- SYNC FIFO
-
- This file is part of the yifive project
- https://github.com/dineshannayya/yifive_r0.git
-
- Description: SYNC FIFO
-
- To Do:
- nothing
-
- Author(s): Dinesh Annayya, dinesha@opencores.org
-
- Copyright (C) 2000 Authors and OPENCORES.ORG
-
- This source file may be used and distributed without
- restriction provided that this copyright statement is not
- removed from the file and that any derivative work contains
- the original copyright notice and the associated disclaimer.
-
- This source file is free software; you can redistribute it
- and/or modify it under the terms of the GNU Lesser General
- Public License as published by the Free Software Foundation;
- either version 2.1 of the License, or (at your option) any
-later version.
-
- This source is distributed in the hope that it will be
- useful, but WITHOUT ANY WARRANTY; without even the implied
- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
- PURPOSE. See the GNU Lesser General Public License for more
- details.
-
- You should have received a copy of the GNU Lesser General
- Public License along with this source; if not, download it
- from http://www.opencores.org/lgpl.shtml
-
-*******************************************************************/
-
-//-------------------------------------------
-// sync FIFO
-//-----------------------------------------------
-//`timescale 1ns/1ps
-
-module spim_fifo (clk,
- reset_n,
- flush,
- wr_en,
- wr_data,
- full,
- afull,
- rd_en,
- empty,
- aempty,
- rd_data);
-
- parameter W = 4'd8;
- parameter DP = 3'd4;
- parameter WR_FAST = 1'b1;
- parameter RD_FAST = 1'b1;
- parameter FULL_DP = DP;
- parameter EMPTY_DP = 1'b0;
-
- parameter AW = (DP == 2) ? 1 :
- (DP == 4) ? 2 :
- (DP == 8) ? 3 :
- (DP == 16) ? 4 :
- (DP == 32) ? 5 :
- (DP == 64) ? 6 :
- (DP == 128) ? 7 :
- (DP == 256) ? 8 : 0;
-
- output [W-1 : 0] rd_data;
- input [W-1 : 0] wr_data;
- input clk, reset_n, wr_en,flush,
- rd_en;
- output full, empty;
- output afull, aempty; // about full and about to empty
-
-
- // synopsys translate_off
-
- initial begin
- if (AW == 0) begin
- $display ("%m : ERROR!!! Fifo depth %d not in range 2 to 256", DP);
- end // if (AW == 0)
- end // initial begin
-
- // synopsys translate_on
-
- reg [W-1 : 0] mem[DP-1 : 0];
-
- /*********************** write side ************************/
- reg [AW:0] wr_ptr;
- reg full_q;
- wire full_c;
- wire afull_c;
- wire [AW:0] wr_ptr_inc = wr_ptr + 1'b1;
- wire [AW:0] wr_cnt = get_cnt(wr_ptr, rd_ptr);
-
- assign full_c = (wr_cnt == FULL_DP) ? 1'b1 : 1'b0;
- assign afull_c = (wr_cnt == FULL_DP-1) ? 1'b1 : 1'b0;
-
-
- always @(posedge clk or negedge reset_n) begin
- if (!reset_n) begin
- wr_ptr <= 0;
- full_q <= 0;
- end
- else begin
- if(flush) begin
- wr_ptr <= 0;
- full_q <= 0;
- end else if (wr_en) begin
- wr_ptr <= wr_ptr_inc;
- if (wr_cnt == (FULL_DP-1)) begin
- full_q <= 1'b1;
- end
- end else begin
- if (full_q && (wr_cnt<FULL_DP)) begin
- full_q <= 1'b0;
- end
- end
- end
- end
-
- assign full = (WR_FAST == 1) ? full_c : full_q;
- assign afull = afull_c;
-
- always @(posedge clk) begin
- if (wr_en) begin
- mem[wr_ptr[AW-1:0]] <= wr_data;
- end
- end
-
-
- /************************ read side *****************************/
- reg [AW:0] rd_ptr;
- reg empty_q;
- wire empty_c;
- wire aempty_c;
- wire [AW:0] rd_ptr_inc = rd_ptr + 1'b1;
- wire [AW:0] rd_cnt = get_cnt(wr_ptr, rd_ptr);
-
- assign empty_c = (rd_cnt == 0) ? 1'b1 : 1'b0;
- assign aempty_c = (rd_cnt == 1) ? 1'b1 : 1'b0;
-
- always @(posedge clk or negedge reset_n) begin
- if (!reset_n) begin
- rd_ptr <= 0;
- empty_q <= 1'b1;
- end
- else begin
- if(flush) begin
- rd_ptr <= 0;
- empty_q <= 1'b1;
- end else if (rd_en) begin
- rd_ptr <= rd_ptr_inc;
- if (rd_cnt==(EMPTY_DP+1)) begin
- empty_q <= 1'b1;
- end
- end else begin
- if (empty_q && (rd_cnt!=EMPTY_DP)) begin
- empty_q <= 1'b0;
- end
- end
- end
- end
-
- assign empty = (RD_FAST == 1) ? empty_c : empty_q;
- assign aempty = aempty_c;
-
- reg [W-1 : 0] rd_data_q;
-
- wire [W-1 : 0] rd_data_c = mem[rd_ptr[AW-1:0]];
- always @(posedge clk) begin
- rd_data_q <= rd_data_c;
- end
- assign rd_data = (RD_FAST == 1) ? rd_data_c : rd_data_q;
-
-
-function [AW:0] get_cnt;
-input [AW:0] wr_ptr, rd_ptr;
-begin
- if (wr_ptr >= rd_ptr) begin
- get_cnt = (wr_ptr - rd_ptr);
- end
- else begin
- get_cnt = DP*2 - (rd_ptr - wr_ptr);
- end
-end
-endfunction
-
-// synopsys translate_off
-always @(posedge clk) begin
- if (wr_en && full) begin
- $display($time, "%m Error! afifo overflow!");
- $stop;
- end
-end
-
-always @(posedge clk) begin
- if (rd_en && empty) begin
- $display($time, "%m error! afifo underflow!");
- $stop;
- end
-end
-// synopsys translate_on
-
-endmodule
diff --git a/verilog/rtl/spi_master/src/spim_if.sv b/verilog/rtl/spi_master/src/spim_if.sv
deleted file mode 100644
index d47adcb..0000000
--- a/verilog/rtl/spi_master/src/spim_if.sv
+++ /dev/null
@@ -1,335 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// SPI WishBone I/F Module ////
-//// ////
-//// This file is part of the YIFive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
-//// ////
-//// Description ////
-//// SPI WishBone I/F module ////
-//// This block support following functionality ////
-//// 1. This block Response to Direct Memory Read and ////
-//// Register Write and Read Command ////
-//// 2. In case of Direct Memory Read, It check send the ////
-//// SPI Read command to SPI Ctrl logic and wait for ////
-//// Read data through Response ////
-//// ////
-//// To Do: ////
-//// 1. Add 4 Word Memory Fetch for better Through Put ////
-//// ////
-//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
-//// ////
-//// Revision : ////
-//// V.0 - June 30, 2021 ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-
-
-module spim_if #( parameter WB_WIDTH = 32) (
- input logic mclk,
- input logic rst_n,
-
- input logic wbd_stb_i, // strobe/request
- input logic [WB_WIDTH-1:0] wbd_adr_i, // address
- input logic wbd_we_i, // write
- input logic [WB_WIDTH-1:0] wbd_dat_i, // data output
- input logic [3:0] wbd_sel_i, // byte enable
- output logic [WB_WIDTH-1:0] wbd_dat_o, // data input
- output logic wbd_ack_o, // acknowlegement
- output logic wbd_err_o, // error
-
-
- // Configuration
- input logic cfg_fsm_reset,
- input logic [3:0] cfg_mem_seq, // SPI MEM SEQUENCE
- input logic [1:0] cfg_addr_cnt, // SPI Addr Count
- input logic [1:0] cfg_dummy_cnt, // SPI Dummy Count
- input logic [7:0] cfg_data_cnt, // SPI Read Count
- input logic [7:0] cfg_cmd_reg, // SPI MEM COMMAND
- input logic [7:0] cfg_mode_reg, // SPI MODE REG
- input logic spi_init_done, // SPI internal Init completed
-
- // Towards Reg I/F
- output logic spim_reg_req, // Reg Request
- output logic [3:0] spim_reg_addr, // Reg Address
- output logic spim_reg_we, // Reg Write/Read Command
- output logic [3:0] spim_reg_be, // Reg Byte Enable
- output logic [31:0] spim_reg_wdata, // Reg Write Data
- input logic spim_reg_ack, // Read Ack
- input logic [31:0] spim_reg_rdata, // Read Read Data
-
- // Towards Command FIFO
- input logic cmd_fifo_empty, // Command FIFO empty
- output logic cmd_fifo_wr, // Command FIFO Write
- output logic [33:0] cmd_fifo_wdata, // Command FIFO WData
-
- // Towards Response FIFO
- input logic res_fifo_empty, // Response FIFO Empty
- output logic res_fifo_rd, // Response FIFO Read
- input logic [31:0] res_fifo_rdata, // Response FIFO Data
-
- output logic [3:0] state
- );
-
-//------------------------------------------------
-// Parameter Decleration
-// -----------------------------------------------
-parameter SOC = 1'b1; // START of COMMAND
-parameter EOC = 1'b1; // END of COMMAND
-parameter NOC = 1'b0; // NORMAL COMMAND
-
-// State Machine state
-parameter IDLE = 4'b000;
-parameter ADR_PHASE = 4'b001;
-parameter CMD_WAIT = 4'b010;
-parameter READ_DATA = 4'b011;
-
-/*************************************************************
-* SPI FSM State Control
-*
-* OPERATION COMMAND SEQUENCE
-*
-* ERASE P4E(0x20) -> COMMAND + ADDRESS
-* ERASE P8E(0x40) -> COMMAND + ADDRESS
-* ERASE SE(0xD8) -> COMMAND + ADDRESS
-* ERASE BE(0x60) -> COMMAND + ADDRESS
-* ERASE BE(0xC7) -> COMMAND
-* PROGRAM PP(0x02) -> COMMAND + ADDRESS + Write DATA
-* PROGRAM QPP(0x32) -> COMMAND + ADDRESS + Write DATA
-* READ READ(0x3) -> COMMAND + ADDRESS + READ DATA
-* READ FAST_READ(0xB) -> COMMAND + ADDRESS + DUMMY + READ DATA
-* READ DOR (0x3B) -> COMMAND + ADDRESS + DUMMY + READ DATA
-* READ QOR (0x6B) -> COMMAND + ADDRESS + DUMMY + READ DATA
-* READ DIOR (0xBB) -> COMMAND + ADDRESS + MODE + READ DATA
-* READ QIOR (0xEB) -> COMMAND + ADDRESS + MODE + DUMMY + READ DATA
-* READ RDID (0x9F) -> COMMAND + READ DATA
-* READ READ_ID (0x90) -> COMMAND + ADDRESS + READ DATA
-* WRITE WREN(0x6) -> COMMAND
-* WRITE WRDI -> COMMAND
-* STATUS RDSR(0x05) -> COMMAND + READ DATA
-* STATUS RCR(0x35) -> COMMAND + READ DATA
-* CONFIG WRR(0x01) -> COMMAND + WRITE DATA
-* CONFIG CLSR(0x30) -> COMMAND
-* Power Saving DP(0xB9) -> COMMAND
-* Power Saving RES(0xAB) -> COMMAND + READ DATA
-* OTP OTPP(0x42) -> COMMAND + ADDR+ WRITE DATA
-* OTP OTPR(0x4B) -> COMMAND + ADDR + DUMMY + READ DATA
-* ********************************************************************/
-
-parameter P_FSM_C = 4'b0000; // Command Phase Only
-parameter P_FSM_CA = 4'b0001; // Command -> Address Phase Only
-
-parameter P_FSM_CAR = 4'b0010; // Command -> Address -> Read Data
-parameter P_FSM_CADR = 4'b0011; // Command -> Address -> Dummy -> Read Data
-parameter P_FSM_CAMR = 4'b0100; // Command -> Address -> Mode -> Read Data
-parameter P_FSM_CAMDR = 4'b0101; // Command -> Address -> Mode -> Dummy -> Read Data
-
-parameter P_FSM_CAW = 4'b0110; // Command -> Address ->Write Data
-parameter P_FSM_CADW = 4'b0111; // Command -> Address -> DUMMY + Write Data
-//---------------------------------------------------------
-// Variable declartion
-// -------------------------------------------------------
-logic spim_mem_req ; // Current Request is Direct Memory Read
-
-
-logic spim_wb_req ;
-logic [WB_WIDTH-1:0] spim_wb_wdata ;
-logic [WB_WIDTH-1:0] spim_wb_addr ;
-logic spim_wb_ack ;
-logic spim_wb_we ;
-logic [3:0] spim_wb_be ;
-logic [WB_WIDTH-1:0] spi_mem_rdata ;
-logic [WB_WIDTH-1:0] spim_wb_rdata ;
-
-logic spim_mem_ack ;
-logic [3:0] next_state ;
-
-logic NextPreDVal ;
-logic [7:0] NextPreDCnt ;
-logic [31:0] NextPreAddr ;
-
-
- //---------------------------------------------------------------
- // Address Decoding
- // 0x0000_0000 - 0x0FFF_FFFF - SPI FLASH MEMORY ACCESS - 256MB
- // 0x1000_0000 - - SPI Register Access
- //
- //
- // Note: Only Bit[28] is decoding done here, other Bit decoding
- // will be done inside the wishbone inter-connect
- // --------------------------------------------------------------
-
- assign spim_mem_req = ((spim_wb_req) && spim_wb_addr[28] == 1'b0);
- assign spim_reg_req = ((spim_wb_req) && spim_wb_addr[28] == 1'b1);
-
- assign spim_reg_addr = spim_wb_addr[5:2];
- assign spim_reg_wdata = spim_wb_wdata;
- assign spim_reg_we = spim_wb_we;
- assign spim_reg_be = spim_wb_be;
-
- assign wbd_dat_o = spim_wb_rdata;
- assign wbd_ack_o = spim_wb_ack;
- assign wbd_err_o = 1'b0;
-
- // To reduce the load/Timing Wishbone I/F, all the variable are registered
-always_ff @(negedge rst_n or posedge mclk) begin
- if ( rst_n == 1'b0 ) begin
- spim_wb_req <= '0;
- spim_wb_wdata <= '0;
- spim_wb_rdata <= '0;
- spim_wb_addr <= '0;
- spim_wb_be <= '0;
- spim_wb_we <= '0;
- spim_wb_ack <= '0;
- end else begin
- if(spi_init_done) begin // Wait for internal SPI Init Done
- spim_wb_req <= wbd_stb_i && ((spim_wb_ack == 0) && (spim_mem_ack ==0) && (spim_reg_ack == 0));
- spim_wb_wdata <= wbd_dat_i;
- spim_wb_addr <= wbd_adr_i;
- spim_wb_be <= wbd_sel_i;
- spim_wb_we <= wbd_we_i;
-
-
- if(!spim_wb_we && spim_mem_req && spim_mem_ack)
- spim_wb_rdata <= spi_mem_rdata;
- else if (spim_reg_req && spim_reg_ack)
- spim_wb_rdata <= spim_reg_rdata;
-
- spim_wb_ack <= (spim_mem_req) ? spim_mem_ack :
- (spim_reg_req) ? spim_reg_ack : 1'b0;
- end
- end
-end
-
-
-always_ff @(negedge rst_n or posedge mclk) begin
- if ( rst_n == 1'b0 ) begin
- state <= IDLE;
- end else begin
- if(cfg_fsm_reset) state <= IDLE;
- else state <= next_state;
- end
-end
-
-/***********************************************************************************
-* This block interface with WishBone Request and Write Command & Read Response FIFO
-* **********************************************************************************/
-
-always_comb
-begin
- cmd_fifo_wr = '0;
- cmd_fifo_wdata = '0;
- res_fifo_rd = 0;
- spi_mem_rdata = '0;
-
- spim_mem_ack = 0;
- next_state = state;
- case(state)
- IDLE: begin
- // Check If any prefetch data available and if see it matched with WB
- // address, If yes, the move to data reading from response fifo, else
- // generate command request
- if(spim_mem_req && NextPreDVal && (spim_wb_addr == NextPreAddr)) begin
- next_state = READ_DATA;
- end else if(spim_mem_req && cmd_fifo_empty) begin
- cmd_fifo_wdata = {SOC,NOC,cfg_data_cnt[7:0],cfg_dummy_cnt[1:0],cfg_addr_cnt[1:0],cfg_mem_seq[3:0],cfg_mode_reg[7:0],cfg_cmd_reg[7:0]};
- cmd_fifo_wr = 1;
- next_state = ADR_PHASE;
- end
- end
- ADR_PHASE: begin
- cmd_fifo_wdata = {NOC,EOC,spim_wb_addr[31:0]};
- cmd_fifo_wr = 1;
- next_state = CMD_WAIT;
- end
- CMD_WAIT: begin
- // Wait for Command Accepted, before reading data
- // to take care of staled data being read due to pre-fetch logic
- if(cmd_fifo_empty) next_state = READ_DATA;
- end
-
-
- READ_DATA: begin
- if(res_fifo_empty != 1) begin
- spi_mem_rdata = res_fifo_rdata;
- res_fifo_rd = 1;
- spim_mem_ack = 1;
- next_state = IDLE;
- end
- end
- endcase
-end
-
-/*****************************************************************
-* This logic help to find any pre-fetch data available inside the response
-* FIFO and if the next data read request address matches with NextPreAddr, The read
-* the data from Response FIFO, else generate new request
-* Note: Basic Assumption is cmd_fifo_wr & res_fifo_rd does not occur in same
-* time as it's generation control through FSM
-* **********************************************************/
-
-always_ff @(negedge rst_n or posedge mclk) begin
- if ( rst_n == 1'b0 ) begin
- NextPreDVal <= 1'b0;
- NextPreDCnt <= 'h0;
- NextPreAddr <= 'h0;
- end else if(cmd_fifo_wr) begin
- NextPreDVal <= 1'b1;
- NextPreDCnt <= cfg_data_cnt;
- NextPreAddr <= spim_wb_addr;
- end else if (res_fifo_rd) begin
- if(NextPreDCnt == 4) begin
- NextPreDVal <= 1'b0;
- end else begin
- NextPreDCnt <= NextPreDCnt-4;
- NextPreAddr <= NextPreAddr+4;
- end
- end
-end
-
-
-endmodule
diff --git a/verilog/rtl/spi_master/src/spim_regs.sv b/verilog/rtl/spi_master/src/spim_regs.sv
deleted file mode 100644
index 0885fe0..0000000
--- a/verilog/rtl/spi_master/src/spim_regs.sv
+++ /dev/null
@@ -1,753 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// SPI WishBone Register I/F Module ////
-//// ////
-//// This file is part of the YIFive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
-//// ////
-//// Description ////
-//// SPI WishBone I/F module ////
-//// This block support following functionality ////
-//// 1. Direct SPI Read memory support for address rang ////
-//// 0x0000 to 0x0FFF_FFFF - Use full for Instruction ////
-//// Data Memory fetch ////
-//// 2. SPI Local Register Access ////
-//// 3. Indirect register way to access SPI Memory ////
-//// ////
-//// To Do: ////
-//// nothing ////
-//// ////
-//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
-//// ////
-//// Revision : ////
-//// V.0 - June 8, 2021 ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-
-
-module spim_regs #( parameter WB_WIDTH = 32) (
- input logic mclk ,
- input logic rst_n ,
- input logic fast_sim_mode , // Set 1 for simulation
-
- output logic [7:0] spi_clk_div ,
- output logic spi_init_done , // SPI internal Init completed
-
- // Status Monitoring
- input logic [31:0] spi_debug ,
-
- // Master 0 Configuration
- output logic cfg_m0_fsm_reset ,
- output logic [3:0] cfg_m0_cs_reg , // Chip select
- output logic [1:0] cfg_m0_spi_mode , // Final SPI Mode
- output logic [1:0] cfg_m0_spi_switch, // SPI Mode Switching Place
- output logic [3:0] cfg_m0_spi_seq , // SPI SEQUENCE
- output logic [1:0] cfg_m0_addr_cnt , // SPI Addr Count
- output logic [1:0] cfg_m0_dummy_cnt , // SPI Dummy Count
- output logic [7:0] cfg_m0_data_cnt , // SPI Read Count
- output logic [7:0] cfg_m0_cmd_reg , // SPI MEM COMMAND
- output logic [7:0] cfg_m0_mode_reg , // SPI MODE REG
-
- output logic [3:0] cfg_m1_cs_reg , // Chip select
- output logic [1:0] cfg_m1_spi_mode , // Final SPI Mode
- output logic [1:0] cfg_m1_spi_switch, // SPI Mode Switching Place
-
- output logic [1:0] cfg_cs_early , // Amount of cycle early CS asserted
- output logic [1:0] cfg_cs_late , // Amount of cycle late CS de-asserted
-
- // Towards Reg I/F
- input logic spim_reg_req , // Reg Request
- input logic [3:0] spim_reg_addr , // Reg Address
- input logic spim_reg_we , // Reg Write/Read Command
- input logic [3:0] spim_reg_be , // Reg Byte Enable
- input logic [31:0] spim_reg_wdata , // Reg Write Data
- output logic spim_reg_ack , // Read Ack
- output logic [31:0] spim_reg_rdata , // Read Read Data
-
- // Towards Command FIFO
- input logic cmd_fifo_full , // Command FIFO full
- input logic cmd_fifo_empty , // Command FIFO empty
- output logic cmd_fifo_wr , // Command FIFO Write
- output logic [33:0] cmd_fifo_wdata , // Command FIFO WData
-
- // Towards Response FIFO
- input logic res_fifo_full , // Response FIFO Empty
- input logic res_fifo_empty , // Response FIFO Empty
- output logic res_fifo_rd , // Response FIFO Read
- input logic [31:0] res_fifo_rdata , // Response FIFO Data
-
- output logic [3:0] state
- );
-//------------------------------------------------
-// Parameter Decleration
-// -----------------------------------------------
-parameter SOC = 1'b1; // START of COMMAND
-parameter EOC = 1'b1; // END of COMMAND
-parameter NOC = 1'b0; // NORMAL COMMAND
-
-parameter BTYPE = 1'b0; // Count is Byte Type
-parameter WTYPE = 1'b1; // Count is Word Type
-
-parameter CNT1 = 2'b00; // BYTE/WORD Count1
-parameter CNT2 = 2'b01; // BYTE/WORD Count2
-parameter CNT3 = 2'b10; // BYTE/WORD Count3
-parameter CNT4 = 2'b11; // BYTE/WORD Count4
-
-
-// Type of command
-parameter NWRITE = 2'b00; // Normal Write
-parameter NREAD = 2'b01; // Normal Read
-parameter DWRITE = 2'b10; // Dummy Write
-parameter DREAD = 2'b11; // Dummy Read
-
-// State Machine state
-parameter FSM_IDLE = 3'b000;
-parameter FSM_ADR_PHASE = 3'b001;
-parameter FSM_WRITE_PHASE = 3'b010;
-parameter FSM_READ_PHASE = 3'b011;
-parameter FSM_READ_BUSY = 3'b100;
-parameter FSM_WRITE_BUSY = 3'b101;
-parameter FSM_ACK_PHASE = 3'b110;
-
-//----------------------------
-// Register Decoding
-// ---------------------------
-parameter GLBL_CTRL = 4'b0000;
-parameter DMEM_CTRL1 = 4'b0001;
-parameter DMEM_CTRL2 = 4'b0010;
-parameter IMEM_CTRL1 = 4'b0011;
-parameter IMEM_CTRL2 = 4'b0100;
-parameter IMEM_ADDR = 4'b0101;
-parameter IMEM_WDATA = 4'b0110;
-parameter IMEM_RDATA = 4'b0111;
-parameter SPI_STATUS = 4'b1000;
-
-// Init FSM
-parameter SPI_INIT_PWUP = 3'b000;
-parameter SPI_INIT_IDLE = 3'b001;
-parameter SPI_INIT_CMD_WAIT = 3'b010;
-parameter SPI_INIT_WREN_CMD = 3'b011;
-parameter SPI_INIT_WREN_WAIT = 3'b100;
-parameter SPI_INIT_WRR_CMD = 3'b101;
-parameter SPI_INIT_WRR_WAIT = 3'b110;
-parameter SPI_INIT_WAIT = 3'b111;
-
-/*************************************************************
-* SPI FSM State Control
-*
-* OPERATION COMMAND SEQUENCE
-*
-* ERASE P4E(0x20) -> COMMAND + ADDRESS
-* ERASE P8E(0x40) -> COMMAND + ADDRESS
-* ERASE SE(0xD8) -> COMMAND + ADDRESS
-* ERASE BE(0x60) -> COMMAND + ADDRESS
-* ERASE BE(0xC7) -> COMMAND
-* PROGRAM PP(0x02) -> COMMAND + ADDRESS + Write DATA
-* PROGRAM QPP(0x32) -> COMMAND + ADDRESS + Write DATA
-* READ READ(0x3) -> COMMAND + ADDRESS + READ DATA
-* READ FAST_READ(0xB) -> COMMAND + ADDRESS + DUMMY + READ DATA
-* READ DOR (0x3B) -> COMMAND + ADDRESS + DUMMY + READ DATA
-* READ QOR (0x6B) -> COMMAND + ADDRESS + DUMMY + READ DATA
-* READ DIOR (0xBB) -> COMMAND + ADDRESS + MODE + READ DATA
-* READ QIOR (0xEB) -> COMMAND + ADDRESS + MODE + DUMMY + READ DATA
-* READ RDID (0x9F) -> COMMAND + READ DATA
-* READ READ_ID (0x90) -> COMMAND + ADDRESS + READ DATA
-* WRITE WREN(0x6) -> COMMAND
-* WRITE WRDI -> COMMAND
-* STATUS RDSR(0x05) -> COMMAND + READ DATA
-* STATUS RCR(0x35) -> COMMAND + READ DATA
-* CONFIG WRR(0x01) -> COMMAND + WRITE DATA
-* CONFIG CLSR(0x30) -> COMMAND
-* Power Saving DP(0xB9) -> COMMAND
-* Power Saving RES(0xAB) -> COMMAND + READ DATA
-* OTP OTPP(0x42) -> COMMAND + ADDR+ WRITE DATA
-* OTP OTPR(0x4B) -> COMMAND + ADDR + DUMMY + READ DATA
-* ********************************************************************/
-parameter P_FSM_C = 4'b0000; // Command Phase Only
-parameter P_FSM_CW = 4'b0001; // Command + Write DATA Phase Only
-parameter P_FSM_CA = 4'b0010; // Command -> Address Phase Only
-
-parameter P_FSM_CAR = 4'b0011; // Command -> Address -> Read Data
-parameter P_FSM_CADR = 4'b0100; // Command -> Address -> Dummy -> Read Data
-parameter P_FSM_CAMR = 4'b0101; // Command -> Address -> Mode -> Read Data
-parameter P_FSM_CAMDR = 4'b0110; // Command -> Address -> Mode -> Dummy -> Read Data
-
-parameter P_FSM_CAW = 4'b0111; // Command -> Address ->Write Data
-parameter P_FSM_CADW = 4'b1000; // Command -> Address -> DUMMY + Write Data
-
-parameter P_FSM_CDR = 4'b1001; // COMMAND -> DUMMY -> READ
-parameter P_FSM_CDW = 4'b1010; // COMMAND -> DUMMY -> WRITE
-parameter P_FSM_CR = 4'b1011; // COMMAND -> READ
-//---------------------------------------------------------
- parameter P_CS0 = 4'b0001;
- parameter P_CS1 = 4'b0010;
- parameter P_CS2 = 4'b0100;
- parameter P_CS3 = 4'b1000;
-
- parameter P_SINGLE = 2'b00;
- parameter P_DOUBLE = 2'b01;
- parameter P_QUAD = 2'b10;
-
- parameter P_MODE_SWITCH_IDLE = 2'b00;
- parameter P_MODE_SWITCH_AT_ADDR = 2'b01;
- parameter P_MODE_SWITCH_AT_DATA = 2'b10;
-
- parameter P_QOR = 8'h6B;
- parameter P_QIOR = 8'hEB;
- parameter P_RES = 8'hAB;
- parameter P_WEN = 8'h06;
- parameter P_WRR = 8'h01;
-
- parameter P_8BIT = 2'b00;
- parameter P_16BIT = 2'b01;
- parameter P_24BIT = 2'b10;
- parameter P_32BIT = 2'b11;
-//---------------------------------------------------------
-// Variable declartion
-// -------------------------------------------------------
-logic [2:0] spi_init_state ;
-logic spim_reg_req_f ;
-
-logic [1:0] cfg_m1_fsm_reset ;
-logic [3:0] cfg_m1_spi_seq ; // SPI SEQUENCE
-logic [1:0] cfg_m1_addr_cnt ; // SPI Addr Count
-logic [1:0] cfg_m1_dummy_cnt ; // SPI Dummy Count
-logic [7:0] cfg_m1_data_cnt ; // SPI Read Count
-logic [7:0] cfg_m1_cmd_reg ; // SPI MEM COMMAND
-logic [7:0] cfg_m1_mode_reg ; // SPI MODE REG
-logic [31:0] cfg_m1_addr ;
-logic [31:0] cfg_m1_wdata ;
-logic [31:0] cfg_m1_rdata ;
-logic cfg_m1_wrdy ;
-logic cfg_m1_req ;
-
-logic [31:0] reg_rdata ;
-
-
-logic [5:0] cur_cnt ;
-logic [5:0] next_cnt ;
-logic [3:0] next_state ;
-
-
-logic [31:0] spim_m1_rdata ;
-logic spim_m1_ack ;
-logic spim_m1_rrdy ;
-logic spim_m1_wrdy ;
-logic [9:0] spi_delay_cnt ;
-logic spim_fifo_rdata_req ;
-logic spim_fifo_wdata_req ;
-
-
-//----------------------------------------------
-// Consolidated Register Ack handling
-// 1. Handles Normal Register Read
-// 2. Indirect Memory Write
-// 3. Indirect Memory Read
-//----------------------------------------------
-//
-assign spim_fifo_rdata_req = spim_reg_req && spim_reg_we == 0 && (spim_reg_addr== IMEM_RDATA);
-assign spim_fifo_wdata_req = spim_reg_req && spim_reg_we == 1 && (spim_reg_addr== IMEM_WDATA);
-
-always_ff @(negedge rst_n or posedge mclk) begin
- if ( rst_n == 1'b0 ) begin
- spim_reg_ack <= 1'b0;
- spim_reg_rdata <= 'h0;
- end else begin
- if(spi_init_done && spim_reg_ack == 0) begin
- if (spim_fifo_wdata_req && (spim_m1_wrdy == 1)) begin // Indirect Memory Write
- // If FIFO Write DATA case, Make sure that there no previous pending
- // need to processed
- spim_reg_ack <= 1'b1;
- end else if (spim_reg_req && spim_reg_we && (spim_reg_addr != IMEM_WDATA)) begin // Indirect memory Write
- spim_reg_ack <= 1'b1;
- end else if (spim_fifo_rdata_req && (spim_m1_rrdy == 1)) begin // Indirect mem Read
- // If FIFO Read DATA case, Make sure that there Data is read from
- // External SPI Memory
- spim_reg_ack <= 1'b1;
- spim_reg_rdata <= reg_rdata;
- end else if (spim_reg_req && spim_reg_we == 0 && (spim_reg_addr != IMEM_RDATA)) begin // Normal Read
- // Read other than FIFO Read Data case
- spim_reg_ack <= 1'b1;
- spim_reg_rdata <= reg_rdata;
- end
- end else begin
- spim_reg_ack <= 1'b0;
- end
- end
-end
-
- //---------------------------------------------
- // Manges the initial Config Phase of SPI Memory
- // 1. Power Up Command - RES(0xAB)
- // 2. Write Enable Command - WEN (0x06)
- // 3. WRITE CONFIG Reg - WRR (0x01) - Set Qaud Mode
- // --------------------------------------------
-
- logic [9:0] cfg_exit_cnt ;
- assign cfg_exit_cnt = (fast_sim_mode) ? 100: 1000;
-
- integer byte_index;
- always_ff @(negedge rst_n or posedge mclk) begin
- if ( rst_n == 1'b0 ) begin
- cfg_m0_fsm_reset <= 'h0;
- cfg_m0_cs_reg <= P_CS0;
- cfg_m0_spi_mode <= P_QUAD;
- cfg_m0_spi_switch <= P_MODE_SWITCH_AT_ADDR;
- cfg_m0_cmd_reg <= P_QIOR;
- cfg_m0_mode_reg <= 'h0;
- cfg_m0_spi_seq[3:0] <= P_FSM_CAMDR;
- cfg_m0_addr_cnt[1:0] <= P_24BIT;
- cfg_m0_dummy_cnt[1:0] <= P_16BIT;
- cfg_m0_data_cnt[7:0] <= 8'h20; // 32 Byte
-
- cfg_m1_fsm_reset <= 'h0;
- cfg_m1_cs_reg <= P_CS0;
- cfg_m1_spi_mode <= P_QUAD;
- cfg_m1_spi_switch <= P_MODE_SWITCH_AT_DATA;
- cfg_m1_cmd_reg <= P_QOR;
- cfg_m1_mode_reg <= 'h0;
- cfg_m1_spi_seq[3:0] <= P_FSM_CADR;
- cfg_m1_addr_cnt[1:0] <= P_24BIT;
- cfg_m1_dummy_cnt[1:0] <= P_8BIT;
- cfg_m1_data_cnt[7:0] <= 0;
- cfg_m1_req <= 0;
- cfg_m1_wrdy <= 1'b0;
- cfg_m1_wdata <= 'h0; // Not Used
-
- cfg_cs_early <= 'h1;
- cfg_cs_late <= 'h1;
- spi_clk_div <= 'h2;
-
- spi_init_done <= 'h0;
- spi_delay_cnt <= 'h0;
- spim_reg_req_f <= 1'b0;
- spi_init_state <= SPI_INIT_PWUP;
- end else begin
- spim_reg_req_f <= spim_reg_req; // Needed for finding Req Edge
- if (spi_init_done == 0) begin
- case(spi_init_state)
-
- //----------------------------------------------
- // SPI MEMORY Need minimum 5Us after power up
- // With 100Mhz, 10ns translated to 500 cycle
- // We are waiting 1000 cycle
- // ---------------------------------------------
- SPI_INIT_PWUP:begin
- if(spi_delay_cnt == cfg_exit_cnt) begin
- spi_init_state <= SPI_INIT_IDLE;
- end else begin
- spi_delay_cnt <= spi_delay_cnt+1;
- end
- end
-
- SPI_INIT_IDLE:
- begin
- cfg_m1_cs_reg <= P_CS0;
- cfg_m1_spi_mode <= P_SINGLE;
- cfg_m1_spi_seq[3:0] <= P_FSM_C;
- cfg_m1_spi_switch <= '0;
- cfg_m1_cmd_reg <= P_RES;
- cfg_m1_mode_reg <= 'h0; // Not Used
- cfg_m1_addr_cnt[1:0] <= 'h0; // Not Used
- cfg_m1_dummy_cnt[1:0]<= 'h0; // Not Used
- cfg_m1_data_cnt[7:0] <= 'h0; // Not Used
- cfg_m1_addr <= 'h0; // Not Used
- cfg_m1_wdata <= 'h0; // Not Used
- cfg_m1_req <= 'h1;
- spi_init_state <= SPI_INIT_CMD_WAIT;
- end
- SPI_INIT_CMD_WAIT:
- begin
- if(spim_m1_ack) begin
- cfg_m1_req <= 1'b0;
- spi_init_state <= SPI_INIT_WREN_CMD;
- end
- end
- SPI_INIT_WREN_CMD:
- begin
- cfg_m1_cs_reg <= P_CS0;
- cfg_m1_spi_mode <= P_SINGLE;
- cfg_m1_spi_seq[3:0] <= P_FSM_C;
- cfg_m1_spi_switch <= '0;
- cfg_m1_cmd_reg <= P_WEN;
- cfg_m1_mode_reg <= 'h0; // Not Used
- cfg_m1_addr_cnt[1:0] <= 'h0; // Not Used
- cfg_m1_dummy_cnt[1:0]<= 'h0; // Not Used
- cfg_m1_data_cnt[7:0] <= 'h0; // Not Used
- cfg_m1_addr <= 'h0; // Not Used
- cfg_m1_wdata <= 'h0; // Not Used
- cfg_m1_req <= 'h1;
- spi_init_state <= SPI_INIT_WREN_WAIT;
- end
- SPI_INIT_WREN_WAIT:
- begin
- if(spim_m1_ack) begin
- cfg_m1_req <= 1'b0;
- spi_init_state <= SPI_INIT_WRR_CMD;
- end
- end
- SPI_INIT_WRR_CMD:
- begin
- cfg_m1_cs_reg <= P_CS0;
- cfg_m1_spi_mode <= P_SINGLE;
- cfg_m1_spi_seq[3:0] <= P_FSM_CW;
- cfg_m1_spi_switch <= '0;
- cfg_m1_cmd_reg <= P_WRR;
- cfg_m1_mode_reg <= 'h0;
- cfg_m1_addr_cnt[1:0] <= 'h0;
- cfg_m1_dummy_cnt[1:0]<= 'h0;
- cfg_m1_data_cnt[7:0] <= 'h2; // 2 Bytes
- cfg_m1_addr <= 'h0;
- cfg_m1_wrdy <= 1'b1;
- cfg_m1_wdata <= {16'h0,8'h2,8'h0}; // <<cr1[7:0]><sr1[7:0]>> cr1[1] = 1 indicate quad mode cr1[7:6]=3
- cfg_m1_req <= 'h1;
- spi_init_state <= SPI_INIT_WRR_WAIT;
- end
- SPI_INIT_WRR_WAIT:
- begin
- if(spim_m1_ack) begin
- spi_delay_cnt <= 'h0;
- cfg_m1_wrdy <= 1'b0;
- cfg_m1_req <= 1'b0;
- spi_init_state <= SPI_INIT_WAIT;
- end
- end
- SPI_INIT_WAIT:
- begin // SPI MEMORY need 5us after WRR Command
- if(spi_delay_cnt == cfg_exit_cnt) begin
- spi_init_done <= 'h1;
- end else begin
- spi_delay_cnt <= spi_delay_cnt+1;
- end
- end
- endcase
- end else if (spim_reg_req && spim_reg_we && spi_init_done )
- begin
- case(spim_reg_addr)
- GLBL_CTRL: begin
- if ( spim_reg_be[0] == 1 ) begin
- cfg_cs_early <= spim_reg_wdata[1:0];
- cfg_cs_late <= spim_reg_wdata[3:2];
- end
- if ( spim_reg_be[1] == 1 ) begin
- spi_clk_div <= spim_reg_wdata[15:8];
- end
- end
- DMEM_CTRL1: begin // This register control Direct Memory Access Type
- if ( spim_reg_be[0] == 1 ) begin
- cfg_m0_cs_reg <= spim_reg_wdata[3:0]; // Chip Select for Memory Interface
- cfg_m0_spi_mode <= spim_reg_wdata[5:4]; // SPI Mode, 0 - Normal, 1- Double, 2 - Qard, 3 - QDDR
- cfg_m0_spi_switch<= spim_reg_wdata[7:6]; // Phase where to switch the SPI Mode
- end
- if ( spim_reg_be[1] == 1 ) begin
- cfg_m0_fsm_reset <= spim_reg_wdata[8];
- end
- end
- DMEM_CTRL2: begin // This register control Direct Memory Access Type
- if ( spim_reg_be[0] == 1 ) begin
- cfg_m0_cmd_reg <= spim_reg_wdata[7:0];
- end
- if ( spim_reg_be[1] == 1 ) begin
- cfg_m0_mode_reg <= spim_reg_wdata[15:8];
- end
- if ( spim_reg_be[2] == 1 ) begin
- cfg_m0_spi_seq[3:0] <= spim_reg_wdata[19:16];
- cfg_m0_addr_cnt[1:0] <= spim_reg_wdata[21:20];
- cfg_m0_dummy_cnt[1:0]<= spim_reg_wdata[23:22];
- end
- if ( spim_reg_be[3] == 1 ) begin
- cfg_m0_data_cnt[7:0] <= spim_reg_wdata[31:24];
- end
- end
- IMEM_CTRL1: begin
- if ( spim_reg_be[0] == 1 ) begin
- cfg_m1_cs_reg <= spim_reg_wdata[3:0]; // Chip Select for Memory Interface
- cfg_m1_spi_mode <= spim_reg_wdata[5:4]; // SPI Mode, 0 - Normal, 1- Double, 2 - Qard
- cfg_m1_spi_switch<= spim_reg_wdata[7:6]; // Phase where to switch the SPI Mode
- end
- if ( spim_reg_be[0] == 1 ) begin
- cfg_m1_fsm_reset <= spim_reg_wdata[8];
- end
- end
- IMEM_CTRL2: begin // This register control Direct Memory Access Type
- if ( spim_reg_be[0] == 1 ) begin
- cfg_m1_cmd_reg <= spim_reg_wdata[7:0];
- end
- if ( spim_reg_be[1] == 1 ) begin
- cfg_m1_mode_reg <= spim_reg_wdata[15:8];
- end
- if ( spim_reg_be[2] == 1 ) begin
- cfg_m1_spi_seq[3:0] <= spim_reg_wdata[19:16];
- cfg_m1_addr_cnt[1:0] <= spim_reg_wdata[21:20];
- cfg_m1_dummy_cnt[1:0]<= spim_reg_wdata[23:22];
- end
- if ( spim_reg_be[3] == 1 ) begin
- cfg_m1_data_cnt[7:0] <= spim_reg_wdata[31:24];
- end
- end
- IMEM_ADDR: begin
- for (byte_index = 0; byte_index < 4; byte_index = byte_index+1 )
- if ( spim_reg_be[byte_index] == 1 )
- cfg_m1_addr[byte_index*8 +: 8] <= spim_reg_wdata[(byte_index*8) +: 8];
- end
- endcase
- end
- end
- end
-
-
-
- // implement slave model register read mux
- always_comb
- begin
- reg_rdata = '0;
- if(spim_reg_req) begin
- case(spim_reg_addr)
- GLBL_CTRL: reg_rdata[31:0] = {16'h0,spi_clk_div,4'h0,cfg_cs_late,cfg_cs_early};
- DMEM_CTRL1: reg_rdata[31:0] = {23'h0,cfg_m0_fsm_reset,cfg_m0_spi_switch,cfg_m0_spi_mode,cfg_m0_cs_reg};
- DMEM_CTRL2: reg_rdata[31:0] = {cfg_m0_data_cnt,cfg_m0_dummy_cnt,cfg_m0_addr_cnt,cfg_m0_spi_seq,cfg_m0_mode_reg,cfg_m0_cmd_reg};
- IMEM_CTRL1: reg_rdata[31:0] = {23'h0, cfg_m1_fsm_reset,cfg_m1_spi_switch,cfg_m1_spi_mode,cfg_m1_cs_reg};
- IMEM_CTRL2: reg_rdata[31:0] = {cfg_m1_data_cnt,cfg_m1_dummy_cnt,cfg_m1_addr_cnt,cfg_m1_spi_seq,cfg_m1_mode_reg,cfg_m1_cmd_reg};
- IMEM_ADDR: reg_rdata[31:0] = cfg_m1_addr;
- IMEM_WDATA: reg_rdata[31:0] = cfg_m1_wdata;
- IMEM_RDATA: reg_rdata[31:0] = cfg_m1_rdata;
- SPI_STATUS: reg_rdata[31:0] = spi_debug;
- endcase
- end
- end
-
-// FSM
-
-always_ff @(negedge rst_n or posedge mclk) begin
- if ( rst_n == 1'b0 ) begin
- cur_cnt <= 'h0;
- state <= FSM_IDLE;
- end else begin
- if(cfg_m1_fsm_reset) begin
- cur_cnt <= 'h0;
- state <= FSM_IDLE;
- end else begin
- cur_cnt <= next_cnt;
- state <= next_state;
- end
- end
-end
-
-/***********************************************************************************
-* This block interface with WishBone Request and Write Command & Read Response FIFO
-* **********************************************************************************/
-
-logic [7:0] cfg_data_cnt;
-logic [31:0] spim_fifo_wdata;
-logic spim_fifo_req;
-assign cfg_data_cnt = cfg_m1_data_cnt-1;
-
-assign spim_fifo_req = cfg_m1_req || spim_fifo_rdata_req || spim_fifo_wdata_req;
-
-assign spim_fifo_wdata = (cfg_m1_req) ? cfg_m1_wdata : spim_reg_wdata;
-
-always_comb
-begin
- cmd_fifo_wr = '0;
- cmd_fifo_wdata = '0;
-
- res_fifo_rd = 0;
- spim_m1_rdata = '0;
-
- spim_m1_ack = 0;
- spim_m1_rrdy = 0;
- next_cnt = cur_cnt;
- next_state = state;
- spim_m1_rrdy = 0;
- spim_m1_wrdy = 0;
- cfg_m1_rdata = 0;
-
- case(state)
- FSM_IDLE: begin
- next_cnt = 0;
- if(spim_fifo_req && cmd_fifo_empty) begin
- case(cfg_m1_spi_seq)
- P_FSM_C: begin
- cmd_fifo_wdata = {SOC,EOC, cfg_m1_data_cnt[7:0],cfg_m1_dummy_cnt[1:0],
- cfg_m1_addr_cnt[1:0],cfg_m1_spi_seq[3:0],
- cfg_m1_mode_reg[7:0],cfg_m1_cmd_reg[7:0]};
- spim_m1_wrdy = 1;
- next_state = FSM_ACK_PHASE;
- end
- P_FSM_CW,
- P_FSM_CDW:
- begin
- cmd_fifo_wdata = {SOC,NOC, cfg_m1_data_cnt[7:0],cfg_m1_dummy_cnt[1:0],
- cfg_m1_addr_cnt[1:0],cfg_m1_spi_seq[3:0],
- cfg_m1_mode_reg[7:0],cfg_m1_cmd_reg[7:0]};
- next_state = FSM_WRITE_PHASE;
- end
- P_FSM_CA,
- P_FSM_CAR,
- P_FSM_CADR,
- P_FSM_CAMR,
- P_FSM_CAMDR,
- P_FSM_CAW,
- P_FSM_CADW:
- begin
- cmd_fifo_wdata = {SOC,NOC, cfg_m1_data_cnt[7:0],cfg_m1_dummy_cnt[1:0],
- cfg_m1_addr_cnt[1:0],cfg_m1_spi_seq[3:0],
- cfg_m1_mode_reg[7:0],cfg_m1_cmd_reg[7:0]};
- next_state = FSM_ADR_PHASE;
- end
- P_FSM_CDR,
- P_FSM_CR:
- begin
- cmd_fifo_wdata = {SOC,EOC, cfg_m1_data_cnt[7:0],cfg_m1_dummy_cnt[1:0],
- cfg_m1_addr_cnt[1:0],cfg_m1_spi_seq[3:0],
- cfg_m1_mode_reg[7:0],cfg_m1_cmd_reg[7:0]};
- next_state = FSM_READ_PHASE;
- end
-
-
- endcase
- cmd_fifo_wr = 1;
- end
- end
- // ADDRESS PHASE
- FSM_ADR_PHASE: begin
- if(!cmd_fifo_full) begin
- case(cfg_m1_spi_seq)
- P_FSM_CA: // COMMAND + ADDRESS PHASE
- begin
- cmd_fifo_wdata = {NOC,EOC,cfg_m1_addr[31:0]};
- spim_m1_wrdy = 1;
- next_state = FSM_ACK_PHASE;
- end
- P_FSM_CAR, // COMMAND + ADDRESS + READ PHASE
- P_FSM_CADR, // COMMAND + ADDRESS + DUMMY + READ PHASE
- P_FSM_CAMR, // COMMAND + ADDRESS + MODE + READ PHASE
- P_FSM_CAMDR: // COMMAND + ADDRESS + MODE + DUMMY + READ PHASE
- begin
- cmd_fifo_wdata = {NOC,EOC,cfg_m1_addr[31:0]};
- next_cnt = 'h0;
- next_state = FSM_READ_PHASE;
- end
-
- P_FSM_CAW,
- P_FSM_CADW:
- begin
- cmd_fifo_wdata = {NOC,NOC,cfg_m1_addr[31:0]};
- next_cnt = 'h0;
- next_state = FSM_WRITE_PHASE;
- end
- endcase
- cmd_fifo_wr = 1;
- end
- end
-
- //----------------------------------------------------------
- // Check Resonse FIFO is not empty then read the data from response fifo
- // ---------------------------------------------------------
- FSM_READ_PHASE: begin
- if(res_fifo_empty != 1 && spim_fifo_rdata_req) begin
- spim_m1_rrdy = 1;
- cfg_m1_rdata = res_fifo_rdata;
- res_fifo_rd = 1;
- if(cfg_data_cnt[7:2] == cur_cnt) begin
- next_state = FSM_ACK_PHASE;
- end else begin
- next_state = FSM_READ_BUSY;
- next_cnt = cur_cnt+1;
- end
- end
- end
- //----------------------------------------------
- // Wait for Previous Read Data Read
- // ---------------------------------------------
- FSM_READ_BUSY: begin
- spim_m1_rrdy = 0;
- if(spim_fifo_rdata_req == 0) begin
- next_state = FSM_READ_PHASE;
- end
- end
-
- //----------------------------------------------------------
- // Check command FIFO is not full and Write Data is available
- // ---------------------------------------------------------
- FSM_WRITE_PHASE: begin
- if(cmd_fifo_full != 1 && spim_fifo_req) begin
- // If this a single word config cycle or
- // in crrent spim_fifo_wr request
- spim_m1_wrdy = 1;
- if(cfg_data_cnt[7:2] == cur_cnt) begin
- cmd_fifo_wdata = {NOC,EOC,spim_fifo_wdata[31:0]};
- next_state = FSM_ACK_PHASE;
- end else begin
- cmd_fifo_wdata = {NOC,NOC,spim_fifo_wdata[31:0]};
- next_state = FSM_WRITE_BUSY;
- next_cnt = cur_cnt+1;
- end
- cmd_fifo_wr = 1;
- end
- end
- //----------------------------------------------
- // Wait for NEXT Data Ready
- // ---------------------------------------------
- FSM_WRITE_BUSY: begin
- spim_m1_wrdy = 0;
- if(spim_fifo_wdata_req == 0) begin
- next_state = FSM_WRITE_PHASE;
- end
- end
-
- FSM_ACK_PHASE: begin
- spim_m1_ack = 1;
- next_state = FSM_IDLE;
- end
-
- endcase
-
-
-end
-
-endmodule
diff --git a/verilog/rtl/spi_master/src/spim_rx.sv b/verilog/rtl/spi_master/src/spim_rx.sv
deleted file mode 100644
index 199ef4c..0000000
--- a/verilog/rtl/spi_master/src/spim_rx.sv
+++ /dev/null
@@ -1,229 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// SPI RX Module ////
-//// ////
-//// This file is part of the YIFive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
-//// ////
-//// Description ////
-//// SPI RX module ////
-//// ////
-//// To Do: ////
-//// nothing ////
-//// ////
-//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
-//// ////
-//// Revision : ////
-//// V.0 - June 8, 2021 ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-
-
-module spim_rx #(
- parameter ENDIEAN = 0 // 0 - Little, 1 - Big endian, since RISV is Little indian default set 0
- )
-(
- input logic clk,
- input logic rstn,
- input logic flush,
- input logic en,
- input logic rx_edge,
- output logic rx_done,
- input logic sdi0,
- input logic sdi1,
- input logic sdi2,
- input logic sdi3,
- input logic [1:0] s_spi_mode,
- input logic [15:0] counter_in,
- input logic counter_in_upd,
- output logic [31:0] data,
- input logic data_ready,
- output logic data_valid,
- output logic clk_en_o
-);
-//------------------------------------------------------
-// Parameter Decleration
-// -----------------------------------------------------
- parameter P_SINGLE = 2'b00;
- parameter P_DOUBLE = 2'b01;
- parameter P_QUAD = 2'b10;
- parameter P_QDDR = 2'b11;
-
-//------------------------------------------------------
-// Variable Decleration
-// -----------------------------------------------------
-
- logic [31:0] data_int;
- logic [31:0] data_int_next;
- logic [15:0] counter;
- logic [15:0] counter_trgt;
- logic [15:0] counter_next;
- logic reg_done;
- logic data_valid_i;
- logic qddr_rx_en;
- enum logic [1:0] { IDLE, RECEIVE, WAIT_FIFO, WAIT_FIFO_DONE } rx_CS, rx_NS;
-
-
- assign reg_done = (s_spi_mode == P_SINGLE && (counter[4:0] == 5'b11111)) ||
- (s_spi_mode == P_DOUBLE && (counter[3:0] == 4'b1111)) ||
- (s_spi_mode == P_QUAD && (counter[2:0] == 3'b111)) ||
- (s_spi_mode == P_QDDR && (counter[2:0] == 3'b111));
-
-
-
- always_comb
- begin
- rx_NS = rx_CS;
- data_int_next = data_int;
- data_valid_i = 1'b0;
- counter_next = counter;
-
- case (rx_CS)
- IDLE: begin
-
- // check first if there is available space instead of later
- if (en) begin
- rx_NS = RECEIVE;
- end
- end
-
- RECEIVE: begin
-
- if (rx_edge || qddr_rx_en) begin
- counter_next = counter + 1;
- if ((s_spi_mode == P_QUAD ) || (s_spi_mode == P_QDDR ))
- data_int_next = {data_int[27:0],sdi3,sdi2,sdi1,sdi0};
- else if (s_spi_mode == P_DOUBLE )
- data_int_next = {data_int[29:0],sdi1,sdi0};
- else
- data_int_next = {data_int[30:0],sdi1};
-
- if (rx_done) begin
- counter_next = 0;
- if (data_ready) begin
- data_valid_i = 1'b1;
- rx_NS = IDLE;
- end else
- rx_NS = WAIT_FIFO_DONE;
- end else if (reg_done) begin
- if (data_ready) begin
- data_valid_i = 1'b1;
- end else begin
- // no space in the FIFO, wait for free space
- rx_NS = WAIT_FIFO;
- end
- end
- end
- end
-
- WAIT_FIFO_DONE: begin
- if (data_ready) begin
- data_valid_i = 1'b1;
- rx_NS = IDLE;
- end
- end
-
- WAIT_FIFO: begin
- if (data_ready) begin
- data_valid_i = 1'b1;
- rx_NS = RECEIVE;
- end
- end
- endcase
- end
-
-
- always_ff @(posedge clk, negedge rstn)
- begin
- if (rstn == 0)
- begin
- counter <= 0;
- counter_trgt <= 'h8;
- data_int <= '0;
- rx_done <= '0;
- clk_en_o <= '0;
- data <= 'b0;
- data_valid <= 1'b0;
- qddr_rx_en <= '0;
- rx_CS <= IDLE;
- end else if(flush && rx_edge) begin
- counter <= 0;
- counter_trgt <= 'h8;
- data_int <= '0;
- rx_done <= '0;
- clk_en_o <= '0;
- data <= 'b0;
- data_valid <= 1'b0;
- qddr_rx_en <= 0;
- rx_CS <= IDLE;
- end else begin
- // Enable qddr rx after first rx edge
- if(en && rx_edge && (rx_CS == RECEIVE) && (s_spi_mode ==P_QDDR)) begin
- qddr_rx_en <= 1;
- end else if(!en || rx_done) begin
- qddr_rx_en <= 0;
- end
-
- data_valid <= data_valid_i;
- data <= (ENDIEAN) ? data_int_next : {data_int_next[7:0],data_int_next[15:8],data_int_next[23:16],data_int_next[31:24]};
- clk_en_o <= (rx_NS == RECEIVE);
- if (rx_edge || qddr_rx_en) begin
- counter <= counter_next;
- data_int <= data_int_next;
- rx_CS <= rx_NS;
- rx_done <= (counter_next == (counter_trgt-1)) && (rx_NS == RECEIVE);
- clk_en_o <= (rx_NS == RECEIVE);
- end
- if (en && counter_in_upd) begin
- counter_trgt <= (s_spi_mode ==P_QDDR ) ? {2'b00,counter_in[15:2]} :
- (s_spi_mode ==P_QUAD ) ? {2'b00,counter_in[15:2]} :
- (s_spi_mode ==P_DOUBLE ) ? {1'b0,counter_in[15:1]} : counter_in;
- end
- end
- end
-
-endmodule
diff --git a/verilog/rtl/spi_master/src/spim_top.sv b/verilog/rtl/spi_master/src/spim_top.sv
deleted file mode 100644
index e8b6320..0000000
--- a/verilog/rtl/spi_master/src/spim_top.sv
+++ /dev/null
@@ -1,475 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// SPI Master Top Module ////
-//// ////
-//// This file is part of the YIFive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
-//// ////
-//// Description ////
-//// SPI Master Top module ////
-//// There are two seperate Data path managed here ////
-//// with seperate command and response memory ////
-//// Master-0 : This is targetted for CORE IMEM request ////
-//// and expect only Read access ////
-//// Master-1: This is targetted to CORE DMEM or ////
-//// Indirect Memory access, Both Write and Read ////
-//// accesss are supported. ////
-//// Upto 255 Byte Read/Write Burst supported ////
-//// Limitation: ////
-//// 1. Write/Read FIFO Abort case not managed M1 port, ////
-//// expect user to clearly close the busrt request ////
-//// 2. Wishbone Request abort not yet supported. ////
-//// 3. Write access through M0 Port not supported ////
-//// 4. When Pre fetch feature used and both port m0 and ////
-//// m1 used, user need to make sure that data pre fetch////
-//// count is withing 8DW, less Read path can hang due ////
-//// to response FIFO full from one master port ////
-//// ////
-//// To Do: ////
-//// 1. Add support for WishBone request timout ////
-//// 2. Add Pre-fetch feature for M0 Port ////
-//// ////
-//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
-//// ////
-//// Revision : ////
-//// V.0 - June 8, 2021 ////
-//// V.1 - June 25, 2021 ////
-//// Pad logic is brought inside the block to avoid ////
-//// logic at digital core level for caravel project ////
-//// V.2 - July 6, 2021 ////
-//// Added Hold fix cell for SPI data out signal to ////
-//// met interface hold ////
-//// V.3 - July 13, 2021 ////
-//// Data Prefetch feature added in M0 port, If Only ////
-//// M0 Read used, then Prefetch read can be 255 Byte, ////
-//// But if the Both M0 and M1 read access enabled, ////
-//// then user need to make sure that M0 Prefetch is ////
-//// with in 8DW or 32 Byte, else there is chance ////
-//// data path can hang due to response FIFO full due ////
-//// to partial reading of data ////
-//// V.4 - July 26, 2021 ////
-//// QDDR (0xED) supported is added ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-
-
-
-module spim_top
-#( parameter WB_WIDTH = 32)
-(
- input logic mclk,
- input logic rst_n,
-
-
- input logic wbd_stb_i, // strobe/request
- input logic [WB_WIDTH-1:0] wbd_adr_i, // address
- input logic wbd_we_i, // write
- input logic [WB_WIDTH-1:0] wbd_dat_i, // data output
- input logic [3:0] wbd_sel_i, // byte enable
- output logic [WB_WIDTH-1:0] wbd_dat_o, // data input
- output logic wbd_ack_o, // acknowlegement
- output logic wbd_err_o, // error
-
- output logic [31:0] spi_debug,
-
- // PAD I/f
- input logic [3:0] spi_sdi,
- output logic spi_clk,
- output logic spi_csn0,// No hold fix for CS#, as it asserted much eariler than SPI clock
- output logic [3:0] spi_sdo,
- output logic [3:0] spi_oen
-);
-
-
-
- logic [7:0] spi_clk_div ;
-
- // Master 0 Configuration
- logic cfg_m0_fsm_reset ;
- logic [3:0] cfg_m0_cs_reg ; // Chip select
- logic [1:0] cfg_m0_spi_mode ; // Final SPI Mode
- logic [1:0] cfg_m0_spi_switch; // SPI Mode Switching Place
- logic [3:0] cfg_m0_spi_seq ; // SPI SEQUENCE
- logic [1:0] cfg_m0_addr_cnt ; // SPI Addr Count
- logic [1:0] cfg_m0_dummy_cnt ; // SPI Dummy Count
- logic [7:0] cfg_m0_data_cnt ; // SPI Read Count
- logic [7:0] cfg_m0_cmd_reg ; // SPI MEM COMMAND
- logic [7:0] cfg_m0_mode_reg ; // SPI MODE REG
-
- logic [3:0] cfg_m1_cs_reg ; // Chip select
- logic [1:0] cfg_m1_spi_mode ; // Final SPI Mode
- logic [1:0] cfg_m1_spi_switch; // SPI Mode Switching Place
-
- logic [1:0] cfg_cs_early ; // Amount of cycle early CS asserted
- logic [1:0] cfg_cs_late ; // Amount of cycle late CS de-asserted
-
- // Towards Reg I/F
- logic spim_reg_req ; // Reg Request
- logic [3:0] spim_reg_addr ; // Reg Address
- logic spim_reg_we ; // Reg Write/Read Command
- logic [3:0] spim_reg_be ; // Reg Byte Enable
- logic [31:0] spim_reg_wdata ; // Reg Write Data
- logic spim_reg_ack ; // Read Ack
- logic [31:0] spim_reg_rdata ; // Read Read Data
-
- // Towards m0 Command FIFO
- logic m0_cmd_fifo_full ; // Command FIFO full
- logic m0_cmd_fifo_empty ; // Command FIFO empty
- logic m0_cmd_fifo_wr ; // Command FIFO Write
- logic m0_cmd_fifo_rd ; // Command FIFO read
- logic [33:0] m0_cmd_fifo_wdata ; // Command FIFO WData
- logic [33:0] m0_cmd_fifo_rdata ; // Command FIFO RData
-
- // Towards m0 Response FIFO
- logic m0_res_fifo_full ; // Response FIFO Empty
- logic m0_res_fifo_empty ; // Response FIFO Empty
- logic m0_res_fifo_wr ; // Response FIFO Write
- logic m0_res_fifo_rd ; // Response FIFO Read
- logic [31:0] m0_res_fifo_wdata ; // Response FIFO WData
- logic [31:0] m0_res_fifo_rdata ; // Response FIFO RData
-
- // Towards m1 Command FIFO
- logic m1_cmd_fifo_full ; // Command FIFO full
- logic m1_cmd_fifo_empty ; // Command FIFO empty
- logic m1_cmd_fifo_wr ; // Command FIFO Write
- logic m1_cmd_fifo_rd ; // Command FIFO Write
- logic [33:0] m1_cmd_fifo_wdata ; // Command FIFO WData
- logic [33:0] m1_cmd_fifo_rdata ; // Command FIFO RData
-
- // Towards m0 Response FIFO
- logic m1_res_fifo_full ; // Response FIFO Empty
- logic m1_res_fifo_empty ; // Response FIFO Empty
- logic m1_res_fifo_wr ; // Response FIFO Read
- logic m1_res_fifo_rd ; // Response FIFO Read
- logic [31:0] m1_res_fifo_wdata ; // Response FIFO WData
- logic [31:0] m1_res_fifo_rdata ; // Response FIFO RData
-
- logic m0_res_fifo_flush ; // m0 response fifo flush
- logic m1_res_fifo_flush ; // m0 response fifo flush
-
-//-----------------------------------------------------
-// SPI Debug monitoring
-// ----------------------------------------------------
- logic [8:0] spi_ctrl_status ;
- logic [3:0] m0_state ;
- logic [3:0] m1_state ;
- logic [3:0] ctrl_state ;
-
-
- assign spi_debug = {m0_res_fifo_flush,m1_res_fifo_flush,spi_init_done,
- m0_cmd_fifo_full,m0_cmd_fifo_empty,m0_res_fifo_full,m0_res_fifo_empty,
- m1_cmd_fifo_full,m1_cmd_fifo_empty,m1_res_fifo_full,m1_res_fifo_empty,
- ctrl_state[3:0], m0_state[3:0],m1_state[3:0],spi_ctrl_status[8:0]};
-
-//-------------------------------------------------------
-// SPI Interface moved inside to support carvel IO pad
-// -------------------------------------------------------
-
-logic spi_csn1;
-logic spi_csn2;
-logic spi_csn3;
-logic [1:0] spi_mode;
-logic spi_en_tx;
-logic spi_init_done;
-logic [3:0] spi_sdo_int;
-
-logic spi_sdo0_dl;
-logic spi_sdo1_dl;
-logic spi_sdo2_dl;
-logic spi_sdo3_dl;
-
-
-
-// ADDing Delay cells for Interface hold fix
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio0 (.X(spi_sdo0_d1),.A(spi_sdo_int[0]));
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio0 (.X(spi_sdo0_d2),.A(spi_sdo0_d1));
-sky130_fd_sc_hd__clkbuf_16 u_buf_sdio0 (.X(spi_sdo[0]),.A(spi_sdo0_d2));
-
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio1 (.X(spi_sdo1_d1),.A(spi_sdo_int[1]));
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio1 (.X(spi_sdo1_d2),.A(spi_sdo1_d1));
-sky130_fd_sc_hd__clkbuf_16 u_buf_sdio1 (.X(spi_sdo[1]),.A(spi_sdo1_d2));
-
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio2 (.X(spi_sdo2_d1),.A(spi_sdo_int[2]));
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio2 (.X(spi_sdo2_d2),.A(spi_sdo2_d1));
-sky130_fd_sc_hd__clkbuf_16 u_buf_sdio2 (.X(spi_sdo[2]),.A(spi_sdo2_d2));
-
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay1_sdio3 (.X(spi_sdo3_d1),.A(spi_sdo_int[3]));
-sky130_fd_sc_hd__dlygate4sd3_1 u_delay2_sdio3 (.X(spi_sdo3_d2),.A(spi_sdo3_d1));
-sky130_fd_sc_hd__clkbuf_16 u_buf_sdio3 (.X(spi_sdo[3]),.A(spi_sdo3_d2));
-
-
-assign #1 spi_oen[0] = !spi_en_tx; // SPI_DIO0
-assign #1 spi_oen[1] = !spi_en_tx; // SPI_DIO1
-assign #1 spi_oen[2] = (spi_mode == 0) ? 1 'b0 : !spi_en_tx; // HOLD
-assign #1 spi_oen[3] = (spi_mode == 0) ? 1 'b0 : !spi_en_tx; //
-
-
-spim_if #( .WB_WIDTH(WB_WIDTH)) u_wb_if(
- .mclk (mclk ),
- .rst_n (rst_n ),
-
- .wbd_stb_i (wbd_stb_i ), // strobe/request
- .wbd_adr_i (wbd_adr_i ), // address
- .wbd_we_i (wbd_we_i ), // write
- .wbd_dat_i (wbd_dat_i ), // data output
- .wbd_sel_i (wbd_sel_i ), // byte enable
- .wbd_dat_o (wbd_dat_o ), // data input
- .wbd_ack_o (wbd_ack_o ), // acknowlegement
- .wbd_err_o (wbd_err_o ), // error
-
- // Configuration
- .cfg_fsm_reset (cfg_m0_fsm_reset ),
- .cfg_mem_seq (cfg_m0_spi_seq ), // SPI MEM SEQUENCE
- .cfg_addr_cnt (cfg_m0_addr_cnt ), // SPI Addr Count
- .cfg_dummy_cnt (cfg_m0_dummy_cnt ), // SPI Dummy Count
- .cfg_data_cnt (cfg_m0_data_cnt ), // SPI Read Count
- .cfg_cmd_reg (cfg_m0_cmd_reg ), // SPI MEM COMMAND
- .cfg_mode_reg (cfg_m0_mode_reg ), // SPI MODE REG
-
- .spi_init_done (spi_init_done ), // SPI internal Init completed
-
- // Towards Reg I/F
- .spim_reg_req (spim_reg_req ), // Reg Request
- .spim_reg_addr (spim_reg_addr ), // Reg Address
- .spim_reg_we (spim_reg_we ), // Reg Write/Read Command
- .spim_reg_be (spim_reg_be ), // Reg Byte Enable
- .spim_reg_wdata (spim_reg_wdata ), // Reg Write Data
- .spim_reg_ack (spim_reg_ack ), // Read Ack
- .spim_reg_rdata (spim_reg_rdata ), // Read Read Data
-
- // Towards Command FIFO
- .cmd_fifo_empty (m0_cmd_fifo_empty ), // Command FIFO empty
- .cmd_fifo_wr (m0_cmd_fifo_wr ), // Command FIFO Write
- .cmd_fifo_wdata (m0_cmd_fifo_wdata ), // Command FIFO WData
-
- // Towards Response FIFO
- .res_fifo_empty (m0_res_fifo_empty ), // Response FIFO Empty
- .res_fifo_rd (m0_res_fifo_rd ), // Response FIFO Read
- .res_fifo_rdata (m0_res_fifo_rdata ), // Response FIFO Data
-
- .state (m0_state )
-
- );
-
-
- spim_regs
- #(
- .WB_WIDTH(WB_WIDTH)
- )
- u_spim_regs
- (
- .mclk (mclk ),
- .rst_n (rst_n ),
- .fast_sim_mode (1'b0 ),
-
- .spi_clk_div (spi_clk_div ),
- .spi_init_done (spi_init_done ),
-
- .spi_debug (spi_debug ),
-
- .cfg_m0_fsm_reset (cfg_m0_fsm_reset ),
- .cfg_m0_cs_reg (cfg_m0_cs_reg ), // Chip select
- .cfg_m0_spi_mode (cfg_m0_spi_mode ), // Final SPI Mode
- .cfg_m0_spi_switch (cfg_m0_spi_switch ), // SPI Mode Switching Place
- .cfg_m0_spi_seq (cfg_m0_spi_seq ), // SPI SEQUENCE
- .cfg_m0_addr_cnt (cfg_m0_addr_cnt ), // SPI Addr Count
- .cfg_m0_dummy_cnt (cfg_m0_dummy_cnt ), // SPI Dummy Count
- .cfg_m0_data_cnt (cfg_m0_data_cnt ), // SPI Read Count
- .cfg_m0_cmd_reg (cfg_m0_cmd_reg ), // SPI MEM COMMAND
- .cfg_m0_mode_reg (cfg_m0_mode_reg ), // SPI MODE REG
-
- .cfg_m1_cs_reg (cfg_m1_cs_reg ), // Chip select
- .cfg_m1_spi_mode (cfg_m1_spi_mode ), // Final SPI Mode
- .cfg_m1_spi_switch (cfg_m1_spi_switch ), // SPI Mode Switching Place
-
- .cfg_cs_early (cfg_cs_early ),
- .cfg_cs_late (cfg_cs_late ),
-
- // Towards Reg I/F
- .spim_reg_req (spim_reg_req ), // Reg Request
- .spim_reg_addr (spim_reg_addr ), // Reg Address
- .spim_reg_we (spim_reg_we ), // Reg Write/Read Command
- .spim_reg_be (spim_reg_be ), // Reg Byte Enable
- .spim_reg_wdata (spim_reg_wdata ), // Reg Write Data
- .spim_reg_ack (spim_reg_ack ), // Read Ack
- .spim_reg_rdata (spim_reg_rdata ), // Read Read Data
-
- // Towards Command FIFO
- .cmd_fifo_full (m1_cmd_fifo_full ), // Command FIFO empty
- .cmd_fifo_empty (m1_cmd_fifo_empty ), // Command FIFO empty
- .cmd_fifo_wr (m1_cmd_fifo_wr ), // Command FIFO Write
- .cmd_fifo_wdata (m1_cmd_fifo_wdata ), // Command FIFO WData
-
- // Towards Response FIFO
- .res_fifo_full (m1_res_fifo_full ), // Response FIFO Empty
- .res_fifo_empty (m1_res_fifo_empty ), // Response FIFO Empty
- .res_fifo_rd (m1_res_fifo_rd ), // Response FIFO Read
- .res_fifo_rdata (m1_res_fifo_rdata ), // Response FIFO Data
-
- .state (m1_state )
-
- );
-
- // Master 0 Command FIFO
- spim_fifo #(.W(34), .DP(2)) u_m0_cmd_fifo (
- .clk (mclk ),
- .reset_n (rst_n ),
- .flush (1'b0 ),
- .wr_en (m0_cmd_fifo_wr ),
- .wr_data (m0_cmd_fifo_wdata ),
- .full (m0_cmd_fifo_full ),
- .afull ( ),
- .rd_en (m0_cmd_fifo_rd ),
- .empty (m0_cmd_fifo_empty ),
- .aempty ( ),
- .rd_data (m0_cmd_fifo_rdata )
- );
-
- // Master 0 Response FIFO
- spim_fifo #(.W(32), .DP(8)) u_m0_res_fifo (
- .clk (mclk ),
- .reset_n (rst_n ),
- .flush (m0_res_fifo_flush ),
- .wr_en (m0_res_fifo_wr ),
- .wr_data (m0_res_fifo_wdata ),
- .full (m0_res_fifo_full ),
- .afull ( ),
- .rd_en (m0_res_fifo_rd ),
- .empty (m0_res_fifo_empty ),
- .aempty ( ),
- .rd_data (m0_res_fifo_rdata )
- );
-
- // Master 1 Command FIFO
- spim_fifo #(.W(34), .DP(4)) u_m1_cmd_fifo (
- .clk (mclk ),
- .reset_n (rst_n ),
- .flush (1'b0 ),
- .wr_en (m1_cmd_fifo_wr ),
- .wr_data (m1_cmd_fifo_wdata ),
- .full (m1_cmd_fifo_full ),
- .afull ( ),
- .rd_en (m1_cmd_fifo_rd ),
- .empty (m1_cmd_fifo_empty ),
- .aempty ( ),
- .rd_data (m1_cmd_fifo_rdata )
- );
- // Master 1 Response FIFO
- spim_fifo #(.W(32), .DP(8)) u_m1_res_fifo (
- .clk (mclk ),
- .reset_n (rst_n ),
- .flush (m1_res_fifo_flush ),
- .wr_en (m1_res_fifo_wr ),
- .wr_data (m1_res_fifo_wdata ),
- .full (m1_res_fifo_full ),
- .afull ( ),
- .rd_en (m1_res_fifo_rd ),
- .empty (m1_res_fifo_empty ),
- .aempty ( ),
- .rd_data (m1_res_fifo_rdata )
- );
-
-
- spim_ctrl u_spictrl
- (
- .clk (mclk ),
- .rstn (rst_n ),
-
- .spi_clk_div (spi_clk_div ),
- .spi_status (spi_ctrl_status ),
-
- .cfg_m0_cs_reg (cfg_m0_cs_reg ), // Chip select
- .cfg_m0_spi_mode (cfg_m0_spi_mode ), // Final SPI Mode
- .cfg_m0_spi_switch (cfg_m0_spi_switch ), // SPI Mode Switching Place
-
- .cfg_m1_cs_reg (cfg_m1_cs_reg ), // Chip select
- .cfg_m1_spi_mode (cfg_m1_spi_mode ), // Final SPI Mode
- .cfg_m1_spi_switch (cfg_m1_spi_switch ), // SPI Mode Switching Place
-
- .cfg_cs_early (cfg_cs_early ),
- .cfg_cs_late (cfg_cs_late ),
-
- .m0_cmd_fifo_empty (m0_cmd_fifo_empty ),
- .m0_cmd_fifo_rd (m0_cmd_fifo_rd ),
- .m0_cmd_fifo_rdata (m0_cmd_fifo_rdata ),
-
- .m0_res_fifo_flush (m0_res_fifo_flush ),
- .m0_res_fifo_empty (m0_res_fifo_empty ),
- .m0_res_fifo_full (m0_res_fifo_full ),
- .m0_res_fifo_wr (m0_res_fifo_wr ),
- .m0_res_fifo_wdata (m0_res_fifo_wdata ),
-
- .m1_cmd_fifo_empty (m1_cmd_fifo_empty ),
- .m1_cmd_fifo_rd (m1_cmd_fifo_rd ),
- .m1_cmd_fifo_rdata (m1_cmd_fifo_rdata ),
-
- .m1_res_fifo_flush (m1_res_fifo_flush ),
- .m1_res_fifo_empty (m1_res_fifo_empty ),
- .m1_res_fifo_full (m1_res_fifo_full ),
- .m1_res_fifo_wr (m1_res_fifo_wr ),
- .m1_res_fifo_wdata (m1_res_fifo_wdata ),
-
- .ctrl_state (ctrl_state ),
-
- .spi_clk (spi_clk ),
- .spi_csn0 (spi_csn0 ),
- .spi_csn1 (spi_csn1 ),
- .spi_csn2 (spi_csn2 ),
- .spi_csn3 (spi_csn3 ),
- .spi_mode (spi_mode ),
- .spi_sdo0 (spi_sdo_int[0] ),
- .spi_sdo1 (spi_sdo_int[1] ),
- .spi_sdo2 (spi_sdo_int[2] ),
- .spi_sdo3 (spi_sdo_int[3] ),
- .spi_sdi0 (spi_sdi[0] ),
- .spi_sdi1 (spi_sdi[1] ),
- .spi_sdi2 (spi_sdi[2] ),
- .spi_sdi3 (spi_sdi[3] ),
- .spi_en_tx_out (spi_en_tx )
- );
-
-endmodule
diff --git a/verilog/rtl/spi_master/src/spim_tx.sv b/verilog/rtl/spi_master/src/spim_tx.sv
deleted file mode 100644
index 4b57e64..0000000
--- a/verilog/rtl/spi_master/src/spim_tx.sv
+++ /dev/null
@@ -1,249 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// SPI TX Module ////
-//// ////
-//// This file is part of the YIFive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
-//// ////
-//// Description ////
-//// This is SPI Master Transmit Word control logic. ////
-//// This logic transmit data upto 32 bit in bit or Quad spi ////
-//// mode ////
-//// ////
-//// To Do: ////
-//// nothing ////
-//// ////
-//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
-//// ////
-//// Revision: ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
-//// Initial version ////
-//// 0.2 - 24th Mar 2021, Dinesh A ////
-//// 1. Comments are added ////
-//// 2. RTL clean-up done and the output are registred////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-
-module spim_tx
-(
- // General Input
- input logic clk, // SPI clock
- input logic rstn, // Active low Reset
- input logic flush, // init the state
- input logic en, // Transmit Enable
- input logic tx_edge, // Transmiting Edge
- output logic tx_done, // Transmission completion
- output logic sdo0, // SPI Dout0
- output logic sdo1, // SPI Dout1
- output logic sdo2, // SPI Dout2
- output logic sdo3, // SPI Dout3
- input logic [1:0] s_spi_mode, // SPI quad mode indication
- input logic [15:0] counter_in, // Transmit counter
- input logic counter_in_upd,
- input logic [31:0] txdata, // 32 bit tranmsit data
- input logic dummy_phase, // dummy data
- input logic data_valid, // Input data valid
- output logic data_ready, // Data in acepted, this for txfifo
- output logic spi_dummy, // spi dummy phase
- output logic clk_en_o // Enable Tx clock
-);
-
-//------------------------------------------------------
-// Parameter Decleration
-// -----------------------------------------------------
- parameter P_SINGLE = 2'b00;
- parameter P_DOUBLE = 2'b01;
- parameter P_QUAD = 2'b10;
- parameter P_QDDR = 2'b11;
-
-//------------------------------------------------------
-// Variable Decleration
-// -----------------------------------------------------
- logic [31:0] data_int ; // Data Input
- logic [31:0] data_int_next ; // Next Data Input
- logic [15:0] counter ; // Tx Counter
- logic [15:0] counter_next ; // tx next counter
- logic [15:0] counter_trgt ; // counter exit counter
- logic tx32b_done ; // 32 bit Transmit done
- logic [1:0] spi_mode ;
- logic [1:0] spi_mode_next;
-
- logic data_ready_i; // Data in acepted, this for txfifo
- logic next_data_ready_i;// Data in acepted, this for txfifo
- enum logic [1:0] { IDLE, TRANSMIT,WAIT_FIFO_AVAIL } tx_CS, tx_NS;
-
-
- // Indicate 32 bit data done, usefull for readining next 32b from txfifo
- assign tx32b_done = (spi_mode == P_SINGLE && (counter[4:0] == 5'b11111)) ||
- (spi_mode == P_DOUBLE && (counter[3:0] == 4'b1111)) ||
- (spi_mode == P_QUAD && (counter[2:0] == 3'b111)) ||
- (spi_mode == P_QDDR && (counter[2:0] == 3'b111));
-
- assign tx_done = (counter == (counter_trgt-1)) && (tx_CS == TRANSMIT);
-
- assign clk_en_o = (tx_NS == TRANSMIT);
-
- always_comb
- begin
- tx_NS = tx_CS;
- data_int_next = data_int;
- data_ready_i = 1'b0;
- next_data_ready_i = 1'b0;
- counter_next = counter;
- spi_mode_next = spi_mode;
-
- case (tx_CS)
- IDLE: begin
- data_int_next = txdata;
- counter_next = '0;
-
- if (en && data_valid && tx_edge) begin
- spi_mode_next = s_spi_mode;
- data_ready_i = 1'b1;
- tx_NS = TRANSMIT;
- end
- end
-
- TRANSMIT: begin
- if ((counter + 1) ==counter_trgt) begin
- counter_next = 0;
- // Check if there is next data
- if (en && data_valid && tx_edge) begin
- spi_mode_next = s_spi_mode;
- data_int_next = txdata;
- data_ready_i = 1'b1;
- tx_NS = TRANSMIT;
- end else begin
- tx_NS = IDLE;
- end
- end else if (tx32b_done) begin
- if (en && (spi_dummy || data_valid) && tx_edge) begin
- spi_mode_next = s_spi_mode;
- data_int_next = txdata;
- next_data_ready_i = 1'b1;
- counter_next = counter + 1;
- tx_NS = TRANSMIT;
- end else begin
- tx_NS = WAIT_FIFO_AVAIL;
- end
- end else begin
- counter_next = counter + 1;
- data_int_next = (spi_mode == P_QDDR ) ? {data_int[27:0],4'b0000} :
- (spi_mode == P_QUAD ) ? {data_int[27:0],4'b0000} :
- (spi_mode == P_DOUBLE ) ? {data_int[29:0],2'b00} : {data_int[30:0],1'b0};
- end
- end
- WAIT_FIFO_AVAIL: begin
- if (en && data_valid && tx_edge) begin
- spi_mode_next = s_spi_mode;
- data_int_next = txdata;
- data_ready_i = 1'b1;
- tx_NS = TRANSMIT;
- end
- end
- endcase
- end
-
- logic data_ready_f;
-
- always_ff @(posedge clk, negedge rstn)
- begin
- if (~rstn)
- begin
- counter <= 0;
- data_int <= 'h0;
- tx_CS <= IDLE;
- sdo0 <= '0;
- sdo1 <= '0;
- sdo2 <= '1;
- sdo3 <= '1;
- counter_trgt <= '0;
- data_ready <= '0;
- data_ready_f <= 0;
- spi_dummy <= 0;
- spi_mode <= P_SINGLE;
- end
- else if(flush && tx_edge) begin
- counter <= 0;
- data_int <= 'h0;
- tx_CS <= IDLE;
- sdo0 <= '0;
- sdo1 <= '0;
- sdo2 <= '1;
- sdo3 <= '1;
- counter_trgt <= '0;
- data_ready <= '0;
- data_ready_f <= 0;
- spi_dummy <= dummy_phase;
- spi_mode <= P_SINGLE;
- end else begin
- data_ready_f <= data_ready_i | next_data_ready_i;
- data_ready <= data_ready_f && !(data_ready_i | next_data_ready_i); // Generate Pulse at falling edge
- if(tx_edge || (spi_mode_next == P_QDDR)) begin
- tx_CS <= tx_NS;
- counter <= counter_next;
- data_int <= data_int_next;
- end
- // Counter Exit condition, quad mode div-4 , else actual counter
- if (en && data_ready_i && tx_edge) begin
- spi_mode <= s_spi_mode;
- spi_dummy <= dummy_phase;
- counter_trgt <= (s_spi_mode == P_QDDR ) ? {2'b00,counter_in[15:2]} :
- (s_spi_mode == P_QUAD ) ? {2'b00,counter_in[15:2]} :
- (s_spi_mode == P_DOUBLE ) ? {1'b0, counter_in[15:1]} : counter_in;
- end else if (en == 0) begin
- spi_dummy <= '0;
- end
- if((tx_edge || (spi_mode_next == P_QDDR)) && tx_NS == TRANSMIT) begin
- sdo0 <= ((spi_mode_next == P_QUAD) || (spi_mode_next == P_QDDR))? data_int_next[28] : (spi_mode_next == P_DOUBLE) ? data_int_next[30] : data_int_next[31];
- sdo1 <= ((spi_mode_next == P_QUAD) || (spi_mode_next == P_QDDR))? data_int_next[29] : (spi_mode_next == P_DOUBLE) ? data_int_next[31] : 1'b0;
- sdo2 <= ((spi_mode_next == P_QUAD) || (spi_mode_next == P_QDDR))? data_int_next[30] : 1'b1; // Protect
- sdo3 <= ((spi_mode_next == P_QUAD) || (spi_mode_next == P_QDDR))? data_int_next[31] : 1'b1; // Hold need to '1'
- end
- end
- end
-endmodule
diff --git a/verilog/rtl/spi_master/synth/Makefile b/verilog/rtl/spi_master/synth/Makefile
deleted file mode 100644
index f6ae1df..0000000
--- a/verilog/rtl/spi_master/synth/Makefile
+++ /dev/null
@@ -1,49 +0,0 @@
-# //////////////////////////////////////////////////////////////////////////////
-# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
-# //
-# // Licensed under the Apache License, Version 2.0 (the "License");
-# // you may not use this file except in compliance with the License.
-# // You may obtain a copy of the License at
-# //
-# // http://www.apache.org/licenses/LICENSE-2.0
-# //
-# // Unless required by applicable law or agreed to in writing, software
-# // distributed under the License is distributed on an "AS IS" BASIS,
-# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# // See the License for the specific language governing permissions and
-# // limitations under the License.
-# // SPDX-License-Identifier: Apache-2.0
-# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
-# // //////////////////////////////////////////////////////////////////////////
-#------------------------------------------------------------------------------
-# Makefile for Synthesis
-#------------------------------------------------------------------------------
-
-# Paths
-export ROOT_DIR := $(shell pwd)
-export REPORT_DIR := $(ROOT_DIR)/reports
-export NETLIST_DIR := $(ROOT_DIR)/netlist
-export TMP_DIR := $(ROOT_DIR)/tmp
-
-
-# Targets
-.PHONY: clean create synth
-
-default: clean create synth
-
-synth: clean create
- yosys -g -c synth.tcl -l synth.log
-
-create:
- mkdir -p ./tmp/synthesis;
- mkdir -p ./reports;
- mkdir -p ./netlist;
- $(OPENLANE_ROOT)/scripts/libtrim.pl $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib $(PDK_ROOT)/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells > ./tmp/trimmed.lib
-
-
-
-clean:
- $(RM) -R synth.log
- $(RM) -R $(REPORT_DIR)
- $(RM) -R $(NETLIST_DIR)
- $(RM) -R $(TMP_DIR)
diff --git a/verilog/rtl/spi_master/synth/synth.tcl b/verilog/rtl/spi_master/synth/synth.tcl
deleted file mode 100755
index aa97d89..0000000
--- a/verilog/rtl/spi_master/synth/synth.tcl
+++ /dev/null
@@ -1,391 +0,0 @@
-# //////////////////////////////////////////////////////////////////////////////
-# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
-# //
-# // Licensed under the Apache License, Version 2.0 (the "License");
-# // you may not use this file except in compliance with the License.
-# // You may obtain a copy of the License at
-# //
-# // http://www.apache.org/licenses/LICENSE-2.0
-# //
-# // Unless required by applicable law or agreed to in writing, software
-# // distributed under the License is distributed on an "AS IS" BASIS,
-# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# // See the License for the specific language governing permissions and
-# // limitations under the License.
-# // SPDX-License-Identifier: Apache-2.0
-# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
-# // //////////////////////////////////////////////////////////////////////////
-# inputs expected as env vars
-#set opt $::env(SYNTH_OPT)
-########### config.tcl ##################
-# User config
-
-# User config
-set ::env(DESIGN_DIR) ../
-
-set ::env(PROJ_DIR) ../../../../
-
-# User config
-set ::env(DESIGN_NAME) spim_ctrl
-
-# Change if needed
-set ::env(VERILOG_FILES) [glob \
- ../src/spim_clkgen.sv \
- ../src/spim_ctrl.sv \
- ../src/spim_fifo.sv \
- ../src/spim_regs.sv \
- ../src/spim_rx.sv \
- ../src/spim_top.sv \
- ../src/spim_tx.sv ]
-
-
-set ::env(SYNTH_DEFINES) [list YOSYS ]
-
-
-set ::env(LIB_SYNTH) ./tmp/trimmed.lib
-
-
-# Fill this
-set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "mclk"
-set ::env(CLOCK_TREE_SYNTH) 0
-
-set ::env(RUN_SIMPLE_CTS) 0
-set ::env(SYNTH_BUFFERING) 0
-set ::env(SYNTH_SIZING) 0
-
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
-set ::env(SYNTH_CAP_LOAD) "17.65"
-set ::env(SYNTH_MAX_TRAN) "[expr {0.1*10.0}]"
-
-set ::env(SYNTH_MAX_FANOUT) 6
-set ::env(FP_CORE_UTIL) 50
-set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
-set ::env(CELL_PAD) 4
-
-set ::env(SYNTH_NO_FLAT) "0"
-
-
-set ::env(SYNTH_STRATEGY) "AREA 0"
-set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_hd__conb_1 LO"
-set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_hd__conb_1 HI"
-set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_hd__buf_2 A X"
-
-
-set ::env(CLOCK_NET) $::env(CLOCK_PORT)
-
-
-
-set ::env(yosys_tmp_file_tag) "./tmp/"
-set ::env(TMP_DIR) "./tmp/"
-set ::env(yosys_netlist_dir) "./netlist"
-set ::env(yosys_report_file_tag) "./reports/yosys"
-set ::env(yosys_result_file_tag) "./reports/yosys.synthesis"
-
-set ::env(SAVE_NETLIST) $::env(yosys_netlist_dir)/$::env(DESIGN_NAME).gv
-
-
-
-########### End of config.tcl
-set buffering $::env(SYNTH_BUFFERING)
-set sizing $::env(SYNTH_SIZING)
-
-yosys -import
-
-set vtop $::env(DESIGN_NAME)
-#set sdc_file $::env(SDC_FILE)
-set sclib $::env(LIB_SYNTH)
-
-if { [info exists ::env(SYNTH_DEFINES) ] } {
- foreach define $::env(SYNTH_DEFINES) {
- log "Defining $define"
- verilog_defines -D$define
- }
-}
-
-set vIdirsArgs ""
-if {[info exist ::env(VERILOG_INCLUDE_DIRS)]} {
- foreach dir $::env(VERILOG_INCLUDE_DIRS) {
- log "Adding include file -I$dir "
- lappend vIdirsArgs "-I$dir"
- }
- set vIdirsArgs [join $vIdirsArgs]
-}
-
-
-
-if { [info exists ::env(EXTRA_LIBS) ] } {
- foreach lib $::env(EXTRA_LIBS) {
- read_liberty {*}$vIdirsArgs -lib -ignore_miss_dir -setattr blackbox $lib
- }
-}
-
-
-
-# ns expected (in sdc as well)
-set clock_period [expr {$::env(CLOCK_PERIOD)*1000}]
-
-set driver $::env(SYNTH_DRIVING_CELL)
-set cload $::env(SYNTH_CAP_LOAD)
-# input pin cap of IN_3VX8
-set max_FO $::env(SYNTH_MAX_FANOUT)
-if {![info exist ::env(SYNTH_MAX_TRAN)]} {
- set ::env(SYNTH_MAX_TRAN) [expr {0.1*$clock_period}]
-} else {
- set ::env(SYNTH_MAX_TRAN) [expr {$::env(SYNTH_MAX_TRAN) * 1000}]
-}
-set max_Tran $::env(SYNTH_MAX_TRAN)
-
-
-# Mapping parameters
-set A_factor 0.00
-set B_factor 0.88
-set F_factor 0.00
-
-# Don't change these unless you know what you are doing
-set stat_ext ".stat.rpt"
-set chk_ext ".chk.rpt"
-set gl_ext ".gl.v"
-set constr_ext ".$clock_period.constr"
-set timing_ext ".timing.txt"
-set abc_ext ".abc"
-
-
-# get old sdc, add library specific stuff for abc scripts
-set sdc_file $::env(yosys_tmp_file_tag).sdc
-set outfile [open ${sdc_file} w]
-#puts $outfile $sdc_data
-puts $outfile "set_driving_cell ${driver}"
-puts $outfile "set_load ${cload}"
-close $outfile
-
-
-# ABC Scrips
-set abc_rs_K "resub,-K,"
-set abc_rs "resub"
-set abc_rsz "resub,-z"
-set abc_rw_K "rewrite,-K,"
-set abc_rw "rewrite"
-set abc_rwz "rewrite,-z"
-set abc_rf "refactor"
-set abc_rfz "refactor,-z"
-set abc_b "balance"
-
-set abc_resyn2 "${abc_b}; ${abc_rw}; ${abc_rf}; ${abc_b}; ${abc_rw}; ${abc_rwz}; ${abc_b}; ${abc_rfz}; ${abc_rwz}; ${abc_b}"
-set abc_share "strash; multi,-m; ${abc_resyn2}"
-set abc_resyn2a "${abc_b};${abc_rw};${abc_b};${abc_rw};${abc_rwz};${abc_b};${abc_rwz};${abc_b}"
-set abc_resyn3 "balance;resub;resub,-K,6;balance;resub,-z;resub,-z,-K,6;balance;resub,-z,-K,5;balance"
-set abc_resyn2rs "${abc_b};${abc_rs_K},6;${abc_rw};${abc_rs_K},6,-N,2;${abc_rf};${abc_rs_K},8;${abc_rw};${abc_rs_K},10;${abc_rwz};${abc_rs_K},10,-N,2;${abc_b},${abc_rs_K},12;${abc_rfz};${abc_rs_K},12,-N,2;${abc_rwz};${abc_b}"
-
-set abc_choice "fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; fraig_restore"
-set abc_choice2 "fraig_store; balance; fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; fraig_restore"
-
-set abc_map_old_cnt "map,-p,-a,-B,0.2,-A,0.9,-M,0"
-set abc_map_old_dly "map,-p,-B,0.2,-A,0.9,-M,0"
-set abc_retime_area "retime,-D,{D},-M,5"
-set abc_retime_dly "retime,-D,{D},-M,6"
-set abc_map_new_area "amap,-m,-Q,0.1,-F,20,-A,20,-C,5000"
-
-set abc_area_recovery_1 "${abc_choice}; map;"
-set abc_area_recovery_2 "${abc_choice2}; map;"
-
-set map_old_cnt "map,-p,-a,-B,0.2,-A,0.9,-M,0"
-set map_old_dly "map,-p,-B,0.2,-A,0.9,-M,0"
-set abc_retime_area "retime,-D,{D},-M,5"
-set abc_retime_dly "retime,-D,{D},-M,6"
-set abc_map_new_area "amap,-m,-Q,0.1,-F,20,-A,20,-C,5000"
-
-if {$buffering==1} {
- set abc_fine_tune "buffer,-N,${max_FO},-S,${max_Tran};upsize,{D};dnsize,{D}"
-} elseif {$sizing} {
- set abc_fine_tune "upsize,{D};dnsize,{D}"
-} else {
- set abc_fine_tune ""
-}
-
-
-set delay_scripts [list \
- "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_map_old_dly};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
- \
- "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice2};${abc_map_old_dly};${abc_area_recovery_2}; retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
- \
- "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice};${abc_map_old_dly};${abc_area_recovery_1}; retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
- \
- "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_old_dly};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
- ]
-
-set area_scripts [list \
- "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
- \
- "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
- \
- "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_choice2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
- ]
-
-set all_scripts [list {*}$delay_scripts {*}$area_scripts]
-
-set strategy_parts [split $::env(SYNTH_STRATEGY)]
-
-proc synth_strategy_format_err { } {
- upvar area_scripts area_scripts
- upvar delay_scripts delay_scripts
- log -stderr "\[ERROR] Misformatted SYNTH_STRATEGY (\"$::env(SYNTH_STRATEGY)\")."
- log -stderr "\[ERROR] Correct format is \"DELAY|AREA 0-[expr [llength $delay_scripts]-1]|0-[expr [llength $area_scripts]-1]\"."
- exit 1
-}
-
-if { [llength $strategy_parts] != 2 } {
- synth_strategy_format_err
-}
-
-set strategy_type [lindex $strategy_parts 0]
-set strategy_type_idx [lindex $strategy_parts 1]
-
-if { $strategy_type != "AREA" && $strategy_type != "DELAY" } {
- log -stderr "\[ERROR] AREA|DELAY tokens not found. ($strategy_type)"
- synth_strategy_format_err
-}
-
-if { $strategy_type == "DELAY" && $strategy_type_idx >= [llength $delay_scripts] } {
- log -stderr "\[ERROR] strategy index ($strategy_type_idx) is too high."
- synth_strategy_format_err
-}
-
-if { $strategy_type == "AREA" && $strategy_type_idx >= [llength $area_scripts] } {
- log -stderr "\[ERROR] strategy index ($strategy_type_idx) is too high."
- synth_strategy_format_err
-}
-
-if { $strategy_type == "DELAY" } {
- set strategy $strategy_type_idx
-} else {
- set strategy [expr {[llength $delay_scripts]+$strategy_type_idx}]
-}
-
-
-for { set i 0 } { $i < [llength $::env(VERILOG_FILES)] } { incr i } {
- read_verilog -sv {*}$vIdirsArgs [lindex $::env(VERILOG_FILES) $i]
-}
-
-if { [info exists ::env(VERILOG_FILES_BLACKBOX)] } {
- foreach verilog_file $::env(VERILOG_FILES_BLACKBOX) {
- read_verilog -sv {*}$vIdirsArgs -lib $verilog_file
- }
-}
-select -module $vtop
-show -format dot -prefix $::env(TMP_DIR)/synthesis/hierarchy
-select -clear
-
-hierarchy -check -top $vtop
-
-# Infer tri-state buffers.
-set tbuf_map false
-if { [info exists ::env(TRISTATE_BUFFER_MAP)] } {
- if { [file exists $::env(TRISTATE_BUFFER_MAP)] } {
- set tbuf_map true
- tribuf
- } else {
- log "WARNING: TRISTATE_BUFFER_MAP is defined but could not be found: $::env(TRISTATE_BUFFER_MAP)"
- }
-}
-
-if { $::env(SYNTH_NO_FLAT) } {
- synth -top $vtop
-} else {
- synth -top $vtop -flatten
-}
-
-share -aggressive
-opt
-opt_clean -purge
-
-tee -o "$::env(yosys_report_file_tag)_pre.stat" stat
-
-# Map tri-state buffers.
-if { $tbuf_map } {
- log {mapping tbuf}
- techmap -map $::env(TRISTATE_BUFFER_MAP)
- simplemap
-}
-
-# handle technology mapping of 4-MUX, and tell Yosys to infer 4-muxes
-if { [info exists ::env(SYNTH_MUX4_MAP)] && [file exists $::env(SYNTH_MUX4_MAP)] } {
- muxcover -mux4
- techmap -map $::env(SYNTH_MUX4_MAP)
- simplemap
-}
-
-# handle technology mapping of 2-MUX
-if { [info exists ::env(SYNTH_MUX_MAP)] && [file exists $::env(SYNTH_MUX_MAP)] } {
- techmap -map $::env(SYNTH_MUX_MAP)
- simplemap
-}
-
-# handle technology mapping of latches
-if { [info exists ::env(SYNTH_LATCH_MAP)] && [file exists $::env(SYNTH_LATCH_MAP)] } {
- techmap -map $::env(SYNTH_LATCH_MAP)
- simplemap
-}
-
-dfflibmap -liberty $sclib
-tee -o "$::env(yosys_report_file_tag)_dff.stat" stat
-
-if { [info exists ::env(SYNTH_EXPLORE)] && $::env(SYNTH_EXPLORE) } {
- design -save myDesign
-
- for { set index 0 } { $index < [llength $all_scripts] } { incr index } {
- log "\[INFO\]: ABC: WireLoad : S_$index"
- design -load myDesign
-
- abc -D $clock_period \
- -constr "$sdc_file" \
- -liberty $sclib \
- -script [lindex $all_scripts $index]
-
- setundef -zero
-
- hilomap -hicell {*}$::env(SYNTH_TIEHI_PORT) -locell {*}$::env(SYNTH_TIELO_PORT)
-
- # get rid of the assignments that make verilog2def fail
- splitnets
- opt_clean -purge
- insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
-
- tee -o "$::env(yosys_report_file_tag)_$index$chk_ext" check
- write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(yosys_result_file_tag)_$index.v"
- design -reset
- }
-} else {
-
- log "\[INFO\]: ABC: WireLoad : S_$strategy"
-
- abc -D $clock_period \
- -constr "$sdc_file" \
- -liberty $sclib \
- -script [lindex $all_scripts $strategy] \
- -showtmp;
-
- setundef -zero
-
- hilomap -hicell {*}$::env(SYNTH_TIEHI_PORT) -locell {*}$::env(SYNTH_TIELO_PORT)
-
- # get rid of the assignments that make verilog2def fail
- splitnets
- opt_clean -purge
- insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
-
- tee -o "$::env(yosys_report_file_tag)_$strategy$chk_ext" check
- write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)"
-}
-
-if { $::env(SYNTH_NO_FLAT) } {
- design -reset
- file copy -force $::env(SAVE_NETLIST) $::env(yosys_tmp_file_tag)_unflat.v
- read_verilog -sv $::env(SAVE_NETLIST)
- synth -top $vtop -flatten
- splitnets
- opt_clean -purge
- insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
- write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)"
- tee -o "$::env(yosys_report_file_tag)_$strategy$chk_ext" check
-}
diff --git a/verilog/rtl/sspim/src/filelist_spi.f b/verilog/rtl/sspim/src/filelist_spi.f
new file mode 100755
index 0000000..23a2ad5
--- /dev/null
+++ b/verilog/rtl/sspim/src/filelist_spi.f
@@ -0,0 +1,5 @@
+sspim_top.sv
+sspim_ctl.sv
+sspim_if.sv
+sspim_cfg.sv
+-v ../../lib/registers.v
diff --git a/verilog/rtl/sspim/src/sspim_cfg.sv b/verilog/rtl/sspim/src/sspim_cfg.sv
new file mode 100755
index 0000000..cd39e1f
--- /dev/null
+++ b/verilog/rtl/sspim/src/sspim_cfg.sv
@@ -0,0 +1,298 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Single SPI Master Interface Module ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// Subbport Single Bit SPI Master ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// V.0 - 06 Oct 2021 ////
+//// Initial SpI Module picked from ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+
+module sspim_cfg (
+ input logic mclk ,
+ input logic reset_n ,
+
+ output logic [1:0] cfg_tgt_sel ,
+
+ output logic cfg_op_req , // SPI operation request
+ output logic [1:0] cfg_op_type , // SPI operation type
+ output logic [1:0] cfg_transfer_size , // SPI transfer size
+ output logic [5:0] cfg_sck_period , // sck clock period
+ output logic [4:0] cfg_sck_cs_period , // cs setup/hold period
+ output logic [7:0] cfg_cs_byte , // cs bit information
+ output logic [31:0] cfg_datain , // data for transfer
+ input logic [31:0] cfg_dataout , // data for received
+ input logic hware_op_done , // operation done
+
+ //---------------------------------
+ // Reg Bus Interface Signal
+ //---------------------------------
+ input logic reg_cs ,
+ input logic reg_wr ,
+ input logic [7:0] reg_addr ,
+ input logic [31:0] reg_wdata ,
+ input logic [3:0] reg_be ,
+
+ // Outputs
+ output logic [31:0] reg_rdata ,
+ output logic reg_ack
+
+
+ );
+
+
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+logic sw_rd_en ;
+logic sw_wr_en;
+logic [1:0] sw_addr; // addressing 16 registers
+logic [31:0] sw_reg_wdata;
+logic [3:0] wr_be ;
+logic reg_cs_l;
+logic reg_cs_2l;
+
+logic [31:0] reg_0; // Software_Reg_0
+logic [31:0] reg_1; // Software-Reg_1
+logic [31:0] reg_2; // Software-Reg_2
+logic [31:0] reg_out;
+
+//-----------------------------------------------------------------------
+// Main code starts here
+//-----------------------------------------------------------------------
+
+//-----------------------------------------------------------------------
+// To avoid interface timing, all the content are registered
+//-----------------------------------------------------------------------
+always @ (posedge mclk or negedge reset_n)
+begin
+ if (reset_n == 1'b0)
+ begin
+ sw_addr <= '0;
+ sw_rd_en <= '0;
+ sw_wr_en <= '0;
+ sw_reg_wdata <= '0;
+ wr_be <= '0;
+ reg_cs_l <= '0;
+ reg_cs_2l <= '0;
+ end else begin
+ sw_addr <= reg_addr [3:2];
+ sw_rd_en <= reg_cs & !reg_wr;
+ sw_wr_en <= reg_cs & reg_wr;
+ sw_reg_wdata <= reg_wdata;
+ wr_be <= reg_be;
+ reg_cs_l <= reg_cs;
+ reg_cs_2l <= reg_cs_l;
+ end
+end
+
+//-----------------------------------------------------------------------
+// Read path mux
+//-----------------------------------------------------------------------
+
+always @ (posedge mclk or negedge reset_n)
+begin : preg_out_Seq
+ if (reset_n == 1'b0) begin
+ reg_rdata [31:0] <= 32'h0000_0000;
+ reg_ack <= 1'b0;
+ end else if (sw_rd_en && !reg_ack && !reg_cs_2l) begin
+ reg_rdata [31:0] <= reg_out [31:0];
+ reg_ack <= 1'b1;
+ end else if (sw_wr_en && !reg_ack && !reg_cs_2l) begin
+ reg_ack <= 1'b1;
+ end else begin
+ reg_ack <= 1'b0;
+ end
+end
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+wire sw_wr_en_0 = sw_wr_en & (sw_addr == 2'h0);
+wire sw_rd_en_0 = sw_rd_en & (sw_addr == 2'h0);
+wire sw_wr_en_1 = sw_wr_en & (sw_addr == 2'h1);
+wire sw_rd_en_1 = sw_rd_en & (sw_addr == 2'h1);
+wire sw_wr_en_2 = sw_wr_en & (sw_addr == 2'h2);
+wire sw_rd_en_2 = sw_rd_en & (sw_addr == 2'h2);
+wire sw_wr_en_3 = sw_wr_en & (sw_addr == 2'h3);
+wire sw_rd_en_3 = sw_rd_en & (sw_addr == 2'h3);
+
+
+always @( *)
+begin : preg_sel_Com
+
+ reg_out [31:0] = 32'd0;
+
+ case (sw_addr [3:0])
+ 4'b0000 : reg_out [31:0] = reg_0 [31:0];
+ 4'b0001 : reg_out [31:0] = reg_1 [31:0];
+ 4'b0010 : reg_out [31:0] = reg_2 [31:0];
+ default : reg_out [31:0] = 32'h0;
+ endcase
+end
+
+
+
+//-----------------------------------------------------------------------
+// Individual register assignments
+//-----------------------------------------------------------------------
+// Logic for Register 0 : SPI Control Register
+//-----------------------------------------------------------------------
+assign cfg_op_req = reg_0[31]; // cpu request
+assign cfg_tgt_sel = reg_0[24:23]; // target chip select
+assign cfg_op_type = reg_0[22:21]; // SPI operation type
+assign cfg_transfer_size = reg_0[20:19]; // SPI transfer size
+assign cfg_sck_period = reg_0[18:13]; // sck clock period
+assign cfg_sck_cs_period = reg_0[12:8]; // cs setup/hold period
+assign cfg_cs_byte = reg_0[7:0]; // cs bit information
+
+generic_register #(8,0 ) u_spi_ctrl_be0 (
+ .we ({8{sw_wr_en_0 &
+ wr_be[0] }} ),
+ .data_in (sw_reg_wdata[7:0] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_0[7:0] )
+ );
+
+generic_register #(8,0 ) u_spi_ctrl_be1 (
+ .we ({8{sw_wr_en_0 &
+ wr_be[1] }} ),
+ .data_in (sw_reg_wdata[15:8] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_0[15:8] )
+ );
+
+generic_register #(8,0 ) u_spi_ctrl_be2 (
+ .we ({8{sw_wr_en_0 &
+ wr_be[2] }} ),
+ .data_in (sw_reg_wdata[23:16] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_0[23:16] )
+ );
+
+assign reg_0[30:24] = 7'h0;
+
+req_register #(0 ) u_spi_ctrl_req (
+ .cpu_we ({sw_wr_en_0 &
+ wr_be[3] } ),
+ .cpu_req (sw_reg_wdata[31] ),
+ .hware_ack (hware_op_done ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_0[31] )
+ );
+
+
+
+
+//-----------------------------------------------------------------------
+// Logic for Register 1 : SPI Data In Register
+//-----------------------------------------------------------------------
+assign cfg_datain = reg_1[31:0];
+
+generic_register #(8,0 ) u_spi_din_be0 (
+ .we ({8{sw_wr_en_1 &
+ wr_be[0] }} ),
+ .data_in (sw_reg_wdata[7:0] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_1[7:0] )
+ );
+
+generic_register #(8,0 ) u_spi_din_be1 (
+ .we ({8{sw_wr_en_1 &
+ wr_be[1] }} ),
+ .data_in (sw_reg_wdata[15:8] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_1[15:8] )
+ );
+
+generic_register #(8,0 ) u_spi_din_be2 (
+ .we ({8{sw_wr_en_1 &
+ wr_be[2] }} ),
+ .data_in (sw_reg_wdata[23:16] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_1[23:16] )
+ );
+
+
+generic_register #(8,0 ) u_spi_din_be3 (
+ .we ({8{sw_wr_en_1 &
+ wr_be[3] }} ),
+ .data_in (sw_reg_wdata[31:24] ),
+ .reset_n (reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_1[31:24] )
+ );
+
+
+//-----------------------------------------------------------------------
+// Logic for Register 2 : SPI Data output Register
+//-----------------------------------------------------------------------
+assign reg_2 = cfg_dataout;
+
+
+
+endmodule
diff --git a/verilog/rtl/sspim/src/sspim_ctl.sv b/verilog/rtl/sspim/src/sspim_ctl.sv
new file mode 100755
index 0000000..f65c0c2
--- /dev/null
+++ b/verilog/rtl/sspim/src/sspim_ctl.sv
@@ -0,0 +1,286 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Single SPI Master Interface Module ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// SPI Control module ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// V.0 - 06 Oct 2021 ////
+//// Initial SpI Module picked from ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+
+module sspim_ctl
+ (
+ input logic clk,
+ input logic reset_n,
+ input logic cfg_op_req,
+ input logic [1:0] cfg_op_type,
+ input logic [1:0] cfg_transfer_size,
+
+ input logic [5:0] cfg_sck_period,
+ input logic [4:0] cfg_sck_cs_period, // cs setup & hold period
+ input logic [7:0] cfg_cs_byte,
+ input logic [31:0] cfg_datain,
+ output logic [31:0] cfg_dataout,
+
+ output logic [7:0] byte_out, // Byte out for Serial Shifting out
+ input logic [7:0] byte_in, // Serial Received Byte
+ output logic sck_int,
+ output logic cs_int_n,
+ output logic sck_pe,
+ output logic sck_ne,
+ output logic shift_out,
+ output logic shift_in,
+ output logic load_byte,
+ output logic op_done
+
+ );
+
+ //*************************************************************************
+
+
+ logic [5:0] clk_cnt;
+ logic [5:0] sck_cnt;
+
+ logic [3:0] spiif_cs;
+ logic shift_enb;
+ logic clr_sck_cnt ;
+ logic sck_out_en;
+
+ logic [5:0] sck_half_period;
+ logic [2:0] byte_cnt;
+
+
+ `define SPI_IDLE 4'b0000
+ `define SPI_CS_SU 4'b0001
+ `define SPI_WRITE 4'b0010
+ `define SPI_READ 4'b0011
+ `define SPI_CS_HLD 4'b0100
+ `define SPI_WAIT 4'b0101
+
+
+ assign sck_half_period = {1'b0, cfg_sck_period[5:1]};
+ // The first transition on the sck_toggle happens one SCK period
+ // after op_en or boot_en is asserted
+ always @(posedge clk or negedge reset_n) begin
+ if(!reset_n) begin
+ sck_ne <= 1'b0;
+ clk_cnt <= 6'h1;
+ sck_pe <= 1'b0;
+ sck_int <= 1'b0;
+ end // if (!reset_n)
+ else
+ begin
+ if(cfg_op_req)
+ begin
+ if(clk_cnt == sck_half_period)
+ begin
+ sck_ne <= 1'b1;
+ sck_pe <= 1'b0;
+ if(sck_out_en) sck_int <= 0;
+ clk_cnt <= clk_cnt + 1'b1;
+ end // if (clk_cnt == sck_half_period)
+ else
+ begin
+ if(clk_cnt == cfg_sck_period)
+ begin
+ sck_ne <= 1'b0;
+ sck_pe <= 1'b1;
+ if(sck_out_en) sck_int <= 1;
+ clk_cnt <= 6'h1;
+ end // if (clk_cnt == cfg_sck_period)
+ else
+ begin
+ clk_cnt <= clk_cnt + 1'b1;
+ sck_pe <= 1'b0;
+ sck_ne <= 1'b0;
+ end // else: !if(clk_cnt == cfg_sck_period)
+ end // else: !if(clk_cnt == sck_half_period)
+ end // if (op_en)
+ else
+ begin
+ clk_cnt <= 6'h1;
+ sck_pe <= 1'b0;
+ sck_ne <= 1'b0;
+ end // else: !if(op_en)
+ end // else: !if(!reset_n)
+ end // always @ (posedge clk or negedge reset_n)
+
+
+wire [1:0] cs_data = (byte_cnt == 2'b00) ? cfg_cs_byte[7:6] :
+ (byte_cnt == 2'b01) ? cfg_cs_byte[5:4] :
+ (byte_cnt == 2'b10) ? cfg_cs_byte[3:2] : cfg_cs_byte[1:0] ;
+
+assign byte_out = (byte_cnt == 2'b00) ? cfg_datain[31:24] :
+ (byte_cnt == 2'b01) ? cfg_datain[23:16] :
+ (byte_cnt == 2'b10) ? cfg_datain[15:8] : cfg_datain[7:0] ;
+
+assign shift_out = shift_enb && sck_ne;
+
+always @(posedge clk or negedge reset_n) begin
+ if(!reset_n) begin
+ spiif_cs <= `SPI_IDLE;
+ sck_cnt <= 6'h0;
+ shift_in <= 1'b0;
+ clr_sck_cnt <= 1'b1;
+ byte_cnt <= 2'b00;
+ cs_int_n <= 1'b1;
+ sck_out_en <= 1'b0;
+ shift_enb <= 1'b0;
+ cfg_dataout <= 32'h0;
+ load_byte <= 1'b0;
+ end
+ else begin
+ if(sck_ne)
+ sck_cnt <= clr_sck_cnt ? 6'h0 : sck_cnt + 1 ;
+
+ case(spiif_cs)
+ `SPI_IDLE :
+ begin
+ op_done <= 0;
+ clr_sck_cnt <= 1'b1;
+ sck_out_en <= 1'b0;
+ shift_enb <= 1'b0;
+ if(cfg_op_req)
+ begin
+ cfg_dataout <= 32'h0;
+ spiif_cs <= `SPI_CS_SU;
+ end
+ else begin
+ spiif_cs <= `SPI_IDLE;
+ end
+ end
+
+ `SPI_CS_SU :
+ begin
+ if(sck_ne) begin
+ cs_int_n <= cs_data[1];
+ if(sck_cnt == cfg_sck_cs_period) begin
+ clr_sck_cnt <= 1'b1;
+ if(cfg_op_type == 0) begin // Write Mode
+ load_byte <= 1'b1;
+ spiif_cs <= `SPI_WRITE;
+ shift_enb <= 1'b0;
+ end else begin
+ shift_in <= 1;
+ spiif_cs <= `SPI_READ;
+ end
+ end
+ else begin
+ clr_sck_cnt <= 1'b0;
+ end
+ end
+ end
+
+ `SPI_WRITE :
+ begin
+ load_byte <= 1'b0;
+ if(sck_ne) begin
+ if(sck_cnt == 3'h7 )begin
+ clr_sck_cnt <= 1'b1;
+ spiif_cs <= `SPI_CS_HLD;
+ shift_enb <= 1'b0;
+ sck_out_en <= 1'b0; // Disable clock output
+ end
+ else begin
+ shift_enb <= 1'b1;
+ sck_out_en <= 1'b1;
+ clr_sck_cnt <= 1'b0;
+ end
+ end else begin
+ shift_enb <= 1'b1;
+ end
+ end
+
+ `SPI_READ :
+ begin
+ if(sck_ne) begin
+ if( sck_cnt == 3'h7 ) begin
+ clr_sck_cnt <= 1'b1;
+ shift_in <= 0;
+ spiif_cs <= `SPI_CS_HLD;
+ sck_out_en <= 1'b0; // Disable clock output
+ end
+ else begin
+ sck_out_en <= 1'b1; // Disable clock output
+ clr_sck_cnt <= 1'b0;
+ end
+ end
+ end
+
+ `SPI_CS_HLD : begin
+ if(sck_ne) begin
+ cs_int_n <= cs_data[0];
+ if(sck_cnt == cfg_sck_cs_period) begin
+ if(cfg_op_type == 1) begin // Read Mode
+ cfg_dataout <= (byte_cnt[1:0] == 2'b00) ? { byte_in, cfg_dataout[23:0] } :
+ (byte_cnt[1:0] == 2'b01) ? { cfg_dataout[31:24] ,
+ byte_in, cfg_dataout[15:0] } :
+ (byte_cnt[1:0] == 2'b10) ? { cfg_dataout[31:16] ,
+ byte_in, cfg_dataout[7:0] } :
+ { cfg_dataout[31:8] ,
+ byte_in } ;
+ end
+ clr_sck_cnt <= 1'b1;
+ if(byte_cnt == cfg_transfer_size) begin
+ spiif_cs <= `SPI_WAIT;
+ byte_cnt <= 0;
+ op_done <= 1;
+ end else begin
+ byte_cnt <= byte_cnt +1;
+ spiif_cs <= `SPI_CS_SU;
+ end
+ end
+ else begin
+ clr_sck_cnt <= 1'b0;
+ end
+ end
+ end // case: `SPI_CS_HLD
+ `SPI_WAIT : begin
+ if(!cfg_op_req) // Wait for Request de-assertion
+ spiif_cs <= `SPI_IDLE;
+ end
+ endcase // casex(spiif_cs)
+ end
+end // always @(sck_ne
+
+endmodule
diff --git a/verilog/rtl/sspim/src/sspim_if.sv b/verilog/rtl/sspim/src/sspim_if.sv
new file mode 100755
index 0000000..42b18f2
--- /dev/null
+++ b/verilog/rtl/sspim/src/sspim_if.sv
@@ -0,0 +1,122 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Single SPI Master Interface Module ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// V.0 - 06 Oct 2021 ////
+//// Initial SpI Module picked from ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module sspim_if
+ (
+ input logic clk,
+ input logic reset_n,
+ input logic sck_pe,
+ input logic sck_int,
+ input logic cs_int_n,
+
+ input logic load_byte,
+ input logic [1:0] cfg_tgt_sel,
+
+ input logic [7:0] byte_out,
+ input logic shift_out,
+ input logic shift_in,
+
+ output logic [7:0] byte_in,
+ output logic sck,
+ output logic so,
+ output logic [3:0] cs_n,
+ input logic si
+ );
+
+
+
+ logic [7:0] so_reg;
+ logic [7:0] si_reg;
+
+
+ //Output Shift Register
+
+ always @(posedge clk or negedge reset_n) begin
+ if(!reset_n) begin
+ so_reg <= 8'h00;
+ so <= 1'b0;
+ end
+ else begin
+ if(load_byte) begin
+ so_reg <= byte_out;
+ if(shift_out) begin
+ // Handling backto back case :
+ // Last Transfer bit + New Trasfer Load
+ so <= so_reg[7];
+ end
+ end // if (load_byte)
+ else begin
+ if(shift_out) begin
+ so <= so_reg[7];
+ so_reg <= {so_reg[6:0],1'b0};
+ end // if (shift_out)
+ end // else: !if(load_byte)
+ end // else: !if(!reset_n)
+ end // always @ (posedge clk or negedge reset_n)
+
+
+// Input shift register
+ always @(posedge clk or negedge reset_n) begin
+ if(!reset_n) begin
+ si_reg <= 8'h0;
+ end
+ else begin
+ if(sck_pe & shift_in) begin
+ si_reg[7:0] <= {si_reg[6:0],si};
+ end // if (sck_pe & shift_in)
+ end // else: !if(!reset_n)
+ end // always @ (posedge clk or negedge reset_n)
+
+
+ assign byte_in[7:0] = si_reg[7:0];
+ assign cs_n[0] = (cfg_tgt_sel[1:0] == 2'b00) ? cs_int_n : 1'b1;
+ assign cs_n[1] = (cfg_tgt_sel[1:0] == 2'b01) ? cs_int_n : 1'b1;
+ assign cs_n[2] = (cfg_tgt_sel[1:0] == 2'b10) ? cs_int_n : 1'b1;
+ assign cs_n[3] = (cfg_tgt_sel[1:0] == 2'b11) ? cs_int_n : 1'b1;
+ assign sck = sck_int;
+
+endmodule
diff --git a/verilog/rtl/sspim/src/sspim_top.sv b/verilog/rtl/sspim/src/sspim_top.sv
new file mode 100755
index 0000000..0c740d6
--- /dev/null
+++ b/verilog/rtl/sspim/src/sspim_top.sv
@@ -0,0 +1,208 @@
+
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SPI Master Top Module ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// This block integrate the SPI Master related module ////
+//// - sspim_if ////
+//// - sspim_ctl ////
+//// - sspim_cfg ////
+//// ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 03 Oct 2021, Dinesh A ////
+//// Initial SpI Module picked from ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+module sspim_top (
+ input logic clk ,
+ input logic reset_n ,
+
+
+ //---------------------------------
+ // Reg Bus Interface Signal
+ //---------------------------------
+ input logic reg_cs ,
+ input logic reg_wr ,
+ input logic [7:0] reg_addr ,
+ input logic [31:0] reg_wdata ,
+ input logic [3:0] reg_be ,
+
+ // Outputs
+ output logic [31:0] reg_rdata ,
+ output logic reg_ack ,
+
+ //-------------------------------------------
+ // Line Interface
+ //-------------------------------------------
+
+ output logic sck , // clock out
+ output logic so , // serial data out
+ input logic si , // serial data in
+ output logic ssn // cs_n
+
+ );
+
+
+//------------------------------------
+// Local declration
+//------------------------------------
+
+logic [7:0] byte_in ;
+logic [7:0] byte_out ;
+
+
+logic [1:0] cfg_tgt_sel ;
+
+logic cfg_op_req ; // SPI operation request
+logic [1:0] cfg_op_type ; // SPI operation type
+logic [1:0] cfg_transfer_size ; // SPI transfer size
+logic [5:0] cfg_sck_period ; // sck clock period
+logic [4:0] cfg_sck_cs_period ; // cs setup/hold period
+logic [7:0] cfg_cs_byte ; // cs bit information
+logic [31:0] cfg_datain ; // data for transfer
+logic [31:0] cfg_dataout ; // data for received
+logic hware_op_done ; // operation done
+logic [3:0] cs_n ; // cs_n
+
+assign ssn = cs_n[0]; // Only 1 chip select supported in riscdunio
+
+sspim_if u_spi_if
+ (
+ . clk (clk ),
+ . reset_n (reset_n ),
+
+ // towards ctrl i/f
+ . sck_pe (sck_pe ),
+ . sck_int (sck_int ),
+ . cs_int_n (cs_int_n ),
+ . byte_in (byte_in ),
+ . load_byte (load_byte ),
+ . byte_out (byte_out ),
+ . shift_out (shift_out ),
+ . shift_in (shift_in ),
+
+ . cfg_tgt_sel (cfg_tgt_sel ),
+
+ . sck (sck ),
+ . so (so ),
+ . si (si ),
+ . cs_n (cs_n )
+ );
+
+
+sspim_ctl u_spi_ctrl
+ (
+ . clk (clk ),
+ . reset_n (reset_n ),
+
+ . cfg_op_req (cfg_op_req ),
+ . cfg_op_type (cfg_op_type ),
+ . cfg_transfer_size (cfg_transfer_size ),
+ . cfg_sck_period (cfg_sck_period ),
+ . cfg_sck_cs_period (cfg_sck_cs_period ),
+ . cfg_cs_byte (cfg_cs_byte ),
+ . cfg_datain (cfg_datain ),
+ . cfg_dataout (cfg_dataout ),
+ . op_done (hware_op_done ),
+
+ . sck_int (sck_int ),
+ . cs_int_n (cs_int_n ),
+ . sck_pe (sck_pe ),
+ . sck_ne (sck_ne ),
+ . shift_out (shift_out ),
+ . shift_in (shift_in ),
+ . load_byte (load_byte ),
+ . byte_out (byte_out ),
+ . byte_in (byte_in )
+
+ );
+
+
+
+
+sspim_cfg u_cfg (
+
+ . mclk (clk ),
+ . reset_n (reset_n ),
+
+ // Reg Bus Interface Signal
+ . reg_cs (reg_cs ),
+ . reg_wr (reg_wr ),
+ . reg_addr (reg_addr ),
+ . reg_wdata (reg_wdata ),
+ . reg_be (reg_be ),
+
+ // Outputs
+ . reg_rdata (reg_rdata ),
+ . reg_ack (reg_ack ),
+
+
+ // configuration signal
+ . cfg_tgt_sel (cfg_tgt_sel ),
+ . cfg_op_req (cfg_op_req ), // SPI operation request
+ . cfg_op_type (cfg_op_type ), // SPI operation type
+ . cfg_transfer_size (cfg_transfer_size ), // SPI transfer size
+ . cfg_sck_period (cfg_sck_period ), // sck clock period
+ . cfg_sck_cs_period (cfg_sck_cs_period ), // cs setup/hold period
+ . cfg_cs_byte (cfg_cs_byte ), // cs bit information
+ . cfg_datain (cfg_datain ), // data for transfer
+ . cfg_dataout (cfg_dataout ), // data for received
+ . hware_op_done (hware_op_done ) // operation done
+
+ );
+
+endmodule
diff --git a/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv b/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
new file mode 100644
index 0000000..13555ae
--- /dev/null
+++ b/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
@@ -0,0 +1,262 @@
+
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// integrated UART,I2C Master, SPU Master & USB1.1 Host ////
+//// ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description: This module integarte Uart , I2C Master ////
+//// SPI Master and USB 1.1 Host. ////
+//// ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module uart_i2c_usb_spi_top
+
+ (
+
+ input logic uart_rstn , // async reset
+ input logic i2c_rstn , // async reset
+ input logic usb_rstn , // async reset
+ input logic spi_rstn , // async reset
+ input logic app_clk ,
+ input logic usb_clk , // 48Mhz usb clock
+
+ // Reg Bus Interface Signal
+ input logic reg_cs,
+ input logic reg_wr,
+ input logic [7:0] reg_addr,
+ input logic [31:0] reg_wdata,
+ input logic reg_be,
+
+ // Outputs
+ output logic [31:0] reg_rdata,
+ output logic reg_ack,
+ /////////////////////////////////////////////////////////
+ // i2c interface
+ ///////////////////////////////////////////////////////
+ input logic scl_pad_i , // SCL-line input
+ output logic scl_pad_o , // SCL-line output (always 1'b0)
+ output logic scl_pad_oen_o , // SCL-line output enable (active low)
+
+ input logic sda_pad_i , // SDA-line input
+ output logic sda_pad_o , // SDA-line output (always 1'b0)
+ output logic sda_padoen_o , // SDA-line output enable (active low)
+
+ output logic i2cm_intr_o ,
+
+ // UART I/F
+ input logic uart_rxd ,
+ output logic uart_txd ,
+
+ // USB 1.1 HOST I/F
+ input logic usb_in_dp ,
+ input logic usb_in_dn ,
+
+ output logic usb_out_dp ,
+ output logic usb_out_dn ,
+ output logic usb_out_tx_oen ,
+
+ output logic usb_intr_o ,
+
+ // SPIM I/F
+ output logic sspim_sck, // clock out
+ output logic sspim_so, // serial data out
+ input logic sspim_si, // serial data in
+ output logic sspim_ssn // cs_n
+
+ );
+
+
+`define SEL_UART 2'b00
+`define SEL_I2C 2'b01
+`define SEL_USB 2'b10
+`define SEL_SPI 2'b11
+
+
+
+//----------------------------------------
+// Register Response Path Mux
+// --------------------------------------
+logic [7:0] reg_uart_rdata;
+logic [7:0] reg_i2c_rdata;
+logic [31:0] reg_usb_rdata;
+logic [31:0] reg_spim_rdata;
+logic reg_uart_ack;
+logic reg_i2c_ack;
+logic reg_usb_ack;
+logic reg_spim_ack;
+
+
+assign reg_rdata = (reg_addr[7:6] == `SEL_UART) ? {24'h0,reg_uart_rdata} :
+ (reg_addr[7:6] == `SEL_I2C) ? {24'h0,reg_i2c_rdata} :
+ (reg_addr[7:6] == `SEL_USB) ? reg_usb_rdata : reg_spim_rdata;
+assign reg_ack = (reg_addr[7:6] == `SEL_UART) ? reg_uart_ack :
+ (reg_addr[7:6] == `SEL_I2C) ? reg_i2c_ack :
+ (reg_addr[7:6] == `SEL_USB) ? reg_usb_ack : reg_spim_ack;
+
+wire reg_uart_cs = (reg_addr[7:6] == `SEL_UART) ? reg_cs : 1'b0;
+wire reg_i2cm_cs = (reg_addr[7:6] == `SEL_I2C) ? reg_cs : 1'b0;
+wire reg_usb_cs = (reg_addr[7:6] == `SEL_UART) ? reg_cs : 1'b0;
+wire reg_spim_cs = (reg_addr[7:6] == `SEL_SPI) ? reg_cs : 1'b0;
+
+uart_core u_uart_core (
+
+ .arst_n (uart_rstn ), // async reset
+ .app_clk (app_clk ),
+
+ // Reg Bus Interface Signal
+ .reg_cs (reg_uart_cs ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr[5:2] ),
+ .reg_wdata (reg_wdata[7:0] ),
+ .reg_be (reg_be ),
+
+ // Outputs
+ .reg_rdata (reg_uart_rdata[7:0]),
+ .reg_ack (reg_uart_ack ),
+
+ // Pad Control
+ .rxd (uart_rxd ),
+ .txd (uart_txd )
+ );
+
+i2cm_top u_i2cm (
+ // wishbone signals
+ .wb_clk_i (app_clk ), // master clock input
+ .sresetn (1'b1 ), // synchronous reset
+ .aresetn (i2c_rstn ), // asynchronous reset
+ .wb_adr_i (reg_addr[4:2] ), // lower address bits
+ .wb_dat_i (reg_wdata[7:0] ), // databus input
+ .wb_dat_o (reg_i2c_rdata ), // databus output
+ .wb_we_i (reg_wr ), // write enable input
+ .wb_stb_i (reg_i2cm_cs ), // stobe/core select signal
+ .wb_cyc_i (reg_i2cm_cs ), // valid bus cycle input
+ .wb_ack_o (reg_i2c_ack ), // bus cycle acknowledge output
+ .wb_inta_o (i2cm_intr_o ), // interrupt request signal output
+
+ // I2C signals
+ // i2c clock line
+ .scl_pad_i (scl_pad_i ), // SCL-line input
+ .scl_pad_o (scl_pad_o ), // SCL-line output (always 1'b0)
+ .scl_padoen_o (scl_pad_oen_o ), // SCL-line output enable (active low)
+
+ // i2c data line
+ .sda_pad_i (sda_pad_i ), // SDA-line input
+ .sda_pad_o (sda_pad_o ), // SDA-line output (always 1'b0)
+ .sda_padoen_o (sda_padoen_o ) // SDA-line output enable (active low)
+
+ );
+
+
+usb1_host u_usb_host (
+ .usb_clk_i (usb_clk ),
+ .usb_rstn_i (usb_rstn ),
+
+ // USB D+/D-
+ .in_dp (usb_in_dp ),
+ .in_dn (usb_in_dn ),
+
+ .out_dp (usb_out_dp ),
+ .out_dn (usb_out_dn ),
+ .out_tx_oen (usb_out_tx_oen),
+
+ // Master Port
+ .wbm_rst_n (usb_rstn ), // Regular Reset signal
+ .wbm_clk_i (app_clk ), // System clock
+ .wbm_stb_i (reg_usb_cs ), // strobe/request
+ .wbm_adr_i (reg_addr[5:0]), // address
+ .wbm_we_i (reg_wr ), // write
+ .wbm_dat_i (reg_wdata ), // data output
+ .wbm_sel_i (reg_be ), // byte enable
+ .wbm_dat_o (reg_usb_rdata ), // data input
+ .wbm_ack_o (reg_usb_ack ), // acknowlegement
+ .wbm_err_o ( ), // error
+
+ // Outputs
+ .usb_intr_o ( usb_intr_o )
+
+ );
+
+sspim_top u_sspim (
+ .clk (app_clk ),
+ .reset_n (spi_rstn ),
+
+
+ //---------------------------------
+ // Reg Bus Interface Signal
+ //---------------------------------
+ .reg_cs (reg_spim_cs ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr ),
+ .reg_wdata (reg_wdata ),
+ .reg_be (reg_be ),
+
+ // Outputs
+ .reg_rdata (reg_spim_rdata ),
+ .reg_ack (reg_spim_ack ),
+
+ //-------------------------------------------
+ // Line Interface
+ //-------------------------------------------
+
+ .sck (sspim_sck), // clock out
+ .so (sspim_so), // serial data out
+ .si (sspim_si), // serial data in
+ .ssn (sspim_ssn) // cs_n
+
+ );
+
+endmodule
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 7610979..3dc1964 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -56,14 +56,14 @@
`include "lib/pulse_gen_type1.sv"
`include "lib/pulse_gen_type2.sv"
- `include "spi_master/src/spim_top.sv"
- `include "spi_master/src/spim_if.sv"
- `include "spi_master/src/spim_fifo.sv"
- `include "spi_master/src/spim_regs.sv"
- `include "spi_master/src/spim_clkgen.sv"
- `include "spi_master/src/spim_ctrl.sv"
- `include "spi_master/src/spim_rx.sv"
- `include "spi_master/src/spim_tx.sv"
+ `include "qspim/src/qspim_top.sv"
+ `include "qspim/src/qspim_if.sv"
+ `include "qspim/src/qspim_fifo.sv"
+ `include "qspim/src/qspim_regs.sv"
+ `include "qspim/src/qspim_clkgen.sv"
+ `include "qspim/src/qspim_ctrl.sv"
+ `include "qspim/src/qspim_rx.sv"
+ `include "qspim/src/qspim_tx.sv"
`include "uart/src/uart_core.sv"
`include "uart/src/uart_cfg.sv"
@@ -87,7 +87,13 @@
`include "usb1_host/src/phy/usb_transceiver.v"
`include "usb1_host/src/top/usb1_host.sv"
- `include "uart_i2c_usb/src/uart_i2c_usb.sv"
+ `include "sspim/src/sspim_top.sv"
+ `include "sspim/src/sspim_ctl.sv"
+ `include "sspim/src/sspim_if.sv"
+ `include "sspim/src/sspim_cfg.sv"
+
+
+ `include "uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv"
`include "lib/async_fifo.sv"
`include "lib/registers.v"
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 66d3db2..856c053 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -26,8 +26,14 @@
//// This is digital core and integrate all the main block ////
//// here. Following block are integrated here ////
//// 1. Risc V Core ////
-//// 2. SPI Master ////
+//// 2. Quad SPI Master ////
//// 3. Wishbone Cross Bar ////
+//// 4. UART ////
+//// 5, USB 1.1 ////
+//// 6. SPI Master (Single) ////
+//// 7. SRAM 2KB ////
+//// 8. 6 Channel ADC ////
+//// 9. Pinmux with GPIO and 6 PWM ////
//// ////
//// To Do: ////
//// nothing ////
@@ -107,6 +113,8 @@
//// 1.3 - 30th Sept 2021, Dinesh.A ////
//// 2KB SRAM Interface added to RISC Core ////
//// ////
+//// 1.4 - 13th Oct 2021, Dinesh A ////
+//// Basic verification and Synthesis cleanup ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
@@ -280,8 +288,8 @@
// CPU Configuration
//----------------------------------------------------
wire cpu_rst_n ;
-wire spi_rst_n ;
-wire sdram_rst_n ;
+wire qspim_rst_n ;
+wire sspim_rst_n ;
wire uart_rst_n ;// uart reset
wire i2c_rst_n ;// i2c reset
wire usb_rst_n ;// i2c reset
@@ -385,7 +393,15 @@
wire [31:0] sram_dout1 ; // Read Data
`endif
+// SPIM I/F
+wire sspim_sck ; // clock out
+wire sspim_so ; // serial data out
+wire sspim_si ; // serial data in
+wire sspim_ssn ; // cs_n
+
+wire usb_intr_o ;
+wire i2cm_intr_o ;
/////////////////////////////////////////////////////////
// Clock Skew Ctrl
////////////////////////////////////////////////////////
@@ -422,8 +438,8 @@
.wbd_int_rst_n (wbd_int_rst_n ),
.cpu_rst_n (cpu_rst_n ),
- .spi_rst_n (spi_rst_n ),
- .sdram_rst_n (sdram_rst_n ),
+ .qspim_rst_n (qspim_rst_n ),
+ .sspim_rst_n (sspim_rst_n ), // spi reset
.uart_rst_n (uart_rst_n ), // uart reset
.i2cm_rst_n (i2c_rst_n ), // i2c reset
.usb_rst_n (usb_rst_n ), // usb reset
@@ -557,15 +573,15 @@
* It supports both the normal SPI mode and QPI mode with 4 data lines.
* *******************************************************/
-spim_top
+qspim_top
#(
`ifndef SYNTHESIS
.WB_WIDTH (WB_WIDTH)
`endif
-) u_spi_master
+) u_qspi_master
(
.mclk (wbd_clk_int ),
- .rst_n (spi_rst_n ),
+ .rst_n (qspim_rst_n ),
.wbd_stb_i (wbd_spim_stb_o ),
.wbd_adr_i (wbd_spim_adr_o ),
@@ -673,10 +689,11 @@
);
-uart_i2c_usb_top u_uart_i2c_usb (
+uart_i2c_usb_spi_top u_uart_i2c_usb_spi (
.uart_rstn (uart_rst_n ), // uart reset
.i2c_rstn (i2c_rst_n ), // i2c reset
- .usb_rstn (usb_rst_n ), // i2c reset
+ .usb_rstn (usb_rst_n ), // USB reset
+ .spi_rstn (sspim_rst_n ), // SPI reset
.app_clk (wbd_clk_int ),
.usb_clk (usb_clk ),
@@ -699,6 +716,8 @@
.sda_pad_i (i2cm_data_i ),
.sda_pad_o (i2cm_data_o ),
.sda_padoen_o (i2cm_data_oen ),
+
+ .i2cm_intr_o (i2cm_intr_o ),
.uart_rxd (uart_rxd ),
.uart_txd (uart_txd ),
@@ -708,7 +727,15 @@
.usb_out_dp (usb_dp_o ),
.usb_out_dn (usb_dn_o ),
- .usb_out_tx_oen (usb_oen )
+ .usb_out_tx_oen (usb_oen ),
+
+ .usb_intr_o (usb_intr_o ),
+
+ // SPIM Master
+ .sspim_sck (sspim_sck ),
+ .sspim_so (sspim_so ),
+ .sspim_si (sspim_si ),
+ .sspim_ssn (sspim_ssn )
);
@@ -736,6 +763,8 @@
.irq_lines (irq_lines ),
.soft_irq (soft_irq ),
.user_irq (user_irq ),
+ .usb_intr (usb_intr_o ),
+ .i2cm_intr (i2cm_intr_o ),
// Digital IO
.digital_io_out (io_out ),
@@ -776,10 +805,10 @@
.i2cm_data_i (i2cm_data_i ),
// SPI MASTER
- .spim_sck (sflash_sck ),
- .spim_ss (sflash_ss ),
- .spim_miso (sflash_do[0] ),
- .spim_mosi ( ),
+ .spim_sck (sspim_sck ),
+ .spim_ss (sspim_ssn ),
+ .spim_miso (sspim_so ),
+ .spim_mosi (sspim_si ),
.pulse1m_mclk (pulse1m_mclk ),
@@ -814,14 +843,16 @@
// DAC I/F
.sar2dac (sar2dac ),
- .analog_dac_out (analog_dac_out) ,
+ //.analog_dac_out (analog_dac_out) , // TODO: Need to connect to DAC O/P
+ .analog_dac_out (analog_io[6]) ,
// ADC Input
.analog_din(analog_io[5:0]) // (Analog)
);
-
+/****
+* TODO: Need to uncomment the DAC
DAC_8BIT u_dac (
`ifdef USE_POWER_PINS
.vdd(vccd2),
@@ -839,7 +870,6 @@
.out_v(analog_dac_out)
);
-
-
+**/
endmodule : user_project_wrapper
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index 184e9b6..114ef20 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -79,8 +79,8 @@
// Global Reset control
output logic wbd_int_rst_n ,
output logic cpu_rst_n ,
- output logic spi_rst_n ,
- output logic sdram_rst_n ,
+ output logic qspim_rst_n ,
+ output logic sspim_rst_n ,
output logic uart_rst_n ,
output logic i2cm_rst_n ,
output logic usb_rst_n ,
@@ -160,8 +160,8 @@
sky130_fd_sc_hd__bufbuf_16 u_buf_wb_rst (.A(cfg_glb_ctrl[0]),.X(wbd_int_rst_n));
sky130_fd_sc_hd__bufbuf_16 u_buf_cpu_rst (.A(cfg_glb_ctrl[1]),.X(cpu_rst_n));
-sky130_fd_sc_hd__bufbuf_16 u_buf_spi_rst (.A(cfg_glb_ctrl[2]),.X(spi_rst_n));
-sky130_fd_sc_hd__bufbuf_16 u_buf_sdram_rst (.A(cfg_glb_ctrl[3]),.X(sdram_rst_n));
+sky130_fd_sc_hd__bufbuf_16 u_buf_qspim_rst (.A(cfg_glb_ctrl[2]),.X(qspim_rst_n));
+sky130_fd_sc_hd__bufbuf_16 u_buf_sspim_rst (.A(cfg_glb_ctrl[3]),.X(sspim_rst_n));
sky130_fd_sc_hd__bufbuf_16 u_buf_uart_rst (.A(cfg_glb_ctrl[4]),.X(uart_rst_n));
sky130_fd_sc_hd__bufbuf_16 u_buf_i2cm_rst (.A(cfg_glb_ctrl[5]),.X(i2cm_rst_n));
sky130_fd_sc_hd__bufbuf_16 u_buf_usb_rst (.A(cfg_glb_ctrl[6]),.X(usb_rst_n));
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index d7b7f7a..c0e9bd7 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -223,11 +223,12 @@
//-------------------------------------------------------------------
// EXTERNAL MEMORY MAP
-// 0x0000_0000 to 0x0FFF_FFFF - SPI FLASH MEMORY
-// 0x1000_0000 to 0x1000_00FF - SPI REGISTER
+// 0x0000_0000 to 0x0FFF_FFFF - QSPI MEMORY
+// 0x1000_0000 to 0x1000_00FF - QSPIM REG
// 0x1001_0000 to 0x1001_003F - UART
// 0x1001_0040 to 0x1001_007F - I2C
-// 0x1001_0080 to 0x1001_008F - USB
+// 0x1001_0080 to 0x1001_00BF - USB
+// 0x1001_00C0 to 0x1001_00FF - SSPIM
// 0x1002_0000 to 0x1002_00FF - ADC
// 0x1003_0000 to 0x1003_00FF - PINMUX
// 0x3080_0000 to 0x3080_00FF - WB HOST (This decoding happens at wb_host block)
@@ -235,18 +236,19 @@
//
wire [3:0] m0_wbd_tid_i = (m0_wbd_adr_i[31:28] == 4'b0000 ) ? 4'b0000 : // SPI
(m0_wbd_adr_i[31:16] == 16'h1000 ) ? 4'b0000 : // SPI REG
- (m0_wbd_adr_i[31:16] == 16'h1001 ) ? 4'b0001 : // UART/I2C/USB
+ (m0_wbd_adr_i[31:16] == 16'h1001 ) ? 4'b0001 : // UART/I2C/USB/SPI
(m0_wbd_adr_i[31:16] == 16'h1002 ) ? 4'b0010 : // ADC
(m0_wbd_adr_i[31:16] == 16'h1003 ) ? 4'b0011 : // PINMUX
4'b0000;
//------------------------------
// RISC Data Memory Map
-// 0x0000_0000 to 0x0FFF_FFFF - SPI FLASH MEMORY
-// 0x1000_0000 to 0x1000_00FF - SPI REGISTER
+// 0x0000_0000 to 0x0FFF_FFFF - QSPIM MEMORY
+// 0x1000_0000 to 0x1000_00FF - QSPIM REG
// 0x1001_0000 to 0x1001_003F - UART
// 0x1001_0040 to 0x1001_007F - I2
-// 0x1001_0080 to 0x1001_008F - USB
+// 0x1001_0080 to 0x1001_00BF - USB
+// 0x1001_00C0 to 0x1001_00FF - SSPIM
// 0x1002_0000 to 0x1002_00FF - ADC
// 0x1003_0000 to 0x1003_00FF - PINMUX
//-----------------------------
